From 2bbb2ecbb7f5dbfba314963752b042f80144dd1f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 28 Aug 2024 09:11:08 -0400 Subject: [PATCH] use get_mainlib helper function --- scgallery/designs/aes/aes.py | 3 ++- scgallery/designs/ariane/ariane.py | 3 ++- scgallery/designs/black_parrot/black_parrot.py | 3 ++- scgallery/designs/caliptra/datavault.py | 3 ++- scgallery/designs/caliptra/keyvault.py | 3 ++- scgallery/designs/caliptra/sha512.py | 3 ++- scgallery/designs/dynamic_node/dynamic_node.py | 3 ++- scgallery/designs/ethmac/ethmac.py | 3 ++- scgallery/designs/heartbeat/heartbeat.py | 3 ++- scgallery/designs/ibex/ibex.py | 3 ++- scgallery/designs/jpeg/jpeg.py | 3 ++- scgallery/designs/mock_alu/mock_alu.py | 3 ++- scgallery/designs/openmsp430/openmsp430.py | 3 ++- scgallery/designs/picorv32/picorv32.py | 3 ++- scgallery/designs/riscv32i/riscv32i.py | 3 ++- scgallery/designs/spi/spi.py | 3 ++- scgallery/designs/swerv/swerv.py | 3 ++- scgallery/designs/tiny_rocket/tiny_rocket.py | 3 ++- scgallery/designs/uart/uart.py | 3 ++- scgallery/rules.py | 3 ++- 20 files changed, 40 insertions(+), 20 deletions(-) diff --git a/scgallery/designs/aes/aes.py b/scgallery/designs/aes/aes.py index af560c1..370fec0 100755 --- a/scgallery/designs/aes/aes.py +++ b/scgallery/designs/aes/aes.py @@ -10,6 +10,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -35,7 +36,7 @@ def setup(target=asap7_demo): chip.add('option', 'idir', src_root, package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') if mainlib.startswith('sky130'): diff --git a/scgallery/designs/ariane/ariane.py b/scgallery/designs/ariane/ariane.py index 561d10d..214bebd 100755 --- a/scgallery/designs/ariane/ariane.py +++ b/scgallery/designs/ariane/ariane.py @@ -10,6 +10,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs import _common from scgallery import Gallery @@ -28,7 +29,7 @@ def setup(target=freepdk45_demo): for src in ('ariane.sv2v.v', 'macros.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'flatten', 'false') diff --git a/scgallery/designs/black_parrot/black_parrot.py b/scgallery/designs/black_parrot/black_parrot.py index f1ae80e..da69c0b 100755 --- a/scgallery/designs/black_parrot/black_parrot.py +++ b/scgallery/designs/black_parrot/black_parrot.py @@ -8,6 +8,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs import _common from scgallery import Gallery @@ -27,7 +28,7 @@ def setup(target=freepdk45_demo): for src in ('pickled.v',): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('option', 'define', 'SYNTHESIS') diff --git a/scgallery/designs/caliptra/datavault.py b/scgallery/designs/caliptra/datavault.py index 54ce17b..c7f9b18 100755 --- a/scgallery/designs/caliptra/datavault.py +++ b/scgallery/designs/caliptra/datavault.py @@ -10,6 +10,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs.caliptra.src import datavault from scgallery import Gallery @@ -28,7 +29,7 @@ def setup(target=freepdk45_demo): chip.set('option', 'entrypoint', 'dv') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('constraint', 'density', 30) diff --git a/scgallery/designs/caliptra/keyvault.py b/scgallery/designs/caliptra/keyvault.py index ec32a82..4b2e530 100755 --- a/scgallery/designs/caliptra/keyvault.py +++ b/scgallery/designs/caliptra/keyvault.py @@ -10,6 +10,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs.caliptra.src import keyvault from scgallery import Gallery @@ -28,7 +29,7 @@ def setup(target=freepdk45_demo): chip.set('option', 'entrypoint', 'kv') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('constraint', 'density', 20) diff --git a/scgallery/designs/caliptra/sha512.py b/scgallery/designs/caliptra/sha512.py index 5c1b5c2..3a51547 100755 --- a/scgallery/designs/caliptra/sha512.py +++ b/scgallery/designs/caliptra/sha512.py @@ -10,6 +10,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs.caliptra.src import sha512 from scgallery import Gallery @@ -28,7 +29,7 @@ def setup(target=freepdk45_demo): chip.set('option', 'entrypoint', 'sha512_ctrl') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('constraint', 'density', 30) diff --git a/scgallery/designs/dynamic_node/dynamic_node.py b/scgallery/designs/dynamic_node/dynamic_node.py index aecb8d3..4440816 100755 --- a/scgallery/designs/dynamic_node/dynamic_node.py +++ b/scgallery/designs/dynamic_node/dynamic_node.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -25,7 +26,7 @@ def setup(target=asap7_demo): chip.input('modules/dynamic_node_2dmesh/NETWORK_2dmesh/dynamic_node_2dmesh.pickle.v', package='OPDB') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') return chip diff --git a/scgallery/designs/ethmac/ethmac.py b/scgallery/designs/ethmac/ethmac.py index 6d597f5..df9acf9 100755 --- a/scgallery/designs/ethmac/ethmac.py +++ b/scgallery/designs/ethmac/ethmac.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs import _common from scgallery import Gallery @@ -53,7 +54,7 @@ def setup(target=asap7_demo): chip.add('option', 'define', 'ETH_VIRTUAL_SILICON_RAM') chip.input(os.path.join('ethmac', 'extra', 'lambda.v'), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('tool', 'openroad', 'task', 'floorplan', 'var', 'rtlmp_enable', 'true') diff --git a/scgallery/designs/heartbeat/heartbeat.py b/scgallery/designs/heartbeat/heartbeat.py index 7a64d28..d24c3fa 100755 --- a/scgallery/designs/heartbeat/heartbeat.py +++ b/scgallery/designs/heartbeat/heartbeat.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -21,7 +22,7 @@ def setup(target=asap7_demo): for src in ('heartbeat.v',): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') return chip diff --git a/scgallery/designs/ibex/ibex.py b/scgallery/designs/ibex/ibex.py index 86e646a..a66d166 100755 --- a/scgallery/designs/ibex/ibex.py +++ b/scgallery/designs/ibex/ibex.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -55,7 +56,7 @@ def setup(target=asap7_demo): chip.add('option', 'define', 'SYNTHESIS') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') if mainlib.startswith('asap7sc7p5t'): diff --git a/scgallery/designs/jpeg/jpeg.py b/scgallery/designs/jpeg/jpeg.py index 73725a6..77bea13 100755 --- a/scgallery/designs/jpeg/jpeg.py +++ b/scgallery/designs/jpeg/jpeg.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -36,7 +37,7 @@ def setup(target=asap7_demo): 'zigzag.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') # Lint setup diff --git a/scgallery/designs/mock_alu/mock_alu.py b/scgallery/designs/mock_alu/mock_alu.py index 8fa3eae..4604c05 100755 --- a/scgallery/designs/mock_alu/mock_alu.py +++ b/scgallery/designs/mock_alu/mock_alu.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -44,7 +45,7 @@ def setup(target=asap7_demo): chip.add('tool', 'chisel', 'task', 'convert', 'var', 'argument', f'--operations {",".join(operations)}') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.add('tool', 'chisel', 'task', 'convert', 'var', 'argument', '--tech none') diff --git a/scgallery/designs/openmsp430/openmsp430.py b/scgallery/designs/openmsp430/openmsp430.py index 7e23e10..689c239 100755 --- a/scgallery/designs/openmsp430/openmsp430.py +++ b/scgallery/designs/openmsp430/openmsp430.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import skywater130_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -46,7 +47,7 @@ def setup(target=skywater130_demo): 'omsp_clock_mux.v'): chip.input(os.path.join(src_root, src), package='openmsp430') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') return chip diff --git a/scgallery/designs/picorv32/picorv32.py b/scgallery/designs/picorv32/picorv32.py index 9fb6ba9..44c92f5 100755 --- a/scgallery/designs/picorv32/picorv32.py +++ b/scgallery/designs/picorv32/picorv32.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import skywater130_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -24,7 +25,7 @@ def setup(target=skywater130_demo): for src in ('picorv32.v',): chip.input(src, package='picorv32') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') return chip diff --git a/scgallery/designs/riscv32i/riscv32i.py b/scgallery/designs/riscv32i/riscv32i.py index f1a86cb..915645b 100755 --- a/scgallery/designs/riscv32i/riscv32i.py +++ b/scgallery/designs/riscv32i/riscv32i.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import skywater130_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -46,7 +47,7 @@ def setup(target=skywater130_demo): 'top.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') # Lint setup diff --git a/scgallery/designs/spi/spi.py b/scgallery/designs/spi/spi.py index dea1539..af19802 100755 --- a/scgallery/designs/spi/spi.py +++ b/scgallery/designs/spi/spi.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -21,7 +22,7 @@ def setup(target=asap7_demo): for src in ('spi.v',): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') return chip diff --git a/scgallery/designs/swerv/swerv.py b/scgallery/designs/swerv/swerv.py index 97fccaf..1191adb 100755 --- a/scgallery/designs/swerv/swerv.py +++ b/scgallery/designs/swerv/swerv.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -77,7 +78,7 @@ def setup(target=asap7_demo): chip.add('option', 'define', 'PHYSICAL') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') # Lint setup diff --git a/scgallery/designs/tiny_rocket/tiny_rocket.py b/scgallery/designs/tiny_rocket/tiny_rocket.py index 8fd73a7..d18750a 100755 --- a/scgallery/designs/tiny_rocket/tiny_rocket.py +++ b/scgallery/designs/tiny_rocket/tiny_rocket.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import freepdk45_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery.designs import _common from scgallery import Gallery @@ -27,7 +28,7 @@ def setup(target=freepdk45_demo): 'plusarg_reader.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') chip.set('option', 'define', 'SYNTHESIS') diff --git a/scgallery/designs/uart/uart.py b/scgallery/designs/uart/uart.py index b39f630..29a0108 100755 --- a/scgallery/designs/uart/uart.py +++ b/scgallery/designs/uart/uart.py @@ -4,6 +4,7 @@ from siliconcompiler import Chip from siliconcompiler.targets import asap7_demo +from siliconcompiler.tools._common.asic import get_mainlib from scgallery import Gallery @@ -24,7 +25,7 @@ def setup(target=asap7_demo): 'uart_rx.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs') # Lint setup diff --git a/scgallery/rules.py b/scgallery/rules.py index 031265b..62cd347 100644 --- a/scgallery/rules.py +++ b/scgallery/rules.py @@ -1,5 +1,6 @@ import argparse from siliconcompiler import Chip, SiliconCompilerError +from siliconcompiler.tools._common.asic import get_mainlib import os import sys import json @@ -135,7 +136,7 @@ def create_rules(chip): def update_rules(chip, method, rules): rules["date"] = datetime.now().strftime("%Y/%m/%d %H:%M:%S") - mainlib = chip.get('asic', 'logiclib')[0] + mainlib = get_mainlib(chip) if mainlib not in rules: raise ValueError(f'{mainlib} is missing from rules')