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gadfortgadfort
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update template generator
1 parent c0c6c85 commit 0f6b610

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3 files changed

+80
-48
lines changed

3 files changed

+80
-48
lines changed

‎lambdalib/ramlib/rtl/la_spram.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ module la_spram #(
4848
.AW (AW),
4949
.PROP (PROP),
5050
.CTRLW (CTRLW),
51-
.TESTW (TESTW),
51+
.TESTW (TESTW)
5252
) ram (
5353
.clk (clk),
5454
.ce (ce),

‎lambdalib/utils/__init__.py

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
from jinja2 import Template
22
import os
3+
import math
34
from collections import OrderedDict
45

56

6-
def write_la_spram(fout, memories, control_signals=None, la_type='ram'):
7+
def write_la_spram(fout, memories, control_signals=None, la_type='ram', minbits=None):
78
template_path = os.path.abspath(os.path.join(os.path.dirname(__file__),
89
'templates',
910
'la_spmemory.v'))
@@ -33,6 +34,13 @@ def write_la_spram(fout, memories, control_signals=None, la_type='ram'):
3334
selection_table = OrderedDict(sorted(selection_table.items(), reverse=True))
3435
for aw, items in selection_table.items():
3536
selection_table[aw] = OrderedDict(sorted(items.items(), reverse=True))
37+
38+
if minbits is not None:
39+
depth = 2**aw
40+
dw = int(math.floor(minbits / depth))
41+
if dw > 0:
42+
selection_table[aw][dw] = "SOFT"
43+
selection_table[min(selection_table.keys()) - 1] = {0: "SOFT"}
3644
widths_table.sort()
3745
depths_table.sort()
3846

‎lambdalib/utils/templates/la_spmemory.v

Lines changed: 70 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -56,61 +56,85 @@ module la_sp{{ type }}
5656
(MEM_PROP == "{{ memory }}") ? {{ depth }} :{% endfor %}
5757
0;
5858

59-
// Create memories
60-
localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
61-
62-
{% if control_signals %}// Control signals{% for line in control_signals %}
63-
{{ line }}{% endfor %}{% endif %}
64-
6559
generate
66-
genvar o;
67-
for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
68-
wire [MEM_ADDRS-1:0] mem_outputs;
69-
assign dout[o] = |mem_outputs;
60+
if (MEM_PROP == "SOFT") begin: isoft
61+
la_spram_impl #(
62+
.DW(DW),
63+
.AW(AW),
64+
.PROP(PROP),
65+
.CTRLW(CTRLW),
66+
.TESTW(TESTW)
67+
) memory(
68+
.clk(clk),
69+
.ce(ce),
70+
.we(we),
71+
.wmask(wmask),
72+
.addr(addr),
73+
.din(din),
74+
.dout(dout),
75+
.vss(vss),
76+
.vdd(vdd),
77+
.vddio(vddio),
78+
.ctrl(ctrl),
79+
.test(test)
80+
);
7081
end
82+
if (MEM_PROP != "SOFT") begin: itech
83+
// Create memories
84+
localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
7185

72-
genvar a;
73-
for (a = 0; a < MEM_ADDRS; a = a + 1) begin: ADDR
74-
wire selected;
75-
wire [MEM_DEPTH-1:0] mem_addr;
86+
{% if control_signals %}// Control signals{% for line in control_signals %}
87+
{{ line }}{% endfor %}{% endif %}
7688

77-
if (MEM_ADDRS == 1) begin: FITS
78-
assign selected = 1'b1;
79-
assign mem_addr = addr;
80-
end else begin: NOFITS
81-
assign selected = addr[AW-1:MEM_DEPTH] == a;
82-
assign mem_addr = addr[MEM_DEPTH-1:0];
89+
genvar o;
90+
for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
91+
wire [MEM_ADDRS-1:0] mem_outputs;
92+
assign dout[o] = |mem_outputs;
8393
end
8494

85-
genvar n;
86-
for (n = 0; n < DW; n = n + MEM_WIDTH) begin: WORD
87-
wire [MEM_WIDTH-1:0] mem_din;
88-
wire [MEM_WIDTH-1:0] mem_dout;
89-
wire [MEM_WIDTH-1:0] mem_wmask;
95+
genvar a;
96+
for (a = 0; a < MEM_ADDRS; a = a + 1) begin: ADDR
97+
wire selected;
98+
wire [MEM_DEPTH-1:0] mem_addr;
9099

91-
genvar i;
92-
for (i = 0; i < MEM_WIDTH; i = i + 1) begin: WORD_SELECT
93-
if (n + i < DW) begin: ACTIVE
94-
assign mem_din[i] = din[n + i];
95-
assign mem_wmask[i] = wmask[n + i];
96-
assign OUTPUTS[n + i].mem_outputs[a] = selected ? mem_dout[i] : 1'b0;
97-
end
98-
else begin: INACTIVE
99-
assign mem_din[i] = 1'b0;
100-
assign mem_wmask[i] = 1'b0;
101-
end
100+
if (MEM_ADDRS == 1) begin: FITS
101+
assign selected = 1'b1;
102+
assign mem_addr = addr;
103+
end else begin: NOFITS
104+
assign selected = addr[AW-1:MEM_DEPTH] == a;
105+
assign mem_addr = addr[MEM_DEPTH-1:0];
102106
end
103107

104-
wire ce_in;
105-
wire we_in;
106-
assign ce_in = ce && selected;
107-
assign we_in = we && selected;
108-
{% for memory, inst_name in inst_map.items() %}
109-
if (MEM_PROP == "{{ memory }}") begin: i{{ memory }}
110-
{{ inst_name }} memory ({% for port, net in port_mapping[memory] %}
111-
.{{ port }}({{ net }}){% if loop.nextitem is defined %},{% endif %}{% endfor %}
112-
);
113-
end{% endfor %}
108+
genvar n;
109+
for (n = 0; n < DW; n = n + MEM_WIDTH) begin: WORD
110+
wire [MEM_WIDTH-1:0] mem_din;
111+
wire [MEM_WIDTH-1:0] mem_dout;
112+
wire [MEM_WIDTH-1:0] mem_wmask;
113+
114+
genvar i;
115+
for (i = 0; i < MEM_WIDTH; i = i + 1) begin: WORD_SELECT
116+
if (n + i < DW) begin: ACTIVE
117+
assign mem_din[i] = din[n + i];
118+
assign mem_wmask[i] = wmask[n + i];
119+
assign OUTPUTS[n + i].mem_outputs[a] = selected ? mem_dout[i] : 1'b0;
120+
end
121+
else begin: INACTIVE
122+
assign mem_din[i] = 1'b0;
123+
assign mem_wmask[i] = 1'b0;
124+
end
125+
end
126+
127+
wire ce_in;
128+
wire we_in;
129+
assign ce_in = ce && selected;
130+
assign we_in = we && selected;
131+
{% for memory, inst_name in inst_map.items() %}
132+
if (MEM_PROP == "{{ memory }}") begin: i{{ memory }}
133+
{{ inst_name }} memory ({% for port, net in port_mapping[memory] %}
134+
.{{ port }}({{ net }}){% if loop.nextitem is defined %},{% endif %}{% endfor %}
135+
);
136+
end{% endfor %}
137+
end
114138
end
115139
end
116140
endgenerate

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