From 260773ba2fd2aa34d6819dba485348b645fe01b8 Mon Sep 17 00:00:00 2001 From: yulong Date: Thu, 21 Nov 2024 17:42:53 +0800 Subject: [PATCH] RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. --- gcc/config/riscv/generic-vector-ooo.md | 2 +- gcc/config/riscv/genrvv-type-indexer.cc | 10 ++++ .../riscv/riscv-vector-builtins-bases.cc | 53 +++++++++++++++++++ .../riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-shapes.cc | 28 ++++++++++ .../riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 51 ++++++++++++------ gcc/config/riscv/riscv-vector-builtins.def | 35 ++++++------ gcc/config/riscv/riscv-vector-builtins.h | 7 +++ gcc/config/riscv/riscv.md | 3 +- .../sifive-vector-builtins-functions.def | 4 ++ gcc/config/riscv/sifive-vector.md | 20 +++++++ gcc/config/riscv/vector-iterators.md | 29 +++++++++- 13 files changed, 212 insertions(+), 33 deletions(-) diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md index 471a112dec99..025ad521d032 100644 --- a/gcc/config/riscv/generic-vector-ooo.md +++ b/gcc/config/riscv/generic-vector-ooo.md @@ -69,7 +69,7 @@ ;; Vector float multiplication and FMA. (define_insn_reservation "vec_fmul" 6 - (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16,vqmacc") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16,vqmacc,vfnrclip") "vxu_ooo_issue,vxu_ooo_alu") ;; Vector crypto, assumed to be a generic operation for now. diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc index 8822e101c530..e1eee34237a3 100644 --- a/gcc/config/riscv/genrvv-type-indexer.cc +++ b/gcc/config/riscv/genrvv-type-indexer.cc @@ -250,6 +250,7 @@ main (int argc, const char **argv) fprintf (fp, " /*MASK*/ %s,\n", mode.str ().c_str ()); fprintf (fp, " /*SIGNED*/ INVALID,\n"); fprintf (fp, " /*UNSIGNED*/ INVALID,\n"); + fprintf (fp, " /*SIGNED_EEW8_INDEX*/ INVALID,\n"); for (unsigned eew : {8, 16, 32, 64}) fprintf (fp, " /*EEW%d_INDEX*/ INVALID,\n", eew); fprintf (fp, " /*SHIFT*/ INVALID,\n"); @@ -316,6 +317,10 @@ main (int argc, const char **argv) inttype (sew, lmul_log2, /*unsigned_p*/ false).c_str ()); fprintf (fp, " /*UNSIGNED*/ %s,\n", inttype (sew, lmul_log2, /*unsigned_p*/ true).c_str ()); + fprintf (fp, " /*SIGNED_EEW8_INDEX*/ %s,\n", + same_ratio_eew_type (sew, lmul_log2, 8, + /*unsigned_p*/ false, false) + .c_str ()); for (unsigned eew : {8, 16, 32, 64}) fprintf (fp, " /*EEW%d_INDEX*/ %s,\n", eew, same_ratio_eew_type (sew, lmul_log2, eew, @@ -432,6 +437,7 @@ main (int argc, const char **argv) inttype (16, lmul_log2, /*unsigned_p*/ false).c_str ()); fprintf (fp, " /*UNSIGNED*/ %s,\n", inttype (16, lmul_log2, /*unsigned_p*/ true).c_str ()); + fprintf (fp, " /*SIGNED_EEW8_INDEX*/ INVALID,\n"); for (unsigned eew : {8, 16, 32, 64}) fprintf ( fp, " /*EEW%d_INDEX*/ %s,\n", eew, @@ -505,6 +511,10 @@ main (int argc, const char **argv) inttype (sew, lmul_log2, /*unsigned_p*/ false).c_str ()); fprintf (fp, " /*UNSIGNED*/ %s,\n", inttype (sew, lmul_log2, /*unsigned_p*/ true).c_str ()); + fprintf (fp, " /*SIGNED_EEW8_INDEX*/ %s,\n", + same_ratio_eew_type (sew, lmul_log2, 8, + /*unsigned_p*/ false, false) + .c_str ()); for (unsigned eew : {8, 16, 32, 64}) fprintf (fp, " /*EEW%d_INDEX*/ %s,\n", eew, same_ratio_eew_type (sew, lmul_log2, eew, diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index f4105c56e487..6874a7e14d99 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -705,6 +705,55 @@ class vnclip : public function_base } }; +/* Implements vfnrclip. */ +template +class vfnrclip_x_f_qf : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + + bool may_require_frm_p () const override { return true; } + + bool can_be_overloaded_p (enum predication_type_index pred) const override + { + return pred != PRED_TYPE_none; + } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn ( + code_for_pred_sf_vfnrclip_x_f_qf (UNSPEC, e.vector_mode ())); + gcc_unreachable (); + } +}; + +template +class vfnrclip_xu_f_qf : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + + bool may_require_frm_p () const override { return true; } + + bool can_be_overloaded_p (enum predication_type_index pred) const override + { + return pred != PRED_TYPE_none; + } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn ( + code_for_pred_sf_vfnrclip_x_f_qf (UNSPEC, e.vector_mode ())); + gcc_unreachable (); + } +}; + /* Implements vmseq/vmsne/vmslt/vmsgt/vmsle/vmsge. */ template class icmp : public function_base @@ -2676,6 +2725,8 @@ static CONSTEXPR const sat_op vssrl_obj; static CONSTEXPR const sat_op vssra_obj; static CONSTEXPR const vnclip vnclip_obj; static CONSTEXPR const vnclip vnclipu_obj; +static CONSTEXPR const vfnrclip_x_f_qf sf_vfnrclip_x_f_qf_obj; +static CONSTEXPR const vfnrclip_xu_f_qf sf_vfnrclip_xu_f_qf_obj; static CONSTEXPR const mask_logic vmand_obj; static CONSTEXPR const mask_nlogic vmnand_obj; static CONSTEXPR const mask_notlogic vmandn_obj; @@ -3010,6 +3061,8 @@ BASE (vssra) BASE (vssrl) BASE (vnclip) BASE (vnclipu) +BASE (sf_vfnrclip_x_f_qf) +BASE (sf_vfnrclip_xu_f_qf) BASE (vmand) BASE (vmnand) BASE (vmandn) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 3f10f41ee865..03f9ada68425 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -126,6 +126,8 @@ extern const function_base *const vssra; extern const function_base *const vssrl; extern const function_base *const vnclip; extern const function_base *const vnclipu; +extern const function_base *const sf_vfnrclip_x_f_qf; +extern const function_base *const sf_vfnrclip_xu_f_qf; extern const function_base *const vmand; extern const function_base *const vmnand; extern const function_base *const vmandn; diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 3d41d04965b4..f784f35518c7 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -1316,6 +1316,33 @@ struct sf_vqmacc_def : public build_base } }; +/* sf_vfnrclip_def class. Handle instructions like vfnrclip. */ +struct sf_vfnrclip_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + b.append_base_name (instance.base_name); + + /* Return nullptr if it can not be overloaded. */ + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return b.finish_name (); + + if (!overloaded_p) + { + vector_type_index ret_type_idx + = instance.op_info->ret.get_function_type_index (instance.type.index); + /* v --> v_. */ + b.append_name (type_suffixes[ret_type_idx].vector); + } + + /* According to SIFIVE vector-intrinsic-doc, it adds suffixes + for vop_m C++ overloaded API.*/ + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + SHAPE(vsetvl, vsetvl) SHAPE(vsetvl, vsetvlmax) SHAPE(loadstore, loadstore) @@ -1351,4 +1378,5 @@ SHAPE(crypto_vv, crypto_vv) SHAPE(crypto_vi, crypto_vi) SHAPE(crypto_vv_no_op_type, crypto_vv_no_op_type) SHAPE (sf_vqmacc, sf_vqmacc) +SHAPE (sf_vfnrclip, sf_vfnrclip) } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index a06960de71e2..16049c460186 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -61,6 +61,7 @@ extern const function_shape *const crypto_vi; extern const function_shape *const crypto_vv_no_op_type; /* Sifive vendor extension. */ extern const function_shape *const sf_vqmacc; +extern const function_shape *const sf_vfnrclip; } } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index d8c0d1e1685f..aa0385dd91cd 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -719,6 +719,10 @@ static CONSTEXPR const rvv_arg_type_info shift_wv_args[] rvv_arg_type_info (RVV_BASE_double_trunc_unsigned_vector), rvv_arg_type_info_end}; +static CONSTEXPR const rvv_arg_type_info clip_args[] + = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_scalar), + rvv_arg_type_info_end}; + /* A list of args for vector_type func (vector_type) function. */ static CONSTEXPR const rvv_arg_type_info v_args[] = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end}; @@ -2542,6 +2546,22 @@ static CONSTEXPR const rvv_op_info i_narrow_shift_vwx_ops rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */ v_size_args /* Args */}; +/* A static operand information for double demote type func (vector_type, + * shift_type) function registration. */ +static CONSTEXPR const rvv_op_info u_clip_qf_ops + = {f32_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_eew8_index), /* Return type */ + clip_args /* Args */}; + +/* A static operand information for double demote type func (vector_type, + * shift_type) function registration. */ +static CONSTEXPR const rvv_op_info i_clip_qf_ops + = {f32_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_signed_eew8_index), /* Return type */ + clip_args /* Args */}; + /* A static operand information for double demote type func (vector_type, * size_t) function registration. */ static CONSTEXPR const rvv_op_info u_narrow_shift_vwx_ops @@ -2982,21 +3002,21 @@ static CONSTEXPR const rvv_op_info u_vvvv_crypto_sew64_ops /* A list of all RVV base function types. */ static CONSTEXPR const function_type_info function_types[] = { #define DEF_RVV_TYPE_INDEX( \ - VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ - EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, QUAD_EMUL_SIGNED, \ - QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, QUAD_FIX_UNSIGNED, OCT_TRUNC, \ - DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ - DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ - DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, QLMUL1, \ - QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET, EEW16_INTERPRET, \ - EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, BOOL2_INTERPRET, \ - BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, BOOL32_INTERPRET, \ - BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \ - SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \ - UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \ - UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, \ - X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \ - X64_VLMUL_EXT, TUPLE_SUBPART) \ + VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX, \ + EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, \ + QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, \ + QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, \ + DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \ + DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, \ + LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET, \ + EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, \ + BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, \ + BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, \ + SIGNED_EEW16_LMUL1_INTERPRET, SIGNED_EEW32_LMUL1_INTERPRET, \ + SIGNED_EEW64_LMUL1_INTERPRET, UNSIGNED_EEW8_LMUL1_INTERPRET, \ + UNSIGNED_EEW16_LMUL1_INTERPRET, UNSIGNED_EEW32_LMUL1_INTERPRET, \ + UNSIGNED_EEW64_LMUL1_INTERPRET, X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, \ + X16_VLMUL_EXT, X32_VLMUL_EXT, X64_VLMUL_EXT, TUPLE_SUBPART) \ { \ VECTOR_TYPE_##VECTOR, \ VECTOR_TYPE_INVALID, \ @@ -3012,6 +3032,7 @@ static CONSTEXPR const function_type_info function_types[] = { VECTOR_TYPE_INVALID, \ VECTOR_TYPE_INVALID, \ VECTOR_TYPE_INVALID, \ + VECTOR_TYPE_##SIGNED_EEW8_INDEX, \ VECTOR_TYPE_##EEW8_INDEX, \ VECTOR_TYPE_##EEW16_INDEX, \ VECTOR_TYPE_##EEW32_INDEX, \ diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 71208450c828..a206444108ce 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -69,21 +69,21 @@ along with GCC; see the file COPYING3. If not see /* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */ #ifndef DEF_RVV_TYPE_INDEX #define DEF_RVV_TYPE_INDEX( \ - VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ - EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, QUAD_EMUL_SIGNED, \ - QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, QUAD_FIX_UNSIGNED, \ - OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ - DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ - DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, QLMUL1, \ - QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET, EEW16_INTERPRET, \ - EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, BOOL2_INTERPRET, \ - BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, BOOL32_INTERPRET, \ - BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \ - SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \ - UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \ - UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, \ - X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \ - X64_VLMUL_EXT, TUPLE_SUBPART) + VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX, \ + EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, \ + QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, \ + QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, \ + DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \ + DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, \ + LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET, \ + EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, \ + BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, \ + BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, \ + SIGNED_EEW16_LMUL1_INTERPRET, SIGNED_EEW32_LMUL1_INTERPRET, \ + SIGNED_EEW64_LMUL1_INTERPRET, UNSIGNED_EEW8_LMUL1_INTERPRET, \ + UNSIGNED_EEW16_LMUL1_INTERPRET, UNSIGNED_EEW32_LMUL1_INTERPRET, \ + UNSIGNED_EEW64_LMUL1_INTERPRET, X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, \ + X16_VLMUL_EXT, X32_VLMUL_EXT, X64_VLMUL_EXT, TUPLE_SUBPART) #endif /* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */ @@ -637,6 +637,8 @@ DEF_RVV_OP_TYPE (xu_w) DEF_RVV_OP_TYPE (s) DEF_RVV_OP_TYPE (4x8x4) DEF_RVV_OP_TYPE (2x8x2) +DEF_RVV_OP_TYPE (x_f_qf) +DEF_RVV_OP_TYPE (xu_f_qf) DEF_RVV_PRED_TYPE (ta) DEF_RVV_PRED_TYPE (tu) @@ -672,6 +674,7 @@ DEF_RVV_BASE_TYPE (size, size_type_node) DEF_RVV_BASE_TYPE (ptrdiff, ptrdiff_type_node) DEF_RVV_BASE_TYPE (unsigned_long, long_unsigned_type_node) DEF_RVV_BASE_TYPE (long, long_integer_type_node) +DEF_RVV_BASE_TYPE (signed_eew8_index, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (eew8_index, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (eew16_index, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (eew32_index, get_vector_type (type_idx)) @@ -726,6 +729,8 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x32, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node)) DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx)) +DEF_RVV_BASE_TYPE (quad_trunc_signed_vector, get_vector_type (type_idx)) +DEF_RVV_BASE_TYPE (quad_trunc_unsigned_vector, get_vector_type (type_idx)) DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU) DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE) diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index fec024d9f948..2602f6c2aa16 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -129,6 +129,7 @@ enum required_ext ZVFBFWMA_EXT, /* Zvfbfwma extension */ XSFVQMACCQOQ_EXT, /* XSFVQMACCQOQ extension */ XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */ + XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */ /* Please update below to isa_name func when add or remove enum type(s). */ }; @@ -166,6 +167,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required) return "xsfvqmaccqoq"; case XSFVQMACCDOD_EXT: return "xsfvqmaccdod"; + case XSFVFNRCLIPXFQF_EXT: + return "xsfvfnrclipxfqf"; default: gcc_unreachable (); } @@ -207,6 +210,8 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: return TARGET_XSFVQMACCDOD; + case XSFVFNRCLIPXFQF_EXT: + return TARGET_XSFVFNRCLIPXFQF; default: gcc_unreachable (); } @@ -351,6 +356,8 @@ struct function_group_info return TARGET_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: return TARGET_XSFVQMACCDOD; + case XSFVFNRCLIPXFQF_EXT: + return TARGET_XSFVFNRCLIPXFQF; default: gcc_unreachable (); } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index deab249aea76..4a28aac0d261 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -390,6 +390,7 @@ ;; vsmul vector single-width fractional multiply with rounding and saturation instructions ;; vsshift vector single-width scaling shift instructions ;; vnclip vector narrowing fixed-point clip instructions +;; vfnrclip vector fp32 to int8 ranged clip instructions ;; 13. Vector floating-point instructions ;; vfalu vector single-width floating-point add/subtract instructions ;; vfwalu vector widening floating-point add/subtract instructions @@ -487,7 +488,7 @@ vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax, vimul,vidiv,viwmul,vimuladd,vqmacc,viwmuladd,vimerge,vimov, - vsalu,vaalu,vsmul,vsshift,vnclip, + vsalu,vaalu,vsmul,vsshift,vnclip,vfnrclip, vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp, vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov, vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi, diff --git a/gcc/config/riscv/sifive-vector-builtins-functions.def b/gcc/config/riscv/sifive-vector-builtins-functions.def index 50d54470c4ec..acb62b530203 100644 --- a/gcc/config/riscv/sifive-vector-builtins-functions.def +++ b/gcc/config/riscv/sifive-vector-builtins-functions.def @@ -14,7 +14,11 @@ DEF_RVV_FUNCTION (sf_vqmacc, sf_vqmacc, none_tu_preds, i_qdvv_ops) DEF_RVV_FUNCTION (sf_vqmaccu, sf_vqmacc, none_tu_preds, u_qdvv_ops) DEF_RVV_FUNCTION (sf_vqmaccsu, sf_vqmacc, none_tu_preds, i_su_qdvv_ops) DEF_RVV_FUNCTION (sf_vqmaccus, sf_vqmacc, none_tu_preds, i_us_qdvv_ops) +#undef REQUIRED_EXTENSIONS +#define REQUIRED_EXTENSIONS XSFVFNRCLIPXFQF_EXT +DEF_RVV_FUNCTION (sf_vfnrclip_x_f_qf, sf_vfnrclip, full_preds, i_clip_qf_ops) +DEF_RVV_FUNCTION (sf_vfnrclip_xu_f_qf, sf_vfnrclip, full_preds, u_clip_qf_ops) #undef REQUIRED_EXTENSIONS #undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/sifive-vector.md b/gcc/config/riscv/sifive-vector.md index e572a4a50ba8..e8f168cd2e00 100644 --- a/gcc/config/riscv/sifive-vector.md +++ b/gcc/config/riscv/sifive-vector.md @@ -141,3 +141,23 @@ "sf.vqmaccus.2x8x2\t%0,%3,%4" [(set_attr "type" "vqmacc") (set_attr "mode" "")]) + +(define_insn "@pred_sf_vfnrclip_x_f_qf" + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else: + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec: + [(match_operand:SF 4 "register_operand" " f, f, f, f") + (match_operand:SF_VF 3 "register_operand" " vr, vr, vr, vr")] VFNRCLIP) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR && TARGET_XSFVFNRCLIPXFQF" + "sf.vfnrclip.x.f.qf\t%0,%3,%4%p1" + [(set_attr "type" "vfnrclip") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 850fac1ba22b..de231844c431 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -104,6 +104,8 @@ UNSPEC_WREDUC_SUM_UNORDERED UNSPEC_SELECT_MASK + UNSPEC_SF_VFNRCLIP + UNSPEC_SF_VFNRCLIPU ]) (define_c_enum "unspecv" [ @@ -3902,6 +3904,8 @@ (define_int_iterator VNCLIP [UNSPEC_VNCLIP UNSPEC_VNCLIPU]) +(define_int_iterator VFNRCLIP [UNSPEC_SF_VFNRCLIP UNSPEC_SF_VFNRCLIPU]) + (define_int_iterator VSLIDES [UNSPEC_VSLIDEUP UNSPEC_VSLIDEDOWN]) (define_int_iterator VSLIDES1 [UNSPEC_VSLIDE1UP UNSPEC_VSLIDE1DOWN]) (define_int_iterator VFSLIDES1 [UNSPEC_VFSLIDE1UP UNSPEC_VFSLIDE1DOWN]) @@ -3930,7 +3934,8 @@ (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su") (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u") - (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")]) + (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u") + (UNSPEC_SF_VFNRCLIP "") (UNSPEC_SF_VFNRCLIPU "u")]) (define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd") (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub") (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl") @@ -4788,3 +4793,25 @@ (RVVM2SI "rvvm2qi") (RVVM1SI "rvvm1qi") ]) + +(define_mode_iterator SF_VF [ + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +]) + + +(define_mode_attr SF_XFQF [ + (RVVMF2SF "RVVMF8QI") + (RVVM1SF "RVVMF4QI") + (RVVM2SF "RVVMF2QI") + (RVVM4SF "RVVM1QI") + (RVVM8SF "RVVM2QI") +]) + +(define_mode_attr sf_xfqf [ + (RVVMF2SF "rvvmf8qi") + (RVVM1SF "rvvmf4qi") + (RVVM2SF "rvvmf2qi") + (RVVM4SF "rvvm1qi") + (RVVM8SF "rvvm2qi") +])