top.core

CAPI=2:
#
# Recommended reading about FuseSoC core files: https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html
#
name: ucsbieee::fpga_screensaver:1.0.0
description: screensaver

# This section describes which functional groups each of the source files belong
# to and in what language they're written.
filesets:
  # default
  rtl:
    files:
      - rtl/top.sv
      - rtl/image.sv
      - rtl/video_timer.sv
    file_type: systemVerilogSource

  tb:
    files:
      - tb/top.tb.sv:           {file_type: systemVerilogSource}
      - tb/to_png.py:           {file_type: user, copyto: to_png.py}

  lint:
    files:
      - lint.vlt:               {file_type: vlt}

  usage:
    files:
      - usage/post.tcl:         {file_type: user, copyto: post.tcl}

  tangnano:
    files:
      - tangnano/Gowin_rPLL.v:  {file_type: verilogSource}
      - tangnano/tangnano.sv:   {file_type: systemVerilogSource}
      - tangnano/pins.cst:      {file_type: CST}

# This section defines the different FuseSoC build targets that can be called
# to either simulate (in some way) or synthesize the FPGA design. Each build
# target specifies which files it requires and how to call the tool specific to
# that process.
targets:
  default: &default
    filesets:
      - rtl
    parameters:
      - IMAGE_SELECT=2

  tb: # fusesoc run --target tb ucsbieee::fpga_screensaver
    <<: *default
    description: Simulate the design
    filesets_append:
      - tb
    toplevel: top_tb
    default_tool: icarus
    tools:
      icarus:
        iverilog_options:
          - -g2012
          - -Wall
          - -Wno-timescale
          - -DSIM

  lint: # fusesoc run --target lint ucsbieee::fpga_screensaver
    <<: *default
    description: Simulate the design
    filesets_append:
      - lint
    toplevel: top
    default_tool: verilator
    tools:
      verilator:
        mode: lint-only
        verilator_options: ["-Wall"]

  usage: # fusesoc run --target usage ucsbieee::fpga_screensaver
    <<: *default
    description: Synthesize
    filesets_append:
      - usage
    toplevel: top
    default_tool: yosys
    tools:
      yosys:
        arch: ice40
        output_format: json
    hooks:
      pre_build:
        - convert_to_prep
      post_build:
        - record_usage

  tangnano: # fusesoc run --target tangnano ucsbieee::fpga_screensaver
    <<: *default
    description: Synthesize for Tang Nano
    default_tool: apicula
    filesets_append:
      - tangnano
    tools:
      apicula:
        device: GW1N-LV1QN48C6/I5
    toplevel: tangnano

# This section defines non-Verilog scripts (e.g. shell commands or Python scripts)
# which are used in the above build targets to simulate the PPGA design.
scripts:
  convert_to_prep:
    cmd: [sed, -i, 's/synth_ice40/prep/g', edalize_yosys_procs.tcl]
  record_usage:
    cmd: [yosys, -c, post.tcl]
    filesets: [usage]

# This section defines human-readable descriptions of the command-line parameters
# used in the above guild targets.
parameters:
  IMAGE_SELECT:
    datatype: int
    description: Select which image to use
    paramtype: vlogparam