From 3caa470c0f89be306e5b43c5da4ca9e625abfe6b Mon Sep 17 00:00:00 2001 From: Sidraya Date: Tue, 19 Mar 2024 13:34:33 +0000 Subject: [PATCH] Use Op_VecX instead of Op_RegF Signed-off-by: Sidraya --- src/hotspot/cpu/s390/globals_s390.hpp | 2 +- src/hotspot/cpu/s390/register_s390.hpp | 9 +- src/hotspot/cpu/s390/s390.ad | 309 ++++++-------------- src/hotspot/cpu/s390/sharedRuntime_s390.cpp | 11 +- src/hotspot/cpu/s390/vm_version_s390.cpp | 11 +- src/hotspot/cpu/s390/vmreg_s390.cpp | 3 - src/hotspot/cpu/s390/vmreg_s390.hpp | 21 +- src/hotspot/cpu/s390/vmreg_s390.inline.hpp | 8 +- 8 files changed, 110 insertions(+), 264 deletions(-) diff --git a/src/hotspot/cpu/s390/globals_s390.hpp b/src/hotspot/cpu/s390/globals_s390.hpp index 0c66ef170b4b7..5a07e49792ed9 100644 --- a/src/hotspot/cpu/s390/globals_s390.hpp +++ b/src/hotspot/cpu/s390/globals_s390.hpp @@ -111,7 +111,7 @@ define_pd_global(intx, InitArrayShortSize, 1*BytesPerLong); /* special instructions */ \ product(bool, SuperwordUseVX, false, \ "Use Z15 Vector instructions for superword optimization.") \ - product(bool, UseSFPV, false, \ + product(bool, UseSFPV, false, DIAGNOSTIC, \ "Use SFPV Vector instructions for superword optimization.") \ \ product(bool, PreferLAoverADD, false, DIAGNOSTIC, \ diff --git a/src/hotspot/cpu/s390/register_s390.hpp b/src/hotspot/cpu/s390/register_s390.hpp index 11a5a4b4cf3a0..6a9be67721072 100644 --- a/src/hotspot/cpu/s390/register_s390.hpp +++ b/src/hotspot/cpu/s390/register_s390.hpp @@ -64,7 +64,6 @@ class Register { public: enum { number_of_registers = 16, - max_slots_per_register = 2, number_of_arg_registers = 5 }; @@ -171,7 +170,6 @@ class FloatRegister { public: enum { number_of_registers = 16, - max_slots_per_register = 2, number_of_arg_registers = 4 }; @@ -289,7 +287,6 @@ class VectorRegister { public: enum { number_of_registers = 32, - max_slots_per_register = 4, number_of_arg_registers = 0 }; @@ -387,9 +384,9 @@ constexpr VectorRegister Z_V31 = as_VectorRegister(31); class ConcreteRegisterImpl : public AbstractRegisterImpl { public: enum { - max_gpr = Register::number_of_registers * Register::max_slots_per_register, - max_fpr = max_gpr + FloatRegister::number_of_registers * FloatRegister::max_slots_per_register, - max_vr = max_fpr + VectorRegister::number_of_registers * VectorRegister::max_slots_per_register, + max_gpr = Register::number_of_registers * 2, + max_fpr = max_gpr + FloatRegister::number_of_registers * 2, + max_vr = max_fpr + VectorRegister::number_of_registers, // A big enough number for C2: all the registers plus flags // This number must be large enough to cover REG_COUNT (defined by c2) registers. diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad index 1fad987b57b84..c8065c496bab3 100644 --- a/src/hotspot/cpu/s390/s390.ad +++ b/src/hotspot/cpu/s390/s390.ad @@ -189,165 +189,38 @@ register %{ // Vector Registers // ---------------------------- // 1st 16 VRs are aliases for the FPRs which are already defined above. - reg_def Z_VR0 ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); - reg_def Z_VR0_H ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); - reg_def Z_VR0_J ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); - reg_def Z_VR0_K ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); - - reg_def Z_VR1 ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad()); - reg_def Z_VR1_H ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad()); - reg_def Z_VR1_J ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad()); - reg_def Z_VR1_K ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad()); - - reg_def Z_VR2 ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad()); - reg_def Z_VR2_H ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad()); - reg_def Z_VR2_J ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad()); - reg_def Z_VR2_K ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad()); - - reg_def Z_VR3 ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad()); - reg_def Z_VR3_H ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad()); - reg_def Z_VR3_J ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad()); - reg_def Z_VR3_K ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad()); - - reg_def Z_VR4 ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad()); - reg_def Z_VR4_H ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad()); - reg_def Z_VR4_J ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad()); - reg_def Z_VR4_K ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad()); - - reg_def Z_VR5 ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad()); - reg_def Z_VR5_H ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad()); - reg_def Z_VR5_J ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad()); - reg_def Z_VR5_K ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad()); - - reg_def Z_VR6 ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad()); - reg_def Z_VR6_H ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad()); - reg_def Z_VR6_J ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad()); - reg_def Z_VR6_K ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad()); - - reg_def Z_VR7 ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad()); - reg_def Z_VR7_H ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad()); - reg_def Z_VR7_J ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad()); - reg_def Z_VR7_K ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad()); - - reg_def Z_VR8 ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad()); - reg_def Z_VR8_H ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad()); - reg_def Z_VR8_J ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad()); - reg_def Z_VR8_K ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad()); - - reg_def Z_VR9 ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad()); - reg_def Z_VR9_H ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad()); - reg_def Z_VR9_J ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad()); - reg_def Z_VR9_K ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad()); - - reg_def Z_VR10 ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad()); - reg_def Z_VR10_H ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad()); - reg_def Z_VR10_J ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad()); - reg_def Z_VR10_K ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad()); - - reg_def Z_VR11 ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad()); - reg_def Z_VR11_H ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad()); - reg_def Z_VR11_J ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad()); - reg_def Z_VR11_K ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad()); - - reg_def Z_VR12 ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad()); - reg_def Z_VR12_H ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad()); - reg_def Z_VR12_J ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad()); - reg_def Z_VR12_K ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad()); - - reg_def Z_VR13 ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad()); - reg_def Z_VR13_H ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad()); - reg_def Z_VR13_J ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad()); - reg_def Z_VR13_K ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad()); - - reg_def Z_VR14 ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad()); - reg_def Z_VR14_H ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad()); - reg_def Z_VR14_J ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad()); - reg_def Z_VR14_K ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad()); - - reg_def Z_VR15 ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad()); - reg_def Z_VR15_H ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad()); - reg_def Z_VR15_J ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad()); - reg_def Z_VR15_K ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad()); - - reg_def Z_VR16 ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg() ); - reg_def Z_VR16_H ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next() ); - reg_def Z_VR16_J ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(2) ); - reg_def Z_VR16_K ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(3) ); - - reg_def Z_VR17 ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg() ); - reg_def Z_VR17_H ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next() ); - reg_def Z_VR17_J ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(2) ); - reg_def Z_VR17_K ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(3) ); - - reg_def Z_VR18 ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg() ); - reg_def Z_VR18_H ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next() ); - reg_def Z_VR18_J ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(2) ); - reg_def Z_VR18_K ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(3) ); - - reg_def Z_VR19 ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg() ); - reg_def Z_VR19_H ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next() ); - reg_def Z_VR19_J ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(2) ); - reg_def Z_VR19_K ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(3) ); - - reg_def Z_VR20 ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg() ); - reg_def Z_VR20_H ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next() ); - reg_def Z_VR20_J ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(2) ); - reg_def Z_VR20_K ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(3) ); - - reg_def Z_VR21 ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg() ); - reg_def Z_VR21_H ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next() ); - reg_def Z_VR21_J ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(2) ); - reg_def Z_VR21_K ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(3) ); - - reg_def Z_VR22 ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg() ); - reg_def Z_VR22_H ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next() ); - reg_def Z_VR22_J ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(2) ); - reg_def Z_VR22_K ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(3) ); - - reg_def Z_VR23 ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg() ); - reg_def Z_VR23_H ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next() ); - reg_def Z_VR23_J ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(2) ); - reg_def Z_VR23_K ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(3) ); - - reg_def Z_VR24 ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg() ); - reg_def Z_VR24_H ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next() ); - reg_def Z_VR24_J ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(2) ); - reg_def Z_VR24_K ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(3) ); - - reg_def Z_VR25 ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg() ); - reg_def Z_VR25_H ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next() ); - reg_def Z_VR25_J ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(2) ); - reg_def Z_VR25_K ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(3) ); - - reg_def Z_VR26 ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg() ); - reg_def Z_VR26_H ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next() ); - reg_def Z_VR26_J ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(2) ); - reg_def Z_VR26_K ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(3) ); - - reg_def Z_VR27 ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg() ); - reg_def Z_VR27_H ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next() ); - reg_def Z_VR27_J ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(2) ); - reg_def Z_VR27_K ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(3) ); - - reg_def Z_VR28 ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg() ); - reg_def Z_VR28_H ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next() ); - reg_def Z_VR28_J ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(2) ); - reg_def Z_VR28_K ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(3) ); - - reg_def Z_VR29 ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg() ); - reg_def Z_VR29_H ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next() ); - reg_def Z_VR29_J ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(2) ); - reg_def Z_VR29_K ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(3) ); - - reg_def Z_VR30 ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg() ); - reg_def Z_VR30_H ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next() ); - reg_def Z_VR30_J ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(2) ); - reg_def Z_VR30_K ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(3) ); - - reg_def Z_VR31 ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg() ); - reg_def Z_VR31_H ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next() ); - reg_def Z_VR31_J ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(2) ); - reg_def Z_VR31_K ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(3) ); + reg_def Z_VR0 ( SOC, SOC, Op_VecX, 0, VMRegImpl::Bad()); + reg_def Z_VR1 ( SOC, SOC, Op_VecX, 1, VMRegImpl::Bad()); + reg_def Z_VR2 ( SOC, SOC, Op_VecX, 2, VMRegImpl::Bad()); + reg_def Z_VR3 ( SOC, SOC, Op_VecX, 3, VMRegImpl::Bad()); + reg_def Z_VR4 ( SOC, SOC, Op_VecX, 4, VMRegImpl::Bad()); + reg_def Z_VR5 ( SOC, SOC, Op_VecX, 5, VMRegImpl::Bad()); + reg_def Z_VR6 ( SOC, SOC, Op_VecX, 6, VMRegImpl::Bad()); + reg_def Z_VR7 ( SOC, SOC, Op_VecX, 7, VMRegImpl::Bad()); + reg_def Z_VR8 ( SOC, SOC, Op_VecX, 8, VMRegImpl::Bad()); + reg_def Z_VR9 ( SOC, SOC, Op_VecX, 9, VMRegImpl::Bad()); + reg_def Z_VR10 ( SOC, SOC, Op_VecX, 10, VMRegImpl::Bad()); + reg_def Z_VR11 ( SOC, SOC, Op_VecX, 11, VMRegImpl::Bad()); + reg_def Z_VR12 ( SOC, SOC, Op_VecX, 12, VMRegImpl::Bad()); + reg_def Z_VR13 ( SOC, SOC, Op_VecX, 13, VMRegImpl::Bad()); + reg_def Z_VR14 ( SOC, SOC, Op_VecX, 14, VMRegImpl::Bad()); + reg_def Z_VR15 ( SOC, SOC, Op_VecX, 15, VMRegImpl::Bad()); + reg_def Z_VR16 ( SOC, SOC, Op_VecX, 16, Z_V16->as_VMReg()); + reg_def Z_VR17 ( SOC, SOC, Op_VecX, 17, Z_V17->as_VMReg()); + reg_def Z_VR18 ( SOC, SOC, Op_VecX, 18, Z_V18->as_VMReg()); + reg_def Z_VR19 ( SOC, SOC, Op_VecX, 19, Z_V19->as_VMReg()); + reg_def Z_VR20 ( SOC, SOC, Op_VecX, 20, Z_V20->as_VMReg()); + reg_def Z_VR21 ( SOC, SOC, Op_VecX, 21, Z_V21->as_VMReg()); + reg_def Z_VR22 ( SOC, SOC, Op_VecX, 22, Z_V22->as_VMReg()); + reg_def Z_VR23 ( SOC, SOC, Op_VecX, 23, Z_V23->as_VMReg()); + reg_def Z_VR24 ( SOC, SOC, Op_VecX, 24, Z_V24->as_VMReg()); + reg_def Z_VR25 ( SOC, SOC, Op_VecX, 25, Z_V25->as_VMReg()); + reg_def Z_VR26 ( SOC, SOC, Op_VecX, 26, Z_V26->as_VMReg()); + reg_def Z_VR27 ( SOC, SOC, Op_VecX, 27, Z_V27->as_VMReg()); + reg_def Z_VR28 ( SOC, SOC, Op_VecX, 28, Z_V28->as_VMReg()); + reg_def Z_VR29 ( SOC, SOC, Op_VecX, 29, Z_V29->as_VMReg()); + reg_def Z_VR30 ( SOC, SOC, Op_VecX, 30, Z_V30->as_VMReg()); + reg_def Z_VR31 ( SOC, SOC, Op_VecX, 31, Z_V31->as_VMReg()); // Special Registers @@ -433,38 +306,38 @@ alloc_class chunk1( ); alloc_class chunk2( - Z_VR0, Z_VR0_H, Z_VR0_J, Z_VR0_K, - Z_VR1, Z_VR1_H, Z_VR1_J, Z_VR1_K, - Z_VR2, Z_VR2_H, Z_VR2_J, Z_VR2_K, - Z_VR3, Z_VR3_H, Z_VR3_J, Z_VR3_K, - Z_VR4, Z_VR4_H, Z_VR4_J, Z_VR4_K, - Z_VR5, Z_VR5_H, Z_VR5_J, Z_VR5_K, - Z_VR6, Z_VR6_H, Z_VR6_J, Z_VR6_K, - Z_VR7, Z_VR7_H, Z_VR7_J, Z_VR7_K, - Z_VR8, Z_VR8_H, Z_VR8_J, Z_VR8_K, - Z_VR9, Z_VR9_H, Z_VR9_J, Z_VR9_K, - Z_VR10, Z_VR10_H, Z_VR10_J, Z_VR10_K, - Z_VR11, Z_VR11_H, Z_VR11_J, Z_VR11_K, - Z_VR12, Z_VR12_H, Z_VR12_J, Z_VR12_K, - Z_VR13, Z_VR13_H, Z_VR13_J, Z_VR13_K, - Z_VR14, Z_VR14_H, Z_VR14_J, Z_VR14_K, - Z_VR15, Z_VR15_H, Z_VR15_J, Z_VR15_K, - Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K, - Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K, - Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K, - Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K, - Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K, - Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K, - Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K, - Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K, - Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K, - Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K, - Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K, - Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K, - Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K, - Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K, - Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K, - Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K, + Z_VR0, + Z_VR1, + Z_VR2, + Z_VR3, + Z_VR4, + Z_VR5, + Z_VR6, + Z_VR7, + Z_VR8, + Z_VR9, + Z_VR10, + Z_VR11, + Z_VR12, + Z_VR13, + Z_VR14, + Z_VR15, + Z_VR16, + Z_VR17, + Z_VR18, + Z_VR19, + Z_VR20, + Z_VR21, + Z_VR22, + Z_VR23, + Z_VR24, + Z_VR25, + Z_VR26, + Z_VR27, + Z_VR28, + Z_VR29, + Z_VR30, + Z_VR31 ); alloc_class chunk3( @@ -743,22 +616,22 @@ reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); reg_class z_v_reg( // Attention: Only these ones are saved & restored at safepoint by RegisterSaver. //1st 16 VRs overlaps with 1st 16 FPRs. - Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K, - Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K, - Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K, - Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K, - Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K, - Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K, - Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K, - Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K, - Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K, - Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K, - Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K, - Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K, - Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K, - Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K, - Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K, - Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K, + Z_VR16, + Z_VR17, + Z_VR18, + Z_VR19, + Z_VR20, + Z_VR21, + Z_VR22, + Z_VR23, + Z_VR24, + Z_VR25, + Z_VR26, + Z_VR27, + Z_VR28, + Z_VR29, + Z_VR30, + Z_VR31 ); %} @@ -1206,12 +1079,12 @@ static enum RC rc_class(OptoReg::Name reg) { } // we have 32 vector register * 4 halves - if (reg < 32+32+128) { + if (reg < 32+32+32) { return rc_vector; } // Between float regs & stack are the flags regs. - assert(OptoReg::is_stack(reg) || reg < 64+64+128, "blow up if spilling flags"); + assert(OptoReg::is_stack(reg) || reg < 32+32+32, "blow up if spilling flags"); return rc_stack; } @@ -1285,28 +1158,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo const char *mnemo = nullptr; unsigned long opc = 0; - if (bottom_type()->isa_vect() != NULL && ideal_reg() == Op_VecX) { - if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { + if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) { + if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { if (cbuf) { C2_MacroAssembler _masm(cbuf); __ z_mvc(Address(Z_SP, 0, dst_offset), Address(Z_SP, 0, src_offset), 16); - } + } size += 6; - } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) { + } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) { VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]); if (cbuf) { C2_MacroAssembler _masm(cbuf); __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset)); } size += 6; - } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) { + } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) { VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]); if (cbuf) { C2_MacroAssembler _masm(cbuf); __ z_vl(Rdst, Address(Z_SP, 0, src_offset)); } size += 6; - } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) { + } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) { VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]); VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]); if (cbuf) { @@ -1314,9 +1187,9 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo __ z_vlr(Rdst, Rsrc); } size += 6; - } else { - ShouldNotReachHere(); - } + } else { + ShouldNotReachHere(); + } return size; } diff --git a/src/hotspot/cpu/s390/sharedRuntime_s390.cpp b/src/hotspot/cpu/s390/sharedRuntime_s390.cpp index b7642e7154e2b..9a7f117d77b15 100644 --- a/src/hotspot/cpu/s390/sharedRuntime_s390.cpp +++ b/src/hotspot/cpu/s390/sharedRuntime_s390.cpp @@ -414,18 +414,10 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, RegisterSet reg for (int i = 0; i < vregstosave_num; i++) { int reg_num = RegisterSaver_LiveVRegs[i].reg_num; - //int reg_type = RegisterSaver_LiveVRegs[i].reg_type; __ z_vst(as_VectorRegister(reg_num), Address(Z_SP, offset)); - map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), - RegisterSaver_LiveVRegs[i].vmreg); - map->set_callee_saved(VMRegImpl::stack2reg((offset + half_reg_size ) >> 2), - RegisterSaver_LiveVRegs[i].vmreg->next()); - map->set_callee_saved(VMRegImpl::stack2reg((offset + (half_reg_size * 2)) >> 2), - RegisterSaver_LiveVRegs[i].vmreg->next(2)); - map->set_callee_saved(VMRegImpl::stack2reg((offset + (half_reg_size * 3)) >> 2), - RegisterSaver_LiveVRegs[i].vmreg->next(3)); + map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), RegisterSaver_LiveVRegs[i].vmreg); offset += v_reg_size; } @@ -578,7 +570,6 @@ void RegisterSaver::restore_live_registers(MacroAssembler* masm, RegisterSet reg for (int i = 0; i < vregstosave_num; i++) { int reg_num = RegisterSaver_LiveVRegs[i].reg_num; - //int reg_type = RegisterSaver_LiveVRegs[i].reg_type; __ z_vl(as_VectorRegister(reg_num), Address(Z_SP, offset)); diff --git a/src/hotspot/cpu/s390/vm_version_s390.cpp b/src/hotspot/cpu/s390/vm_version_s390.cpp index 010802f6df604..d02c12f3cd347 100644 --- a/src/hotspot/cpu/s390/vm_version_s390.cpp +++ b/src/hotspot/cpu/s390/vm_version_s390.cpp @@ -98,19 +98,20 @@ void VM_Version::initialize() { #ifdef COMPILER2 int model_ix = get_model_index(); + if ( model_ix >= 7 ) { if (FLAG_IS_DEFAULT(SuperwordUseVX)) { FLAG_SET_ERGO(SuperwordUseVX, true); } if (model_ix > 7 && FLAG_IS_DEFAULT(UseSFPV) && SuperwordUseVX) { - FLAG_SET_ERGO(UseSFPV, true); + FLAG_SET_ERGO(UseSFPV, true); } else if (model_ix == 7 && UseSFPV) { - warning("UseSFPV specified, but needs at least Z14."); - FLAG_SET_DEFAULT(UseSFPV, false); + warning("UseSFPV specified, but needs at least Z14."); + FLAG_SET_DEFAULT(UseSFPV, false); } } else if (SuperwordUseVX) { - warning("SuperwordUseVX specified, but needs at least Z13."); - FLAG_SET_DEFAULT(SuperwordUseVX, false); + warning("SuperwordUseVX specified, but needs at least Z13."); + FLAG_SET_DEFAULT(SuperwordUseVX, false); } MaxVectorSize = SuperwordUseVX ? 16 : 8; #endif diff --git a/src/hotspot/cpu/s390/vmreg_s390.cpp b/src/hotspot/cpu/s390/vmreg_s390.cpp index 5bec8313a48c4..2240e27e19c17 100644 --- a/src/hotspot/cpu/s390/vmreg_s390.cpp +++ b/src/hotspot/cpu/s390/vmreg_s390.cpp @@ -46,9 +46,6 @@ void VMRegImpl::set_regName() { VectorRegister vreg = ::as_VectorRegister(0); for (; i < ConcreteRegisterImpl::max_vr;) { - regName[i++] = vreg->name(); - regName[i++] = vreg->name(); - regName[i++] = vreg->name(); regName[i++] = vreg->name(); vreg = vreg->successor(); } diff --git a/src/hotspot/cpu/s390/vmreg_s390.hpp b/src/hotspot/cpu/s390/vmreg_s390.hpp index 96acb725e9b44..75b9e0cb6f2a4 100644 --- a/src/hotspot/cpu/s390/vmreg_s390.hpp +++ b/src/hotspot/cpu/s390/vmreg_s390.hpp @@ -42,33 +42,22 @@ inline bool is_VectorRegister() { inline Register as_Register() { assert(is_Register() && is_even(value()), "even-aligned GPR name"); - return ::as_Register(value() / Register::max_slots_per_register); + return ::as_Register(value() >> 1); } inline FloatRegister as_FloatRegister() { assert(is_FloatRegister() && is_even(value()), "must be"); - return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) - / FloatRegister::max_slots_per_register); + return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); } inline VectorRegister as_VectorRegister() { - assert(is_VectorRegister() - && (value() % VectorRegister::max_slots_per_register == 0), "must be"); - return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr) - / VectorRegister::max_slots_per_register); + assert(is_VectorRegister(), "must be"); + return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr)); } inline bool is_concrete() { assert(is_reg(), "must be"); - if (is_FloatRegister()) { - int base = value() - ConcreteRegisterImpl::max_gpr; - return (base % FloatRegister::max_slots_per_register) == 0; - } else if (is_VectorRegister()) { - int base = value() - ConcreteRegisterImpl::max_fpr; - return (base % VectorRegister::max_slots_per_register) == 0; - } else { - return is_even(value()); - } + return is_even(value()); } #endif // CPU_S390_VMREG_S390_HPP diff --git a/src/hotspot/cpu/s390/vmreg_s390.inline.hpp b/src/hotspot/cpu/s390/vmreg_s390.inline.hpp index 22a55befcf31e..9cf20687dd976 100644 --- a/src/hotspot/cpu/s390/vmreg_s390.inline.hpp +++ b/src/hotspot/cpu/s390/vmreg_s390.inline.hpp @@ -27,17 +27,15 @@ #define CPU_S390_VMREG_S390_INLINE_HPP inline VMReg Register::as_VMReg() const { - return VMRegImpl::as_VMReg(encoding() * Register::max_slots_per_register); + return VMRegImpl::as_VMReg(encoding() << 1); } inline VMReg FloatRegister::as_VMReg() const { - return VMRegImpl::as_VMReg((encoding() * FloatRegister::max_slots_per_register) + - ConcreteRegisterImpl::max_gpr); + return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); } inline VMReg VectorRegister::as_VMReg() const { - return VMRegImpl::as_VMReg((encoding() * VectorRegister::max_slots_per_register) + - ConcreteRegisterImpl::max_fpr); + return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_fpr); } inline VMReg ConditionRegister::as_VMReg() const {