Why RoCC accelerator requires physical address when accessing L1D cache?

[allencho1222]

I was hacking the source code of Rocket SoC, and found that Rocket uses virtual address when having access to L1D cache(from the source code of nonblocking cache code).

But, from the following code:

As far as I know, the interface between L1D cache and Accelerator(co-processor) is same as the interface between core and L1D cache.

L1D cache accepts virtual address because it is virtually indexed and physically tagged. So, accelerator also has to use virtual address.

If L1D cache accepts physical address, the indexing of TLB will use physical address, which is non-sesnse.

The core uses virtual address in the 'store' and the 'load' instruction. But, why the virtual address needs to be translated into physical address before the accelerator accesses L1D cache?

[seldridge]

This was never actually clear to me and I would need to read some code and/or do some experiments to figure out what is going on here. My original understanding of this is that RoCC should be dealing with virtual memory addresses and passing those exclusively (though that conflicts with how the pk code here is working).

I hesitant to speculate on what is going on here... I'll try and get some more data as time allows.