Pipeline AES

[Yzgll]

Hello, Professor Sun. I would like to implement pipelined AES on MGPUSim, but everything is quite chaotic right now, and I’m not sure where to start. Could you give me some advice?

[syifan]

Do you know how to implement the program in CUDA? Basically, you need several streams (equal to the number of stages). At the beginning of each round, you inject tasks into the streams. Then you can drain all the streams so that all the tasks are executed.

This is similar to the code here. https://github.com/sarchlab/mgpusim/blob/v3/benchmarks/heteromark/fir/fir.go#L132

Can you check the code and see if it helps?

[Yzgll]

My plan is to map the four key stages of AES to four GPUs, with each GPU executing one stage. When GPU1 finishes the first stage for data block 1, it passes the data to GPU2 for the second stage. While GPU2 is processing the second stage of data block 1, GPU1 is working on the first stage of data block 2, and so on. This is the pipeline I want to design. So, I wrote the four AES stages as kernel functions in kernels.cl and used loadProgram to load them. I also designed four CommandQueue instances to manage each GPU and submit the corresponding stage's tasks to the appropriate GPU. However, this approach seems to merely assign different stages to different GPUs in sequence, rather than truly achieving pipelining. What should I do to implement a real pipeline?

[syifan]

OK. This is harder than what I was expecting. I think true pipelining means that the kernel can accept another kernel's input while it is running, right? This is very difficult as GPUs do not have good enough memory coherency control. You need to consider how one GPU can notify another GPU that a chunk of data is processed and how the other GPU can wait for the signal. Can you describe how would you want to design GPUs that can achieve this goal?

[Yzgll]

The pipeline I want to design looks like this

[syifan]

Yes. I understand this. My question is, how does GPU 1 know that the SubBytes part of GPU1 is completed? Two options,

1. Each block on each GPU is a kernel.
2. You can use a spinlock on each GPU. Do you have the OpenCL kernel that uses a spinlock to synchronize?

There may be better solutions, but it may require some architecture modifications.