Model-Based V&V Concept using SystemVerilog and Cocotb

Experimentation of the "cocotb" (coroutine cosimulation test bench) approach using SystemVerilog for the design of a D Flip-Flop and Python for its test bench. The main goal is to test the time constraints described in the D Flip-Flop 74HC74 datasheet. The verification and validation of the modelled system is done on the basis of assertions written in Python in the test bench.

Author

Sami Föry