forked from lwfinger/rtw89
-
Notifications
You must be signed in to change notification settings - Fork 0
/
rtw8852a_rfk.c
3911 lines (3329 loc) · 122 KB
/
rtw8852a_rfk.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "coex.h"
#include "debug.h"
#include "mac.h"
#include "phy.h"
#include "reg.h"
#include "rtw8852a.h"
#include "rtw8852a_rfk.h"
#include "rtw8852a_rfk_table.h"
#include "rtw8852a_table.h"
static void
_rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{
rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
}
static void
_rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{
rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
}
static void
_rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{
rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
}
static void
_rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{
rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
}
static void
_rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{
udelay(def->data);
}
static void
(*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
[RTW89_RFK_F_WRF] = _rfk_write_rf,
[RTW89_RFK_F_WM] = _rfk_write32_mask,
[RTW89_RFK_F_WS] = _rfk_write32_set,
[RTW89_RFK_F_WC] = _rfk_write32_clr,
[RTW89_RFK_F_DELAY] = _rfk_delay,
};
static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
static void
rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
{
const struct rtw89_reg5_def *p = tbl->defs;
const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
for (; p < end; p++)
_rfk_handler[p->flag](rtwdev, p);
}
#define rtw89_rfk_parser_by_cond(rtwdev, cond, tbl_t, tbl_f) \
do { \
typeof(rtwdev) _dev = (rtwdev); \
if (cond) \
rtw89_rfk_parser(_dev, (tbl_t)); \
else \
rtw89_rfk_parser(_dev, (tbl_f)); \
} while (0)
static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n",
rtwdev->dbcc_en, phy_idx);
if (!rtwdev->dbcc_en)
return RF_AB;
if (phy_idx == RTW89_PHY_0)
return RF_A;
else
return RF_B;
}
static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852a_backup_bb_regs)
#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852a_backup_rf_regs)
static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
{
u32 i;
for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
backup_bb_reg_val[i] =
rtw89_phy_read32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]backup bb reg : %x, value =%x\n",
rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
}
}
static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
u8 rf_path)
{
u32 i;
for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
backup_rf_reg_val[i] =
rtw89_read_rf(rtwdev, rf_path,
rtw8852a_backup_rf_regs[i], RFREG_MASK);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]backup rf S%d reg : %x, value =%x\n", rf_path,
rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
}
}
static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
u32 backup_bb_reg_val[])
{
u32 i;
for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
rtw89_phy_write32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
MASKDWORD, backup_bb_reg_val[i]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]restore bb reg : %x, value =%x\n",
rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
}
}
static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
u32 backup_rf_reg_val[], u8 rf_path)
{
u32 i;
for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
rtw89_write_rf(rtwdev, rf_path, rtw8852a_backup_rf_regs[i],
RFREG_MASK, backup_rf_reg_val[i]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]restore rf S%d reg: %x, value =%x\n", rf_path,
rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
}
}
static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
{
u8 path;
u32 rf_mode;
int ret;
for (path = 0; path < RF_PATH_MAX; path++) {
if (!(kpath & BIT(path)))
continue;
ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2, 5000, false, rtwdev, path, 0x00,
RR_MOD_MASK);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
path, ret);
}
}
static void _dack_dump(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
u8 t;
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[0][0], dack->addck_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[1][0], dack->addck_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[0][0], dack->dadck_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[1][0], dack->dadck_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[0][0], dack->biask_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[1][0], dack->biask_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[0][0][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[0][1][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[1][0][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[1][1][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
}
static void _afe_init(struct rtw89_dev *rtwdev)
{
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_afe_init_defs_tbl);
}
static void _addck_backup(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
rtw89_phy_write32_clr(rtwdev, R_S0_RXDC2, B_S0_RXDC2_SEL);
dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
B_S0_ADDCK_Q);
dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
B_S0_ADDCK_I);
rtw89_phy_write32_clr(rtwdev, R_S1_RXDC2, B_S1_RXDC2_SEL);
dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
B_S1_ADDCK_Q);
dack->addck_d[1][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
B_S1_ADDCK_I);
}
static void _addck_reload(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]);
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2, B_S0_RXDC2_Q2,
(dack->addck_d[0][1] >> 6));
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_Q,
(dack->addck_d[0][1] & 0x3f));
rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN);
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]);
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC2, B_S1_RXDC2_Q2,
(dack->addck_d[1][1] >> 6));
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_Q,
(dack->addck_d[1][1] & 0x3f));
rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN);
}
static void _dack_backup_s0(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
rtw89_phy_write32_mask(rtwdev, R_S0_DACKI, B_S0_DACKI_AR, i);
dack->msbk_d[0][0][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI7, B_S0_DACKI7_K);
rtw89_phy_write32_mask(rtwdev, R_S0_DACKQ, B_S0_DACKQ_AR, i);
dack->msbk_d[0][1][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ7, B_S0_DACKQ7_K);
}
dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2,
B_S0_DACKI2_K);
dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2,
B_S0_DACKQ2_K);
dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8,
B_S0_DACKI8_K) - 8;
dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8,
B_S0_DACKQ8_K) - 8;
}
static void _dack_backup_s1(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
rtw89_phy_write32_mask(rtwdev, R_S1_DACKI, B_S1_DACKI_AR, i);
dack->msbk_d[1][0][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI7, B_S1_DACKI_K);
rtw89_phy_write32_mask(rtwdev, R_S1_DACKQ, B_S1_DACKQ_AR, i);
dack->msbk_d[1][1][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ7, B_S1_DACKQ7_K);
}
dack->biask_d[1][0] =
(u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI2, B_S1_DACKI2_K);
dack->biask_d[1][1] =
(u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ2, B_S1_DACKQ2_K);
dack->dadck_d[1][0] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI8, B_S1_DACKI8_K) - 8;
dack->dadck_d[1][1] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ8, B_S1_DACKQ8_K) - 8;
}
static void _dack_reload_by_path(struct rtw89_dev *rtwdev,
enum rtw89_rf_path path, u8 index)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 tmp = 0, tmp_offset, tmp_reg;
u8 i;
u32 idx_offset, path_offset;
if (index == 0)
idx_offset = 0;
else
idx_offset = 0x50;
if (path == RF_PATH_A)
path_offset = 0;
else
path_offset = 0x2000;
tmp_offset = idx_offset + path_offset;
/* msbk_d: 15/14/13/12 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
tmp_reg = 0x5e14 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 11/10/9/8 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
tmp_reg = 0x5e18 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 7/6/5/4 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
tmp_reg = 0x5e1c + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 3/2/1/0 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i] << (i * 8);
tmp_reg = 0x5e20 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* dadak_d/biask_d */
tmp = 0x0;
tmp = (dack->biask_d[path][index] << 22) |
(dack->dadck_d[path][index] << 14);
tmp_reg = 0x5e24 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
}
static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
u8 i;
for (i = 0; i < 2; i++)
_dack_reload_by_path(rtwdev, path, i);
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_dack_reload_defs_a_tbl,
&rtw8852a_rfk_dack_reload_defs_b_tbl);
}
#define ADDC_T_AVG 100
static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
s32 dc_re = 0, dc_im = 0;
u32 tmp;
u32 i;
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_addc_defs_a_tbl,
&rtw8852a_rfk_check_addc_defs_b_tbl);
for (i = 0; i < ADDC_T_AVG; i++) {
tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
}
dc_re /= ADDC_T_AVG;
dc_im /= ADDC_T_AVG;
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
}
static void _addck(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
/* S0 */
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_a_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
_check_addc(rtwdev, RF_PATH_A);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x1e00, BIT(0));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
dack->addck_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
_check_addc(rtwdev, RF_PATH_A);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_a_tbl);
/* S1 */
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_b_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
_check_addc(rtwdev, RF_PATH_B);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x3e00, BIT(0));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
dack->addck_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
_check_addc(rtwdev, RF_PATH_B);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_b_tbl);
}
static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_dadc_defs_f_a_tbl,
&rtw8852a_rfk_check_dadc_defs_f_b_tbl);
_check_addc(rtwdev, path);
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_dadc_defs_r_a_tbl,
&rtw8852a_rfk_check_dadc_defs_r_b_tbl);
}
static void _dack_s0(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e28, BIT(15));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e78, BIT(15));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
dack->msbk_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e48, BIT(17));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e98, BIT(17));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADACK timeout\n");
dack->dadck_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_a_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
_check_dadc(rtwdev, RF_PATH_A);
_dack_backup_s0(rtwdev);
_dack_reload(rtwdev, RF_PATH_A);
rtw89_phy_write32_clr(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
}
static void _dack_s1(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e28, BIT(15));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e78, BIT(15));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
dack->msbk_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e48, BIT(17));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e98, BIT(17));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
dack->dadck_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_b_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
_check_dadc(rtwdev, RF_PATH_B);
_dack_backup_s1(rtwdev);
_dack_reload(rtwdev, RF_PATH_B);
rtw89_phy_write32_clr(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
}
static void _dack(struct rtw89_dev *rtwdev)
{
_dack_s0(rtwdev);
_dack_s1(rtwdev);
}
static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 rf0_0, rf1_0;
u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB);
dack->dack_done = false;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n");
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
_afe_init(rtwdev);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
_addck(rtwdev);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
_addck_backup(rtwdev);
_addck_reload(rtwdev);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
_dack(rtwdev);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
_dack_dump(rtwdev);
dack->dack_done = true;
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
dack->dack_cnt++;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
}
#define RTW8852A_NCTL_VER 0xd
#define RTW8852A_IQK_VER 0x2a
#define RTW8852A_IQK_SS 2
#define RTW8852A_IQK_THR_REK 8
#define RTW8852A_IQK_CFIR_GROUP_NR 4
enum rtw8852a_iqk_type {
ID_TXAGC,
ID_FLOK_COARSE,
ID_FLOK_FINE,
ID_TXK,
ID_RXAGC,
ID_RXK,
ID_NBTXK,
ID_NBRXK,
};
static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path)
{
u8 i = 0x0;
u32 fft[6] = {0x0};
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000);
fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000);
fft[1] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000);
fft[2] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000);
fft[3] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000);
fft[4] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000);
fft[5] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
for (i = 0; i < 6; i++)
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x,fft[%x]= %x\n",
path, i, fft[i]);
}
static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path)
{
u8 i = 0x0;
u32 tmp = 0x0;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1);
for (i = 0x0; i < 0x18; i++) {
rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N2, MASKDWORD);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n",
path, BIT(path), tmp);
udelay(1);
}
rtw89_phy_write32_clr(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX);
rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100);
udelay(1);
}
static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
u8 group)
{
static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
{0x8f20, 0x8f54, 0x8f88, 0x8fbc},
{0x9320, 0x9354, 0x9388, 0x93bc},
};
u8 idx = 0x0;
u32 tmp = 0x0;
u32 base_addr;
if (path >= RTW8852A_IQK_SS) {
rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
return;
}
if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
return;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
base_addr = base_addrs[path][group];
for (idx = 0; idx < 0x0d; idx++) {
tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK] %x = %x\n",
base_addr + (idx << 2), tmp);
}
if (path == 0x0) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp);
} else {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc);
udelay(1);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
BIT(path), tmp);
}
static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
u8 group)
{
static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
{0x8d00, 0x8d44, 0x8d88, 0x8dcc},
{0x9100, 0x9144, 0x9188, 0x91cc},
};
u8 idx = 0x0;
u32 tmp = 0x0;
u32 base_addr;
if (path >= RTW8852A_IQK_SS) {
rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
return;
}
if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
return;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
base_addr = base_addrs[path][group];
for (idx = 0; idx < 0x10; idx++) {
tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]%x = %x\n",
base_addr + (idx << 2), tmp);
}
if (path == 0x0) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp);
} else {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
BIT(path), tmp);
}
static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
{
u32 tmp = 0x0;
u32 i = 0x0;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
for (i = 0; i <= 0x9f; i++) {
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
}
for (i = 0; i <= 0x9f; i++) {
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX2, MASKDWORD);
rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX, MASKDWORD);
}
static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
u32 tmp = 0x0;
rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5);
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
break;
default:
break;
}
tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
fsleep_alt(128);
}
static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
{
u32 tmp;
u32 val;
int ret;
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200,
false, rtwdev, 0xbff8, MASKBYTE0);
if (ret)
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n");
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
return false;
}
static bool _iqk_one_shot(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 path, u8 ktype)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
bool fail = false;
u32 iqk_cmd = 0x0;
u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path);
u32 addr_rfc_ctl = 0x0;
if (path == RF_PATH_A)
addr_rfc_ctl = 0x5864;
else
addr_rfc_ctl = 0x7864;
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
switch (ktype) {
case ID_TXAGC:
iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
break;
case ID_FLOK_COARSE:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
iqk_cmd = 0x108 | (1 << (4 + path));
break;
case ID_FLOK_FINE:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
iqk_cmd = 0x208 | (1 << (4 + path));
break;
case ID_TXK:
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
iqk_cmd = 0x008 | (1 << (path + 4)) |
(((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
break;
case ID_RXAGC:
iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
break;
case ID_RXK:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
iqk_cmd = 0x008 | (1 << (path + 4)) |
(((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
break;
case ID_NBTXK:
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
iqk_cmd = 0x308 | (1 << (4 + path));
break;
case ID_NBRXK:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
iqk_cmd = 0x608 | (1 << (4 + path));
break;
default:
return false;
}
rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
udelay(1);
fail = _iqk_check_cal(rtwdev, path, ktype);
if (iqk_info->iqk_xym_en)
_iqk_read_xym_dbcc0(rtwdev, path);
if (iqk_info->iqk_fft_en)
_iqk_read_fft_dbcc0(rtwdev, path);
if (iqk_info->iqk_sram_en)
_iqk_sram(rtwdev, path);
if (iqk_info->iqk_cfir_en) {
if (ktype == ID_TXK) {
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x0);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x1);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x2);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x3);
} else {
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3);
}
}
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
return fail;
}
static bool _rxk_group_sel(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 path)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0};
static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30};
static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1};
static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0};
static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a};
static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0};
u8 gp = 0x0;
bool fail = false;
u32 rf0 = 0x0;
for (gp = 0; gp < 0x4; gp++) {
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]);
break;
default:
break;
}
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI,
rf0 | iqk_info->syn1to2);
rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
}
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);