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DefFindSetLeftBit
1 parent 4b077d6 commit 41fe478Copy full SHA for 41fe478
src/aml/mod.rs
@@ -1378,11 +1378,14 @@ where
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0
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} else {
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/*
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- * TODO: this is a particular instance where not respecting integers being
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- * 32-bit on revision 1 tables does cause properly incorrect behaviour...
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- * TODO: we can fix this now we have the DSDT revision
+ * This is a particularly important place to respect the integer width as set
+ * by the DSDT revision.
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*/
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- (operand.leading_zeros() + 1) as u64
+ if self.dsdt_revision >= 2 {
+ (operand.leading_zeros() + 1) as u64
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+ } else {
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+ ((operand as u32).leading_zeros() + 1) as u64
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+ }
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}
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Opcode::FindSetRightBit => {
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