Add riscv32 CI run

Author: sayantn

.github/workflows/main.yml

@@ -58,6 +58,8 @@ jobs:
           os: ubuntu-latest
         - tuple: aarch64_be-unknown-linux-gnu
           os: ubuntu-latest
+        - tuple: riscv32gc-unknown-linux-gnu
+          os: ubuntu-latest
         - tuple: riscv64gc-unknown-linux-gnu
           os: ubuntu-latest
         - tuple: powerpc-unknown-linux-gnu
@@ -155,6 +157,11 @@ jobs:
             os: ubuntu-latest
           disable_assert_instr: true
           test_everything: true
+        - target:
+            tuple: riscv32gc-unknown-linux-gnu
+            os: ubuntu-latest
+          test_everything: true
+          build_std: true
         - target:
             tuple: riscv64gc-unknown-linux-gnu
             os: ubuntu-latest

ci/docker/riscv32gc-unknown-linux-gnu/Dockerfile

@@ -0,0 +1,17 @@
+FROM ubuntu:25.04
+
+RUN apt-get update && apt-get install -y --no-install-recommends \
+        gcc libc6-dev qemu-user ca-certificates \
+        wget xz-utils make file llvm
+
+ENV VERSION=2025.01.20
+
+RUN wget "https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${VERSION}/riscv32-glibc-ubuntu-24.04-gcc-nightly-${VERSION}-nightly.tar.xz" \
+    -O riscv-toolchain.tar.xz
+RUN tar -xJf riscv-toolchain.tar.xz
+
+ENV CARGO_TARGET_RISCV32GC_UNKNOWN_LINUX_GNU_LINKER=/riscv/bin/riscv32-unknown-linux-gnu-gcc \
+    CARGO_TARGET_RISCV32GC_UNKNOWN_LINUX_GNU_RUNNER="qemu-riscv32 -cpu max -L /riscv/sysroot" \
+    OBJDUMP=llvm-objdump
+
+ENV CARGO_UNSTABLE_BUILD_STD=std

crates/stdarch-test/src/disassembly.rs

@@ -77,7 +77,7 @@ pub(crate) fn disassemble_myself() -> HashSet<Function> {
     let add_args = if cfg!(target_vendor = "apple") && cfg!(target_arch = "aarch64") {
         // Target features need to be enabled for LLVM objdump on Darwin ARM64
         vec!["--mattr=+v8.6a,+crypto,+tme"]
-    } else if cfg!(target_arch = "riscv64") {
+    } else if cfg!(any(target_arch = "riscv32", target_arch = "riscv64")) {
         vec!["--mattr=+zk,+zks,+zbc,+zbb"]
     } else {
         vec![]