Extend the tests

Author: lu-zero

coresimd/powerpc/altivec.rs

@@ -750,18 +750,93 @@ mod tests {
     use simd::*;
     use stdsimd_test::simd_test;
 
-    #[simd_test(enable = "altivec")]
-    unsafe fn vec_perm_u16x8() {
-        let a: vector_signed_short = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7).into_bits();
-        let b = u16x8::new(10, 11, 12, 13, 14, 15, 16, 17).into_bits();
-
-        let c = u8x16::new(0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
-                           0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17).into_bits();
-        let d = u16x8::new(0, 10, 1, 11, 2, 12, 3, 13);
-
-        assert_eq!(d, vec_perm(a, b, c).into_bits());
+    macro_rules! test_vec_perm {
+        {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
+            #[simd_test(enable = "altivec")]
+            unsafe fn $name() {
+                let a: $longtype = $shorttype::new($($a),+).into_bits();
+                let b = $shorttype::new($($b),+).into_bits();
+                let c = u8x16::new($($c),+).into_bits();
+                let d = $shorttype::new($($d),+);
+
+                assert_eq!(d, vec_perm(a, b, c).into_bits());
+            }
+        }
     }
 
+    test_vec_perm!{test_vec_perm_u8x16,
+                   u8x16, vector_unsigned_char,
+                   [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                   [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
+    test_vec_perm!{test_vec_perm_i8x16,
+                   i8x16, vector_signed_char,
+                   [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                   [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
+    test_vec_perm!{test_vec_perm_m8x16,
+                   m8x16, vector_bool_char,
+                   [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false],
+                   [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [false, false, true, true, false, false, true, true, false, false, true, true, false, false, true, true]}
+
+    test_vec_perm!{test_vec_perm_u16x8,
+                   u16x8, vector_unsigned_short,
+                   [0, 1, 2, 3, 4, 5, 6, 7],
+                   [10, 11, 12, 13, 14, 15, 16, 17],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [0, 10, 1, 11, 2, 12, 3, 13]}
+    test_vec_perm!{test_vec_perm_i16x8,
+                   i16x8, vector_signed_short,
+                   [0, 1, 2, 3, 4, 5, 6, 7],
+                   [10, 11, 12, 13, 14, 15, 16, 17],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [0, 10, 1, 11, 2, 12, 3, 13]}
+    test_vec_perm!{test_vec_perm_m16x8,
+                   m16x8, vector_bool_short,
+                   [false, false, false, false, false, false, false, false],
+                   [true, true, true, true, true, true, true, true],
+                   [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+                    0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+                   [false, true, false, true, false, true, false, true]}
+
+    test_vec_perm!{test_vec_perm_u32x4,
+                   u32x4, vector_unsigned_int,
+                   [0, 1, 2, 3],
+                   [10, 11, 12, 13],
+                   [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+                    0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+                   [0, 10, 1, 11]}
+    test_vec_perm!{test_vec_perm_i32x4,
+                   i32x4, vector_signed_int,
+                   [0, 1, 2, 3],
+                   [10, 11, 12, 13],
+                   [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+                    0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+                   [0, 10, 1, 11]}
+    test_vec_perm!{test_vec_perm_m32x4,
+                   m32x4, vector_bool_int,
+                   [false, false, false, false],
+                   [true, true, true, true],
+                   [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+                    0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+                   [false, true, false, true]}
+    test_vec_perm!{test_vec_perm_f32x4,
+                   f32x4, vector_float,
+                   [0.0, 1.0, 2.0, 3.0],
+                   [1.0, 1.1, 1.2, 1.3],
+                   [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+                    0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+                   [0.0, 1.0, 1.0, 1.1]}
+
     #[simd_test(enable = "altivec")]
     unsafe fn vec_add_i32x4_i32x4() {
         let x = i32x4::new(1, 2, 3, 4);