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| 1 | +# Changelog |
| 2 | + |
| 3 | +## [Unreleased] |
| 4 | + |
| 5 | +## [v0.8.0] 2020-10-26 |
| 6 | + |
| 7 | +* **Breaking**: Ethernet PHY configuration feature flags removed. The user must |
| 8 | + now instantiate an instance of the PHY type in order to configure the PHY. |
| 9 | +* pac: Upgrade to stm32-rs v0.12.0 |
| 10 | +* devices: Add support for 7B3, 7B0, 7A3 |
| 11 | +* Add USB support |
| 12 | +* Add I2S support |
| 13 | +* Add RTC support |
| 14 | +* Add LPTIM support |
| 15 | +* Add DMA support, but the current API is depreciated and will be replaced |
| 16 | +* timer: add tick_timer and set_tick_freq to configure the timer's counter frequency [#144](https://github.com/stm32-rs/stm32h7xx-hal/pull/144) |
| 17 | +* Add RTC support [#143](https://github.com/stm32-rs/stm32h7xx-hal/pull/143) |
| 18 | +* pwr: add PowerConfiguration to ensure VoltageScale isn't modified from pwr.freeze() to rcc.freeze() [#141](https://github.com/stm32-rs/stm32h7xx-hal/pull/141) |
| 19 | +* impl Copy, Clone, PartialEq for enums [#139](https://github.com/stm32-rs/stm32h7xx-hal/pull/139) |
| 20 | +* ethernet: automatically configure MDC clock based on hclk |
| 21 | +* time: add types for microseconds and nanoseconds |
| 22 | +* rec: add `low_power` methods for configuring peripherals |
| 23 | + |
| 24 | +## [v0.7.1] 2020-09-04 |
| 25 | + |
| 26 | +* Update docs |
| 27 | + |
| 28 | +## [v0.7.0] 2020-09-03 |
| 29 | + |
| 30 | +* **Breaking**: Fix PWM pin types. See #110 |
| 31 | +* Add QSPI support |
| 32 | +* Add SDMMC support |
| 33 | +* Add Ethernet support |
| 34 | +* Add FMC support |
| 35 | +* spi: add new configuration options |
| 36 | +* i2c: fix i2c bus clock frequency calculation |
| 37 | +* i2c: extend write duration until transaction finishes |
| 38 | +* timer: Fix timer first cycle invalid #72 |
| 39 | +* timer: Add set_timeout method |
| 40 | +* adc: add method to initialise ADC1 and ADC2 together, see examples |
| 41 | +* Added method to switch to VOS0 (480MHz) |
| 42 | +* Allow external HSE clock input (bypass mode) |
| 43 | +* Use ACLK (AXI clock) frequency for calculating flash waitstates |
| 44 | +* pll: Add fractional strategies |
| 45 | +* pll: fix very subtle error in PLL Q,R frequencies |
| 46 | +* serial: rename usart method to serial, will be depreciated in future |
| 47 | +* examples: Added logging framework |
| 48 | +* MSRV increased to 1.43.0 |
| 49 | + |
| 50 | +## [v0.6.0] 2020-06-25 |
| 51 | + |
| 52 | +* **Breaking:** Peripheral driver constructors now consume a peripheralREC |
| 53 | + singleton. Previously they inconsistently took `&mut` or `&` references |
| 54 | + to the CCDR struct itself. See the examples for the new constructors |
| 55 | +* **Breaking:** Erase pins from peripheral driver types. `free()` method return |
| 56 | + types may have changed. |
| 57 | +* Expose `new_unchecked` methods for instantiating peripheral drivers without |
| 58 | + providing pins |
| 59 | +* Improved top-level docs |
| 60 | +* Add DAC peripheral driver |
| 61 | +* Added MCO pins |
| 62 | +* Add `.free()` method for ADC |
| 63 | +* MSRV increased to 1.41.0 |
| 64 | +* rtfm crate was renamed to rtic |
| 65 | +* Added alternate flash size definitions to memory.x |
| 66 | +* Bump dependency versions: cortex-m, cortex-m-rt, cast, paste, bare-metal |
| 67 | + |
| 68 | +## [v0.5.0] 2020-04-27 |
| 69 | + |
| 70 | +* pac: Upgrade to stm32-rs v0.11.0 |
| 71 | +* pwr: Remove need for unsafe, add documentation describing Run* mode |
| 72 | +* rcc: Add a safe interface for the user and other crates to access the RCC |
| 73 | +* spi: 16-bit word support |
| 74 | +* i2c: Remove reference to I2C1 in macro generic for all I2Cs |
| 75 | +* Add HAL for Serial Audio Interface, PDM mode |
| 76 | +* Implement default blocking write for serial |
| 77 | + |
| 78 | +## [v0.4.0] 2020-03-20 |
| 79 | + |
| 80 | +* pac: Upgrade to stm32-rs v0.10.0 |
| 81 | +* rcc: Add iterative PLL configuration strategy |
| 82 | +* rcc: Improve documentation |
| 83 | +* pwr: configure core supply on parts with SMPS (dual core). Prevents |
| 84 | + lock-up without unsafe for certain hardware configurations |
| 85 | +* i2c: wait for end of previous address phase before setting START |
| 86 | +* i2c: return immediately when TXIS / RXNE is set |
| 87 | +* timers: implement TIM3/4/5/6/7/8/12/13/14/15/16/17 |
| 88 | +* gpio: fix error in PF7 definition |
| 89 | +* add MSRV 1.39.0 |
| 90 | + |
| 91 | +## [v0.3.0] 2019-12-27 |
| 92 | + |
| 93 | +* timer: add method to clear interrupt flag |
| 94 | +* gpio: initialise gpio in the correct typestate |
| 95 | +* i2c: flush the TXDR register when a NACK condition occurs |
| 96 | +* Fix `clear_interrupt_pending_bit()` |
| 97 | +* i2c: detect not-acknowledge error, clear errors when detected |
| 98 | +* Run CI against stable since Rust 1.37.0 |
| 99 | +* Upgrade to stm32-rs v0.9.0 (including svd2rust v0.16) |
| 100 | +* Started Changelog |
| 101 | + |
| 102 | +[Unreleased]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.8.0...HEAD |
| 103 | +[v0.8.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.7.1...v0.8.0 |
| 104 | +[v0.7.1]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.7.0...v0.7.1 |
| 105 | +[v0.7.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.6.0...v0.7.0 |
| 106 | +[v0.6.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.5.0...v0.6.0 |
| 107 | +[v0.5.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.4.0...v0.5.0 |
| 108 | +[v0.4.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.3.0...v0.4.0 |
| 109 | +[v0.3.0]: https://github.com/stm32-rs/stm32h7xx-hal/compare/v0.2.1...v0.3.0 |
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