From 0cd442df6ca0aff89348d1f7c7de8498f5d2bca5 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 19:37:12 +0200 Subject: [PATCH 1/6] feat: Add coprocessor access --- cortex-m/src/coprocessor.rs | 94 +++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 cortex-m/src/coprocessor.rs diff --git a/cortex-m/src/coprocessor.rs b/cortex-m/src/coprocessor.rs new file mode 100644 index 00000000..29f07bac --- /dev/null +++ b/cortex-m/src/coprocessor.rs @@ -0,0 +1,94 @@ +//! Coprocessor access assembly instructions. + + + +/// Internal function to create an inlined MCR instruction. +/// This instruction moves one Register to a Coprocessor Register. +/// For this function to compile to a single instruction, compile to opt-level > 2. +#[inline(always)] +pub(crate) fn mcr(value: u32) { + unsafe { + core::arch::asm!( + "MCR p{cp}, #{op1}, {0}, c{crn}, c{crm}, #{op2}", + in(reg) value, + cp = const CP, + op1 = const OP1, + crn = const CRN, + crm = const CRM, + op2 = const OP2, + options(nostack, nomem) + ) + } +} + + + +/// Internal function to create an inlined MRC instruction. +/// This instruction moves one Coprocessor Register to a Register. +/// For this function to compile to a single instruction, compile to opt-level > 2. +#[inline(always)] +pub(crate) fn mrc() -> u32 { + // Preallocate the value. + let a: u32; + + unsafe { + core::arch::asm!( + "MRC p{cp}, #{op1}, {0}, c{crn}, c{crm}, #{op2}", + out(reg) a, + cp = const CP, + op1 = const OP1, + crn = const CRN, + crm = const CRM, + op2 = const OP2, + options(nostack, nomem) + ) + } + + a +} + + + +/// Internal function to create an inlined MCRR instruction. +/// This instruction moves two Registers to Coprocessor Registers. +/// For this function to compile to a single instruction, compile to opt-level > 2. +#[inline(always)] +pub(crate) fn mcrr(a: u32, b: u32) { + unsafe { + core::arch::asm!( + "MCRR p{cp}, #{op1}, {0}, {1}, c{crm}", + in(reg) a, + in(reg) b, + cp = const CP, + op1 = const OP1, + crm = const CRM, + options(nostack, nomem) + ) + } +} + + + +/// Internal function to create an inlined MRRC instruction. +/// This instruction moves two Coprocessor Registers to Registers. +/// For this function to compile to a single instruction, compile to opt-level > 2. +#[inline(always)] +pub(crate) fn mrrc() -> (u32, u32) { + // Preallocate the values. + let a: u32; + let b: u32; + + unsafe { + core::arch::asm!( + "MRRC p{cp}, #{opc}, {0}, {1}, c{crm}", + out(reg) a, + out(reg) b, + cp = const CP, + opc = const OPC, + crm = const CRM, + options(nostack, nomem) + ) + } + + (a, b) +} From defd5cf5fd8284fb35d87402568440fdddc87948 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 19:37:26 +0200 Subject: [PATCH 2/6] feat: Add feature gate to coprocessor access --- cortex-m/Cargo.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index 27228d5f..b7668a83 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -34,6 +34,7 @@ cm7-r0p1 = ["cm7"] linker-plugin-lto = [] std = [] critical-section-single-core = ["critical-section/restore-state-bool"] +coprocessor = [] [package.metadata.docs.rs] targets = [ From f04b8b66e9376e442b637a13f6bdce9b937bb8d2 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 19:37:53 +0200 Subject: [PATCH 3/6] feat: Add coprocessor access to all cortex-m excep ARMV6 --- cortex-m/src/lib.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cortex-m/src/lib.rs b/cortex-m/src/lib.rs index f74fcbf7..1aef82e0 100644 --- a/cortex-m/src/lib.rs +++ b/cortex-m/src/lib.rs @@ -59,6 +59,8 @@ mod macros; pub mod asm; #[cfg(armv8m)] pub mod cmse; +#[cfg(all(not(armv6m), feature = "coprocessor"))] +pub mod coprocessor; pub mod delay; pub mod interrupt; #[cfg(all(not(armv6m), not(armv8m_base)))] From 7b3bc97ce68b382ed886e4604df40a5ecc343dc4 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 21:03:32 +0200 Subject: [PATCH 4/6] fix: Change pub(crate) to pub --- cortex-m/src/coprocessor.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cortex-m/src/coprocessor.rs b/cortex-m/src/coprocessor.rs index 29f07bac..14f2c83b 100644 --- a/cortex-m/src/coprocessor.rs +++ b/cortex-m/src/coprocessor.rs @@ -6,7 +6,7 @@ /// This instruction moves one Register to a Coprocessor Register. /// For this function to compile to a single instruction, compile to opt-level > 2. #[inline(always)] -pub(crate) fn mcr(value: u32) { +pub fn mcr(value: u32) { unsafe { core::arch::asm!( "MCR p{cp}, #{op1}, {0}, c{crn}, c{crm}, #{op2}", @@ -27,7 +27,7 @@ pub(crate) fn mcr 2. #[inline(always)] -pub(crate) fn mrc() -> u32 { +pub fn mrc() -> u32 { // Preallocate the value. let a: u32; @@ -53,7 +53,7 @@ pub(crate) fn mrc 2. #[inline(always)] -pub(crate) fn mcrr(a: u32, b: u32) { +pub fn mcrr(a: u32, b: u32) { unsafe { core::arch::asm!( "MCRR p{cp}, #{op1}, {0}, {1}, c{crm}", @@ -73,7 +73,7 @@ pub(crate) fn mcrr(a: u32, b: u32 /// This instruction moves two Coprocessor Registers to Registers. /// For this function to compile to a single instruction, compile to opt-level > 2. #[inline(always)] -pub(crate) fn mrrc() -> (u32, u32) { +pub fn mrrc() -> (u32, u32) { // Preallocate the values. let a: u32; let b: u32; From df5e0b5dd192585c1d120fe6fb03c329411fb7e5 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 21:05:42 +0200 Subject: [PATCH 5/6] doc: Remove compilation gaurantee --- cortex-m/src/coprocessor.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/cortex-m/src/coprocessor.rs b/cortex-m/src/coprocessor.rs index 14f2c83b..1f606d59 100644 --- a/cortex-m/src/coprocessor.rs +++ b/cortex-m/src/coprocessor.rs @@ -4,7 +4,6 @@ /// Internal function to create an inlined MCR instruction. /// This instruction moves one Register to a Coprocessor Register. -/// For this function to compile to a single instruction, compile to opt-level > 2. #[inline(always)] pub fn mcr(value: u32) { unsafe { @@ -25,7 +24,6 @@ pub fn mcr 2. #[inline(always)] pub fn mrc() -> u32 { // Preallocate the value. @@ -51,7 +49,6 @@ pub fn mrc 2. #[inline(always)] pub fn mcrr(a: u32, b: u32) { unsafe { @@ -71,7 +68,6 @@ pub fn mcrr(a: u32, b: u32) { /// Internal function to create an inlined MRRC instruction. /// This instruction moves two Coprocessor Registers to Registers. -/// For this function to compile to a single instruction, compile to opt-level > 2. #[inline(always)] pub fn mrrc() -> (u32, u32) { // Preallocate the values. From 3139b375969a085024154f83fda6887de661f1a0 Mon Sep 17 00:00:00 2001 From: agrc Date: Fri, 17 May 2024 21:07:02 +0200 Subject: [PATCH 6/6] fix: Remove feature gate --- cortex-m/Cargo.toml | 1 - cortex-m/src/lib.rs | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index b7668a83..27228d5f 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -34,7 +34,6 @@ cm7-r0p1 = ["cm7"] linker-plugin-lto = [] std = [] critical-section-single-core = ["critical-section/restore-state-bool"] -coprocessor = [] [package.metadata.docs.rs] targets = [ diff --git a/cortex-m/src/lib.rs b/cortex-m/src/lib.rs index 1aef82e0..70ef61dd 100644 --- a/cortex-m/src/lib.rs +++ b/cortex-m/src/lib.rs @@ -59,7 +59,7 @@ mod macros; pub mod asm; #[cfg(armv8m)] pub mod cmse; -#[cfg(all(not(armv6m), feature = "coprocessor"))] +#[cfg(not(armv6m))] pub mod coprocessor; pub mod delay; pub mod interrupt;