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Auto merge of #71 - japaric:unimplemented-asm, r=japaric
map asm! ops to unimplemented! on non ARM targets closes #63 cc @hannobraun
2 parents 9a80bae + f79f4b7 commit bdc7ca9

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14 files changed

+194
-202
lines changed

14 files changed

+194
-202
lines changed

‎src/asm.rs

+26-47
Original file line numberDiff line numberDiff line change
@@ -7,74 +7,57 @@
77
/// cause an exception
88
#[inline(always)]
99
pub fn bkpt() {
10-
#[cfg(target_arch = "arm")]
11-
unsafe {
12-
asm!("bkpt"
13-
:
14-
:
15-
:
16-
: "volatile");
10+
match () {
11+
#[cfg(target_arch = "arm")]
12+
() => unsafe { asm!("bkpt" :::: "volatile") },
13+
#[cfg(not(target_arch = "arm"))]
14+
() => unimplemented!(),
1715
}
1816
}
1917

2018
/// A no-operation. Useful to prevent delay loops from being optimized away.
21-
#[inline(always)]
19+
#[inline]
2220
pub fn nop() {
23-
unsafe {
24-
asm!("nop"
25-
:
26-
:
27-
:
28-
: "volatile");
21+
match () {
22+
#[cfg(target_arch = "arm")]
23+
() => unsafe { asm!("nop" :::: "volatile") },
24+
#[cfg(not(target_arch = "arm"))]
25+
() => unimplemented!(),
2926
}
3027
}
3128
/// Wait For Event
32-
#[inline(always)]
29+
#[inline]
3330
pub fn wfe() {
3431
match () {
3532
#[cfg(target_arch = "arm")]
36-
() => unsafe {
37-
asm!("wfe"
38-
:
39-
:
40-
:
41-
: "volatile")
42-
},
33+
() => unsafe { asm!("wfe" :::: "volatile") },
4334
#[cfg(not(target_arch = "arm"))]
44-
() => {}
35+
() => unimplemented!(),
4536
}
4637
}
4738

4839
/// Wait For Interrupt
49-
#[inline(always)]
40+
#[inline]
5041
pub fn wfi() {
5142
match () {
5243
#[cfg(target_arch = "arm")]
53-
() => unsafe{
54-
asm!("wfi"
55-
:
56-
:
57-
:
58-
: "volatile")
59-
},
44+
() => unsafe { asm!("wfi" :::: "volatile") },
6045
#[cfg(not(target_arch = "arm"))]
61-
() => {}
46+
() => unimplemented!(),
6247
}
6348
}
6449

6550
/// Instruction Synchronization Barrier
6651
///
6752
/// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
6853
/// from cache or memory, after the instruction has been completed.
69-
#[inline(always)]
54+
#[inline]
7055
pub fn isb() {
7156
match () {
7257
#[cfg(target_arch = "arm")]
73-
() => unsafe {
74-
asm!("isb 0xF" : : : "memory" : "volatile");
75-
},
58+
() => unsafe { asm!("isb 0xF" : : : "memory" : "volatile") },
7659
#[cfg(not(target_arch = "arm"))]
77-
() => {}
60+
() => unimplemented!(),
7861
}
7962
}
8063

@@ -86,15 +69,13 @@ pub fn isb() {
8669
///
8770
/// * any explicit memory access made before this instruction is complete
8871
/// * all cache and branch predictor maintenance operations before this instruction complete
89-
#[inline(always)]
72+
#[inline]
9073
pub fn dsb() {
9174
match () {
9275
#[cfg(target_arch = "arm")]
93-
() => unsafe {
94-
asm!("dsb 0xF" : : : "memory" : "volatile");
95-
},
76+
() => unsafe { asm!("dsb 0xF" : : : "memory" : "volatile") },
9677
#[cfg(not(target_arch = "arm"))]
97-
() => {}
78+
() => unimplemented!(),
9879
}
9980
}
10081

@@ -103,14 +84,12 @@ pub fn dsb() {
10384
/// Ensures that all explicit memory accesses that appear in program order before the `DMB`
10485
/// instruction are observed before any explicit memory accesses that appear in program order
10586
/// after the `DMB` instruction.
106-
#[inline(always)]
87+
#[inline]
10788
pub fn dmb() {
10889
match () {
10990
#[cfg(target_arch = "arm")]
110-
() => unsafe {
111-
asm!("dmb 0xF" : : : "memory" : "volatile");
112-
},
91+
() => unsafe { asm!("dmb 0xF" : : : "memory" : "volatile") },
11392
#[cfg(not(target_arch = "arm"))]
114-
() => {}
93+
() => unimplemented!(),
11594
}
11695
}

‎src/interrupt.rs

+6-16
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,15 @@
33
pub use bare_metal::{CriticalSection, Mutex, Nr};
44

55
/// Disables all interrupts
6-
#[inline(always)]
6+
#[inline]
77
pub fn disable() {
88
match () {
99
#[cfg(target_arch = "arm")]
1010
() => unsafe {
11-
asm!("cpsid i"
12-
:
13-
:
14-
: "memory"
15-
: "volatile");
11+
asm!("cpsid i" ::: "memory" : "volatile");
1612
},
1713
#[cfg(not(target_arch = "arm"))]
18-
() => {}
14+
() => unimplemented!(),
1915
}
2016
}
2117

@@ -24,19 +20,13 @@ pub fn disable() {
2420
/// # Safety
2521
///
2622
/// - Do not call this function inside an `interrupt::free` critical section
27-
#[inline(always)]
23+
#[inline]
2824
pub unsafe fn enable() {
2925
match () {
3026
#[cfg(target_arch = "arm")]
31-
() => {
32-
asm!("cpsie i"
33-
:
34-
:
35-
: "memory"
36-
: "volatile");
37-
}
27+
() => asm!("cpsie i" ::: "memory" : "volatile"),
3828
#[cfg(not(target_arch = "arm"))]
39-
() => {}
29+
() => unimplemented!(),
4030
}
4131
}
4232

‎src/peripheral/cbp.rs

+10-10
Original file line numberDiff line numberDiff line change
@@ -35,23 +35,23 @@ const CBP_SW_SET_MASK: u32 = 0x1FF << CBP_SW_SET_POS;
3535

3636
impl RegisterBlock {
3737
/// I-cache invalidate all to PoU
38-
#[inline(always)]
38+
#[inline]
3939
pub fn iciallu(&self) {
4040
unsafe {
4141
self.iciallu.write(0);
4242
}
4343
}
4444

4545
/// I-cache invalidate by MVA to PoU
46-
#[inline(always)]
46+
#[inline]
4747
pub fn icimvau(&self, mva: u32) {
4848
unsafe {
4949
self.icimvau.write(mva);
5050
}
5151
}
5252

5353
/// D-cache invalidate by MVA to PoC
54-
#[inline(always)]
54+
#[inline]
5555
pub fn dcimvac(&self, mva: u32) {
5656
unsafe {
5757
self.dcimvac.write(mva);
@@ -61,7 +61,7 @@ impl RegisterBlock {
6161
/// D-cache invalidate by set-way
6262
///
6363
/// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
64-
#[inline(always)]
64+
#[inline]
6565
pub fn dcisw(&self, set: u16, way: u16) {
6666
// The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way
6767
// operations have a register data format which depends on the implementation's
@@ -81,15 +81,15 @@ impl RegisterBlock {
8181
}
8282

8383
/// D-cache clean by MVA to PoU
84-
#[inline(always)]
84+
#[inline]
8585
pub fn dccmvau(&self, mva: u32) {
8686
unsafe {
8787
self.dccmvau.write(mva);
8888
}
8989
}
9090

9191
/// D-cache clean by MVA to PoC
92-
#[inline(always)]
92+
#[inline]
9393
pub fn dccmvac(&self, mva: u32) {
9494
unsafe {
9595
self.dccmvac.write(mva);
@@ -99,7 +99,7 @@ impl RegisterBlock {
9999
/// D-cache clean by set-way
100100
///
101101
/// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
102-
#[inline(always)]
102+
#[inline]
103103
pub fn dccsw(&self, set: u16, way: u16) {
104104
// See comment for dcisw() about the format here
105105
unsafe {
@@ -111,7 +111,7 @@ impl RegisterBlock {
111111
}
112112

113113
/// D-cache clean and invalidate by MVA to PoC
114-
#[inline(always)]
114+
#[inline]
115115
pub fn dccimvac(&self, mva: u32) {
116116
unsafe {
117117
self.dccimvac.write(mva);
@@ -121,7 +121,7 @@ impl RegisterBlock {
121121
/// D-cache clean and invalidate by set-way
122122
///
123123
/// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
124-
#[inline(always)]
124+
#[inline]
125125
pub fn dccisw(&self, set: u16, way: u16) {
126126
// See comment for dcisw() about the format here
127127
unsafe {
@@ -133,7 +133,7 @@ impl RegisterBlock {
133133
}
134134

135135
/// Branch predictor invalidate all
136-
#[inline(always)]
136+
#[inline]
137137
pub fn bpiall(&self) {
138138
unsafe {
139139
self.bpiall.write(0);

‎src/peripheral/mod.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ static mut CORE_PERIPHERALS: bool = false;
6969

7070
impl Peripherals {
7171
/// Returns all the core peripherals *once*
72-
#[inline(always)]
72+
#[inline]
7373
pub fn take() -> Option<Self> {
7474
interrupt::free(|_| {
7575
if unsafe { CORE_PERIPHERALS } {

‎src/register/apsr.rs

+12-9
Original file line numberDiff line numberDiff line change
@@ -39,15 +39,18 @@ impl Apsr {
3939
}
4040

4141
/// Reads the CPU register
42-
#[inline(always)]
42+
#[inline]
4343
pub fn read() -> Apsr {
44-
let r: u32;
45-
unsafe {
46-
asm!("mrs $0, APSR"
47-
: "=r"(r)
48-
:
49-
:
50-
: "volatile");
44+
match () {
45+
#[cfg(target_arch = "arm")]
46+
() => {
47+
let r: u32;
48+
unsafe {
49+
asm!("mrs $0, APSR" : "=r"(r) ::: "volatile");
50+
}
51+
Apsr { bits: r }
52+
}
53+
#[cfg(not(target_arch = "arm"))]
54+
() => unimplemented!(),
5155
}
52-
Apsr { bits: r }
5356
}

‎src/register/basepri.rs

+20-16
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,29 @@
11
//! Base Priority Mask Register
22
33
/// Reads the CPU register
4-
#[inline(always)]
4+
#[inline]
55
pub fn read() -> u8 {
6-
let r: u32;
7-
unsafe {
8-
asm!("mrs $0, BASEPRI"
9-
: "=r"(r)
10-
:
11-
:
12-
: "volatile");
6+
match () {
7+
#[cfg(target_arch = "arm")]
8+
() => {
9+
let r: u32;
10+
unsafe {
11+
asm!("mrs $0, BASEPRI" : "=r"(r) ::: "volatile");
12+
}
13+
r as u8
14+
}
15+
#[cfg(not(target_arch = "arm"))]
16+
() => unimplemented!(),
1317
}
14-
r as u8
1518
}
1619

1720
/// Writes to the CPU register
18-
#[inline(always)]
19-
pub unsafe fn write(basepri: u8) {
20-
asm!("msr BASEPRI, $0"
21-
:
22-
: "r"(basepri)
23-
: "memory"
24-
: "volatile");
21+
#[inline]
22+
pub unsafe fn write(_basepri: u8) {
23+
match () {
24+
#[cfg(target_arch = "arm")]
25+
() => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
26+
#[cfg(not(target_arch = "arm"))]
27+
() => unimplemented!(),
28+
}
2529
}

‎src/register/basepri_max.rs

+9-8
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,14 @@
44
///
55
/// - `basepri != 0` AND `basepri::read() == 0`, OR
66
/// - `basepri != 0` AND `basepri < basepri::read()`
7-
#[inline(always)]
8-
pub fn write(basepri: u8) {
9-
unsafe {
10-
asm!("msr BASEPRI_MAX, $0"
11-
:
12-
: "r"(basepri)
13-
: "memory"
14-
: "volatile");
7+
#[inline]
8+
pub fn write(_basepri: u8) {
9+
match () {
10+
#[cfg(target_arch = "arm")]
11+
() => unsafe {
12+
asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile");
13+
},
14+
#[cfg(not(target_arch = "arm"))]
15+
() => unimplemented!(),
1516
}
1617
}

‎src/register/control.rs

+10-9
Original file line numberDiff line numberDiff line change
@@ -104,15 +104,16 @@ impl Fpca {
104104
}
105105

106106
/// Reads the CPU register
107-
#[inline(always)]
107+
#[inline]
108108
pub fn read() -> Control {
109-
let r: u32;
110-
unsafe {
111-
asm!("mrs $0, CONTROL"
112-
: "=r"(r)
113-
:
114-
:
115-
: "volatile");
109+
match () {
110+
#[cfg(target_arch = "arm")]
111+
() => {
112+
let r: u32;
113+
unsafe { asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
114+
Control { bits: r }
115+
}
116+
#[cfg(not(target_arch = "arm"))]
117+
() => unimplemented!(),
116118
}
117-
Control { bits: r }
118119
}

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