diff --git a/Makefile b/Makefile
index a49edf7bc..6b37c8ce9 100755
--- a/Makefile
+++ b/Makefile
@@ -41,9 +41,9 @@ FORKNAME = raceflight
CC3D_TARGETS = CC3D CC3D_OPBL
F1_TARGETS = NAZE OLIMEXINO CJMCU EUSTM32F103RC PORT103R ALIENWIIF1 AFROMINI
F3_TARGETS = STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENWIIF3 COLIBRI_RACE MOTOLAB RMDO LUX_RACE
-F4_TARGETS = REVO REVO_OPBL SPARKY2 SPARKY2_OPBL REVONANO REVONANO_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE QUANTON KKNGF4
+F4_TARGETS = REVO REVO_OPBL SPARKY2 SPARKY2_OPBL REVONANO REVONANO_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE QUANTON KKNGF4 KAKUTEF4
-F405_TARGETS = REVO REVO_OPBL SPARKY2 SPARKY2_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE QUANTON KKNGF4
+F405_TARGETS = REVO REVO_OPBL SPARKY2 SPARKY2_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE QUANTON KKNGF4 KAKUTEF4
F405_TARGETS_16 = QUANTON
F411_TARGETS = REVONANO REVONANO_OPBL
@@ -459,7 +459,10 @@ STM32F4xx_COMMON_SRC = \
drivers/timer.c \
drivers/timer_stm32f4xx.c \
drivers/flash_m25p16.c \
- io/flashfs.c
+ io/flashfs.c \
+ drivers/light_ws2811strip.c \
+ drivers/light_ws2811strip_stm32f4xx.c \
+ drivers/dma_stm32f4xx.c
VCP_SRC = \
vcp/hw_config.c \
@@ -693,6 +696,14 @@ SPARKY2_SRC = $(STM32F4xx_COMMON_SRC) \
$(COMMON_SRC) \
$(VCPF4_SRC)
+KAKUTEF4_SRC = $(STM32F4xx_COMMON_SRC) \
+ drivers/accgyro_spi_mpu9250.c \
+ drivers/barometer_ms5611.c \
+ drivers/compass_hmc5883l.c \
+ $(HIGHEND_SRC) \
+ $(COMMON_SRC) \
+ $(VCPF4_SRC)
+
ALIENFLIGHTF4_SRC = $(STM32F4xx_COMMON_SRC) \
drivers/accgyro_spi_mpu9250.c \
drivers/barometer_bmp280.c \
@@ -747,7 +758,8 @@ STM32F30x_COMMON_SRC = \
drivers/sound_beeper.c \
drivers/system_stm32f30x.c \
drivers/timer.c \
- drivers/timer_stm32f30x.c
+ drivers/timer_stm32f30x.c \
+ drivers/dma.c
NAZE32PRO_SRC = \
$(STM32F30x_COMMON_SRC) \
@@ -915,7 +927,7 @@ LTO_FLAGS = $(OPTIMIZE)
else
ifeq ($(TARGET),$(filter $(TARGET),SPARKY2 SPARKY2_OPBL))
OPTIMIZE = -O2
-else ifeq ($(TARGET),$(filter $(TARGET),REVO REVO_OPBL REVONANO REVONANO_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE KKNGF4))
+else ifeq ($(TARGET),$(filter $(TARGET),REVO REVO_OPBL REVONANO REVONANO_OPBL ALIENFLIGHTF4 BLUEJAYF4 VRCORE KKNGF4 KAKUTEF4))
OPTIMIZE = -O2
else
OPTIMIZE = -Os
diff --git a/src/main/drivers/dma.c b/src/main/drivers/dma.c
new file mode 100644
index 000000000..a3104d0e7
--- /dev/null
+++ b/src/main/drivers/dma.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "build_config.h"
+
+#include "drivers/dma.h"
+
+/*
+ * DMA handlers for DMA resources that are shared between different features depending on run-time configuration.
+ */
+static dmaHandlers_t dmaHandlers;
+
+#if defined(STM32F1) || defined(STM32F3)
+void dmaNoOpHandler(DMA_Channel_TypeDef *channel)
+{
+ UNUSED(channel);
+}
+
+void DMA1_Channel2_IRQHandler(void)
+{
+ dmaHandlers.dma1Channel2IRQHandler(DMA1_Channel2);
+}
+
+void DMA1_Channel3_IRQHandler(void)
+{
+ dmaHandlers.dma1Channel3IRQHandler(DMA1_Channel3);
+}
+
+void DMA1_Channel6_IRQHandler(void)
+{
+ dmaHandlers.dma1Channel6IRQHandler(DMA1_Channel6);
+}
+
+void DMA1_Channel7_IRQHandler(void)
+{
+ dmaHandlers.dma1Channel7IRQHandler(DMA1_Channel7);
+}
+#endif
+
+void dmaInit(void)
+{
+ memset(&dmaHandlers, 0, sizeof(dmaHandlers));
+ dmaHandlers.dma1Channel2IRQHandler = dmaNoOpHandler;
+ dmaHandlers.dma1Channel3IRQHandler = dmaNoOpHandler;
+ dmaHandlers.dma1Channel6IRQHandler = dmaNoOpHandler;
+ dmaHandlers.dma1Channel7IRQHandler = dmaNoOpHandler;
+}
+
+void dmaSetHandler(dmaHandlerIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback)
+{
+ switch (identifier) {
+ case DMA1_CH2_HANDLER:
+ dmaHandlers.dma1Channel2IRQHandler = callback;
+ break;
+ case DMA1_CH3_HANDLER:
+ dmaHandlers.dma1Channel3IRQHandler = callback;
+ break;
+ case DMA1_CH6_HANDLER:
+ dmaHandlers.dma1Channel6IRQHandler = callback;
+ break;
+ case DMA1_CH7_HANDLER:
+ dmaHandlers.dma1Channel7IRQHandler = callback;
+ break;
+ }
+}
+
+
diff --git a/src/main/drivers/dma.h b/src/main/drivers/dma.h
new file mode 100644
index 000000000..b3ea6d751
--- /dev/null
+++ b/src/main/drivers/dma.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+
+#pragma once
+#include
+
+#if defined(STM32F4)
+ typedef void (*dmaCallbackHandlerFuncPtr)(DMA_Stream_TypeDef *stream);
+
+ typedef enum {
+ DMA1_ST2_HANDLER = 0,
+ DMA1_ST7_HANDLER,
+ } dmaHandlerIdentifier_e;
+
+ typedef struct dmaHandlers_s {
+ dmaCallbackHandlerFuncPtr dma1Stream2IRQHandler;
+ dmaCallbackHandlerFuncPtr dma1Stream7IRQHandler;
+ } dmaHandlers_t;
+
+#else
+
+ typedef void (*dmaCallbackHandlerFuncPtr)(DMA_Channel_TypeDef *channel);
+
+ typedef enum {
+ DMA1_CH2_HANDLER = 0,
+ DMA1_CH3_HANDLER,
+ DMA1_CH6_HANDLER,
+ DMA1_CH7_HANDLER,
+ } dmaHandlerIdentifier_e;
+
+ typedef struct dmaHandlers_s {
+ dmaCallbackHandlerFuncPtr dma1Channel2IRQHandler;
+ dmaCallbackHandlerFuncPtr dma1Channel3IRQHandler;
+ dmaCallbackHandlerFuncPtr dma1Channel6IRQHandler;
+ dmaCallbackHandlerFuncPtr dma1Channel7IRQHandler;
+ } dmaHandlers_t;
+
+#endif
+
+ void dmaInit(void);
+ void dmaSetHandler(dmaHandlerIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback);
+
+
diff --git a/src/main/drivers/dma_stm32f4xx.c b/src/main/drivers/dma_stm32f4xx.c
new file mode 100644
index 000000000..69fc0182a
--- /dev/null
+++ b/src/main/drivers/dma_stm32f4xx.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "build_config.h"
+
+#include "drivers/dma.h"
+
+/*
+ * DMA handlers for DMA resources that are shared between different features depending on run-time configuration.
+ */
+static dmaHandlers_t dmaHandlers;
+
+void dmaNoOpHandler(DMA_Stream_TypeDef *stream)
+{
+ UNUSED(stream);
+}
+
+void DMA1_Stream2_IRQHandler(void)
+{
+ dmaHandlers.dma1Stream2IRQHandler(DMA1_Stream2);
+}
+
+void DMA1_Stream7_IRQHandler(void)
+{
+ dmaHandlers.dma1Stream7IRQHandler(DMA1_Stream7);
+}
+
+void dmaInit(void)
+{
+ memset(&dmaHandlers, 0, sizeof(dmaHandlers));
+ dmaHandlers.dma1Stream2IRQHandler = dmaNoOpHandler;
+ dmaHandlers.dma1Stream7IRQHandler = dmaNoOpHandler;
+}
+
+void dmaSetHandler(dmaHandlerIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback)
+{
+ switch (identifier) {
+ case DMA1_ST2_HANDLER:
+ dmaHandlers.dma1Stream2IRQHandler = callback;
+ break;
+ case DMA1_ST7_HANDLER:
+ dmaHandlers.dma1Stream7IRQHandler = callback;
+ break;
+ }
+}
+
+
diff --git a/src/main/drivers/io_impl.h b/src/main/drivers/io_impl.h
index a283b7d09..e27cc4659 100644
--- a/src/main/drivers/io_impl.h
+++ b/src/main/drivers/io_impl.h
@@ -19,19 +19,24 @@ extern ioRec_t ioRecs[DEFIO_IO_USED_COUNT];
int IO_GPIOPortIdx(IO_t io);
int IO_GPIOPinIdx(IO_t io);
-#if defined(STM32F10X)
-int IO_GPIO_PinSource(IO_t io);
-int IO_GPIO_PortSource(IO_t io);
-#elif defined(STM32F303xC)
-int IO_GPIO_PinSource(IO_t io);
-int IO_GPIO_PortSource(IO_t io);
+//#if defined(STM32F10X)
+//int IO_GPIO_PinSource(IO_t io);
+//int IO_GPIO_PortSource(IO_t io);
+//#elif defined(STM32F303xC)
+//int IO_GPIO_PinSource(IO_t io);
+//int IO_GPIO_PortSource(IO_t io);
+//int IO_EXTI_PortSourceGPIO(IO_t io);
+//int IO_EXTI_PinSource(IO_t io);
+//#elif defined(STM32F40_41xxx) || defined(STM32F411xE)
+
+#if defined(STM32F3) || defined(STM32F4)
int IO_EXTI_PortSourceGPIO(IO_t io);
-int IO_EXTI_PinSource(IO_t io);
-#elif defined(STM32F40_41xxx) || defined(STM32F411xE)
+int IO_EXTI_PinSource(IO_t io);
+GPIO_TypeDef* IO_GPIO(IO_t io);
+#endif
+
int IO_GPIO_PinSource(IO_t io);
int IO_GPIO_PortSource(IO_t io);
-int IO_EXTI_PortSourceGPIO(IO_t io);
-int IO_EXTI_PinSource(IO_t io);
-# endif
+
uint32_t IO_EXTI_Line(IO_t io);
ioRec_t *IO_Rec(IO_t io);
diff --git a/src/main/drivers/light_ws2811strip.c b/src/main/drivers/light_ws2811strip.c
index d9bd58b65..092197c2a 100644
--- a/src/main/drivers/light_ws2811strip.c
+++ b/src/main/drivers/light_ws2811strip.c
@@ -27,13 +27,15 @@
#include
#include
-#include "platform.h"
+#include
#include "build_config.h"
#include "common/color.h"
#include "common/colorconversion.h"
-#include "drivers/light_ws2811strip.h"
+//#include "drivers/light_ws2811strip.h"
+#include "light_ws2811strip.h"
+
uint8_t ledStripDMABuffer[WS2811_DMA_BUFFER_SIZE];
volatile uint8_t ws2811LedDataTransferInProgress = 0;
@@ -133,7 +135,8 @@ void ws2811UpdateStrip(void)
// wait until previous transfer completes
while(ws2811LedDataTransferInProgress) {
- waitCounter++;
+ //waitCounter++;
+ return;
}
dmaBufferOffset = 0; // reset buffer memory index
diff --git a/src/main/drivers/light_ws2811strip.h b/src/main/drivers/light_ws2811strip.h
index 88282ca59..2c0c0e338 100644
--- a/src/main/drivers/light_ws2811strip.h
+++ b/src/main/drivers/light_ws2811strip.h
@@ -25,8 +25,14 @@
#define WS2811_DMA_BUFFER_SIZE (WS2811_DATA_BUFFER_SIZE + WS2811_DELAY_BUFFER_LENGTH) // number of bytes needed is #LEDs * 24 bytes + 42 trailing bytes)
+#if defined(STM32F40_41xxx)
+#define BIT_COMPARE_1 67 // timer compare value for logical 1
+#define BIT_COMPARE_0 33 // timer compare value for logical 0
+#else
#define BIT_COMPARE_1 17 // timer compare value for logical 1
#define BIT_COMPARE_0 9 // timer compare value for logical 0
+#endif
+
void ws2811LedStripInit(void);
diff --git a/src/main/drivers/light_ws2811strip_stm32f10x.c b/src/main/drivers/light_ws2811strip_stm32f10x.c
index 2b0de69bd..d8faa8f0d 100644
--- a/src/main/drivers/light_ws2811strip_stm32f10x.c
+++ b/src/main/drivers/light_ws2811strip_stm32f10x.c
@@ -21,9 +21,18 @@
#include "platform.h"
#include "common/color.h"
-#include "drivers/light_ws2811strip.h"
+#include "light_ws2811strip.h"
+#include "dma.h"
#include "nvic.h"
+void ws2811DMAHandler(DMA_Channel_TypeDef *channel) {
+ if (DMA_GetFlagStatus(WS2811_DMA_TC_FLAG)) {
+ ws2811LedDataTransferInProgress = 0;
+ DMA_Cmd(channel, DISABLE);
+ DMA_ClearFlag(WS2811_DMA_TC_FLAG);
+ }
+}
+
void ws2811LedStripHardwareInit(void)
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
@@ -77,6 +86,8 @@ void ws2811LedStripHardwareInit(void)
/* DMA clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+ dmaSetHandler(WS2811_DMA_HANDLER_IDENTIFER, ws2811DMAHandler);
+
/* DMA1 Channel6 Config */
DMA_DeInit(DMA1_Channel6);
diff --git a/src/main/drivers/light_ws2811strip_stm32f30x.c b/src/main/drivers/light_ws2811strip_stm32f30x.c
index 7404f8e53..5c6d01f08 100644
--- a/src/main/drivers/light_ws2811strip_stm32f30x.c
+++ b/src/main/drivers/light_ws2811strip_stm32f30x.c
@@ -24,7 +24,9 @@
#include "nvic.h"
#include "common/color.h"
-#include "drivers/light_ws2811strip.h"
+#include "light_ws2811strip.h"
+#include "dma.h"
+
#ifndef WS2811_GPIO
#define USE_LED_STRIP_ON_DMA1_CHANNEL3
@@ -39,6 +41,14 @@
#define WS2811_IRQ DMA1_Channel3_IRQn
#endif
+void ws2811DMAHandler(DMA_Channel_TypeDef *channel) {
+ if (DMA_GetFlagStatus(WS2811_DMA_TC_FLAG)) {
+ ws2811LedDataTransferInProgress = 0;
+ DMA_Cmd(channel, DISABLE);
+ DMA_ClearFlag(WS2811_DMA_TC_FLAG);
+ }
+}
+
void ws2811LedStripHardwareInit(void)
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
@@ -61,6 +71,7 @@ void ws2811LedStripHardwareInit(void)
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(WS2811_GPIO, &GPIO_InitStructure);
+ dmaSetHandler(WS2811_DMA_HANDLER_IDENTIFER, ws2811DMAHandler);
RCC_APB2PeriphClockCmd(WS2811_TIMER_APB2_PERIPHERAL, ENABLE);
diff --git a/src/main/drivers/light_ws2811strip_stm32f4xx.c b/src/main/drivers/light_ws2811strip_stm32f4xx.c
index 3113c5583..737ee125c 100644
--- a/src/main/drivers/light_ws2811strip_stm32f4xx.c
+++ b/src/main/drivers/light_ws2811strip_stm32f4xx.c
@@ -21,38 +21,51 @@
#include "platform.h"
#include "common/color.h"
-#include "drivers/light_ws2811strip.h"
+#include "light_ws2811strip.h"
#include "nvic.h"
+#include "dma.h"
+#include "io.h"
+
+#if !defined(WS2811_PIN)
+#define WS2811_GPIO_AF GPIO_AF_TIM5
+#define WS2811_PIN PA0
+#define WS2811_TIMER TIM5
+#define WS2811_TIMER_APB1_PERIPHERAL RCC_APB1Periph_TIM5
+#define WS2811_DMA_HANDLER_IDENTIFER DMA1_ST2_HANDLER
+#define WS2811_DMA_STREAM DMA1_Stream2
+#define WS2811_DMA_CHANNEL DMA_Channel_6
+#define WS2811_DMA_IRQ DMA1_Stream2_IRQn
+#endif
-#if defined(REVO) || defined(REVONANO) || defined(SPARKY2) || defined(ALIENFLIGHTF4) || defined(VRCORE)
+void ws2811DMAHandler(DMA_Stream_TypeDef *stream)
+{
+ if (DMA_GetFlagStatus(stream, DMA_FLAG_TCIF2)) {
+ ws2811LedDataTransferInProgress = 0;
+ DMA_Cmd(stream, DISABLE);
+ TIM_DMACmd(WS2811_TIMER, TIM_DMA_CC1, DISABLE);
+ DMA_ClearITPendingBit(stream, DMA_IT_TCIF2);
+ }
+}
+
void ws2811LedStripHardwareInit(void)
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
DMA_InitTypeDef DMA_InitStructure;
uint16_t prescalerValue;
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
-
+#ifdef WS2811_TIMER_APB1_PERIPHERAL
+ RCC_APB1PeriphClockCmd(WS2811_TIMER_APB1_PERIPHERAL, ENABLE);
+#elif WS2811_TIMER_APB2_PERIPHERAL
+ RCC_APB2PeriphClockCmd(WS2811_TIMER_APB2_PERIPHERAL, ENABLE);
+#endif
/* GPIOA Configuration: TIM5 Channel 1 as alternate function push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM5);
-
-
+ IOInit(IOGetByTag(IO_TAG(WS2811_PIN)), OWNER_SYSTEM, RESOURCE_OUTPUT);
+ IOConfigGPIOAF(IOGetByTag(IO_TAG(WS2811_PIN)), IOCFG_AF_PP, WS2811_GPIO_AF);
// Stop timer
- TIM_Cmd(TIM5, DISABLE);
-
+ TIM_Cmd(WS2811_TIMER, DISABLE);
/* Compute the prescaler value */
prescalerValue = (uint16_t) (SystemCoreClock / 2 / 84000000) - 1;
/* Time base configuration */
@@ -60,26 +73,29 @@ void ws2811LedStripHardwareInit(void)
TIM_TimeBaseStructure.TIM_Prescaler = prescalerValue;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInit(TIM5, &TIM_TimeBaseStructure);
+ TIM_TimeBaseInit(WS2811_TIMER, &TIM_TimeBaseStructure);
/* PWM1 Mode configuration: Channel1 */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OCInitStructure.TIM_Pulse = 0;
- TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OC1Init(TIM5, &TIM_OCInitStructure);
- TIM_OC1PreloadConfig(TIM5, TIM_OCPreload_Enable);
-
- TIM_Cmd(TIM5, ENABLE);
-
-
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCNPolarity_High;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 0;
+
+ TIM_OC1Init(WS2811_TIMER, &TIM_OCInitStructure);
+ TIM_OC1PreloadConfig(WS2811_TIMER, TIM_OCPreload_Enable);
+ TIM_Cmd(WS2811_TIMER, ENABLE);
+
+ dmaSetHandler(WS2811_DMA_HANDLER_IDENTIFER, ws2811DMAHandler);
+
/* configure DMA */
/* DMA1 Channel Config */
- DMA_Cmd(DMA1_Stream2, DISABLE); // disable DMA channel 6
- DMA_DeInit(DMA1_Stream2);
+
+ DMA_Cmd(WS2811_DMA_STREAM, DISABLE);
+ DMA_DeInit(WS2811_DMA_STREAM);
DMA_StructInit(&DMA_InitStructure);
- DMA_InitStructure.DMA_Channel = DMA_Channel_6;
- DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(TIM5->CCR1);
+
+ DMA_InitStructure.DMA_Channel = WS2811_DMA_CHANNEL;
+ DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(WS2811_TIMER->CCR1);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)ledStripDMABuffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = WS2811_DMA_BUFFER_SIZE;
@@ -93,14 +109,15 @@ void ws2811LedStripHardwareInit(void)
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
- DMA_Init(DMA1_Stream2, &DMA_InitStructure);
- DMA_ITConfig(DMA1_Stream2, DMA_IT_TC, ENABLE);
- DMA_ClearITPendingBit(DMA1_Stream2, DMA_IT_TCIF2); // clear DMA1 Channel 6 transfer complete flag
+ DMA_Init(WS2811_DMA_STREAM, &DMA_InitStructure);
+
+ DMA_ITConfig(WS2811_DMA_STREAM, DMA_IT_TC, ENABLE);
+ DMA_ClearITPendingBit(WS2811_DMA_STREAM, DMA_IT_TCIF2);
NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream2_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannel = WS2811_DMA_IRQ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(NVIC_PRIO_WS2811_DMA);
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(NVIC_PRIO_WS2811_DMA);
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@@ -108,23 +125,18 @@ void ws2811LedStripHardwareInit(void)
setStripColor(&hsv_white);
ws2811UpdateStrip();
-}
-void DMA1_Stream2_IRQHandler(void)
-{
- if (DMA_GetFlagStatus(DMA1_Stream2, DMA_FLAG_TCIF2)) {
- ws2811LedDataTransferInProgress = 0;
- DMA_Cmd(DMA1_Stream2, DISABLE);
- TIM_DMACmd(TIM5, TIM_DMA_CC1, DISABLE);
- DMA_ClearITPendingBit(DMA1_Stream2, DMA_IT_TCIF2);
- }
+
}
+
void ws2811LedStripDMAEnable(void)
{
- DMA_SetCurrDataCounter(DMA1_Stream2, WS2811_DMA_BUFFER_SIZE); // load number of bytes to be transferred
- TIM_SetCounter(TIM5, 0);
- DMA_Cmd(DMA1_Stream2, ENABLE);
- TIM_DMACmd(TIM5, TIM_DMA_CC1, ENABLE);
+ DMA_SetCurrDataCounter(WS2811_DMA_STREAM, WS2811_DMA_BUFFER_SIZE); // load number of bytes to be transferred
+ TIM_SetCounter(WS2811_TIMER, 0);
+ DMA_Cmd(WS2811_DMA_STREAM, ENABLE);
+ TIM_DMACmd(WS2811_TIMER, TIM_DMA_CC1, ENABLE);
}
-#endif
+
+
+
diff --git a/src/main/drivers/pwm_mapping.c b/src/main/drivers/pwm_mapping.c
index 1ed0627a6..dbf2b1509 100755
--- a/src/main/drivers/pwm_mapping.c
+++ b/src/main/drivers/pwm_mapping.c
@@ -600,6 +600,52 @@ static const uint16_t airPWM[] = {
};
#endif
+#ifdef KAKUTEF4
+static const uint16_t multiPPM[] = {
+ PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t multiPWM[] = {
+ PWM1 | (MAP_TO_PWM_INPUT << 8),
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t airPPM[] = {
+ PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM5 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM6 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM7 | (MAP_TO_SERVO_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t airPWM[] = {
+ PWM1 | (MAP_TO_PWM_INPUT << 8),
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
+ 0xFFFF
+};
+#endif
+
#ifdef BLUEJAYF4
static const uint16_t multiPPM[] = {
PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input
@@ -1092,6 +1138,11 @@ if (init->useBuzzerP6) {
#if defined(STM32F303xC) && defined(WS2811_GPIO) && defined(WS2811_PIN_SOURCE)
if (timerHardwarePtr->gpio == WS2811_GPIO && timerHardwarePtr->gpioPinSource == WS2811_PIN_SOURCE)
continue;
+#elif defined(STM32F4) && defined(WS2811_PIN)
+ if (timerHardwarePtr->gpio == IO_GPIO(IOGetByTag(IO_TAG(WS2811_PIN)))
+ && timerHardwarePtr->gpioPinSource == IO_GPIO_PinSource(IOGetByTag(IO_TAG(WS2811_PIN))))
+ continue;
+
#endif
}
@@ -1212,21 +1263,31 @@ if (init->useBuzzerP6) {
}
#endif
+#define AVOIDANCE_CONDITION (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate))
+
if (type == MAP_TO_PPM_INPUT) {
#ifdef REVO
- if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
- ppmAvoidPWMTimerClash(timerHardwarePtr, TIM12);
- ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8);
+ //if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
+ // ppmAvoidPWMTimerClash(timerHardwarePtr, TIM12);
+ // ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8);
+ if (AVOIDANCE_CONDITION) {
+ ppmAvoidPWMTimerClash(timerHardwarePtr, TIM12, init);
+ ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8, init);
}
#endif
-#ifdef REVONANO
- if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
- ppmAvoidPWMTimerClash(timerHardwarePtr, TIM2);
+//#ifdef REVONANO
+ //if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
+ // ppmAvoidPWMTimerClash(timerHardwarePtr, TIM2);
+#if defined(REVONANO) || defined(SPARKY) || defined(ALIENFLIGHTF3)
+ if (AVOIDANCE_CONDITION) {
+ ppmAvoidPWMTimerClash(timerHardwarePtr, TIM2, init);
}
#endif
#ifdef SPARKY2
- if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
- ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8);
+ // if (init->useMultiShot || init->useOneshot || isMotorBrushed(init->motorPwmRate)) {
+ // ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8);
+ if (AVOIDANCE_CONDITION) {
+ ppmAvoidPWMTimerClash(timerHardwarePtr, TIM8, init);
}
#endif
#ifdef ALIENFLIGHTF4
diff --git a/src/main/drivers/timer.c b/src/main/drivers/timer.c
index ff240dcbb..3ed9ffa6d 100755
--- a/src/main/drivers/timer.c
+++ b/src/main/drivers/timer.c
@@ -318,6 +318,25 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
#endif
+#if defined(KAKUTEF4)
+const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
+ { TIM8, GPIOC, Pin_7, TIM_Channel_2, TIM8_CC_IRQn, 0, GPIO_Mode_AF, GPIO_PinSource7, GPIO_AF_TIM8}, // PPM IN
+ { TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource0, GPIO_AF_TIM3}, // S1_OUT
+ { TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource1, GPIO_AF_TIM3}, // S2_OUT
+ { TIM9, GPIOA, Pin_3, TIM_Channel_2, TIM1_BRK_TIM9_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource3, GPIO_AF_TIM9}, // S3_OUT
+ { TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource2, GPIO_AF_TIM2}, // S4_OUT
+ { TIM12, GPIOB, Pin_14, TIM_Channel_1, TIM8_BRK_TIM12_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource14, GPIO_AF_TIM12}, // S5_OUT
+ { TIM12, GPIOB, Pin_15, TIM_Channel_2, TIM8_BRK_TIM12_IRQn, 1, GPIO_Mode_AF, GPIO_PinSource15, GPIO_AF_TIM12}, // S6_OUT
+};
+
+#define USED_TIMERS ( TIM_N(2) | TIM_N(3) | TIM_N(12) | TIM_N(8) | TIM_N(9))
+
+#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM12 | RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC)
+#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM9)
+
+#endif
+
+
#if defined(BLUEJAYF4)
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
{ TIM8, GPIOC, Pin_7, TIM_Channel_2, TIM8_CC_IRQn, 0, GPIO_Mode_AF, GPIO_PinSource7, GPIO_AF_TIM8}, // PPM IN
diff --git a/src/main/platform.h b/src/main/platform.h
index 53c79fdcf..a5cf83925 100644
--- a/src/main/platform.h
+++ b/src/main/platform.h
@@ -18,6 +18,8 @@
#pragma once
#if defined(STM32F40_41xxx) || defined (STM32F411xE)
+#define STM32F4
+
#include "stm32f4xx_conf.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_gpio.h"
@@ -32,6 +34,8 @@
#ifdef STM32F303xC
+#define STM32F3
+
#include "stm32f30x_conf.h"
#include "stm32f30x_rcc.h"
#include "stm32f30x_gpio.h"
@@ -45,6 +49,7 @@
#endif
#ifdef STM32F10X
+#define STM32F1
#include "stm32f10x_conf.h"
#include "stm32f10x_gpio.h"
diff --git a/src/main/target/KAKUTEF4/system_stm32f4xx.c b/src/main/target/KAKUTEF4/system_stm32f4xx.c
new file mode 100644
index 000000000..33169994a
--- /dev/null
+++ b/src/main/target/KAKUTEF4/system_stm32f4xx.c
@@ -0,0 +1,1227 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @version V1.6.1
+ * @date 21-October-2015
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F4xx devices.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+ * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F40xxx/41xxx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 168000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 168000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 4
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 10
+ *-----------------------------------------------------------------------------
+ * PLL_N | 420
+ *-----------------------------------------------------------------------------
+ * PLL_P | 2
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 5
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F42xxx/43xxx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 4
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 25000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 25
+ *-----------------------------------------------------------------------------
+ * PLL_N | 360
+ *-----------------------------------------------------------------------------
+ * PLL_P | 2
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 5
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F401xx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 84000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 84000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 25000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 25
+ *-----------------------------------------------------------------------------
+ * PLL_N | 336
+ *-----------------------------------------------------------------------------
+ * PLL_P | 4
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F411xx/STM32F410xx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSI)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 100000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 100000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * HSI Frequency(Hz) | 16000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 16
+ *-----------------------------------------------------------------------------
+ * PLL_N | 400
+ *-----------------------------------------------------------------------------
+ * PLL_P | 4
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 3
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F446xx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 4
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 8
+ *-----------------------------------------------------------------------------
+ * PLL_N | 360
+ *-----------------------------------------------------------------------------
+ * PLL_P | 2
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLL_R | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_M | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_P | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_Q | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 5
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f4xx.h"
+
+uint32_t hse_value = HSE_VALUE;
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F410xx) || defined(STM32F411xE)
+/*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass
+ through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
+ and is fixed at 8 MHz.
+ Hardware configuration needed for Nucleo Board:
+ – SB54, SB55 OFF
+ – R35 removed
+ – SB16, SB50 ON */
+/* #define USE_HSE_BYPASS */
+
+#if defined(USE_HSE_BYPASS)
+#define HSE_BYPASS_INPUT_FREQUENCY 8000000
+#endif /* USE_HSE_BYPASS */
+#endif /* STM32F410xx || STM32F411xE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/************************* PLL Parameters *************************************/
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+ #define PLL_M 8
+#elif defined (STM32F446xx)
+ #define PLL_M 8
+#elif defined (STM32F410xx) || defined (STM32F411xE)
+ #if defined(USE_HSE_BYPASS)
+ #define PLL_M 8
+ #else /* !USE_HSE_BYPASS */
+ #define PLL_M 8
+ #endif /* USE_HSE_BYPASS */
+#else
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
+
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
+#define PLL_Q 8
+
+#if defined(STM32F446xx)
+/* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */
+#define PLL_R 7
+#endif /* STM32F446xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define PLL_N 360
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 2
+#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined (STM32F40_41xxx)
+#define PLL_N 384
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 2
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F401xx)
+#define PLL_N 336
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 4
+#endif /* STM32F401xx */
+
+#if defined(STM32F410xx) || defined(STM32F411xE)
+#define PLL_N 400
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 4
+#endif /* STM32F410xx || STM32F411xE */
+
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+
+#if defined(STM32F40_41xxx)
+ uint32_t SystemCoreClock = 192000000;
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ uint32_t SystemCoreClock = 180000000;
+#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F401xx)
+ uint32_t SystemCoreClock = 84000000;
+#endif /* STM32F401xx */
+
+#if defined(STM32F410xx) || defined(STM32F411xE)
+ uint32_t SystemCoreClock = 100000000;
+#endif /* STM32F410xx || STM32F401xE */
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+void SetSysClock(void);
+
+#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings ----------------------------------*/
+ SetSysClock();
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+#if defined(STM32F446xx)
+ uint32_t pllr = 2;
+#endif /* STM32F446xx */
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL P used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+#elif defined(STM32F410xx) || defined(STM32F411xE)
+#if defined(USE_HSE_BYPASS)
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+#else
+ if (pllsource == 0)
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+#endif /* USE_HSE_BYPASS */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx || STM32F469_479xx */
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+#if defined(STM32F446xx)
+ case 0x0C: /* PLL R used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_R
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
+ SystemCoreClock = pllvco/pllr;
+ break;
+#endif /* STM32F446xx */
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @Note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Select regulator voltage output Scale 1 mode */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+ PWR->CR |= PWR_CR_VOS;
+
+ /* HCLK = SYSCLK / 1*/
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ /* PCLK2 = HCLK / 2*/
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+
+ /* PCLK1 = HCLK / 4*/
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F401xx)
+ /* PCLK2 = HCLK / 2*/
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 4*/
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
+#endif /* STM32F401xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
+ /* Configure the main PLL */
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+ /* Configure the main PLL */
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
+#endif /* STM32F446xx */
+
+ /* Enable the main PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till the main PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+ PWR->CR |= PWR_CR_ODEN;
+ while((PWR->CSR & PWR_CSR_ODRDY) == 0)
+ {
+ }
+ PWR->CR |= PWR_CR_ODSWEN;
+ while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
+ {
+ }
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx)
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F401xx)
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+#endif /* STM32F401xx */
+
+ /* Select the main PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ /* Wait till the main PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+#elif defined(STM32F410xx) || defined(STM32F411xE)
+#if defined(USE_HSE_BYPASS)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* Enable HSE and HSE BYPASS */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Select regulator voltage output Scale 1 mode */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+ PWR->CR |= PWR_CR_VOS;
+
+ /* HCLK = SYSCLK / 1*/
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 2*/
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 4*/
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
+
+ /* Configure the main PLL */
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+ /* Enable the main PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till the main PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+
+ /* Select the main PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ /* Wait till the main PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+#else /* HSI will be used as PLL clock source */
+ /* Select regulator voltage output Scale 1 mode */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+ PWR->CR |= PWR_CR_VOS;
+
+ /* HCLK = SYSCLK / 1*/
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 2*/
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 4*/
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
+
+ /* Configure the main PLL */
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
+
+ /* Enable the main PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till the main PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+
+ /* Select the main PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+ /* Wait till the main PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+ {
+ }
+#endif /* USE_HSE_BYPASS */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+--------------+
+ + SRAM pins assignment +
+ +-------------------+--------------------+------------------+--------------+
+ | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
+ | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
+ | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
+ | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
+ | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
+ | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
+ | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
+ | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
+ | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
+ | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
+ | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
+ | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
+ | | PE15 <-> FMC_D12 |
+ +------------------+------------------+
+*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00cc00cc;
+ GPIOD->AFR[1] = 0xcccccccc;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xaaaa0a0a;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xffff0f0f;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xcccccccc;
+ GPIOE->AFR[1] = 0xcccccccc;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xaaaaaaaa;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xffffffff;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00cccccc;
+ GPIOF->AFR[1] = 0xcccc0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xaa000aaa;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xff000fff;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00cccccc;
+ GPIOG->AFR[1] = 0x000000c0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00080aaa;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000c0fff;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx)
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F40_41xxx */
+
+/*
+ Bank1_SRAM2 is configured as follow:
+ In case of FSMC configuration
+ NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
+ NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
+ NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
+ NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
+ NORSRAMTimingStructure.FSMC_CLKDivision = 0;
+ NORSRAMTimingStructure.FSMC_DataLatency = 0;
+ NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
+
+ In case of FMC configuration
+ NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
+ NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
+ NORSRAMTimingStructure.FMC_DataSetupTime = 2;
+ NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
+ NORSRAMTimingStructure.FMC_CLKDivision = 0;
+ NORSRAMTimingStructure.FMC_DataLatency = 0;
+ NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
+
+ FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
+ FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
+ FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
+ FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
+ FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
+ FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
+ FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
+ FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
+ FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
+ FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
+ FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
+*/
+
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef DATA_IN_ExtSDRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external SDRAM mounted on STM324x9I_EVAL board
+ * This SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001FC;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] = 0x0000000c;
+ GPIOC->AFR[1] = 0x00007700;
+ /* Configure PCx pins in Alternate function mode */
+ GPIOC->MODER = 0x00a00002;
+ /* Configure PCx pins speed to 50 MHz */
+ GPIOC->OSPEEDR = 0x00a00002;
+ /* Configure PCx pins Output type to push-pull */
+ GPIOC->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PCx pins */
+ GPIOC->PUPDR = 0x00500000;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xcccccccc;
+ GPIOF->AFR[1] = 0xcccccccc;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xcccccccc;
+ GPIOG->AFR[1] = 0xcccccccc;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xaaaaaaaa;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xaaaaaaaa;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank1 */
+ FMC_Bank5_6->SDCR[0] = 0x000039D0;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+/*
+ Bank1_SDRAM is configured as follow:
+
+ FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
+ FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
+ FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
+ FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
+ FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
+ FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
+ FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
+
+ FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
+ FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
+ FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
+ FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
+ FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
+ FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
+ FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
+ FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
+ FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
+ FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
+ FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
+*/
+
+}
+#endif /* DATA_IN_ExtSDRAM */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/main/target/KAKUTEF4/system_stm32f4xx.h b/src/main/target/KAKUTEF4/system_stm32f4xx.h
new file mode 100644
index 000000000..5e30ef818
--- /dev/null
+++ b/src/main/target/KAKUTEF4/system_stm32f4xx.h
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V1.6.1
+ * @date 21-October-2015
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/main/target/KAKUTEF4/target.h b/src/main/target/KAKUTEF4/target.h
new file mode 100644
index 000000000..53369a209
--- /dev/null
+++ b/src/main/target/KAKUTEF4/target.h
@@ -0,0 +1,149 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+#pragma once
+#define TARGET_BOARD_IDENTIFIER "KTF4"
+
+#define CONFIG_START_FLASH_ADDRESS 0x08080000 //0x08080000 to 0x080A0000 (FLASH_Sector_8)
+//#define CONFIG_SERIALRX_PROVIDER 2
+#define CONFIG_BLACKBOX_DEVICE 1
+#define CONFIG_SERIALRX_PROVIDER SERIALRX_SBUS
+#define CONFIG_FEATURE_RX_SERIAL
+#define CONFIG_FEATURE_ONESHOT125
+#define CONFIG_MSP_PORT 3
+#define CONFIG_RX_SERIAL_PORT 4
+
+#define USBD_PRODUCT_STRING "KakuteF4"
+#ifdef OPBL
+ #define USBD_SERIALNUMBER_STRING "0x8020000"
+#endif
+
+#define LED0 PB5
+#define LED1 PB4
+//#define LED2 PB6
+
+#define BEEPER PC9
+#define BEEPER_INVERTED
+
+#define INVERTER PC6
+#define INVERTER_USART USART6
+
+#define MPU9250_CS_PIN PC4
+#define MPU9250_SPI_INSTANCE SPI1
+
+#define ACC
+#define USE_ACC_MPU9250
+#define USE_ACC_SPI_MPU9250
+#define ACC_MPU9250_ALIGN CW270_DEG
+
+#define GYRO
+#define USE_GYRO_MPU9250
+#define USE_GYRO_SPI_MPU9250
+#define GYRO_MPU9250_ALIGN CW270_DEG
+
+#define MAG
+//#define USE_MAG_HMC5883
+
+#define BARO
+#define USE_BARO_MS5611
+
+#define M25P16_CS_PIN PB3
+#define M25P16_SPI_INSTANCE SPI3
+
+#define USE_FLASHFS
+#define USE_FLASH_M25P16
+
+#define USABLE_TIMER_CHANNEL_COUNT 7
+
+#define USE_SERIAL_1WIRE
+#define S1W_TX_GPIO GPIOB
+#define S1W_TX_PIN GPIO_Pin_10
+#define S1W_RX_GPIO GPIOB
+#define S1W_RX_PIN GPIO_Pin_11
+
+// MPU9250 interrupt
+//#define DEBUG_MPU_DATA_READY_INTERRUPT
+#define USE_MPU_DATA_READY_SIGNAL
+#define ENSURE_MPU_DATA_READY_IS_LOW
+#define EXTI_CALLBACK_HANDLER_COUNT 1 // MPU data ready
+#define MPU_INT_EXTI PC5
+#define USE_EXTI
+
+#define USE_VCP
+#define VBUS_SENSING_PIN PA8
+
+#define USE_USART1
+#define USART1_RX_PIN PA10
+#define USART1_TX_PIN PA9
+#define USART1_AHB1_PERIPHERALS RCC_AHB1Periph_DMA2
+
+#define USE_USART3
+#define USART3_RX_PIN PB11
+#define USART3_TX_PIN PB10
+
+#define USE_USART6
+#define USART6_RX_PIN PC7
+#define USART6_TX_PIN PC6 //inverter
+#define SERIAL_PORT_COUNT 4
+
+#define USE_SPI
+
+#define USE_SPI_DEVICE_1 //MPU9250
+#define SPI1_NSS_PIN PC4
+#define SPI1_SCK_PIN PA5
+#define SPI1_MISO_PIN PA6
+#define SPI1_MOSI_PIN PA7
+
+#define USE_SPI_DEVICE_3 //dataflash
+#define SPI3_NSS_PIN PB3
+#define SPI3_SCK_PIN PC10
+#define SPI3_MISO_PIN PC11
+#define SPI3_MOSI_PIN PC12
+
+#define USE_FLASH_TOOLS
+
+#define USE_I2C
+#define I2C_DEVICE (I2CDEV_1)
+//#define I2C_DEVICE_EXT (I2CDEV_2)
+
+#define BOARD_HAS_VOLTAGE_DIVIDER
+#define USE_ADC
+#define VBAT_ADC_PIN PC3
+#define VBAT_ADC_CHANNEL ADC_Channel_13
+
+#define CURRENT_METER_ADC_PIN PC2
+#define CURRENT_METER_ADC_CHANNEL ADC_Channel_12
+
+#define RSSI_ADC_PIN PC1
+#define RSSI_ADC_CHANNEL ADC_Channel_11
+
+#define LED_STRIP
+//#define LED_STRIP_TIMER TIM5
+
+#define GPS
+#define BLACKBOX
+#define TELEMETRY
+#define SERIAL_RX
+#define GTUNE
+#define USE_SERVOS
+#define USE_CLI
+
+#define USE_QUATERNION
+
+#define TARGET_IO_PORTA 0xffff
+#define TARGET_IO_PORTB 0xffff
+#define TARGET_IO_PORTC 0xffff