Support constraint files (SDC / XDC)?

[mithro]

A big part of writing reliable Verilog designs is specifying things like timing constraints.

The most popular format for constraints is called SDC - Synopsis Design Constraints.

Variants of the language are supported by Quartus and Vivado uses XDC which is an expansion of the language. Verilog to Routing supports a bunch of SDC constraints too.

Technically the language is tcl but most tools don't really treat it as such. The library VtR uses is C++ and can be found here.. It is likely the SymbiFlow project will write a python based parser for SDC and XDC too.

[rochus-keller]

Thanks for the hint. I will take a look at it even though other formats that are higher on my list. Is there a standard or specification for SDC which we could use? It is called the "industry standard" but there seems to be no formal specification.