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[robseb]

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[Andy2No]

Thanks, @robseb !

I initially bought a DE10-Nano, mostly because it was the biggest FPGA I could reasonably afford, in terms of Logic Elements. I'd read and watched a few lectures by Bruce Land, mostly via the YouTube channel he posts on (https://www.youtube.com/channel/UCgpQgWLXEZWSplxs1eB9Gvw) about the DE1-SoC. The main thing I took away from him was that using the HPS to FPGA bridge puts compile times "through the roof", so I wasn't sure how much I'd use that... and I'm still not sure, but using rsYocto lets me try out a few things easily.

I've found I can still send a new FPGA image that doesn't use the bridge, from the Programmer window in Quartus, after booting with rsYocto, and I can still use the rsYocto linux command line, provided I don't try to do anything that uses the bridge functions - if I do, the HPS reboots, shortly after, and reloads the FPGA image from the microSD card.

On previous experiments, with the DE10-Nano, I found I could send an FPGA image (in x16 format) over the USB-serial connection using TeraTerm, then load it manually, or have it automatically overwrite the standard image, as part of the boot process, by editing one of the startup files. I found that easier than building a new microSD card image. I'll try to reproduce what I did and add a discussion about it, at some point.

I also bought the DE0-Nano-SoC and more recently the DE10-Standard, both used. The DE0-Nano-SoC "CD" download has some examples in C, which were aimed at a cross compiler, but I find I can get those to work via gcc and make from the linux command line in rsYocto, by making some changes to the Makefiles for them. I'm able to get the same hps examples to work on the DE10-Standard, so it seems likely that they work for all three.

I'll start a separate discussion thread about that, when I've collected my thoughts. I'm pleased it works because I don't really know Python, and I couldn't figure out how to set up a cross compiler running in Windows - I tried for a while, then gave up. I'm fine with learning Python, but it's a bit of a stumbling block, at the moment. Running gcc on the HPS is plenty fast enough, so that seems a good way to do it.

[lucasmmanco]

Hi @robseb ,

I'm Lucas. I started to use RSYOCTO last year in a proof of concept project in the company I work with the DE0-Nano-SoC Kit/Atlas-SoC Kit. It worked pretty well. Thanks for RSYOCTO.

Now I'm working on another Development Kit from Aries (MCVEVP). This development kit comes with a Yocto Kirskstone. I would like to use the same FPGA tools you develop on the RSYOCTO in this board. Is it possible to a downgrade of the meta-intelfpga to add to the Aries Yocto project? Or do an upgrade of the meta-aries to add to the RSYOCTO Project?