diff --git a/examples/python/SevenSigCounter.py b/examples/python/SevenSigCounter.py index c0debe9..152e130 100644 --- a/examples/python/SevenSigCounter.py +++ b/examples/python/SevenSigCounter.py @@ -6,7 +6,7 @@ rstools shell command @date: 18.09.2019 -@device: Intel Cyclone V +@device: Intel Cyclone V & Intel Arria 10 SX @author: Robin Sebastian (https://github.com/robseb) ''' @@ -15,11 +15,15 @@ import time import sys +# Selected maximum countable value for the SevenSig Display +SEVENSIG_MAX_VALUE = [2000,0,254] + if __name__ == '__main__': - print('Counting a number on the Seven Segment Display on the DE10-Standard with a shell command!\n') + print('Counting a number on the Seven Segment Display with a Linux shell command!\n') - # Check that the running board is a Terasic DE10-Standard - de10StDetected = False + # Check that the running board is a Terasic DE10-Standard- or Han Pilot Development Board + # Used development board + devboard = 1 # 0: DE10 Standard | 1: DE10 Nano | 2: Han Pilot # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" if os.path.isfile("/usr/rsyocto/suppBoard.txt"): @@ -27,16 +31,29 @@ with open("/usr/rsyocto/suppBoard.txt", "r") as f: supportStr = f.read() if not supportStr.find('Terasic DE10 Standard') ==-1 : - de10StDetected = True + devboard = 0 + elif not supportStr.find('Terasic HAN Pilot') ==-1 : + devboard = 2 - if not de10StDetected : - print("Error: This script only works with a Terasic DE10 Standard Board!") + if devboard==1: + print("Error: This script only works with a Terasic DE10 Standard- or Han Pilot Board!") sys.exit() # Count the Seven Segment Display with a rstools shell command - for count in range(120): - os.system('FPGA-writeBridge -lw 38 -h '+ str(count) +' -b') + for count in range(SEVENSIG_MAX_VALUE[devboard]): + print('Sample: '+str(count)+'/'+str(SEVENSIG_MAX_VALUE[devboard])) + + if(devboard==2): + os.system('FPGA-writeBridge -lw 8 -h '+ str(count) +' -b') + else: # DE10 Standard Board + os.system('FPGA-writeBridge -lw 38 -h '+ str(count) +' -b') + # Delate last console line + sys.stdout.write("\033[F") # Reset the Display value - os.system('FPGA-writeBridge -lw 38 0 -b') + if(devboard==2): + os.system('FPGA-writeBridge -lw 8 0 -b') + else:# DE10 Standard Board + os.system('FPGA-writeBridge -lw 38 0 -b') + print('End...') \ No newline at end of file diff --git a/examples/python/adcTest.py b/examples/python/adcTest.py index 5a06b7b..7d1048e 100644 --- a/examples/python/adcTest.py +++ b/examples/python/adcTest.py @@ -5,10 +5,11 @@ @disc: ADC readout Sensor Test (Analog Devices LTC2308) Fast way over the virtual memory -@date: 21.01.2020 +@date: 22.06.2020 @device: Intel Cyclone V @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time @@ -21,9 +22,9 @@ import devmem # Demo duration -TEST_DURATIONS =30 +TEST_DURATIONS =100 -# the Lightweight HPS-to-FPGA Bus base address offset +# The Lightweight HPS-to-FPGA Bus base address offset HPS_LW_ADRS_OFFSET = 0xFF200000 # LTC2308 Address offset @@ -41,11 +42,20 @@ ### FIFO Convention Data Size for average calculation FIFO_SIZE = 255 # MAX=1024 -VALUE_OR_VOLTAGE_OUTPUT = 0 # 1: Raw Value output | 0: Volage - if __name__ == '__main__': print("ADC readout Demo for LTC2308 ADC with Channel "+str(ADC_CH)) + # Read the name of the used development board + #-> Only the Terasic DE10 Standard and Nano Boards are allowed! + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + if not supportStr.find('Terasic HAN Pilot') ==-1 : + print('The Terasic HAN Pilot Board has no LTC2308 and is not supported!') + sys.exit() + # The ADC is only supported with rsYocto Version 1.031 or later versionNo = 0 # The rsYocto Version Number is located here: "/usr/rsyocto/version.txt" @@ -68,9 +78,13 @@ # (Base address, byte length to acceses, interface) de = devmem.DevMem(HPS_LW_ADRS_OFFSET, ADC_ADDRES_OFFSET+0x8, "/dev/mem") + print('Reading the current ADC value ...') + # Enter test loop for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) + # Set meassure number for ADC convert de.write(ADC_ADDRES_OFFSET+ADC_DATA_REG_OFFSET,[FIFO_SIZE]) # Enable the convention with CH0 @@ -95,14 +109,19 @@ value = rawValue / FIFO_SIZE - if VALUE_OR_VOLTAGE_OUTPUT: - value = round(value,2) - print("ADC AVG: "+str(value)) - else: - # Convert ADC Value to Volage - volage = round(value/1000,2) - print("U AVG: "+str(volage)+"V") + value = round(value,2) + print("-> ADC AVG: "+str(value)) + + # Convert ADC Value to Volage + volage = round(value/1000,2) + print("-> U AVG: "+str(volage)+"V") time.sleep(.2) # 200ms delay + if var != TEST_DURATIONS-1: + # Delate last 3 console line + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") + print('End of demo...') diff --git a/examples/python/blinkLed.py b/examples/python/blinkLed.py index b2fa075..def378b 100644 --- a/examples/python/blinkLed.py +++ b/examples/python/blinkLed.py @@ -4,24 +4,48 @@ ''' @disc: Toggling the HPS LED Demo -@device: Intel Cyclone V -@date: 23.09.2019 +@device: Intel Cyclone V & Intel Arria 10 SX +@date: 22.06.2020 @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time +import sys + +# Demo duration +TEST_DURATIONS = 20 + + +PATH_OF_HPS_LED_DRIVER = '/sys/class/leds/hps_led0/brightness' if __name__ == '__main__': print('Hello from a Python Application running on a SoC-FPGA !\n') print('Toggling HPS LED Example') - # Repeat 20 times - for var in range(20): - print("turn: ",var) + + # Read the name of the used development board + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + print('Your dev board: '+supportStr) + + for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) + # Turn the HPS LED 0 ON - os.system("echo 100 > /sys/class/leds/hps_led0/brightness") + os.system("echo 100 > "+PATH_OF_HPS_LED_DRIVER) time.sleep(.200) + # Turn the HPS LED 0 OFF - os.system("echo 0 > /sys/class/leds/hps_led0/brightness") + os.system("echo 0 > "+PATH_OF_HPS_LED_DRIVER) time.sleep(.500) + + # Delate last console line + sys.stdout.write("\033[F") + + # Turn the HPS LED 0 OFF + os.system("echo 0 > /sys/class/leds/hps_led0/brightness") print('End of demo...') \ No newline at end of file diff --git a/examples/python/blinkingFPGAled.py b/examples/python/blinkingFPGAled.py index 4ef5e73..4419514 100644 --- a/examples/python/blinkingFPGAled.py +++ b/examples/python/blinkingFPGAled.py @@ -5,25 +5,40 @@ @disc: Toggling a FPGA LED with a rstools Linux Shell command -@date: 21.10.2019 +@date: 22.06.2020 @device: Intel Cyclone V @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time +import sys + +# Demo duration +TEST_DURATIONS = 20 if __name__ == '__main__': - print('Toggling the FPGA LED[7] with a Shell command\n') + print('Toggling the FPGA LED[7] with a Linux Shell command') # Turn all FPGA LEDs Off os.system("FPGA-writeBridge -lw 20 0 -b") - for var in range(20): - print("turn: ",var) + for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) + # Turn the FPGA LED 7 ON os.system("FPGA-writeBridge -lw 20 -b 7 1 -b") + # Wait for 50ms time.sleep(.50) + # Turn the FPGA LED 7 ON os.system("FPGA-writeBridge -lw 20 -b 7 0 -b") # Wait for 50ms time.sleep(.50) + + # Delate last console line + sys.stdout.write("\033[F") + + # Turn all FPGA LEDs Off + os.system("FPGA-writeBridge -lw 20 0 -b") + print('End of demo...') \ No newline at end of file diff --git a/examples/python/devmem.py b/examples/python/devmem.py deleted file mode 100644 index f2b1cc8..0000000 --- a/examples/python/devmem.py +++ /dev/null @@ -1,276 +0,0 @@ -#!/usr/bin/env python -""" -This is designed primarily for use with accessing /dev/mem on OMAP platforms. -It should work on other platforms and work to mmap() files rather then just -/dev/mem, but these use cases aren't well tested. - -All file accesses are aligned to DevMem.word bytes, which is 4 bytes on ARM -platforms to avoid data abort faults when accessing peripheral registers. - -References: - http://wiki.python.org/moin/PythonSpeed/PerformanceTips - http://www.python.org/dev/peps/pep-0008/ - -""" - -import os -import sys -import mmap -import struct -import optparse - -""" DevMemBuffer -This class holds data for objects returned from DevMem class -It allows an easy way to print hex data -""" -class DevMemBuffer: - - def __init__(self, base_addr, data): - self.data = data - self.base_addr = base_addr - - def __len__(self): - return len(self.data) - - def __getitem__(self, key): - return self.data[key] - - def __setitem__(self, key, value): - self.data[key] = value - - def hexdump(self, word_size = 4, words_per_row = 4): - # Build a list of strings and then join them in the last step. - # This is more efficient then concat'ing immutable strings. - - d = self.data - dump = [] - - word = 0 - while (word < len(d)): - dump.append('0x{0:02x}: '.format(self.base_addr - + word_size * word)) - - max_col = word + words_per_row - if max_col > len(d): max_col = len(d) - - while (word < max_col): - # If the word is 4 bytes, then handle it and continue the - # loop, this should be the normal case - if word_size == 4: - dump.append(" {0:08x} ".format(d[word])) - word += 1 - continue - - # Otherwise the word_size is not an int, pack it so it can be - # un-packed to the desired word size. This should blindly - # handle endian problems (Verify?) - packed = struct.pack('I',(d[word])) - if word_size == 2: - dh = struct.unpack('HH', packed) - dump.append(" {0:04x}".format(dh[0])) - word += 1 - elif word_size == 1: - db = struct.unpack('BBBB', packed) - dump.append(" {0:02x}".format(db[0])) - word += 1 - - dump.append('\n') - - # Chop off the last new line character and join the list of strings - # in to a single string - return ''.join(dump[:-1]) - - def __str__(self): - return self.hexdump() - - -""" DevMem -Class to read and write data aligned to word boundaries of /dev/mem -""" -class DevMem: - # Size of a word that will be used for reading/writing - word = 4 - mask = ~(word - 1) - - def __init__(self, base_addr, length = 1, filename = '/dev/mem', - debug = 0): - - if base_addr < 0 or length < 0: raise AssertionError - self._debug = debug - - self.base_addr = base_addr & ~(mmap.PAGESIZE - 1) - self.base_addr_offset = base_addr - self.base_addr - - stop = base_addr + length * self.word - if (stop % self.mask): - stop = (stop + self.word) & ~(self.word - 1) - - self.length = stop - self.base_addr - self.fname = filename - - # Check filesize (doesn't work with /dev/mem) - #filesize = os.stat(self.fname).st_size - #if (self.base_addr + self.length) > filesize: - # self.length = filesize - self.base_addr - - self.debug('init with base_addr = {0} and length = {1} on {2}'. - format(hex(self.base_addr), hex(self.length), self.fname)) - - # Open file and mmap - f = os.open(self.fname, os.O_RDWR | os.O_SYNC) - self.mem = mmap.mmap(f, self.length, mmap.MAP_SHARED, - mmap.PROT_READ | mmap.PROT_WRITE, - offset=self.base_addr) - - - """ - Read length number of words from offset - """ - def read(self, offset, length): - if offset < 0 or length < 0: raise AssertionError - - # Make reading easier (and faster... won't resolve dot in loops) - mem = self.mem - - self.debug('reading {0} bytes from offset {1}'. - format(length * self.word, hex(offset))) - - # Compensate for the base_address not being what the user requested - # and then seek to the aligned offset. - virt_base_addr = self.base_addr_offset & self.mask - mem.seek(virt_base_addr + offset) - - # Read length words of size self.word and return it - data = [] - for i in range(length): - data.append(struct.unpack('I', mem.read(self.word))[0]) - - abs_addr = self.base_addr + virt_base_addr - return DevMemBuffer(abs_addr + offset, data) - - - """ - Write length number of words to offset - """ - def write(self, offset, din): - if offset < 0 or len(din) <= 0: raise AssertionError - - self.debug('writing {0} bytes to offset {1}'. - format(len(din), hex(offset))) - - # Make reading easier (and faster... won't resolve dot in loops) - mem = self.mem - - # Compensate for the base_address not being what the user requested - offset += self.base_addr_offset - - # Check that the operation is going write to an aligned location - if (offset & ~self.mask): raise AssertionError - - # Seek to the aligned offset - virt_base_addr = self.base_addr_offset & self.mask - mem.seek(virt_base_addr + offset) - - # Read until the end of our aligned address - for i in range(0, len(din), self.word): - self.debug('writing at position = {0}: 0x{1:x}'. - format(self.mem.tell(), din[i])) - # Write one word at a time - mem.write(struct.pack('I', din[i])) - - def debug_set(self, value): - self._debug = value - - def debug(self, debug_str): - if self._debug: print('DevMem Debug: {0}'.format(debug_str)) - - -""" Main -If this is run as a script (rather then imported as a module) it provides -some basic functionality out of the box -""" -def main(): - parser = optparse.OptionParser() - - parser.add_option("-r", "--read", dest="read", metavar="ADDR", - type=int, help="read a value") - - parser.add_option("-w", "--write", dest="write", help="write a value", - nargs=2, type=int, metavar="ADDR VALUE") - - parser.add_option("-n", "--num", dest="num", - help="number of words to read", - type=int, default=1) - - parser.add_option("-s", "--word-size", dest="word_size", - help="size of word when displayed", - type=int, default=4) - - parser.add_option("-m", "--mmap", dest="mmap", - metavar="FILE", - help="file to open with mmap()", - type=str, default="/dev/mem") - - parser.add_option("-v", action="store_true", dest="verbose", - help="provide more information regarding operation") - - parser.add_option("-d", action="store_true", dest="debug", - help="provide debugging information") - - (options, args) = parser.parse_args() - - # Check for sane arguments - if options.write is not None and options.read is not None: - parser.print_help() - print("\nError: Both read and write are specified") - return -1 - elif options.write is None and options.read is None: - parser.print_help() - print("\nError: Neither read or write are specified") - return -1 - - if options.num < 0: - parser.print_help() - print("\nError: Invalid num of words specified") - return -1 - - if (options.word_size != 1 and options.word_size != 2 - and options.word_size != 4): - parser.print_help() - print("\nError: Invalid word size specified") - return -1 - - # Only support writing one word at a time, force this - if options.write is not None and options.num != 1: - print("Warning: Forcing number of words to 1 for set operation\n") - options.num = 1 - - # Determine base address to operate on - addr = options.read - if options.write is not None: addr = options.write[0] - - # Create the Dev Mem object that does the magic - mem = DevMem(addr, length=options.num, filename=options.mmap, - debug=options.debug) - - if options.debug: - mem.debug_set(1) - - # Perform the actual read or write - if options.write is not None: - if options.verbose: - print("Value before write:\t{0}".format( - mem.read(0x0, options.num).hexdump(options.word_size))) - - mem.write(0x0, [options.write[1]]) - - if options.verbose: - print("Value after write:\t{0}".format( - mem.read(0x0, options.num).hexdump(options.word_size))) - else: - print(mem.read(0x0, options.num).hexdump(options.word_size)) - - -if __name__ == '__main__': - - sys.exit(main()) diff --git a/examples/python/fpgaInputDemo.py b/examples/python/fpgaInputDemo.py index 745f66b..e3a9b92 100644 --- a/examples/python/fpgaInputDemo.py +++ b/examples/python/fpgaInputDemo.py @@ -5,10 +5,11 @@ @disc: Reading the Key and Switches via the LightWight HPS2FPGA Bridge -@date: 19.10.2019 +@date: 22.06.2020 @device: Intel Cyclone V @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time @@ -25,34 +26,67 @@ HPS_LW_ADRS_OFFSET = 0xFF200000 # the offset addresses of the input devices -HPS_LW_ADRS_OFFSET_SYSID = 0x30 # const system id with 0xCADEACDC -HPS_LW_ADRS_OFFSET_KEYS = 0x10 # 2 key button input values -HPS_LW_ADRS_OFFSET_SWI = 0 # 4 switches input values - +# CY5 , A10 +HPS_LW_ADRS_OFFSET_SYSID = [0x30,0x140] # const system id with 0xCADEACDC +HPS_LW_ADRS_OFFSET_KEYS = [0x10,0x100] # 2 key button input values +HPS_LW_ADRS_OFFSET_SWI = [0x00,0x110] # 4 switches input values +HPS_FPGA_SYSID = [0xCAFEACDC,0xCAFEACDC] # ID of the SysID IP ledValue = 0 -HPS_FPGA_SYSID = 0xCADEACDC + # The FPGA family used for this demo +Fpgafamily =0 # 0 : Cyclone V | 1: Arria 10 SX + +# Demo duration +TEST_DURATIONS = 100 if __name__ == '__main__': print("FPGA LED Bin Counter (HPS-Bridge Demo)") + + # Read the name of the used development board + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + if not supportStr.find('Terasic HAN Pilot') ==-1 : + Fpgafamily = 1 + print('Your dev board: '+supportStr) - # Open the memory access to the Lightweight HPS-to- FPGA Bus + # Open the memory access to the Lightweight HPS-to-FPGA Bridge # (Base address, byte length to acceses, interface) - de = devmem.DevMem(HPS_LW_ADRS_OFFSET, HPS_LW_ADRS_OFFSET_SYSID+1, "/dev/mem") + de = devmem.DevMem(HPS_LW_ADRS_OFFSET, HPS_LW_ADRS_OFFSET_SYSID[Fpgafamily]+1, "/dev/mem") # Read the system ID - sysID = de.read(HPS_LW_ADRS_OFFSET_SYSID,1) - print("The system ID is:"+str(sysID.data)) - - # Read the Key Buttons - pb = de.read(HPS_LW_ADRS_OFFSET_KEYS,1) - print('The value of the push buttons: ') - print(str(pb)) - - # Read the switches - sw = de.read(HPS_LW_ADRS_OFFSET_SWI,1) - print('The value of the switches: ') - print(str(sw)) + sysIDraw = de.read(HPS_LW_ADRS_OFFSET_SYSID[Fpgafamily],1) + sysID = sysIDraw.data[0] + + print("The system ID is: "+hex(sysID)) + # Check that the ID os vailed + if sysID == HPS_FPGA_SYSID[Fpgafamily]: + print('The system ID is vailed!') + else: + print('The system ID is not vailed!') + + print('Reading the FPGA Buttons and Swiches') + for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) + + # Read the Key Buttons + pb = de.read(HPS_LW_ADRS_OFFSET_KEYS[Fpgafamily],1) + print('Push Buttons: '+str(pb)+' 0b'+bin(pb.data[0])) + + # Read the switches + sw = de.read(HPS_LW_ADRS_OFFSET_SWI[Fpgafamily],1) + print('Swicthes: '+str(sw)+' 0b'+bin(sw.data[0])) + + # Wait for 100ms + time.sleep(.100) + + if var != TEST_DURATIONS-1: + # Delate last 3 console line + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") print('End of demo...') \ No newline at end of file diff --git a/examples/python/fpgaInputDemoA10.py b/examples/python/fpgaInputDemoA10.py deleted file mode 100644 index 7d11cca..0000000 --- a/examples/python/fpgaInputDemoA10.py +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/env python -# coding: utf-8 - -''' -@disc: Reading the Key and Switches via the - Lightweight HPS-to-FPGA Bridge - -@date: 03.11.2019 -@device: Intel Arria 10 SX -@author: Robin Sebastian - (https://github.com/robseb) -''' -import os -import time -import sys - -# -# This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem) -# be sure that this file is on the same directory -# -import devmem - -# Demo duration -TEST_DURATIONS =50 - - -# The Lightweight HPS-to-FPGA bridge base address offset -HPS_LW_ADRS_OFFSET = 0xFF200000 - -# The offset address input devices -HPS_LW_ADRS_OFFSET_SYSID = 0x140 # const system id with 0xCADEABCD -HPS_LW_ADRS_OFFSET_KEYS = 0x100 # 2 key button input values -HPS_LW_ADRS_OFFSET_SWI = 0x110 # 2 switch button input values - -ledValue = 0 - -HPS_FPGA_SYSID = 0xCADEABCD - -if __name__ == '__main__': - print("FPGA LED Bin Counter (HPS-Bridge Demo)") - - # Open the memory access to the Lightweight HPS-to-FPGA Bridge - # (Base address, byte len to acceses, interface) - de = devmem.DevMem(HPS_LW_ADRS_OFFSET, HPS_LW_ADRS_OFFSET_SYSID+1, "/dev/mem") - - # Read the system ID - sysID = de.read(HPS_LW_ADRS_OFFSET_SYSID,1) - print("The system ID is") - print(str(sysID)) - - for var in range(TEST_DURATIONS): - - print('SWI: ') - sw = de.read(HPS_LW_ADRS_OFFSET_SWI,1) - print(str(sw)) - print('KEY: ') - sw = de.read(HPS_LW_ADRS_OFFSET_KEYS,1) - print(str(sw)) - - # wait 200ms - time.sleep(.20) - - -print('End of demo...') \ No newline at end of file diff --git a/examples/python/fpgaLedCounter.py b/examples/python/fpgaLedCounter.py index efe7f7f..ce78d53 100644 --- a/examples/python/fpgaLedCounter.py +++ b/examples/python/fpgaLedCounter.py @@ -5,10 +5,11 @@ @disc: Counting the FPGA LEDs up Fast way over the virtual memory -@date: 16.09.2019 -@device: Intel Cyclone V +@date: 22.06.2020 +@device: Intel Cyclone V & Intel Arria 10 SX @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time @@ -19,54 +20,79 @@ # import devmem -# Demo duration -TEST_DURATIONS =12 - # # This demo uses the python pip package "processbar2" please install this package with the following command: -# pip install progressbar2 +# pip3 install progressbar2 # -import progressbar -from time import sleep -bar = progressbar.ProgressBar(maxval=TEST_DURATIONS, \ - widgets=[progressbar.Bar('=', '[', ']'), ' ', progressbar.Percentage()]) +try: + import progressbar +except ImportError: + print('This Demo uses the Python pip package "processbar2"') + print('Run following command to install it:') + print('pip3 install progressbar2') + +# Used development board +devboard =0 # 0: DE10 Standard | 1: DE10 Nano | 2: Han Pilot + # the HPS Lightweight HPS-to-FPGA bridge base address HPS_LW_ADRS_OFFSET = 0xFF200000 # the offset address of the LED GPIO Controller -LEDS_ADDRES_OFFSET = 0x20 +# CY5 ,CY5, A10 +LEDS_ADDRES_OFFSET = [0x20,0x20,0x130] +# DE10ST,DE10NA, HAN +LED_MAX_COUNT_VALUE = [255,1024,4] ledValue = 0 +from time import sleep +bar = progressbar.ProgressBar(maxval=LED_MAX_COUNT_VALUE[devboard], \ + widgets=[progressbar.Bar('=', '[', ']'), ' ', progressbar.Percentage()]) + + if __name__ == '__main__': print("FPGA LED Bin Counter (HPS-Bridge Demo) - Faster way") + # Read the name of the used development board + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + if not supportStr.find('Terasic DE10 Nano') ==-1 : + devboard = 1 + elif not supportStr.find('Terasic HAN Pilot') ==-1 : + devboard = 2 + print('Your dev board: '+supportStr) + # open the memory Access to the Lightweight HPS-to-FPGA bridge # (Base address, byte length to acceses, interface) - de = devmem.DevMem(HPS_LW_ADRS_OFFSET, 0x21, "/dev/mem") + de = devmem.DevMem(HPS_LW_ADRS_OFFSET, LEDS_ADDRES_OFFSET[devboard], "/dev/mem") # start the process bar bar.start() - for var in range(TEST_DURATIONS): + for var in range(LED_MAX_COUNT_VALUE[devboard]): # count the LED value up - if(ledValue < 255): + if(ledValue < LED_MAX_COUNT_VALUE[devboard]): ledValue +=1 else: ledValue =0 # write the LED value to FPGA GPIO Controller - de.write(LEDS_ADDRES_OFFSET, [ledValue]) + de.write(LEDS_ADDRES_OFFSET[devboard], [ledValue]) # update the bar status bar.update(var) - # wait 200ms - time.sleep(.020) + # wait 100ms + time.sleep(.10) bar.finish() +# Turn all LEDs off +de.write(LEDS_ADDRES_OFFSET[devboard], [0]) print('End of demo...') \ No newline at end of file diff --git a/examples/python/fpgaLedCounterA10.py b/examples/python/fpgaLedCounterA10.py deleted file mode 100644 index 01df23c..0000000 --- a/examples/python/fpgaLedCounterA10.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env python -# coding: utf-8 -''' -@disc: Counting the FPGA LEDs up - Fast way over the virtual memory - -@date: 19.10.2019 -@device: Intel Arria 10 SX -@author: Robin Sebastian - (https://github.com/robseb) -''' -import os -import time - -# -# This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem) -# be sure that this file is same directory -# -import devmem - -# demo duration -TEST_DURATIONS =16 - - -from time import sleep - - -# The Lightweight HPS-to-FPGA base address offset -HPS_LW_ADRS_OFFSET = 0xFF200000 - -# The offset address of the LED GPIO Controller -LEDS_ADDRES_OFFSET = 0x130 - -ledValue = 0 - -if __name__ == '__main__': - print("FPGA LED Bin Counter for Arria 10 SX (HPS-Bridge Demo)") - - # open the memory access to the Lightweight HPS-to-FPGA bridge - # (Base address, byte len to acceses, interface) - de = devmem.DevMem(HPS_LW_ADRS_OFFSET, 0x121, "/dev/mem") - - for var in range(TEST_DURATIONS): - - # count the LED value up - if(ledValue < 2): - ledValue +=1 - else: - ledValue =0 - - # write the LED value to FPGA GPIO Controller - de.write(LEDS_ADDRES_OFFSET, [ledValue]) - - # wait 200ms - time.sleep(.080) - -print('End of demo...') diff --git a/examples/python/fpgaSevenSigCounterA10.py b/examples/python/fpgaSevenSigCounterA10.py deleted file mode 100644 index 6a58bdd..0000000 --- a/examples/python/fpgaSevenSigCounterA10.py +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env python -# coding: utf-8 -''' -@disc: Counting the Seven Segment Display up - Fast way over the virtual memory - -@date: 19.10.2019 -@device: Intel Arria 10 SX -@author: Robin Sebastian - (https://github.com/robseb) -''' -import os -import time - -# -# This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem) -# be sure that this file is on the same directory -# -import devmem - -# Demo duration -TEST_DURATIONS =256 - - -from time import sleep - - -# The HPS2FPGA AXI Bridge base address offset -HPS2FPGA_ADRS_OFFSET = 0xc0000000 - -# The offset address of the seven segment Display Controller -SEVENSIG_ADDRES_OFFSET = 0x008 - -ledValue = 0 - -if __name__ == '__main__': - print("FPGA LED Bin Counter for Arria 10 SX (HPS-Bridge Demo)") - - # Open the memory access to the AXI HPS2FPGA Bus - # (Base address, byte len to acceses, interface) - de = devmem.DevMem(HPS2FPGA_ADRS_OFFSET, 0x012, "/dev/mem") - - for var in range(TEST_DURATIONS): - - # Count the LED value up - if(ledValue < 0xFF): - ledValue +=1 - else: - ledValue =0 - - # Write the LED value to FPGA GPIO Controller - de.write(SEVENSIG_ADDRES_OFFSET, [ledValue]) - - # Wait 20ms - time.sleep(.020) - - # Reset the value - ledValue = 0 - de.write(SEVENSIG_ADDRES_OFFSET, [ledValue]) -print('End of demo...') diff --git a/examples/python/fpgaSevenSigCounterMemory.py b/examples/python/fpgaSevenSigCounterMemory.py index 4e65d05..9b65ec8 100644 --- a/examples/python/fpgaSevenSigCounterMemory.py +++ b/examples/python/fpgaSevenSigCounterMemory.py @@ -4,13 +4,15 @@ @disc: Counting the Seven Segment Display up Fast way over the virtual memory -@date: 19.10.2019 -@device: Intel Cyclone V +@date: 22.06.2020 +@device: Intel Cyclone V & Arria 10 SX @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time +import sys # # This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem) @@ -18,10 +20,6 @@ # import devmem -# Demo duration -TEST_DURATIONS =4096 - - from time import sleep @@ -29,15 +27,22 @@ HPS_LW_ADRS_OFFSET = 0xFF200000 # The offset address of the seven segment Display Controller -SEVENSIG_ADDRES_OFFSET = 0x038 +# DE10 Standard, , HAN Pilot +SEVENSIG_ADDRES_OFFSET = [0x038,0x0,0x008] ledValue = 0 +# Selected maximum countable value for the SevenSig Display +SEVENSIG_MAX_VALUE = [2000,0,254] +# Delay in ms between every count +DELAY_DURATION= [0.01,0,0.050] + if __name__ == '__main__': print('Counting a number on the Seven Segment Display on the DE10-Standard with virtual Memory!\n') - # Check that the running board is a Terasic DE10-Standard - de10StDetected = False + # Check that the running board is a Terasic DE10-Standard- or Han Pilot Development Board + # Used development board + devboard = 1 # 0: DE10 Standard | 1: DE10 Nano | 2: Han Pilot # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" if os.path.isfile("/usr/rsyocto/suppBoard.txt"): @@ -45,31 +50,37 @@ with open("/usr/rsyocto/suppBoard.txt", "r") as f: supportStr = f.read() if not supportStr.find('Terasic DE10 Standard') ==-1 : - de10StDetected = True + devboard = 0 + elif not supportStr.find('Terasic HAN Pilot') ==-1 : + devboard = 2 - if not de10StDetected : - print("Error: This script works only with a Terasic DE10 Standard Board!") + if devboard==1: + print("Error: This script only works with a Terasic DE10 Standard- or Han Pilot Board!") sys.exit() # Open the memory access to the Lightweight HPS-to-FPGA bridge # (Base address, byte len to accesses, interface) - de = devmem.DevMem(HPS_LW_ADRS_OFFSET, 0x042, "/dev/mem") - - for var in range(TEST_DURATIONS): + de = devmem.DevMem(HPS_LW_ADRS_OFFSET, SEVENSIG_ADDRES_OFFSET[devboard]+1, "/dev/mem") + for var in range(SEVENSIG_MAX_VALUE[devboard]): + print('Sample: '+str(var)+'/'+str(SEVENSIG_MAX_VALUE[devboard])) + # Count the LED value up - if(ledValue < 0xFF): + if(ledValue < SEVENSIG_MAX_VALUE[devboard]): ledValue +=1 else: ledValue =0 # Write the LED value to FPGA GPIO Controller - de.write(SEVENSIG_ADDRES_OFFSET, [ledValue]) + de.write(SEVENSIG_ADDRES_OFFSET[devboard], [ledValue]) + + # Wait + time.sleep(DELAY_DURATION[devboard]) - # Wait 10ms - time.sleep(.010) + # Delate last console line + sys.stdout.write("\033[F") # Reset the Value ledValue = 0 - de.write(SEVENSIG_ADDRES_OFFSET, [ledValue]) + de.write(SEVENSIG_ADDRES_OFFSET[devboard], [ledValue]) print('End of demo...') diff --git a/examples/python/gsensorDemo.py b/examples/python/gsensorDemo.py index 7cbc48d..799dd36 100644 --- a/examples/python/gsensorDemo.py +++ b/examples/python/gsensorDemo.py @@ -5,10 +5,11 @@ @disc: Reading the ADXL345 Accelerometer over the i2c-Bus -@date: 14.09.2019 +@date: 22.06.2020 @device: Intel Cyclone V @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import sys @@ -42,9 +43,24 @@ ADXL345_DATAZ0 = 0x36 # z Axis low value register ADXL345_DATAZ1 = 0x37 # z Axis high value register +# Demo duration +TEST_DURATIONS = 100 + if __name__ == '__main__': print("I2C ADXL345 G-Sensor Demo") + # Read the name of the used development board + #-> Only the Terasic DE10 Standard and Nano Boards are allowed! + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + if not supportStr.find('Terasic HAN Pilot') ==-1 : + print('The Terasic HAN Pilot Board has no ADXL345 and is not supported!') + sys.exit() + + ### Open the onboard I²C-Bus 0 dev = os.open("/dev/i2c-0", os.O_RDWR) @@ -89,8 +105,8 @@ row_val_y =[0,0] row_val_z =[0,0] - for var in range(50): - + for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) ### Read the x-axis values rList =[ADXL345_DATAX0] arr = bytearray(rList) @@ -147,6 +163,12 @@ # Wait 300ms time.sleep(.300) + if(var != TEST_DURATIONS-1): + # Delate last two console line + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") + + ## Disable the measurement mode # Register (address), 8bit data rList =[ADXL345_POWER_CTL,0] diff --git a/examples/python/serialEchoDemo.py b/examples/python/serialEchoDemo.py index 26c8dfb..1d8d1b4 100644 --- a/examples/python/serialEchoDemo.py +++ b/examples/python/serialEchoDemo.py @@ -12,23 +12,32 @@ | D0 - TXD <--- -@date: 10.09.2019 +@date: 22.06.2020 @device: Intel Cyclone V @author: Robin Sebastian (https://github.com/robseb) + (git@robseb.de) ''' import os import time +import sys ### The package "serial" must be installed with the Python pip package manager ### Connect the Board to the internet and run following command inside the Linux console: -## -> pip install pyserial +## -> pip3 install pyserial -import serial + +try: + import serial +except ImportError: + print('This Demo uses the Python pip package "pyserial"') + print('Run following command to install it:') + print('pip3 install pyserial') + sys.exit() # Demo duration -TEST_DURATIONS = 10 +TEST_DURATIONS = 5 # Documentation and examples with Python Serial: # https://pyserial.readthedocs.io/en/latest/shortintro.html @@ -36,7 +45,29 @@ if __name__ == '__main__': print("Python Serial Echo Demo") + # Read the name of the used development board + #-> Only the Terasic DE10 Standard and Nano Boards are allowed! + # The Board name for the image is located here: "/usr/rsyocto/suppBoard.txt" + if os.path.isfile("/usr/rsyocto/suppBoard.txt"): + supportStr = "" + with open("/usr/rsyocto/suppBoard.txt", "r") as f: + supportStr = f.read() + if not supportStr.find('Terasic HAN Pilot') ==-1 : + print('The Terasic HAN Pilot Board is not supported!') + sys.exit() + + print('This demo writes a String over COM1 and checks that the data is received again') + print('Connect RXD and TXD with a juper wire together') + print('Standard/Nano') + print(' 1/D0 - TXD ---->') + print(' |') + print(' |') + print(' 2/D1 - RXD <----') + tmp = input('Press enter to countinue\n') + + for var in range(TEST_DURATIONS): + print('Sample: '+str(var)+'/'+str(TEST_DURATIONS)) # Open UART1 with Baud 9600 and timeout after 1sec ser = serial.Serial('/dev/ttyS1',9600, timeout=1 ) @@ -49,13 +80,18 @@ line = ser.readline() # Print the readout to the console - print(line) + print('RXD: '+str(line)) # Close the COM port ser.close() # trigger the Task in 50ms again time.sleep(.050) + + if(var != TEST_DURATIONS-1): + # Delate last two console line + sys.stdout.write("\033[F") + sys.stdout.write("\033[F") print('End of demo...') diff --git a/fpga/D10STDNANO_DDR3.qprs b/fpga/D10STDNANO_DDR3.qprs new file mode 100644 index 0000000..b82a075 --- /dev/null +++ b/fpga/D10STDNANO_DDR3.qprs @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/DE10STDrsyocto.qar b/fpga/DE10STDrsyocto.qar index cced96e..bd19b2c 100644 Binary files a/fpga/DE10STDrsyocto.qar and b/fpga/DE10STDrsyocto.qar differ diff --git a/fpga/DE10STDrsyocto.v b/fpga/DE10STDrsyocto.v index 56a4cdf..72b1dee 100644 --- a/fpga/DE10STDrsyocto.v +++ b/fpga/DE10STDrsyocto.v @@ -19,22 +19,17 @@ `define USE_HPS `define USE_HEX -`define USE_ADC //`define USE_SDRAM //`define USE_VIDEO_IN //`define USE_VGA //`define USE_AUDO //`define USE_PS2 - +`define USE_ADC //`define IR_LED //`define USE_PS2_VIDO_IF - - - - module DE10STDrsyocto( /////////////////////////////////////////////// CLOCK //////////////////////////////////////////////// @@ -45,7 +40,7 @@ module DE10STDrsyocto( /////////////////////////////////////////////// KEY ///////////////////////////////////////////////// input [3:0] KEY, - + /////////////////////////////////////////////// SW /////////////////////////////////////////////////// input [9:0] SW, @@ -74,7 +69,7 @@ module DE10STDrsyocto( output DRAM_WE_N, `endif -////////////////////////////////////////////////// Video-In /////////////////////////////////////////// +///////////////////////l/////////////////////////// Video-In /////////////////////////////////////////// `ifdef USE_VIDEO_IN input TD_CLK27, input [7:0] TD_DATA, @@ -335,6 +330,11 @@ base_hps u0 ( // .hps_0_spim0_ss_2_n (), // .hps_0_spim0_ss_3_n (), +////////////////////////////////////////////////// SPIO LCD //////////////////////////////////////////// + .hps_0_io_hps_io_spim0_inst_CLK (HPS_LCM_SPIM_CLK), + .hps_0_io_hps_io_spim0_inst_MOSI (HPS_LCM_SPIM_MOSI), + .hps_0_io_hps_io_spim0_inst_MISO (HPS_LCM_SPIM_MISO), + .hps_0_io_hps_io_spim0_inst_SS0 (HPS_LCM_SPIM_SS), /////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -344,17 +344,20 @@ base_hps u0 ( /////////////////////////////////////////// HPS LED & KEY /////////////////////////////////////////// .hps_0_io_hps_io_gpio_inst_GPIO53 ( HPS_LED), .hps_0_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY), - + +////////////////////////////////////////////// HPS GPIO ///////////////////////////////////////////// + .hps_0_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N), + .hps_0_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N), + .hps_0_io_hps_io_gpio_inst_GPIO37 (HPS_LCM_BK), + + .hps_0_io_hps_io_gpio_inst_GPIO41 (HPS_LCM_D_C), + .hps_0_io_hps_io_gpio_inst_GPIO44 (HPS_LCM_RST_N), + .hps_0_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL), + .hps_0_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT), + ////////////////////////////////// G-Sensor: I2C0 (Terasic Docu I2C1) //////////////////////////////// .hps_0_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT), - .hps_0_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK), - - -////////////////////////////////// ADC: Analog Devices LTC2308 //////////////////////////////// - .adc_ltc2308_conduit_end_CONVST (ADC_CONVST), - .adc_ltc2308_conduit_end_SCK (ADC_SCLK), - .adc_ltc2308_conduit_end_SDI (ADC_DIN), - .adc_ltc2308_conduit_end_SDO (ADC_DOUT), + .hps_0_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK), /////////////////////////////////// onboard LEDs, Switches and Keys /////////////////////////////////// .led_pio_external_connection_export (LEDR), // LEDR @@ -362,17 +365,29 @@ base_hps u0 ( .sw_pio_external_connection_export (SW), ////////////////////////////////// 24 Bit seven sigment HEX Display /////////////////////////////////// - .de10std7sig_hex0_export (HEX0), - .de10std7sig_hex1_readdata (HEX1), - .de10std7sig_hex2_readdata (HEX2), - .de10std7sig_hex3_readdata (HEX3), - .de10std7sig_hex4_readdata (HEX4), - .de10std7sig_hex5_readdata (HEX5), + .de10std7sig_hex_io0_readdata (HEX0), + .de10std7sig_hex_io1_readdata (HEX1), + .de10std7sig_hex_io2_readdata (HEX2), + .de10std7sig_hex_io3_readdata (HEX3), + .de10std7sig_hex_io4_readdata (HEX4), + .de10std7sig_hex_io5_readdata (HEX5), + + +////////////////////////////////// ADC: Analog Devices LTC2308 //////////////////////////////// + .ltc2308_io_convst_writeresponsevalid_n (ADC_CONVST), + .ltc2308_io_sck_writeresponsevalid_n (ADC_SCLK), + .ltc2308_io_sdi_writeresponsevalid_n (ADC_DIN), + .ltc2308_io_sdo_beginbursttransfer (ADC_DOUT), + ////////////////////////////////// HPS -> FPGA GPIO /////////////////////////////////// .hps_0_h2f_gp_gp_in (32'hACDCACDC), - .hps_0_h2f_gp_gp_out () + .hps_0_h2f_gp_gp_out (), + + /////////////////// USER CLOCK TEST //////////////////////////// + .hps_0_h2f_user0_clock_clk (GPIO[34]), + .hps_0_h2f_user2_clock_clk (GPIO[35]) ); diff --git a/fpga/DE10_IP/ADC_LTC2308/adc_data_fifo.v b/fpga/DE10_IP/ADC_LTC2308/adc_data_fifo.v new file mode 100644 index 0000000..2cc029b --- /dev/null +++ b/fpga/DE10_IP/ADC_LTC2308/adc_data_fifo.v @@ -0,0 +1,179 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: adc_data_fifo.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module adc_data_fifo ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull); + + input aclr; + input [11:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [11:0] q; + output rdempty; + output wrfull; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire wrfull = sub_wire0; + wire [11:0] q = sub_wire1[11:0]; + wire rdempty = sub_wire2; + + dcfifo dcfifo_component ( + .rdclk (rdclk), + .wrclk (wrclk), + .wrreq (wrreq), + .aclr (aclr), + .data (data), + .rdreq (rdreq), + .wrfull (sub_wire0), + .q (sub_wire1), + .rdempty (sub_wire2), + .rdfull (), + .rdusedw (), + .wrempty (), + .wrusedw ()); + defparam + dcfifo_component.intended_device_family = "Cyclone V", + dcfifo_component.lpm_numwords = 2048, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 12, + dcfifo_component.lpm_widthu = 11, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 4, + dcfifo_component.read_aclr_synch = "OFF", + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.write_aclr_synch = "OFF", + dcfifo_component.wrsync_delaypipe = 4; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "12" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "12" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" +// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]" +// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308.v b/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308.v new file mode 100644 index 0000000..54c19b4 --- /dev/null +++ b/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308.v @@ -0,0 +1,203 @@ +module adc_ltc2308( + clk, // max 40mhz + + // start measure + measure_start, // posedge triggle + measure_ch, + measure_done, + measure_dataread, + + // adc interface + ADC_CONVST, + ADC_SCK, + ADC_SDI, + ADC_SDO +); + +input clk; + +// start measure +input measure_start; +input [2:0] measure_ch; +output reg measure_done; +output [11:0] measure_dataread; + + + +output ADC_CONVST; +output ADC_SCK; +output reg ADC_SDI; +input ADC_SDO; + + +///////////////////////////////// +// Timing definition + +// using 40MHz clock +// to acheive fsample = 500KHz +// ntcyc = 2us / 25ns = 80 + + + +`define DATA_BITS_NUM 12 +`define CMD_BITS_NUM 6 +`define CH_NUM 8 + +`define tWHCONV 3 // CONVST High Time, min 20 ns +`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52 + // set 64 for suite for 1.6 us max +// +12 //data + +`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below + // If the source impedance of the driving circuit is low, the ADC inputs can be driven directly. + //Otherwise, more acquisition time should be allowed for a source with higher impedance. + + // for acheiving 500KHz fmax. set n cyc = 80. +`define tCONVST_HIGH_START 0 +`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV) + +`define tCONFIG_START (`tCONVST_HIGH_END) +`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1) + +`define tCLK_START (`tCONVST_HIGH_START+`tCONV) +`define tCLK_END (`tCLK_START+`DATA_BITS_NUM) + +`define tDONE (`tCLK_END+`tHCONVST) + +// create triggle message: reset_n +reg pre_measure_start; +always @ (posedge clk) +begin + pre_measure_start <= measure_start; +end + +wire reset_n; +assign reset_n = (~pre_measure_start & measure_start)?1'b0:1'b1; + +// tick +reg [15:0] tick; +always @ (posedge clk or negedge reset_n) +begin + if (~reset_n) + tick <= 0; + else if (tick < `tDONE) + tick <= tick + 1; +end + + +///////////////////////////////// +// ADC_CONVST +assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0; + +///////////////////////////////// +// ADC_SCK + +reg clk_enable; // must sync to clk in clk low +always @ (negedge clk or negedge reset_n) +begin + if (~reset_n) + clk_enable <= 1'b0; + else if ((tick >= `tCLK_START && tick < `tCLK_END)) + clk_enable <= 1'b1; + else + clk_enable <= 1'b0; +end + +assign ADC_SCK = clk_enable?clk:1'b0; + + +/////////////////////////////// +// read data +reg [(`DATA_BITS_NUM-1):0] read_data; +reg [3:0] write_pos; + + + +assign measure_dataread = read_data; + +always @ (negedge clk or negedge reset_n) +begin + if (~reset_n) + begin + read_data <= 0; + write_pos <= `DATA_BITS_NUM-1; + end + else if (clk_enable) + begin + read_data[write_pos] <= ADC_SDO; + write_pos <= write_pos - 1; + end +end + +/////////////////////////////// +// measure done +wire read_ch_done; + +assign read_ch_done = (tick == `tDONE)?1'b1:1'b0; + +always @ (posedge clk or negedge reset_n) +begin + if (~reset_n) + measure_done <= 1'b0; + else if (read_ch_done) + measure_done <= 1'b1; +end + +/////////////////////////////// +// adc channel config + +// pre-build config command +reg [(`CMD_BITS_NUM-1):0] config_cmd; + + +`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar +`define SLP_MODE 1'b0 //1: enable sleep + +always @(negedge reset_n) +begin + if (~reset_n) + begin + case (measure_ch) + 0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE}; + 1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE}; + 2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE}; + 3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE}; + 4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE}; + 5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE}; + 6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE}; + 7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE}; + default : config_cmd <= {4'hF, 2'b00}; + endcase + end +end + +// serial config command to adc chip +wire config_init; +wire config_enable; +wire config_done; +reg [2:0] sdi_index; + +assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0; +assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle +assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0; +always @(negedge clk) +begin + if (config_init) + begin + ADC_SDI <= config_cmd[`CMD_BITS_NUM-1]; + sdi_index <= `CMD_BITS_NUM-2; + end + else if (config_enable) + begin + ADC_SDI <= config_cmd[sdi_index]; + sdi_index <= sdi_index - 1; + end + else if (config_done) + ADC_SDI <= 1'b0; // +end + + + + +endmodule + diff --git a/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308_fifo.v b/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308_fifo.v new file mode 100644 index 0000000..2086a53 --- /dev/null +++ b/fpga/DE10_IP/ADC_LTC2308/adc_ltc2308_fifo.v @@ -0,0 +1,216 @@ +/* note for avalon interface + bus type: nagtive + read legacy = 0 (to consistent to FIFO) + +*/ + +module adc_ltc2308_fifo( + // avalon slave port + slave_clk, + slave_reset_n, + slave_chipselect_n, + slave_addr, + slave_read_n, + slave_wrtie_n, + slave_readdata, + slave_wriredata, + + adc_clk, // max 40mhz + // adc interface + ADC_CONVST, + ADC_SCK, + ADC_SDI, + ADC_SDO +); + + // avalon slave port +input slave_clk; +input slave_reset_n; +input slave_chipselect_n; +input slave_addr; +input slave_read_n; +input slave_wrtie_n; +output reg [15:0] slave_readdata; +input [15:0] slave_wriredata; + + + +input adc_clk; + +output ADC_CONVST; +output ADC_SCK; +output ADC_SDI; +input ADC_SDO; + + +//////////////////////////////////// +// avalon slave port +`define WRITE_REG_START_CH 0 +`define WRITE_REG_MEASURE_NUM 1 + +// write for control +reg measure_fifo_start; +reg [11:0] measure_fifo_num; +reg [2:0] measure_fifo_ch; +always @ (posedge slave_clk or negedge slave_reset_n) +begin + if (~slave_reset_n) + measure_fifo_start <= 1'b0; + else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_START_CH) + {measure_fifo_ch, measure_fifo_start} <= slave_wriredata[3:0]; + else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_MEASURE_NUM) + measure_fifo_num <= slave_wriredata; +end + +/////////////////////// +// read +`define READ_REG_MEASURE_DONE 0 +`define READ_REG_ADC_VALUE 1 +wire slave_read_status; +wire slave_read_data; + + +assign slave_read_status = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0; +assign slave_read_data = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0; + +reg measure_fifo_done; +always @ (posedge slave_clk) +begin + if (slave_read_status) + slave_readdata <= {11'b0, measure_fifo_done}; + else if (slave_read_data) + slave_readdata <= fifo_q; +end + +reg pre_slave_read_data; +always @ (posedge slave_clk or negedge slave_reset_n) +begin + if (~slave_reset_n) + pre_slave_read_data <= 1'b0; + else + pre_slave_read_data <= slave_read_data; +end + +// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock) +assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0; + +//////////////////////////////////// +// create triggle message: adc_reset_n + +reg pre_measure_fifo_start; +always @ (posedge adc_clk) +begin + pre_measure_fifo_start <= measure_fifo_start; +end + +wire adc_reset_n; +assign adc_reset_n = (~pre_measure_fifo_start & measure_fifo_start)?1'b0:1'b1; + +//////////////////////////////////// +// control measure_start +reg [11:0] measure_count; + +reg config_first; +reg wait_measure_done; +reg measure_start; +wire measure_done; +wire [11:0] measure_dataread; + +always @ (posedge adc_clk or negedge adc_reset_n) +begin + if (~adc_reset_n) + begin + measure_start <= 1'b0; + config_first <= 1'b1; + measure_count <= 0; + measure_fifo_done <= 1'b0; + wait_measure_done <= 1'b0; + end + else if (~measure_fifo_done & ~measure_start & ~wait_measure_done) + begin + measure_start <= 1'b1; + wait_measure_done <= 1'b1; + end + else if (wait_measure_done) // && measure_start) + begin + measure_start <= 1'b0; + if (measure_done) + begin + if (config_first) + config_first <= 1'b0; + else + begin // read data and save into fifo + + if (measure_count < measure_fifo_num) // && ~fifo_wrfull) + begin + measure_count <= measure_count + 1; + wait_measure_done <= 1'b0; + end + else + measure_fifo_done <= 1'b1; + end + end + end +end + + +// write data into fifo + +reg pre_measure_done; + +always @ (posedge adc_clk or negedge adc_reset_n) +begin + if (~adc_reset_n) + pre_measure_done <= 1'b0; + else + pre_measure_done <= measure_done; +end + +assign fifo_wrreq = (~pre_measure_done & measure_done & ~config_first)?1'b1:1'b0; + + +/////////////////////////////////////// +// SPI + +adc_ltc2308 adc_ltc2308_inst( + .clk(adc_clk), // max 40mhz + + // start measure + .measure_start(measure_start), // posedge triggle + .measure_done(measure_done), + .measure_ch(measure_fifo_ch), + .measure_dataread(measure_dataread), + + + // adc interface + .ADC_CONVST(ADC_CONVST), + .ADC_SCK(ADC_SCK), + .ADC_SDI(ADC_SDI), + .ADC_SDO(ADC_SDO) +); + + +/////////////////////////////////////// +// FIFO +wire fifo_wrfull; +wire fifo_rdempty; +wire fifo_wrreq; +wire [11:0] fifo_q; +wire fifo_rdreq; + + +adc_data_fifo adc_data_fifo_inst( + .aclr(~adc_reset_n), + .data(measure_dataread), + .rdclk(slave_clk), + .rdreq(fifo_rdreq), + .wrclk(adc_clk), + .wrreq(fifo_wrreq), + .q(fifo_q), + .rdempty(fifo_rdempty), + .wrfull(fifo_wrfull) +); + + +endmodule + \ No newline at end of file diff --git a/fpga/HAN_A10rsyocto.qar b/fpga/HAN_A10rsyocto.qar deleted file mode 100644 index 76bc6c7..0000000 Binary files a/fpga/HAN_A10rsyocto.qar and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/A10_IP/HAN_FanControll/HAN_FanTempControll.sv b/fpga/HAN_A10rsyocto/A10_IP/HAN_FanControll/HAN_FanTempControll.sv deleted file mode 100644 index 4756b89..0000000 --- a/fpga/HAN_A10rsyocto/A10_IP/HAN_FanControll/HAN_FanTempControll.sv +++ /dev/null @@ -1,152 +0,0 @@ -`define USE_TEMP_LED - -module HAN_FanTempControll -( - //////////// Avalon Bus Interface ////////// - input logic clk_50Mhz, // 50MHZ - input logic reset_n, read, // Avalon Bus Interface - input logic address, // Avalon Bus Interface - output logic [31:0] readdata, // Avalon Bus Interface - - //////////// Signal Ouptut pins ////////// - output logic Temp_HI, // FPGA TEMPERATURE IS HIGH >37 degree C - output logic Temp_OK, // FPGA TEMPERATURE IS SAFE 32-37 degree C - output logic Temp_LOW, // FPGA TEMPERATURE IS LOW < 32 degree C - -`ifdef USE_TEMP_LED - output logic Temp_LED, -`endif - //////////// I/O Pins ////////// - output I2C_SCL_TempFan, // I2C SCL with the connected Temp Sensor and FAN controller - inout I2C_SDA_TempFan, // I2C SDA with the connected Temp Sensor and FAN controller - input FAN_ALERT_n // FAN controller ISR output pin - -); - - //======================================================= - // temp values to avoid warnings - //======================================================= - - logic dataRedy,temp_hi,temp_ok,temp_low,temp_led, i2c_scl; - logic [31:0] outputReg [1:0]; - - //======================================================= - // read Registers - //======================================================= - - logic [7:0] FPGA_TEMP_C; - logic [7:0] BOARD_TEMP_C; - logic [15:0]FAN_RPM; - - logic [7:0] FAN_DAC; - logic [7:0] ALARM_STATUS; - - - ///////////////////// Avalon Register Set ///////////////////// - /// ------------- write ------------- // - /// none // - /// ------------- read ------------- // - /// 0 - SENSORS // - /// 1 - ALARM // - /////////////////////////////////////////////////////////////// - - /////////////////////// SENSOR REGISTER /////////////////////////// - //// Bit 0-7 : internel FPGA Temperature in degree C /// - //// Bit 8-15 : Board Temerature I2C Sensor in degree C /// - //// Bit 16-31 : Fan rotations per minute (RPM) /// - /////////////////////////////////////////////////////////////////// - - /////////////////////// ALARM REGISTER //////////////////////////// - /// Bit 0-7 : Alarm Status Code /// - /// Bit 16-23 : Fan controller DAC value /// - /// /// - /////////////////////////////////////////////////////////////////// - - - //======================================================= - // temp value assignment to avoid warnings - //======================================================= - assign Temp_HI = temp_hi; - assign Temp_OK = temp_ok; - assign Temp_LOW = temp_low; - assign Temp_LED = temp_led; - assign I2C_SCL_TempFan = i2c_scl; - - - //======================================================= - // data latching - //======================================================= - /// buffer data in case the data is reday - always_ff@(negedge reset_n or posedge dataRedy) begin - if(!reset_n) begin - outputReg[0] = 32'd0; - outputReg[1] = 32'd0; - end - else if (dataRedy) begin - outputReg[0] = {FPGA_TEMP_C,BOARD_TEMP_C,FAN_RPM}; - outputReg[1] = {ALARM_STATUS,FAN_DAC}; - end - end - - - always_ff@(posedge clk_50Mhz) - if(reset_n==1'b0) - readdata <=32'b0; - else begin - if(read) - readdata <= outputReg[address]; - end - - //======================================================= - // STATUS LED output - //======================================================= - // Temperature 32-37 degree C -> LED ON (OK) - // Tempeature < 32 degree C -> LED OFF (LOW) - // Tempeature > 32 degree C -> LED flashing 10Hz (HIGH) -`ifdef USE_TEMP_LED - logic flashClk; - CLOCKMEM k10( .CLK(clk_50Mhz),.CLK_FREQ (5000000),.CK_1HZ(flashClk) ) ; - - always_ff@(posedge clk_50Mhz) begin - if(!reset_n) - temp_led <= 1'b0; - else if (flashClk) begin - if (temp_hi) - temp_led <=!temp_led; - else if((!reset_n) || (temp_ok)) - temp_led <= 1'b0; - else if (temp_low) - temp_led <= 1'b1; - end - end - -`endif - - //======================================================= - // Module - //======================================================= - - //-------- FAN_IP --- - TEMP_FAN_LOOP lp( - .OSC_50 ( clk_50Mhz ), // 50MHZ CLOCK - .RESET_N ( reset_n ) , // RESET - .I2C_SCL ( i2c_scl), // I2C SCLK ( FAN & TEMPERATURE IC ) - .I2C_SDA ( I2C_SDA_TempFan), // I2C SDA ( FAN & TEMPERATURE IC ) - - .MANU_AUTO_SW ( 0), // 1:Test,0:Auto by Temperature - .FPGA_T_ISM ( ) , // Simulatet Temeture Values for test - .FAN_ALERT_n ( FAN_ALERT_n ), // FAN ALARM PIN - .ALARM_STATUS ( ALARM_STATUS) , // FAN ALARM STATUS - .FAN_DAC ( FAN_DAC) , // FAN DAC - .FAN_RPM ( FAN_RPM) , // FAN RPM - .BUSY ( dataRedy ), // GO HI , DATA is SAFE (READY ) - .TEMP_HI ( temp_hi) , // "1" FPGA TEMPERATURE IS HIGH >37 degree C - .TEMP_OK ( temp_ok) , // "1" FPGA TEMPERATURE IS SAFE 32~37 degree C - .TEMP_LO ( temp_low) , // "1" FPGA TEMPERATURE IS LOW < 32 degree C - .FPGA_TEMP_C ( FPGA_TEMP_C ) , // FPGA TEMPERATURE degree C - .BOARD_TEMP_C ( BOARD_TEMP_C) , // BOARD TEMPERATURE degree C - //--test-- - .BUSY_GO_HI ( ) - ); - -endmodule \ No newline at end of file diff --git a/fpga/HAN_A10rsyocto/A10_IP/sevenSigDisplay/sevenSigDispaly.sv b/fpga/HAN_A10rsyocto/A10_IP/sevenSigDisplay/sevenSigDispaly.sv deleted file mode 100644 index d683c8c..0000000 --- a/fpga/HAN_A10rsyocto/A10_IP/sevenSigDisplay/sevenSigDispaly.sv +++ /dev/null @@ -1,132 +0,0 @@ -module sevenSigDisplay -( - //////////// Avalon Bus Interface ////////// - input logic clk_50Mhz, // 50MHZ - input logic reset_n, write, // Avalon Bus Interface - input logic address, // Avalon Bus Interface - input logic [31:0] writedata, // Avalon Bus Interface - - //////////// 7sig I/O pins ////////// - output logic HEX0_DP, - output logic [6:0] HEX0_D, - output logic HEX1_DP, - output logic [6:0] HEX1_D - -); - - //======================================================= - // temp values to avoid warnings - //======================================================= - logic [31:0] inputReg; - - //======================================================= - // read Registers - //======================================================= - localparam TRAGET_FRQ = 12; //[Hz] - localparam ClOCK_CYCELS = 50000000; // Speed / OSCI_SPEED - - ///////////////////// Avalon Register Set ///////////////////// - /// ------------- write ------------- // - /// 0: Seven Sigment Output Byte // - /// ------------- read ------------- // - /// none // - /////////////////////////////////////////////////////////////// - - ////////////////////// SEVENSIG REGISTER ///////////////////////// - //// Bit 0-3 : lower Seven Sigment Display (HEX0) /// - //// Bit 4-7 : uper Seven Sigment Display (HEX1) /// - //// Bit 8 : HEX0 Dot point /// - //// Bit 9 : HEX0 Dot point /// - ////////////////////////////////////////////////////////////////// - logic update; - assign update = (write && !address); - - always_ff@(posedge clk_50Mhz) - if(reset_n==1'b0) - inputReg <=32'b0; - else begin - if(update) - inputReg <= writedata; - end - - - //======================================================= - // Generate refrech clock - //======================================================= - - localparam pres = (ClOCK_CYCELS/TRAGET_FRQ); - - logic [31:0] time_base_counter = 32'd0; - always_ff@(posedge clk_50Mhz) - if(reset_n==1'b0) - time_base_counter <=32'd0; - else - begin - if(time_base_counter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl b/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl deleted file mode 100644 index 32f4f95..0000000 --- a/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl +++ /dev/null @@ -1,178 +0,0 @@ -# TCL File Generated by Component Editor 18.1 -# Mon Dec 16 13:30:08 CET 2019 -# DO NOT MODIFY - - -# -# SevenSigmentDisplay "SevenSigmentDisplay" v1.0 -# Robin Sebastian 2019.12.16.13:30:08 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module SevenSigmentDisplay -# -set_module_property DESCRIPTION "" -set_module_property NAME SevenSigmentDisplay -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property GROUP "Basic Functions/I/O" -set_module_property AUTHOR "Robin Sebastian" -set_module_property DISPLAY_NAME SevenSigmentDisplay -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL sevenSigDisplay -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file sevenSigDispaly.sv SYSTEM_VERILOG PATH A10_IP/sevenSigDisplay/sevenSigDispaly.sv TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point avalon_slave_0 -# -add_interface avalon_slave_0 avalon end -set_interface_property avalon_slave_0 addressUnits WORDS -set_interface_property avalon_slave_0 associatedClock clock50 -set_interface_property avalon_slave_0 associatedReset reset -set_interface_property avalon_slave_0 bitsPerSymbol 8 -set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false -set_interface_property avalon_slave_0 burstcountUnits WORDS -set_interface_property avalon_slave_0 explicitAddressSpan 0 -set_interface_property avalon_slave_0 holdTime 0 -set_interface_property avalon_slave_0 linewrapBursts false -set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 -set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 -set_interface_property avalon_slave_0 readLatency 0 -set_interface_property avalon_slave_0 readWaitTime 1 -set_interface_property avalon_slave_0 setupTime 0 -set_interface_property avalon_slave_0 timingUnits Cycles -set_interface_property avalon_slave_0 writeWaitTime 0 -set_interface_property avalon_slave_0 ENABLED true -set_interface_property avalon_slave_0 EXPORT_OF "" -set_interface_property avalon_slave_0 PORT_NAME_MAP "" -set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" -set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" - -add_interface_port avalon_slave_0 write write Input 1 -add_interface_port avalon_slave_0 address address Input 1 -add_interface_port avalon_slave_0 writedata writedata Input 32 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock50 -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset_n reset_n Input 1 - - -# -# connection point clock50 -# -add_interface clock50 clock end -set_interface_property clock50 clockRate 0 -set_interface_property clock50 ENABLED true -set_interface_property clock50 EXPORT_OF "" -set_interface_property clock50 PORT_NAME_MAP "" -set_interface_property clock50 CMSIS_SVD_VARIABLES "" -set_interface_property clock50 SVD_ADDRESS_GROUP "" - -add_interface_port clock50 clk_50Mhz clk Input 1 - - -# -# connection point IO_HEX_D0 -# -add_interface IO_HEX_D0 conduit end -set_interface_property IO_HEX_D0 associatedClock clock50 -set_interface_property IO_HEX_D0 associatedReset reset -set_interface_property IO_HEX_D0 ENABLED true -set_interface_property IO_HEX_D0 EXPORT_OF "" -set_interface_property IO_HEX_D0 PORT_NAME_MAP "" -set_interface_property IO_HEX_D0 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_D0 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_D0 HEX0_D readdata Output 7 - - -# -# connection point IO_HEX_D1 -# -add_interface IO_HEX_D1 conduit end -set_interface_property IO_HEX_D1 associatedClock clock50 -set_interface_property IO_HEX_D1 associatedReset reset -set_interface_property IO_HEX_D1 ENABLED true -set_interface_property IO_HEX_D1 EXPORT_OF "" -set_interface_property IO_HEX_D1 PORT_NAME_MAP "" -set_interface_property IO_HEX_D1 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_D1 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_D1 HEX1_D readdata Output 7 - - -# -# connection point IO_HEX_DP0 -# -add_interface IO_HEX_DP0 conduit end -set_interface_property IO_HEX_DP0 associatedClock clock50 -set_interface_property IO_HEX_DP0 associatedReset reset -set_interface_property IO_HEX_DP0 ENABLED true -set_interface_property IO_HEX_DP0 EXPORT_OF "" -set_interface_property IO_HEX_DP0 PORT_NAME_MAP "" -set_interface_property IO_HEX_DP0 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_DP0 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_DP0 HEX0_DP writeresponsevalid_n Output 1 - - -# -# connection point IO_HEX_DP1 -# -add_interface IO_HEX_DP1 conduit end -set_interface_property IO_HEX_DP1 associatedClock clock50 -set_interface_property IO_HEX_DP1 associatedReset reset -set_interface_property IO_HEX_DP1 ENABLED true -set_interface_property IO_HEX_DP1 EXPORT_OF "" -set_interface_property IO_HEX_DP1 PORT_NAME_MAP "" -set_interface_property IO_HEX_DP1 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_DP1 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_DP1 HEX1_DP writeresponsevalid_n Output 1 - diff --git a/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl~ b/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl~ deleted file mode 100644 index 531173e..0000000 --- a/fpga/HAN_A10rsyocto/SevenSigmentDisplay_hw.tcl~ +++ /dev/null @@ -1,177 +0,0 @@ -# TCL File Generated by Component Editor 18.1 -# Mon Dec 16 13:29:45 CET 2019 -# DO NOT MODIFY - - -# -# SevenSigmentDisplay "new_component" v1.0 -# Robin Sebastian 2019.12.16.13:29:45 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module SevenSigmentDisplay -# -set_module_property DESCRIPTION "" -set_module_property NAME SevenSigmentDisplay -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "Robin Sebastian" -set_module_property DISPLAY_NAME new_component -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL sevenSigDisplay -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file sevenSigDispaly.sv SYSTEM_VERILOG PATH A10_IP/sevenSigDisplay/sevenSigDispaly.sv TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point avalon_slave_0 -# -add_interface avalon_slave_0 avalon end -set_interface_property avalon_slave_0 addressUnits WORDS -set_interface_property avalon_slave_0 associatedClock clock50 -set_interface_property avalon_slave_0 associatedReset reset -set_interface_property avalon_slave_0 bitsPerSymbol 8 -set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false -set_interface_property avalon_slave_0 burstcountUnits WORDS -set_interface_property avalon_slave_0 explicitAddressSpan 0 -set_interface_property avalon_slave_0 holdTime 0 -set_interface_property avalon_slave_0 linewrapBursts false -set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 -set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 -set_interface_property avalon_slave_0 readLatency 0 -set_interface_property avalon_slave_0 readWaitTime 1 -set_interface_property avalon_slave_0 setupTime 0 -set_interface_property avalon_slave_0 timingUnits Cycles -set_interface_property avalon_slave_0 writeWaitTime 0 -set_interface_property avalon_slave_0 ENABLED true -set_interface_property avalon_slave_0 EXPORT_OF "" -set_interface_property avalon_slave_0 PORT_NAME_MAP "" -set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" -set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" - -add_interface_port avalon_slave_0 write write Input 1 -add_interface_port avalon_slave_0 address address Input 1 -add_interface_port avalon_slave_0 writedata writedata Input 32 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 -set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock50 -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset_n reset_n Input 1 - - -# -# connection point clock50 -# -add_interface clock50 clock end -set_interface_property clock50 clockRate 0 -set_interface_property clock50 ENABLED true -set_interface_property clock50 EXPORT_OF "" -set_interface_property clock50 PORT_NAME_MAP "" -set_interface_property clock50 CMSIS_SVD_VARIABLES "" -set_interface_property clock50 SVD_ADDRESS_GROUP "" - -add_interface_port clock50 clk_50Mhz clk Input 1 - - -# -# connection point IO_HEX_D0 -# -add_interface IO_HEX_D0 conduit end -set_interface_property IO_HEX_D0 associatedClock clock50 -set_interface_property IO_HEX_D0 associatedReset reset -set_interface_property IO_HEX_D0 ENABLED true -set_interface_property IO_HEX_D0 EXPORT_OF "" -set_interface_property IO_HEX_D0 PORT_NAME_MAP "" -set_interface_property IO_HEX_D0 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_D0 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_D0 HEX0_D readdata Output 7 - - -# -# connection point IO_HEX_D1 -# -add_interface IO_HEX_D1 conduit end -set_interface_property IO_HEX_D1 associatedClock clock50 -set_interface_property IO_HEX_D1 associatedReset reset -set_interface_property IO_HEX_D1 ENABLED true -set_interface_property IO_HEX_D1 EXPORT_OF "" -set_interface_property IO_HEX_D1 PORT_NAME_MAP "" -set_interface_property IO_HEX_D1 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_D1 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_D1 HEX1_D readdata Output 7 - - -# -# connection point IO_HEX_DP0 -# -add_interface IO_HEX_DP0 conduit end -set_interface_property IO_HEX_DP0 associatedClock clock50 -set_interface_property IO_HEX_DP0 associatedReset reset -set_interface_property IO_HEX_DP0 ENABLED true -set_interface_property IO_HEX_DP0 EXPORT_OF "" -set_interface_property IO_HEX_DP0 PORT_NAME_MAP "" -set_interface_property IO_HEX_DP0 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_DP0 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_DP0 HEX0_DP writeresponsevalid_n Output 1 - - -# -# connection point IO_HEX_DP1 -# -add_interface IO_HEX_DP1 conduit end -set_interface_property IO_HEX_DP1 associatedClock clock50 -set_interface_property IO_HEX_DP1 associatedReset reset -set_interface_property IO_HEX_DP1 ENABLED true -set_interface_property IO_HEX_DP1 EXPORT_OF "" -set_interface_property IO_HEX_DP1 PORT_NAME_MAP "" -set_interface_property IO_HEX_DP1 CMSIS_SVD_VARIABLES "" -set_interface_property IO_HEX_DP1 SVD_ADDRESS_GROUP "" - -add_interface_port IO_HEX_DP1 HEX1_DP writeresponsevalid_n Output 1 - diff --git a/fpga/HAN_A10rsyocto/a10s.archive.rpt b/fpga/HAN_A10rsyocto/a10s.archive.rpt deleted file mode 100644 index f6502f9..0000000 --- a/fpga/HAN_A10rsyocto/a10s.archive.rpt +++ /dev/null @@ -1,306 +0,0 @@ -Archive Project report for a10s -Mon Dec 16 18:03:00 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Archive Project Summary - 3. Archive Project Messages - 4. Files Archived - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+----------------------------------------------------------------+ -; Archive Project Summary ; -+------------------------+---------------------------------------+ -; Archive Project Status ; Successful - Mon Dec 16 18:03:00 2019 ; -; Revision Name ; a10s ; -; Top-level Entity Name ; a10s ; -; Family ; Arria 10 ; -+------------------------+---------------------------------------+ - - -+--------------------------+ -; Archive Project Messages ; -+--------------------------+ -Info: File Set 'Source control' contains: - Info: Project source and settings files - Info: Automatically detected source files -Warning: Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver -Info: Archive will store files relative to the closest common parent directory -Info (13213): Using common directory D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/ -Info: ---------------------------------------------------------- -Info: ---------------------------------------------------------- -Info: Generated archive 'D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/HAN_A10rsyocto.qar' -Info: ---------------------------------------------------------- -Info: ---------------------------------------------------------- -Info: Generated report 'a10s.archive.rpt' -Info (23030): Evaluation of Tcl script c:/intelfpga/18.1/quartus/common/tcl/apps/qpm/qar.tcl was successful -Info: Quartus Prime Shell was successful. 0 errors, 86 warnings - Info: Peak virtual memory: 4898 megabytes - Info: Processing ended: Mon Dec 16 18:03:00 2019 - Info: Elapsed time: 00:01:10 - Info: Total CPU time (on all processors): 00:01:32 - - -+--------------------------------------------------------------------------------------------------------------------+ -; Files Archived ; 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a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy_cfg.v ; -; a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca.v ; -; a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca_cfg.v ; -; a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi.sv ; -; a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv ; -; a10s_ghrd/altera_arria10_interface_generator_140/synth/hps.pre.xml ; -; a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v ; -; a10s_ghrd/altera_avalon_mm_bridge_181/synth/altera_avalon_mm_bridge.v ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.sdc ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.v ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_mm_clock_crossing_bridge.v ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_dcfifo_synchronizer_bundle.v ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_std_synchronizer_nocut.v ; -; a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v ; -; a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_onchip_memory2.hex ; -; a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v ; -; a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_b3m6h3q.v ; -; a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_na6njny.v ; -; a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_u6z2bzq.v ; -; a10s_ghrd/altera_avalon_sc_fifo_181/synth/altera_avalon_sc_fifo.v ; -; a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi.v ; -; a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi_cfg.v ; -; a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri.v ; -; a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri_cfg.v ; -; a10s_ghrd/altera_avalon_st_bytes_to_packets_181/synth/altera_avalon_st_bytes_to_packets.v ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_clock_crosser.v ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.sdc ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.v ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_pipeline_base.v ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_std_synchronizer_nocut.v ; -; a10s_ghrd/altera_avalon_st_packets_to_bytes_181/synth/altera_avalon_st_packets_to_bytes.v ; -; a10s_ghrd/altera_avalon_sysid_qsys_181/synth/a10s_ghrd_altera_avalon_sysid_qsys_181_d2s6oxq.v ; -; a10s_ghrd/altera_avalon_sysid_qsys_181/synth/a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy.v ; -; a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci.v ; -; a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci_cfg.v ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sdc ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_ip_parameters.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_parameters.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_pin_map.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_readme.txt ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_report_io_timing.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_report_timing.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_report_timing_core.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_cal.hex ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_sim.hex ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_sim.txt ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_synth.hex ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_synth.txt ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_utils.tcl ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_abphy_mux.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_afi_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_df.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_se.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_cp_i.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_i.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_o.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_i.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_o.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_unused.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_core_clks_rsts.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_amm_data_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_ast_data_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_avl_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_mmr_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_sideband_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hps_clks_rsts.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_abphy.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_oct.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_extra_clks.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_fast_sim.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_regs.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct_um_fsm.sv ; -; a10s_ghrd/altera_emif_arch_nf_181/synth/emif.pre.xml ; -; a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v ; -; a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_4ipexzi.sv ; -; a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_acw3b6a.sv ; -; a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_s3yuekq.sv ; -; a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v ; -; a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja_cfg.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_inserter.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_remover.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.sdc ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_base.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_stage.sv ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_std_synchronizer_nocut.v ; -; a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_address_alignment.sv ; -; a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_axi_master_ni.sv ; -; a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_avalon_sc_fifo.v ; -; a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_address_alignment.sv ; -; a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv ; -; a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_burst_uncompressor.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_base.v ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_stage.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_default_burst_converter.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_incr_burst_converter.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_address_alignment.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_new.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_uncmpr.sv ; -; a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_wrap_burst_converter.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_edscloq.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_uhus3qi.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq.sv ; -; a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q.sv ; -; a10s_ghrd/altera_merlin_master_agent_181/synth/altera_merlin_master_agent.sv ; -; a10s_ghrd/altera_merlin_master_translator_181/synth/altera_merlin_master_translator.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_owhafhq.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_vfnb4aq.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_zoswswa.sv ; -; a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_jalzaga.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv ; -; a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv ; -; a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_burst_uncompressor.sv ; -; a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv ; -; a10s_ghrd/altera_merlin_slave_translator_181/synth/altera_merlin_slave_translator.sv ; -; a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_sc_fifo.v ; -; a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_st_pipeline_base.v ; -; a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_reorder_memory.sv ; -; a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_traffic_limiter.sv ; -; a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_address_alignment.sv ; -; a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_burst_uncompressor.sv ; -; a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia_cfg.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_u7e5kea.v ; -; a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_u7e5kea_cfg.v ; -; a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.sdc ; -; a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.v ; -; a10s_ghrd/altera_reset_controller_181/synth/altera_reset_synchronizer.v ; -; a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_arrjpdi.sv ; -; a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_xiycpqq.sv ; -; a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_6bjmpii.sv ; -; a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_rr5nq7i.sv ; -; a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv ; -; a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v ; -; a10s_ghrd/interrupt_latency_counter_181/synth/irq_detector.v ; -; a10s_ghrd/interrupt_latency_counter_181/synth/state_machine_counter.v ; -; a10s_ghrd/SevenSigmentDisplay_10/synth/sevenSigDispaly.sv ; -; a10s_ghrd/synth/a10s_ghrd.qicache ; -; a10s_ghrd/synth/a10s_ghrd.v ; -; a10s_ghrd/synth/a10s_ghrd_cfg.v ; -; a10s_ghrd/timing_adapter_181/synth/a10s_ghrd_timing_adapter_181_v2af63i.sv ; -; c:/intelfpga/18.1/quartus/bin64/assignment_defaults.qdf ; -; HAN_FanControll_hw.tcl ; -; IP/autofan/CLOCKMEM.v ; -; IP/autofan/FAN_ONOFF.v ; -; IP/autofan/FAN_TEMP_CORE.v ; -; IP/autofan/FAN_TEMP_I2C.v ; -; IP/autofan/I2C_READ_BYTE.v ; -; IP/autofan/I2C_READ_DATA.v ; -; IP/autofan/I2C_WRITE_BYTE.v ; -; IP/autofan/I2C_WRITE_POINTER.v ; -; IP/autofan/RESET_DELY.v ; -; IP/autofan/SEG7_LUT_V.v ; -; IP/autofan/TEMP_FAN_LOOP.v ; -; IP/debounce/debounce.v ; -; IP/edge_detect/altera_edge_detector.v ; -; SevenSigmentDisplay_hw.tcl ; -+--------------------------------------------------------------------------------------------------------------------+ - - diff --git a/fpga/HAN_A10rsyocto/a10s.qpf b/fpga/HAN_A10rsyocto/a10s.qpf deleted file mode 100644 index 6715e95..0000000 --- a/fpga/HAN_A10rsyocto/a10s.qpf +++ /dev/null @@ -1,6 +0,0 @@ -DATE = "Tue Aug 15 15:32:52 2017" -QUARTUS_VERSION = "16.1" - -# Revisions - -PROJECT_REVISION = "a10s" diff --git a/fpga/HAN_A10rsyocto/a10s.qsf b/fpga/HAN_A10rsyocto/a10s.qsf deleted file mode 100644 index 361f715..0000000 --- a/fpga/HAN_A10rsyocto/a10s.qsf +++ /dev/null @@ -1,1691 +0,0 @@ -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -#============================================================ -# Build by Terasic V2.0.0 -#============================================================ - -set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AS066K3F40E2SG -set_global_assignment -name TOP_LEVEL_ENTITY "a10s" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1 -set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE AUG 15 15:32:52 2017" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLKUSR_100 -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_50_B2A -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_50_B2H -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_50_B3F -set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_50_B3H -set_location_assignment PIN_AJ18 -to CLKUSR_100 -set_location_assignment PIN_AW16 -to CLK_50_B2A -set_location_assignment PIN_AR23 -to CLK_50_B2H -set_location_assignment PIN_F3 -to CLK_50_B3F -set_location_assignment PIN_D11 -to CLK_50_B3H - -#============================================================ -# Buttons -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to CPU_RESET_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to KEY[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to KEY[1] -set_location_assignment PIN_AN18 -to CPU_RESET_n -set_location_assignment PIN_AU15 -to KEY[0] -set_location_assignment PIN_AT15 -to KEY[1] - -#============================================================ -# Swtiches -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[1] -set_location_assignment PIN_AJ19 -to SW[0] -set_location_assignment PIN_AV16 -to SW[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[1] -set_location_assignment PIN_C26 -to LED[0] -set_location_assignment PIN_B24 -to LED[1] - -#============================================================ -# HEX0 -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_D[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX0_DP -set_location_assignment PIN_AT32 -to HEX0_D[0] -set_location_assignment PIN_AR32 -to HEX0_D[1] -set_location_assignment PIN_AU32 -to HEX0_D[2] -set_location_assignment PIN_AU30 -to HEX0_D[3] -set_location_assignment PIN_AT30 -to HEX0_D[4] -set_location_assignment PIN_AU29 -to HEX0_D[5] -set_location_assignment PIN_AV29 -to HEX0_D[6] -set_location_assignment PIN_AU31 -to HEX0_DP - -#============================================================ -# HEX1 -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_D[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HEX1_DP -set_location_assignment PIN_AT28 -to HEX1_D[0] -set_location_assignment PIN_AT29 -to HEX1_D[1] -set_location_assignment PIN_AR30 -to HEX1_D[2] -set_location_assignment PIN_AM27 -to HEX1_D[3] -set_location_assignment PIN_AL27 -to HEX1_D[4] -set_location_assignment PIN_AK27 -to HEX1_D[5] -set_location_assignment PIN_AM26 -to HEX1_D[6] -set_location_assignment PIN_AR31 -to HEX1_DP - -#============================================================ -# DDR4A -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to DDR4A_REFCLK_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BG[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BG[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4A_CK -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4A_CK_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[8] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[4] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[5] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[6] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[7] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[32] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[33] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[34] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[35] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[36] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[37] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[38] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[39] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[40] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[41] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[42] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[43] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[44] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[45] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[46] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[47] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[48] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[49] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[50] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[51] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[52] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[53] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[54] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[55] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[56] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[57] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[58] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[59] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[60] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[61] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[62] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[63] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[64] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[65] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[66] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[67] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[68] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[69] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[70] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[71] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_CS_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_RESET_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_ODT -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_PAR -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_ALERT_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_ACT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_EVENT_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_AC_R[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_AC_R[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_C[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_C[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_RZQ -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_SDA -set_location_assignment PIN_AB12 -to DDR4A_REFCLK_p -set_location_assignment PIN_AC1 -to DDR4A_A[0] -set_location_assignment PIN_AB1 -to DDR4A_A[1] -set_location_assignment PIN_AB4 -to DDR4A_A[2] -set_location_assignment PIN_AA5 -to DDR4A_A[3] -set_location_assignment PIN_AA3 -to DDR4A_A[4] -set_location_assignment PIN_AA4 -to DDR4A_A[5] -set_location_assignment PIN_Y2 -to DDR4A_A[6] -set_location_assignment PIN_AA2 -to DDR4A_A[7] -set_location_assignment PIN_AB5 -to DDR4A_A[8] -set_location_assignment PIN_AB6 -to DDR4A_A[9] -set_location_assignment PIN_W5 -to DDR4A_A[10] -set_location_assignment PIN_Y5 -to DDR4A_A[11] -set_location_assignment PIN_AA9 -to DDR4A_A[12] -set_location_assignment PIN_AB7 -to DDR4A_A[13] -set_location_assignment PIN_AA7 -to DDR4A_A[14] -set_location_assignment PIN_AB10 -to DDR4A_A[15] -set_location_assignment PIN_AB11 -to DDR4A_A[16] -set_location_assignment PIN_Y7 -to DDR4A_BA[0] -set_location_assignment PIN_AB9 -to DDR4A_BA[1] -set_location_assignment PIN_AA10 -to DDR4A_BG[0] -set_location_assignment PIN_AE2 -to DDR4A_BG[1] -set_location_assignment PIN_AD3 -to DDR4A_CK -set_location_assignment PIN_AD4 -to DDR4A_CK_n -set_location_assignment PIN_AC2 -to DDR4A_CKE -set_location_assignment PIN_AE8 -to DDR4A_DQS[0] -set_location_assignment PIN_AF7 -to DDR4A_DQS[1] -set_location_assignment PIN_AN1 -to DDR4A_DQS[2] -set_location_assignment PIN_AH2 -to DDR4A_DQS[3] -set_location_assignment PIN_P1 -to DDR4A_DQS[4] -set_location_assignment PIN_J3 -to DDR4A_DQS[5] -set_location_assignment PIN_R5 -to DDR4A_DQS[6] -set_location_assignment PIN_V9 -to DDR4A_DQS[7] -set_location_assignment PIN_V2 -to DDR4A_DQS[8] -set_location_assignment PIN_AD8 -to DDR4A_DQS_n[0] -set_location_assignment PIN_AE7 -to DDR4A_DQS_n[1] -set_location_assignment PIN_AN2 -to DDR4A_DQS_n[2] -set_location_assignment PIN_AH3 -to DDR4A_DQS_n[3] -set_location_assignment PIN_R1 -to DDR4A_DQS_n[4] -set_location_assignment PIN_K3 -to DDR4A_DQS_n[5] -set_location_assignment PIN_R6 -to DDR4A_DQS_n[6] -set_location_assignment PIN_W9 -to DDR4A_DQS_n[7] -set_location_assignment PIN_V3 -to DDR4A_DQS_n[8] -set_location_assignment PIN_AC11 -to DDR4A_DQ[0] -set_location_assignment PIN_AD10 -to DDR4A_DQ[1] -set_location_assignment PIN_AC9 -to DDR4A_DQ[2] -set_location_assignment PIN_AG7 -to DDR4A_DQ[3] -set_location_assignment PIN_AD13 -to DDR4A_DQ[4] -set_location_assignment PIN_AD11 -to DDR4A_DQ[5] -set_location_assignment PIN_AC8 -to DDR4A_DQ[6] -set_location_assignment PIN_AF8 -to DDR4A_DQ[7] -set_location_assignment PIN_AE6 -to DDR4A_DQ[8] -set_location_assignment PIN_AJ6 -to DDR4A_DQ[9] -set_location_assignment PIN_AG6 -to DDR4A_DQ[10] -set_location_assignment PIN_AD6 -to DDR4A_DQ[11] -set_location_assignment PIN_AG5 -to DDR4A_DQ[12] -set_location_assignment PIN_AK5 -to DDR4A_DQ[13] -set_location_assignment PIN_AC7 -to DDR4A_DQ[14] -set_location_assignment PIN_AH6 -to DDR4A_DQ[15] -set_location_assignment PIN_AK1 -to DDR4A_DQ[16] -set_location_assignment PIN_AL4 -to DDR4A_DQ[17] -set_location_assignment PIN_AJ4 -to DDR4A_DQ[18] -set_location_assignment PIN_AM1 -to DDR4A_DQ[19] -set_location_assignment PIN_AK3 -to DDR4A_DQ[20] -set_location_assignment PIN_AL2 -to DDR4A_DQ[21] -set_location_assignment PIN_AJ3 -to DDR4A_DQ[22] -set_location_assignment PIN_AM2 -to DDR4A_DQ[23] -set_location_assignment PIN_AF2 -to DDR4A_DQ[24] -set_location_assignment PIN_AH1 -to DDR4A_DQ[25] -set_location_assignment PIN_AG4 -to DDR4A_DQ[26] -set_location_assignment PIN_AE5 -to DDR4A_DQ[27] -set_location_assignment PIN_AF3 -to DDR4A_DQ[28] -set_location_assignment PIN_AH4 -to DDR4A_DQ[29] -set_location_assignment PIN_AG1 -to DDR4A_DQ[30] -set_location_assignment PIN_AF4 -to DDR4A_DQ[31] -set_location_assignment PIN_K1 -to DDR4A_DQ[32] -set_location_assignment PIN_P4 -to DDR4A_DQ[33] -set_location_assignment PIN_N2 -to DDR4A_DQ[34] -set_location_assignment PIN_K2 -to DDR4A_DQ[35] -set_location_assignment PIN_M2 -to DDR4A_DQ[36] -set_location_assignment PIN_P3 -to DDR4A_DQ[37] -set_location_assignment PIN_N1 -to DDR4A_DQ[38] -set_location_assignment PIN_J1 -to DDR4A_DQ[39] -set_location_assignment PIN_N3 -to DDR4A_DQ[40] -set_location_assignment PIN_P5 -to DDR4A_DQ[41] -set_location_assignment PIN_M5 -to DDR4A_DQ[42] -set_location_assignment PIN_R2 -to DDR4A_DQ[43] -set_location_assignment PIN_N4 -to DDR4A_DQ[44] -set_location_assignment PIN_P6 -to DDR4A_DQ[45] -set_location_assignment PIN_L4 -to DDR4A_DQ[46] -set_location_assignment PIN_R3 -to DDR4A_DQ[47] -set_location_assignment PIN_V6 -to DDR4A_DQ[48] -set_location_assignment PIN_T7 -to DDR4A_DQ[49] -set_location_assignment PIN_U5 -to DDR4A_DQ[50] -set_location_assignment PIN_U7 -to DDR4A_DQ[51] -set_location_assignment PIN_T4 -to DDR4A_DQ[52] -set_location_assignment PIN_W6 -to DDR4A_DQ[53] -set_location_assignment PIN_T3 -to DDR4A_DQ[54] -set_location_assignment PIN_U6 -to DDR4A_DQ[55] -set_location_assignment PIN_W8 -to DDR4A_DQ[56] -set_location_assignment PIN_Y12 -to DDR4A_DQ[57] -set_location_assignment PIN_Y11 -to DDR4A_DQ[58] -set_location_assignment PIN_W10 -to DDR4A_DQ[59] -set_location_assignment PIN_Y13 -to DDR4A_DQ[60] -set_location_assignment PIN_Y8 -to DDR4A_DQ[61] -set_location_assignment PIN_Y10 -to DDR4A_DQ[62] -set_location_assignment PIN_W11 -to DDR4A_DQ[63] -set_location_assignment PIN_V1 -to DDR4A_DQ[64] -set_location_assignment PIN_Y1 -to DDR4A_DQ[65] -set_location_assignment PIN_W3 -to DDR4A_DQ[66] -set_location_assignment PIN_W1 -to DDR4A_DQ[67] -set_location_assignment PIN_Y3 -to DDR4A_DQ[68] -set_location_assignment PIN_W4 -to DDR4A_DQ[69] -set_location_assignment PIN_U1 -to DDR4A_DQ[70] -set_location_assignment PIN_U2 -to DDR4A_DQ[71] -set_location_assignment PIN_AD9 -to DDR4A_DBI_n[0] -set_location_assignment PIN_AJ5 -to DDR4A_DBI_n[1] -set_location_assignment PIN_AK2 -to DDR4A_DBI_n[2] -set_location_assignment PIN_AG2 -to DDR4A_DBI_n[3] -set_location_assignment PIN_L2 -to DDR4A_DBI_n[4] -set_location_assignment PIN_L3 -to DDR4A_DBI_n[5] -set_location_assignment PIN_U4 -to DDR4A_DBI_n[6] -set_location_assignment PIN_V8 -to DDR4A_DBI_n[7] -set_location_assignment PIN_V4 -to DDR4A_DBI_n[8] -set_location_assignment PIN_AE1 -to DDR4A_CS_n -set_location_assignment PIN_AE3 -to DDR4A_RESET_n -set_location_assignment PIN_AC3 -to DDR4A_ODT -set_location_assignment PIN_AC6 -to DDR4A_PAR -set_location_assignment PIN_AC12 -to DDR4A_ALERT_n -set_location_assignment PIN_AD1 -to DDR4A_ACT_n -set_location_assignment PIN_T5 -to DDR4A_EVENT_n -set_location_assignment PIN_AD5 -to DDR4A_AC_R[0] -set_location_assignment PIN_Y6 -to DDR4A_AC_R[1] -set_location_assignment PIN_AC4 -to DDR4A_C[0] -set_location_assignment PIN_AB2 -to DDR4A_C[1] -set_location_assignment PIN_AA8 -to DDR4A_RZQ -set_location_assignment PIN_AF5 -to DDR4A_SCL -set_location_assignment PIN_AJ1 -to DDR4A_SDA - - -#============================================================ -# DDR4B -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to DDR4B_REFCLK_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BG[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BG[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4B_CK -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4B_CK_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_CS_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_RESET_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_ODT -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_PAR -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_ALERT_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_ACT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_RZQ -set_location_assignment PIN_AU7 -to DDR4B_REFCLK_p -set_location_assignment PIN_AJ11 -to DDR4B_A[0] -set_location_assignment PIN_AH12 -to DDR4B_A[1] -set_location_assignment PIN_AP11 -to DDR4B_A[2] -set_location_assignment PIN_AN11 -to DDR4B_A[3] -set_location_assignment PIN_AM10 -to DDR4B_A[4] -set_location_assignment PIN_AM11 -to DDR4B_A[5] -set_location_assignment PIN_AP9 -to DDR4B_A[6] -set_location_assignment PIN_AN9 -to DDR4B_A[7] -set_location_assignment PIN_AR10 -to DDR4B_A[8] -set_location_assignment PIN_AP10 -to DDR4B_A[9] -set_location_assignment PIN_AM9 -to DDR4B_A[10] -set_location_assignment PIN_AL10 -to DDR4B_A[11] -set_location_assignment PIN_AV8 -to DDR4B_A[12] -set_location_assignment PIN_AT8 -to DDR4B_A[13] -set_location_assignment PIN_AT9 -to DDR4B_A[14] -set_location_assignment PIN_AR7 -to DDR4B_A[15] -set_location_assignment PIN_AR8 -to DDR4B_A[16] -set_location_assignment PIN_AU6 -to DDR4B_BA[0] -set_location_assignment PIN_AP8 -to DDR4B_BA[1] -set_location_assignment PIN_AN8 -to DDR4B_BG[0] -set_location_assignment PIN_AJ14 -to DDR4B_BG[1] -set_location_assignment PIN_AL13 -to DDR4B_CK -set_location_assignment PIN_AK13 -to DDR4B_CK_n -set_location_assignment PIN_AK10 -to DDR4B_CKE -set_location_assignment PIN_AE12 -to DDR4B_DQS[0] -set_location_assignment PIN_AL7 -to DDR4B_DQS[1] -set_location_assignment PIN_AR6 -to DDR4B_DQS[2] -set_location_assignment PIN_AT2 -to DDR4B_DQS[3] -set_location_assignment PIN_AF13 -to DDR4B_DQS_n[0] -set_location_assignment PIN_AK8 -to DDR4B_DQS_n[1] -set_location_assignment PIN_AP6 -to DDR4B_DQS_n[2] -set_location_assignment PIN_AT3 -to DDR4B_DQS_n[3] -set_location_assignment PIN_AJ9 -to DDR4B_DQ[0] -set_location_assignment PIN_AG11 -to DDR4B_DQ[1] -set_location_assignment PIN_AF9 -to DDR4B_DQ[2] -set_location_assignment PIN_AG12 -to DDR4B_DQ[3] -set_location_assignment PIN_AG9 -to DDR4B_DQ[4] -set_location_assignment PIN_AF12 -to DDR4B_DQ[5] -set_location_assignment PIN_AJ10 -to DDR4B_DQ[6] -set_location_assignment PIN_AG10 -to DDR4B_DQ[7] -set_location_assignment PIN_AL9 -to DDR4B_DQ[8] -set_location_assignment PIN_AH9 -to DDR4B_DQ[9] -set_location_assignment PIN_AK6 -to DDR4B_DQ[10] -set_location_assignment PIN_AK7 -to DDR4B_DQ[11] -set_location_assignment PIN_AH8 -to DDR4B_DQ[12] -set_location_assignment PIN_AH7 -to DDR4B_DQ[13] -set_location_assignment PIN_AJ8 -to DDR4B_DQ[14] -set_location_assignment PIN_AE11 -to DDR4B_DQ[15] -set_location_assignment PIN_AT4 -to DDR4B_DQ[16] -set_location_assignment PIN_AM7 -to DDR4B_DQ[17] -set_location_assignment PIN_AP5 -to DDR4B_DQ[18] -set_location_assignment PIN_AL5 -to DDR4B_DQ[19] -set_location_assignment PIN_AM5 -to DDR4B_DQ[20] -set_location_assignment PIN_AM6 -to DDR4B_DQ[21] -set_location_assignment PIN_AM4 -to DDR4B_DQ[22] -set_location_assignment PIN_AR5 -to DDR4B_DQ[23] -set_location_assignment PIN_AP1 -to DDR4B_DQ[24] -set_location_assignment PIN_AR3 -to DDR4B_DQ[25] -set_location_assignment PIN_AN3 -to DDR4B_DQ[26] -set_location_assignment PIN_AR1 -to DDR4B_DQ[27] -set_location_assignment PIN_AU2 -to DDR4B_DQ[28] -set_location_assignment PIN_AP4 -to DDR4B_DQ[29] -set_location_assignment PIN_AR2 -to DDR4B_DQ[30] -set_location_assignment PIN_AU1 -to DDR4B_DQ[31] -set_location_assignment PIN_AF10 -to DDR4B_DBI_n[0] -set_location_assignment PIN_AL8 -to DDR4B_DBI_n[1] -set_location_assignment PIN_AN7 -to DDR4B_DBI_n[2] -set_location_assignment PIN_AN4 -to DDR4B_DBI_n[3] -set_location_assignment PIN_AJ13 -to DDR4B_CS_n -set_location_assignment PIN_AH14 -to DDR4B_RESET_n -set_location_assignment PIN_AL12 -to DDR4B_ODT -set_location_assignment PIN_AM12 -to DDR4B_PAR -set_location_assignment PIN_AH11 -to DDR4B_ALERT_n -set_location_assignment PIN_AH13 -to DDR4B_ACT_n -set_location_assignment PIN_AW8 -to DDR4B_RZQ - -#============================================================ -# DDR4H -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to DDR4H_REFCLK_p -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[15] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_A[16] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_BG[0] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_BG[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4H_CK -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4H_CK_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4H_DQS_n[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[3] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[4] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[5] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[6] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[7] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[8] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[9] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[10] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[11] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[12] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[13] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[14] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[15] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[16] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[17] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[18] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[19] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[20] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[21] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[22] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[23] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[24] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[25] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[26] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[27] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[28] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[29] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[30] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DQ[31] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DBI_n[0] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DBI_n[1] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DBI_n[2] -set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4H_DBI_n[3] -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_CS_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4H_RESET_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_ODT -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_PAR -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_ALERT_n -set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4H_ACT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4H_RZQ -set_location_assignment PIN_M27 -to DDR4H_REFCLK_p -set_location_assignment PIN_U27 -to DDR4H_A[0] -set_location_assignment PIN_V27 -to DDR4H_A[1] -set_location_assignment PIN_P28 -to DDR4H_A[2] -set_location_assignment PIN_N27 -to DDR4H_A[3] -set_location_assignment PIN_N26 -to DDR4H_A[4] -set_location_assignment PIN_P26 -to DDR4H_A[5] -set_location_assignment PIN_R26 -to DDR4H_A[6] -set_location_assignment PIN_R25 -to DDR4H_A[7] -set_location_assignment PIN_R28 -to DDR4H_A[8] -set_location_assignment PIN_R27 -to DDR4H_A[9] -set_location_assignment PIN_T25 -to DDR4H_A[10] -set_location_assignment PIN_U25 -to DDR4H_A[11] -set_location_assignment PIN_K26 -to DDR4H_A[12] -set_location_assignment PIN_G29 -to DDR4H_A[13] -set_location_assignment PIN_H28 -to DDR4H_A[14] -set_location_assignment PIN_K28 -to DDR4H_A[15] -set_location_assignment PIN_L28 -to DDR4H_A[16] -set_location_assignment PIN_H27 -to DDR4H_BA[0] -set_location_assignment PIN_E32 -to DDR4H_BA[1] -set_location_assignment PIN_E31 -to DDR4H_BG[0] -set_location_assignment PIN_W26 -to DDR4H_BG[1] -set_location_assignment PIN_U26 -to DDR4H_CK -set_location_assignment PIN_V26 -to DDR4H_CK_n -set_location_assignment PIN_V28 -to DDR4H_CKE -set_location_assignment PIN_A20 -to DDR4H_DQS[0] -set_location_assignment PIN_B17 -to DDR4H_DQS[1] -set_location_assignment PIN_L15 -to DDR4H_DQS[2] -set_location_assignment PIN_F18 -to DDR4H_DQS[3] -set_location_assignment PIN_B20 -to DDR4H_DQS_n[0] -set_location_assignment PIN_C17 -to DDR4H_DQS_n[1] -set_location_assignment PIN_M15 -to DDR4H_DQS_n[2] -set_location_assignment PIN_F19 -to DDR4H_DQS_n[3] -set_location_assignment PIN_C19 -to DDR4H_DQ[0] -set_location_assignment PIN_B21 -to DDR4H_DQ[1] -set_location_assignment PIN_C21 -to DDR4H_DQ[2] -set_location_assignment PIN_A22 -to DDR4H_DQ[3] -set_location_assignment PIN_D19 -to DDR4H_DQ[4] -set_location_assignment PIN_B19 -to DDR4H_DQ[5] -set_location_assignment PIN_G19 -to DDR4H_DQ[6] -set_location_assignment PIN_A19 -to DDR4H_DQ[7] -set_location_assignment PIN_C18 -to DDR4H_DQ[8] -set_location_assignment PIN_B16 -to DDR4H_DQ[9] -set_location_assignment PIN_D18 -to DDR4H_DQ[10] -set_location_assignment PIN_E17 -to DDR4H_DQ[11] -set_location_assignment PIN_A17 -to DDR4H_DQ[12] -set_location_assignment PIN_A15 -to DDR4H_DQ[13] -set_location_assignment PIN_A18 -to DDR4H_DQ[14] -set_location_assignment PIN_K17 -to DDR4H_DQ[15] -set_location_assignment PIN_J16 -to DDR4H_DQ[16] -set_location_assignment PIN_G16 -to DDR4H_DQ[17] -set_location_assignment PIN_H17 -to DDR4H_DQ[18] -set_location_assignment PIN_H16 -to DDR4H_DQ[19] -set_location_assignment PIN_J15 -to DDR4H_DQ[20] -set_location_assignment PIN_G15 -to DDR4H_DQ[21] -set_location_assignment PIN_K15 -to DDR4H_DQ[22] -set_location_assignment PIN_C16 -to DDR4H_DQ[23] -set_location_assignment PIN_F20 -to DDR4H_DQ[24] -set_location_assignment PIN_D21 -to DDR4H_DQ[25] -set_location_assignment PIN_F17 -to DDR4H_DQ[26] -set_location_assignment PIN_G20 -to DDR4H_DQ[27] -set_location_assignment PIN_E21 -to DDR4H_DQ[28] -set_location_assignment PIN_C22 -to DDR4H_DQ[29] -set_location_assignment PIN_G17 -to DDR4H_DQ[30] -set_location_assignment PIN_D20 -to DDR4H_DQ[31] -set_location_assignment PIN_H18 -to DDR4H_DBI_n[0] -set_location_assignment PIN_E18 -to DDR4H_DBI_n[1] -set_location_assignment PIN_D16 -to DDR4H_DBI_n[2] -set_location_assignment PIN_E20 -to DDR4H_DBI_n[3] -set_location_assignment PIN_W25 -to DDR4H_CS_n -set_location_assignment PIN_Y26 -to DDR4H_RESET_n -set_location_assignment PIN_Y28 -to DDR4H_ODT -set_location_assignment PIN_T27 -to DDR4H_PAR -set_location_assignment PIN_A23 -to DDR4H_ALERT_n -set_location_assignment PIN_Y25 -to DDR4H_ACT_n -set_location_assignment PIN_J26 -to DDR4H_RZQ - -#============================================================ -# HDMI_TX -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to HDMI_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_TX_CLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_TX_D_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_TX_D_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_TX_D_p[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_TX_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_TX_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_TX_HPD -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_TX_CEC -set_location_assignment PIN_V31 -to HDMI_REFCLK_p -set_location_assignment PIN_V39 -to HDMI_TX_CLK_p -set_location_assignment PIN_U37 -to HDMI_TX_D_p[0] -set_location_assignment PIN_T39 -to HDMI_TX_D_p[1] -set_location_assignment PIN_R37 -to HDMI_TX_D_p[2] -set_location_assignment PIN_A25 -to HDMI_TX_SCL -set_location_assignment PIN_B25 -to HDMI_TX_SDA -set_location_assignment PIN_AF28 -to HDMI_TX_HPD -set_location_assignment PIN_AK26 -to HDMI_TX_CEC - - -#============================================================ -# HDMI_RX -#============================================================ -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_RX_CLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_RX_D_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_RX_D_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to HDMI_RX_D_p[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to HDMI_RX_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to HDMI_RX_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_RX_5V_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_RX_HPD -set_instance_assignment -name IO_STANDARD "1.8 V" -to HDMI_RX_CEC -set_instance_assignment -name IO_STANDARD "1.8 V" -to DDCSCL_RX -set_instance_assignment -name IO_STANDARD "1.8 V" -to DDCSDA_RX -set_location_assignment PIN_Y31 -to HDMI_RX_CLK_p -set_location_assignment PIN_Y35 -to HDMI_RX_D_p[0] -set_location_assignment PIN_W37 -to HDMI_RX_D_p[1] -set_location_assignment PIN_W33 -to HDMI_RX_D_p[2] -set_location_assignment PIN_V7 -to HDMI_RX_SCL -set_location_assignment PIN_T2 -to HDMI_RX_SDA -set_location_assignment PIN_AG27 -to HDMI_RX_HPD -set_location_assignment PIN_C29 -to HDMI_RX_5V_n -set_location_assignment PIN_AP29 -to HDMI_RX_CEC -set_location_assignment PIN_AN27 -to DDCSCL_RX -set_location_assignment PIN_AJ26 -to DDCSDA_RX - - -#============================================================ -# USB3 XCVR -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB_HOST_DEV_OE_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB_HOST_DEV_SEL_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB_SSFX3_PATH_OEN -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB_SSFX3_PATH_SELN -set_instance_assignment -name IO_STANDARD LVDS -to USB_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to USB_TX_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to USB_RX_p -set_location_assignment PIN_AE27 -to USB_HOST_DEV_OE_n -set_location_assignment PIN_AD26 -to USB_HOST_DEV_SEL_n -set_location_assignment PIN_AF25 -to USB_SSFX3_PATH_OE_n -set_location_assignment PIN_AE25 -to USB_SSFX3_PATH_SEL_n -set_location_assignment PIN_AB31 -to USB_REFCLK_p -set_location_assignment PIN_AB39 -to USB_TX_p -set_location_assignment PIN_AA37 -to USB_RX_p - - -#============================================================ -# USB20 -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB20_SW -set_location_assignment PIN_C27 -to USB20_SW -set_instance_assignment -name IO_STANDARD "1.8 V" -to USB20_OE_n -set_location_assignment PIN_A24 -to USB20_OE_n - - - -#============================================================ -# USBFX3 -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_RESET_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_PCLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL0_SLCS_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_UART_TX -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_UART_RX -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL10 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL11_A1 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL12_A0 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL15_INT_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL1_SLWR_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL2_SLOE_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL3_SLRD_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL4_FLAGA -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL5_FLAGB -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL6 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL7_PKTEND_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_CTL9 -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[24] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[25] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[26] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[27] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[28] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[29] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[30] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_DQ[31] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBFX3_OTG_ID -set_location_assignment PIN_AJ24 -to USBFX3_RESET_n -set_location_assignment PIN_AT27 -to USBFX3_PCLK -set_location_assignment PIN_AV26 -to USBFX3_CTL0_SLCS_n -set_location_assignment PIN_AP23 -to USBFX3_UART_TX -set_location_assignment PIN_AU27 -to USBFX3_UART_RX -set_location_assignment PIN_AU24 -to USBFX3_CTL10 -set_location_assignment PIN_AU22 -to USBFX3_CTL11_A1 -set_location_assignment PIN_AT23 -to USBFX3_CTL12_A0 -set_location_assignment PIN_AW21 -to USBFX3_CTL15_INT_n -set_location_assignment PIN_AT22 -to USBFX3_CTL1_SLWR_n -set_location_assignment PIN_AT25 -to USBFX3_CTL2_SLOE_n -set_location_assignment PIN_AR27 -to USBFX3_CTL3_SLRD_n -set_location_assignment PIN_AN22 -to USBFX3_CTL4_FLAGA -set_location_assignment PIN_AN23 -to USBFX3_CTL5_FLAGB -set_location_assignment PIN_AL24 -to USBFX3_CTL6 -set_location_assignment PIN_AL25 -to USBFX3_CTL7_PKTEND_n -set_location_assignment PIN_AV21 -to USBFX3_CTL8 -set_location_assignment PIN_AV22 -to USBFX3_CTL9 -set_location_assignment PIN_AU21 -to USBFX3_DQ[0] -set_location_assignment PIN_AW23 -to USBFX3_DQ[1] -set_location_assignment PIN_AW24 -to USBFX3_DQ[2] -set_location_assignment PIN_AW25 -to USBFX3_DQ[3] -set_location_assignment PIN_AW26 -to USBFX3_DQ[4] -set_location_assignment PIN_AV24 -to USBFX3_DQ[5] -set_location_assignment PIN_AW28 -to USBFX3_DQ[6] -set_location_assignment PIN_AW30 -to USBFX3_DQ[7] -set_location_assignment PIN_AW29 -to USBFX3_DQ[8] -set_location_assignment PIN_AV27 -to USBFX3_DQ[9] -set_location_assignment PIN_AV28 -to USBFX3_DQ[10] -set_location_assignment PIN_AU26 -to USBFX3_DQ[11] -set_location_assignment PIN_AV23 -to USBFX3_DQ[12] -set_location_assignment PIN_AU25 -to USBFX3_DQ[13] -set_location_assignment PIN_AR25 -to USBFX3_DQ[14] -set_location_assignment PIN_AP24 -to USBFX3_DQ[15] -set_location_assignment PIN_AL23 -to USBFX3_DQ[16] -set_location_assignment PIN_AM24 -to USBFX3_DQ[17] -set_location_assignment PIN_AK25 -to USBFX3_DQ[18] -set_location_assignment PIN_AM25 -to USBFX3_DQ[19] -set_location_assignment PIN_AT24 -to USBFX3_DQ[20] -set_location_assignment PIN_AR26 -to USBFX3_DQ[21] -set_location_assignment PIN_AP26 -to USBFX3_DQ[22] -set_location_assignment PIN_AP25 -to USBFX3_DQ[23] -set_location_assignment PIN_AN24 -to USBFX3_DQ[24] -set_location_assignment PIN_AN26 -to USBFX3_DQ[25] -set_location_assignment PIN_AK23 -to USBFX3_DQ[26] -set_location_assignment PIN_AJ25 -to USBFX3_DQ[27] -set_location_assignment PIN_AJ23 -to USBFX3_DQ[28] -set_location_assignment PIN_AH23 -to USBFX3_DQ[29] -set_location_assignment PIN_AR20 -to USBFX3_DQ[30] -set_location_assignment PIN_AP20 -to USBFX3_DQ[31] -set_location_assignment PIN_AG26 -to USBFX3_OTG_ID - -#============================================================ -# I2C -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to I2C_INT -set_location_assignment PIN_AH27 -to I2C_INT - -#============================================================ -# I2Cs -#============================================================ -set_instance_assignment -name IO_STANDARD "1.2 V" -to FPGA_I2C_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to FPGA_I2C_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to REFCLK0_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to REFCLK0_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to REFCLK1_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to REFCLK1_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to CDCM6208_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to CDCM6208_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_ALERT_n -set_location_assignment PIN_M1 -to FPGA_I2C_SCL -set_location_assignment PIN_M4 -to FPGA_I2C_SDA -set_location_assignment PIN_AU20 -to REFCLK0_SCL -set_location_assignment PIN_AT20 -to REFCLK0_SDA -set_location_assignment PIN_AR22 -to REFCLK1_SCL -set_location_assignment PIN_AR21 -to REFCLK1_SDA -set_location_assignment PIN_AK21 -to CDCM6208_SCL -set_location_assignment PIN_AK22 -to CDCM6208_SDA -set_location_assignment PIN_E25 -to FAN_ALERT_n - -#============================================================ -# PM -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to PM_ALERT_n -set_location_assignment PIN_D25 -to PM_ALERT_n - -#============================================================ -# FMC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK2_BIDIR_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK2_BIDIR_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK3_BIDIR_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK3_BIDIR_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK_M2C_p[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK_M2C_p[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK_M2C_n[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_CLK_M2C_n[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_p[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HA_n[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_p[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_HB_n[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[24] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[25] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[26] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[27] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[28] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[29] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[30] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[31] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[32] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_p[33] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[24] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[25] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[26] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[27] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[28] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[29] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[30] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[31] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[32] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_LA_n[33] -set_instance_assignment -name IO_STANDARD LVDS -to FMC_GBTCLK_M2C_p[0] -set_instance_assignment -name IO_STANDARD LVDS -to FMC_GBTCLK_M2C_p[1] -set_instance_assignment -name IO_STANDARD LVDS -to FMC_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_C2M_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to FMC_DP_M2C_p[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_GA[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_GA[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_RZQ -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to FMC_SDA -set_location_assignment PIN_AW18 -to FMC_CLK2_BIDIR_p -set_location_assignment PIN_AV17 -to FMC_CLK2_BIDIR_n -set_location_assignment PIN_C1 -to FMC_CLK3_BIDIR_p -set_location_assignment PIN_D1 -to FMC_CLK3_BIDIR_n -set_location_assignment PIN_K5 -to FMC_CLK_M2C_p[0] -set_location_assignment PIN_AW14 -to FMC_CLK_M2C_p[1] -set_location_assignment PIN_L5 -to FMC_CLK_M2C_n[0] -set_location_assignment PIN_AW15 -to FMC_CLK_M2C_n[1] -set_location_assignment PIN_K12 -to FMC_HA_p[0] -set_location_assignment PIN_M12 -to FMC_HA_p[1] -set_location_assignment PIN_D10 -to FMC_HA_p[2] -set_location_assignment PIN_E12 -to FMC_HA_p[3] -set_location_assignment PIN_H13 -to FMC_HA_p[4] -set_location_assignment PIN_J11 -to FMC_HA_p[5] -set_location_assignment PIN_N13 -to FMC_HA_p[6] -set_location_assignment PIN_L13 -to FMC_HA_p[7] -set_location_assignment PIN_J14 -to FMC_HA_p[8] -set_location_assignment PIN_F13 -to FMC_HA_p[9] -set_location_assignment PIN_D13 -to FMC_HA_p[10] -set_location_assignment PIN_G14 -to FMC_HA_p[11] -set_location_assignment PIN_A10 -to FMC_HA_p[12] -set_location_assignment PIN_G12 -to FMC_HA_p[13] -set_location_assignment PIN_A12 -to FMC_HA_p[14] -set_location_assignment PIN_A7 -to FMC_HA_p[15] -set_location_assignment PIN_A9 -to FMC_HA_p[16] -set_location_assignment PIN_C12 -to FMC_HA_p[17] -set_location_assignment PIN_B11 -to FMC_HA_p[18] -set_location_assignment PIN_M7 -to FMC_HA_p[19] -set_location_assignment PIN_F10 -to FMC_HA_p[20] -set_location_assignment PIN_C9 -to FMC_HA_p[21] -set_location_assignment PIN_C8 -to FMC_HA_p[22] -set_location_assignment PIN_G11 -to FMC_HA_p[23] -set_location_assignment PIN_L12 -to FMC_HA_n[0] -set_location_assignment PIN_N12 -to FMC_HA_n[1] -set_location_assignment PIN_E10 -to FMC_HA_n[2] -set_location_assignment PIN_F12 -to FMC_HA_n[3] -set_location_assignment PIN_J13 -to FMC_HA_n[4] -set_location_assignment PIN_K11 -to FMC_HA_n[5] -set_location_assignment PIN_P13 -to FMC_HA_n[6] -set_location_assignment PIN_L14 -to FMC_HA_n[7] -set_location_assignment PIN_K13 -to FMC_HA_n[8] -set_location_assignment PIN_F14 -to FMC_HA_n[9] -set_location_assignment PIN_E13 -to FMC_HA_n[10] -set_location_assignment PIN_H14 -to FMC_HA_n[11] -set_location_assignment PIN_B10 -to FMC_HA_n[12] -set_location_assignment PIN_H12 -to FMC_HA_n[13] -set_location_assignment PIN_B12 -to FMC_HA_n[14] -set_location_assignment PIN_A8 -to FMC_HA_n[15] -set_location_assignment PIN_B9 -to FMC_HA_n[16] -set_location_assignment PIN_C13 -to FMC_HA_n[17] -set_location_assignment PIN_C11 -to FMC_HA_n[18] -set_location_assignment PIN_N7 -to FMC_HA_n[19] -set_location_assignment PIN_G10 -to FMC_HA_n[20] -set_location_assignment PIN_D9 -to FMC_HA_n[21] -set_location_assignment PIN_D8 -to FMC_HA_n[22] -set_location_assignment PIN_H11 -to FMC_HA_n[23] -set_location_assignment PIN_E1 -to FMC_HB_p[0] -set_location_assignment PIN_G4 -to FMC_HB_p[1] -set_location_assignment PIN_N8 -to FMC_HB_p[2] -set_location_assignment PIN_J4 -to FMC_HB_p[3] -set_location_assignment PIN_H2 -to FMC_HB_p[4] -set_location_assignment PIN_G5 -to FMC_HB_p[5] -set_location_assignment PIN_D3 -to FMC_HB_p[6] -set_location_assignment PIN_A2 -to FMC_HB_p[7] -set_location_assignment PIN_B1 -to FMC_HB_p[8] -set_location_assignment PIN_AT13 -to FMC_HB_p[9] -set_location_assignment PIN_AM17 -to FMC_HB_p[10] -set_location_assignment PIN_AJ16 -to FMC_HB_p[11] -set_location_assignment PIN_AW13 -to FMC_HB_p[12] -set_location_assignment PIN_AV14 -to FMC_HB_p[13] -set_location_assignment PIN_AP14 -to FMC_HB_p[14] -set_location_assignment PIN_AK16 -to FMC_HB_p[15] -set_location_assignment PIN_AU16 -to FMC_HB_p[16] -set_location_assignment PIN_AT17 -to FMC_HB_p[17] -set_location_assignment PIN_AM15 -to FMC_HB_p[18] -set_location_assignment PIN_AR15 -to FMC_HB_p[19] -set_location_assignment PIN_AP16 -to FMC_HB_p[20] -set_location_assignment PIN_AV18 -to FMC_HB_p[21] -set_location_assignment PIN_E2 -to FMC_HB_n[0] -set_location_assignment PIN_H4 -to FMC_HB_n[1] -set_location_assignment PIN_P8 -to FMC_HB_n[2] -set_location_assignment PIN_J5 -to FMC_HB_n[3] -set_location_assignment PIN_H3 -to FMC_HB_n[4] -set_location_assignment PIN_H6 -to FMC_HB_n[5] -set_location_assignment PIN_E3 -to FMC_HB_n[6] -set_location_assignment PIN_B2 -to FMC_HB_n[7] -set_location_assignment PIN_C2 -to FMC_HB_n[8] -set_location_assignment PIN_AT14 -to FMC_HB_n[9] -set_location_assignment PIN_AL17 -to FMC_HB_n[10] -set_location_assignment PIN_AH16 -to FMC_HB_n[11] -set_location_assignment PIN_AV13 -to FMC_HB_n[12] -set_location_assignment PIN_AU14 -to FMC_HB_n[13] -set_location_assignment PIN_AP15 -to FMC_HB_n[14] -set_location_assignment PIN_AK17 -to FMC_HB_n[15] -set_location_assignment PIN_AU17 -to FMC_HB_n[16] -set_location_assignment PIN_AT18 -to FMC_HB_n[17] -set_location_assignment PIN_AM16 -to FMC_HB_n[18] -set_location_assignment PIN_AR16 -to FMC_HB_n[19] -set_location_assignment PIN_AN16 -to FMC_HB_n[20] -set_location_assignment PIN_AV19 -to FMC_HB_n[21] -set_location_assignment PIN_A3 -to FMC_LA_p[0] -set_location_assignment PIN_B4 -to FMC_LA_p[1] -set_location_assignment PIN_T9 -to FMC_LA_p[2] -set_location_assignment PIN_M10 -to FMC_LA_p[3] -set_location_assignment PIN_U9 -to FMC_LA_p[4] -set_location_assignment PIN_J10 -to FMC_LA_p[5] -set_location_assignment PIN_H8 -to FMC_LA_p[6] -set_location_assignment PIN_L9 -to FMC_LA_p[7] -set_location_assignment PIN_M9 -to FMC_LA_p[8] -set_location_assignment PIN_G6 -to FMC_LA_p[9] -set_location_assignment PIN_E8 -to FMC_LA_p[10] -set_location_assignment PIN_B6 -to FMC_LA_p[11] -set_location_assignment PIN_A5 -to FMC_LA_p[12] -set_location_assignment PIN_D5 -to FMC_LA_p[13] -set_location_assignment PIN_B7 -to FMC_LA_p[14] -set_location_assignment PIN_E6 -to FMC_LA_p[15] -set_location_assignment PIN_E5 -to FMC_LA_p[16] -set_location_assignment PIN_F9 -to FMC_LA_p[17] -set_location_assignment PIN_K8 -to FMC_LA_p[18] -set_location_assignment PIN_R8 -to FMC_LA_p[19] -set_location_assignment PIN_F7 -to FMC_LA_p[20] -set_location_assignment PIN_C4 -to FMC_LA_p[21] -set_location_assignment PIN_U11 -to FMC_LA_p[22] -set_location_assignment PIN_V11 -to FMC_LA_p[23] -set_location_assignment PIN_R11 -to FMC_LA_p[24] -set_location_assignment PIN_F2 -to FMC_LA_p[25] -set_location_assignment PIN_R7 -to FMC_LA_p[26] -set_location_assignment PIN_T12 -to FMC_LA_p[27] -set_location_assignment PIN_J6 -to FMC_LA_p[28] -set_location_assignment PIN_G1 -to FMC_LA_p[29] -set_location_assignment PIN_K7 -to FMC_LA_p[30] -set_location_assignment PIN_P10 -to FMC_LA_p[31] -set_location_assignment PIN_M6 -to FMC_LA_p[32] -set_location_assignment PIN_N11 -to FMC_LA_p[33] -set_location_assignment PIN_A4 -to FMC_LA_n[0] -set_location_assignment PIN_C3 -to FMC_LA_n[1] -set_location_assignment PIN_T10 -to FMC_LA_n[2] -set_location_assignment PIN_M11 -to FMC_LA_n[3] -set_location_assignment PIN_U10 -to FMC_LA_n[4] -set_location_assignment PIN_K10 -to FMC_LA_n[5] -set_location_assignment PIN_J8 -to FMC_LA_n[6] -set_location_assignment PIN_L10 -to FMC_LA_n[7] -set_location_assignment PIN_N9 -to FMC_LA_n[8] -set_location_assignment PIN_H7 -to FMC_LA_n[9] -set_location_assignment PIN_F8 -to FMC_LA_n[10] -set_location_assignment PIN_C6 -to FMC_LA_n[11] -set_location_assignment PIN_B5 -to FMC_LA_n[12] -set_location_assignment PIN_D6 -to FMC_LA_n[13] -set_location_assignment PIN_C7 -to FMC_LA_n[14] -set_location_assignment PIN_E7 -to FMC_LA_n[15] -set_location_assignment PIN_F5 -to FMC_LA_n[16] -set_location_assignment PIN_G9 -to FMC_LA_n[17] -set_location_assignment PIN_L8 -to FMC_LA_n[18] -set_location_assignment PIN_P9 -to FMC_LA_n[19] -set_location_assignment PIN_G7 -to FMC_LA_n[20] -set_location_assignment PIN_D4 -to FMC_LA_n[21] -set_location_assignment PIN_U12 -to FMC_LA_n[22] -set_location_assignment PIN_V12 -to FMC_LA_n[23] -set_location_assignment PIN_R12 -to FMC_LA_n[24] -set_location_assignment PIN_G2 -to FMC_LA_n[25] -set_location_assignment PIN_T8 -to FMC_LA_n[26] -set_location_assignment PIN_T13 -to FMC_LA_n[27] -set_location_assignment PIN_K6 -to FMC_LA_n[28] -set_location_assignment PIN_H1 -to FMC_LA_n[29] -set_location_assignment PIN_L7 -to FMC_LA_n[30] -set_location_assignment PIN_R10 -to FMC_LA_n[31] -set_location_assignment PIN_N6 -to FMC_LA_n[32] -set_location_assignment PIN_P11 -to FMC_LA_n[33] -set_location_assignment PIN_P31 -to FMC_GBTCLK_M2C_p[0] -set_location_assignment PIN_K31 -to FMC_GBTCLK_M2C_p[1] -set_location_assignment PIN_T31 -to FMC_REFCLK_p -set_location_assignment PIN_M39 -to FMC_DP_C2M_p[0] -set_location_assignment PIN_L37 -to FMC_DP_C2M_p[1] -set_location_assignment PIN_K39 -to FMC_DP_C2M_p[2] -set_location_assignment PIN_J37 -to FMC_DP_C2M_p[3] -set_location_assignment PIN_H39 -to FMC_DP_C2M_p[4] -set_location_assignment PIN_G37 -to FMC_DP_C2M_p[5] -set_location_assignment PIN_F39 -to FMC_DP_C2M_p[6] -set_location_assignment PIN_E37 -to FMC_DP_C2M_p[7] -set_location_assignment PIN_D39 -to FMC_DP_C2M_p[8] -set_location_assignment PIN_C37 -to FMC_DP_C2M_p[9] -set_location_assignment PIN_P35 -to FMC_DP_M2C_p[0] -set_location_assignment PIN_R33 -to FMC_DP_M2C_p[1] -set_location_assignment PIN_M35 -to FMC_DP_M2C_p[2] -set_location_assignment PIN_N33 -to FMC_DP_M2C_p[3] -set_location_assignment PIN_K35 -to FMC_DP_M2C_p[4] -set_location_assignment PIN_L33 -to FMC_DP_M2C_p[5] -set_location_assignment PIN_H35 -to FMC_DP_M2C_p[6] -set_location_assignment PIN_J33 -to FMC_DP_M2C_p[7] -set_location_assignment PIN_F35 -to FMC_DP_M2C_p[8] -set_location_assignment PIN_G33 -to FMC_DP_M2C_p[9] -set_location_assignment PIN_E11 -to FMC_GA[0] -set_location_assignment PIN_AL18 -to FMC_GA[1] -set_location_assignment PIN_H9 -to FMC_RZQ -set_location_assignment PIN_J9 -to FMC_SCL -set_location_assignment PIN_F4 -to FMC_SDA - -#============================================================ -# SMA -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKIN_p -set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKOUT_p -set_location_assignment PIN_AJ21 -to SMA_CLKIN_p -set_location_assignment PIN_AN21 -to SMA_CLKOUT_p - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to OB_PCIE_REFCLK_p -set_instance_assignment -name IO_STANDARD LVDS -to PCIE_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_TX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_TX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_TX_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_TX_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_RX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_RX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_RX_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to PCIE_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_WAKE_n -set_location_assignment PIN_AK31 -to OB_PCIE_REFCLK_p -set_location_assignment PIN_AH31 -to PCIE_REFCLK_p -set_location_assignment PIN_AR37 -to PCIE_TX_p[0] -set_location_assignment PIN_AP39 -to PCIE_TX_p[1] -set_location_assignment PIN_AN37 -to PCIE_TX_p[2] -set_location_assignment PIN_AM39 -to PCIE_TX_p[3] -set_location_assignment PIN_AL33 -to PCIE_RX_p[0] -set_location_assignment PIN_AM35 -to PCIE_RX_p[1] -set_location_assignment PIN_AJ33 -to PCIE_RX_p[2] -set_location_assignment PIN_AK35 -to PCIE_RX_p[3] -set_location_assignment PIN_AW20 -to PCIE_PERST_n -set_location_assignment PIN_AL19 -to PCIE_WAKE_n - -#============================================================ -# SATA -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to SATA_HOST_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_HOST_TX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_HOST_TX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_HOST_RX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_HOST_RX_p[1] -set_instance_assignment -name IO_STANDARD LVDS -to SATA_DEVICE_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_DEVICE_TX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_DEVICE_TX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_DEVICE_RX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SATA_DEVICE_RX_p[1] -set_location_assignment PIN_AF31 -to SATA_HOST_REFCLK_p -set_location_assignment PIN_AJ37 -to SATA_HOST_TX_p[0] -set_location_assignment PIN_AH39 -to SATA_HOST_TX_p[1] -set_location_assignment PIN_AE33 -to SATA_HOST_RX_p[0] -set_location_assignment PIN_AF35 -to SATA_HOST_RX_p[1] -set_location_assignment PIN_M31 -to SATA_DEVICE_REFCLK_p -set_location_assignment PIN_B39 -to SATA_DEVICE_TX_p[0] -set_location_assignment PIN_A37 -to SATA_DEVICE_TX_p[1] -set_location_assignment PIN_D35 -to SATA_DEVICE_RX_p[0] -set_location_assignment PIN_B35 -to SATA_DEVICE_RX_p[1] - -#============================================================ -# SFP+ x4 -#============================================================ -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_TXDISABLE -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_TXFAULT -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPA_TX_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPA_RX_p -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_LOS -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_MOD0_PRSNT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_MOD1_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPA_MOD2_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPA_RATESEL[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPA_RATESEL[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_TXDISABLE -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_TXFAULT -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPB_TX_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPB_RX_p -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_LOS -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_MOD0_PRSNT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_MOD1_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPB_MOD2_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPB_RATESEL[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPB_RATESEL[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_TXDISABLE -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_TXFAULT -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPC_TX_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPC_RX_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_LOS -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_MOD0_PRSNT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPC_MOD1_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPC_MOD2_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_RATESEL[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPC_RATESEL[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_TXDISABLE -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_TXFAULT -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPD_TX_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to SFPD_RX_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_LOS -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_MOD0_PRSNT_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPD_MOD1_SCL -set_instance_assignment -name IO_STANDARD "1.2 V" -to SFPD_MOD2_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_RATESEL[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SFPD_RATESEL[1] -set_instance_assignment -name IO_STANDARD LVDS -to SFP_REFCLK_p -set_location_assignment PIN_AV6 -to SFPA_TXDISABLE -set_location_assignment PIN_AP3 -to SFPA_TXFAULT -set_location_assignment PIN_AG37 -to SFPA_TX_p -set_location_assignment PIN_AD35 -to SFPA_RX_p -set_location_assignment PIN_AN6 -to SFPA_LOS -set_location_assignment PIN_AU4 -to SFPA_MOD0_PRSNT_n -set_location_assignment PIN_AW6 -to SFPA_MOD1_SCL -set_location_assignment PIN_AW5 -to SFPA_MOD2_SDA -set_location_assignment PIN_AM19 -to SFPA_RATESEL[0] -set_location_assignment PIN_AN17 -to SFPA_RATESEL[1] -set_location_assignment PIN_AU5 -to SFPB_TXDISABLE -set_location_assignment PIN_AE10 -to SFPB_TXFAULT -set_location_assignment PIN_AF39 -to SFPB_TX_p -set_location_assignment PIN_AC37 -to SFPB_RX_p -set_location_assignment PIN_AN12 -to SFPB_LOS -set_location_assignment PIN_AT5 -to SFPB_MOD0_PRSNT_n -set_location_assignment PIN_AW4 -to SFPB_MOD1_SCL -set_location_assignment PIN_AV4 -to SFPB_MOD2_SDA -set_location_assignment PIN_AR18 -to SFPB_RATESEL[0] -set_location_assignment PIN_AP18 -to SFPB_RATESEL[1] -set_location_assignment PIN_AP30 -to SFPC_TXDISABLE -set_location_assignment PIN_AP28 -to SFPC_TXFAULT -set_location_assignment PIN_AE37 -to SFPC_TX_p -set_location_assignment PIN_AC33 -to SFPC_RX_p -set_location_assignment PIN_AN28 -to SFPC_LOS -set_location_assignment PIN_B27 -to SFPC_MOD0_PRSNT_n -set_location_assignment PIN_AV3 -to SFPC_MOD1_SCL -set_location_assignment PIN_AW3 -to SFPC_MOD2_SDA -set_location_assignment PIN_AK18 -to SFPC_RATESEL[0] -set_location_assignment PIN_AR17 -to SFPC_RATESEL[1] -set_location_assignment PIN_AR28 -to SFPD_TXDISABLE -set_location_assignment PIN_AP21 -to SFPD_TXFAULT -set_location_assignment PIN_AD39 -to SFPD_TX_p -set_location_assignment PIN_AB35 -to SFPD_RX_p -set_location_assignment PIN_D26 -to SFPD_LOS -set_location_assignment PIN_AL28 -to SFPD_MOD0_PRSNT_n -set_location_assignment PIN_AV2 -to SFPD_MOD1_SCL -set_location_assignment PIN_AV1 -to SFPD_MOD2_SDA -set_location_assignment PIN_AH18 -to SFPD_RATESEL[0] -set_location_assignment PIN_AW19 -to SFPD_RATESEL[1] -set_location_assignment PIN_AD31 -to SFP_REFCLK_p - - - -#============================================================ -# DP -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to DP_REFCLK_p -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_TX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_TX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_TX_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_TX_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_RX_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_RX_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_RX_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to DP_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DP_AUX_SEL -set_instance_assignment -name IO_STANDARD "1.8 V" -to DP_AUX_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to DP_DX_SEL -set_location_assignment PIN_AM31 -to DP_REFCLK_p -set_location_assignment PIN_AW37 -to DP_TX_p[0] -set_location_assignment PIN_AV39 -to DP_TX_p[1] -set_location_assignment PIN_AU37 -to DP_TX_p[2] -set_location_assignment PIN_AT39 -to DP_TX_p[3] -set_location_assignment PIN_AV35 -to DP_RX_p[0] -set_location_assignment PIN_AT35 -to DP_RX_p[1] -set_location_assignment PIN_AN33 -to DP_RX_p[2] -set_location_assignment PIN_AP35 -to DP_RX_p[3] -set_location_assignment PIN_AC28 -to DP_AUX_SEL -set_location_assignment PIN_AM22 -to DP_AUX_p -set_location_assignment PIN_AB27 -to DP_DX_SEL - -#============================================================ -# ETH -#============================================================ -set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p -set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_INT_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_MDC -set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_MDIO -set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_RST_n -set_location_assignment PIN_AP19 -to ETH_TX_p -set_location_assignment PIN_AM20 -to ETH_RX_p -set_location_assignment PIN_AU19 -to ETH_INT_n -set_location_assignment PIN_AT19 -to ETH_MDC -set_location_assignment PIN_AJ20 -to ETH_MDIO -set_location_assignment PIN_AK20 -to ETH_RST_n - - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CLK_25 -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_GPIO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_GPIO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_GPIO[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_GPIO[3] -#set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[12] -#set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_DIO[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_I2C0_SCLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_I2C0_SDAT -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_KEY -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_RESET_n -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_RXD -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_TXD -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_STP -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_WARM_RST_n -set_location_assignment PIN_E22 -to HPS_CLK_25 -set_location_assignment PIN_J18 -to HPS_DIO[0] -set_location_assignment PIN_F22 -to HPS_DIO[1] -set_location_assignment PIN_K18 -to HPS_DIO[2] -set_location_assignment PIN_E23 -to HPS_DIO[3] -set_location_assignment PIN_G21 -to HPS_DIO[4] -set_location_assignment PIN_H21 -to HPS_DIO[5] -set_location_assignment PIN_H22 -to HPS_DIO[6] -set_location_assignment PIN_H19 -to HPS_DIO[7] -set_location_assignment PIN_D23 -to HPS_GPIO[0] -set_location_assignment PIN_C23 -to HPS_GPIO[1] -set_location_assignment PIN_F23 -to HPS_GPIO[2] -set_location_assignment PIN_G22 -to HPS_GPIO[3] -#set_location_assignment PIN_J19 -to HPS_DIO[12] -#set_location_assignment PIN_L20 -to HPS_DIO[13] -set_location_assignment PIN_J19 -to HPS_TXD -set_location_assignment PIN_L20 -to HPS_RXD -set_location_assignment PIN_F25 -to HPS_ENET_GTX_CLK -set_location_assignment PIN_D24 -to HPS_ENET_MDC -set_location_assignment PIN_C24 -to HPS_ENET_MDIO -set_location_assignment PIN_K22 -to HPS_ENET_RX_CLK -set_location_assignment PIN_H23 -to HPS_ENET_RX_DATA[0] -set_location_assignment PIN_J23 -to HPS_ENET_RX_DATA[1] -set_location_assignment PIN_F24 -to HPS_ENET_RX_DATA[2] -set_location_assignment PIN_G24 -to HPS_ENET_RX_DATA[3] -set_location_assignment PIN_L22 -to HPS_ENET_RX_DV -set_location_assignment PIN_H24 -to HPS_ENET_TX_DATA[0] -set_location_assignment PIN_J24 -to HPS_ENET_TX_DATA[1] -set_location_assignment PIN_M22 -to HPS_ENET_TX_DATA[2] -set_location_assignment PIN_M21 -to HPS_ENET_TX_DATA[3] -set_location_assignment PIN_G25 -to HPS_ENET_TX_EN -set_location_assignment PIN_B30 -to HPS_I2C0_SCLK -set_location_assignment PIN_A30 -to HPS_I2C0_SDAT -set_location_assignment PIN_A29 -to HPS_KEY -set_location_assignment PIN_D29 -to HPS_LED -set_location_assignment PIN_K21 -to HPS_RESET_n -#set_location_assignment PIN_D28 -to HPS_RXD -#set_location_assignment PIN_C28 -to HPS_TXD -set_location_assignment PIN_L25 -to HPS_USB_CLKOUT -set_location_assignment PIN_K25 -to HPS_USB_DATA[0] -set_location_assignment PIN_G26 -to HPS_USB_DATA[1] -set_location_assignment PIN_E27 -to HPS_USB_DATA[2] -set_location_assignment PIN_F27 -to HPS_USB_DATA[3] -set_location_assignment PIN_L24 -to HPS_USB_DATA[4] -set_location_assignment PIN_M24 -to HPS_USB_DATA[5] -set_location_assignment PIN_K23 -to HPS_USB_DATA[6] -set_location_assignment PIN_L23 -to HPS_USB_DATA[7] -set_location_assignment PIN_J25 -to HPS_USB_DIR -set_location_assignment PIN_H26 -to HPS_USB_NXT -set_location_assignment PIN_M25 -to HPS_USB_STP -set_location_assignment PIN_J21 -to HPS_WARM_RST_n - -#============================================================ -# MPU -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to MPU_INT -set_location_assignment PIN_E26 -to MPU_INT - -#============================================================ -# RX -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to RX_SENSE_p -set_instance_assignment -name IO_STANDARD "1.8 V" -to RX_SENSE_n -set_location_assignment PIN_AC27 -to RX_SENSE_p -set_location_assignment PIN_AC26 -to RX_SENSE_n - -#============================================================ -# SINK -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to SINK_DP_HPD -set_location_assignment PIN_AD28 -to SINK_DP_HPD - -#============================================================ -# SRC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to SRC_DP_HPD -set_location_assignment PIN_AD25 -to SRC_DP_HPD - -#============================================================ -# TYPEC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.8 V" -to TYPEC_5V_EN -set_instance_assignment -name IO_STANDARD "1.8 V" -to TYPEC_PD_SLAVE_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to TYPEC_PD_SLAVE_SDA -set_instance_assignment -name IO_STANDARD "1.8 V" -to TYPEC_PD_SCL -set_instance_assignment -name IO_STANDARD "1.8 V" -to TYPEC_PD_SDA - -set_location_assignment PIN_AT15 -to TYPEC_5V_EN -set_location_assignment PIN_AG25 -to TYPEC_PD_SLAVE_SCL -set_location_assignment PIN_AH28 -to TYPEC_PD_SLAVE_SDA -set_location_assignment PIN_AF27 -to TYPEC_PD_SCL -set_location_assignment PIN_AE26 -to TYPEC_PD_SDA - - -# DisplayPort CrossBar Setting -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBDP_SW_CNF[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBDP_SW_CNF[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to USBDP_SW_CNF[2] -set_location_assignment PIN_AA27 -to USBDP_SW_CNF[0] -set_location_assignment PIN_AB26 -to USBDP_SW_CNF[1] -set_location_assignment PIN_AB25 -to USBDP_SW_CNF[2] - - - -#============================================================ -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name ENABLE_OCT_DONE OFF -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ -set_global_assignment -name HPS_EARLY_IO_RELEASE OFF - -set_global_assignment -name VERILOG_FILE a10s.v -set_global_assignment -name VERILOG_FILE IP/autofan/TEMP_FAN_LOOP.v -set_global_assignment -name VERILOG_FILE IP/autofan/SEG7_LUT_V.v -set_global_assignment -name VERILOG_FILE IP/autofan/RESET_DELY.v -set_global_assignment -name VERILOG_FILE IP/autofan/I2C_WRITE_POINTER.v -set_global_assignment -name VERILOG_FILE IP/autofan/I2C_WRITE_BYTE.v -set_global_assignment -name VERILOG_FILE IP/autofan/I2C_READ_DATA.v -set_global_assignment -name VERILOG_FILE IP/autofan/FAN_TEMP_I2C.v -set_global_assignment -name VERILOG_FILE IP/autofan/I2C_READ_BYTE.v -set_global_assignment -name VERILOG_FILE IP/autofan/FAN_TEMP_CORE.v -set_global_assignment -name VERILOG_FILE IP/autofan/FAN_ONOFF.v -set_global_assignment -name VERILOG_FILE IP/autofan/CLOCKMEM.v -set_global_assignment -name VERILOG_FILE IP/debounce/debounce.v -set_global_assignment -name VERILOG_FILE IP/edge_detect/altera_edge_detector.v -set_global_assignment -name QSYS_FILE a10s_ghrd.qsys -set_global_assignment -name SDC_FILE a10s.sdc - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/HAN_A10rsyocto/a10s.qws b/fpga/HAN_A10rsyocto/a10s.qws deleted file mode 100644 index 1d22cd7..0000000 Binary files a/fpga/HAN_A10rsyocto/a10s.qws and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/a10s.sdc b/fpga/HAN_A10rsyocto/a10s.sdc deleted file mode 100644 index 25e547c..0000000 --- a/fpga/HAN_A10rsyocto/a10s.sdc +++ /dev/null @@ -1,91 +0,0 @@ -#************************************************************** -# This .sdc file is created by Terasic Tool. -# Users are recommended to modify this file to match users logic. -#************************************************************** - -#************************************************************** -# Create Clock -#************************************************************** -# CLOCK -create_clock -period 10 [get_ports CLKUSR_100] -create_clock -period 20 [get_ports CLK_50_B2H] -create_clock -period 20 [get_ports CLK_50_B3H] - - -create_clock -period "266.666 MHz" [get_ports DDR4H_REFCLK_p] -create_clock -period "100.000000 MHz" [get_ports PCIE_REFCLK_p] -create_clock -period "266.666 MHz" [get_ports DDR4A_REFCLK_p] -create_clock -period "266.666 MHz" [get_ports DDR4B_REFCLK_p] - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -#************************************************************** - - - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - diff --git a/fpga/HAN_A10rsyocto/a10s.v b/fpga/HAN_A10rsyocto/a10s.v deleted file mode 100644 index a3ee751..0000000 --- a/fpga/HAN_A10rsyocto/a10s.v +++ /dev/null @@ -1,552 +0,0 @@ - -// -// ######## ###### ## ## ####### ###### ######## ####### -// ## ## ## ## ## ## ## ## ## ## ## ## ## -// ## ## ## #### ## ## ## ## ## ## -// ######## ###### ## ## ## ## ## ## ## -// ## ## ## ## ## ## ## ## ## ## -// ## ## ## ## ## ## ## ## ## ## ## ## -// ## ## ###### ## ####### ###### ## ####### -// -// rsYocto reference FPGA project of the Terasic DE10 Nano Board -// created by Robin Sebastian (https://github.com/robseb) -// -// - - - -//`define ENABLE_DDR4A -//`define ENABLE_DDR4B -`define ENABLE_DDR4H -//`define ENABLE_HDMI_TX -//`define ENABLE_HDMI_RX -//`define ENABLE_PCIE -//`define ENABLE_SATA -//`define ENABLE_SFP -//`define ENABLE_DP -`define ENABLE_HPS -//`define ENABLE_TYPEC -//`define ENABLE_TYPEC_USB3_XCVR - -module a10s( - - ///////// CLOCK ///////// - input CLKUSR_100, - input CLK_50_B2H, - input CLK_50_B3H, - - ///////// Buttons ///////// - input CPU_RESET_n, - input [ 1: 0] KEY, //KEY is Low-Active - - ///////// Swtiches ///////// - input [ 1: 0] SW, - - ///////// LED ///////// - output [ 1: 0] LED, //LED is Low-Active - - ///////// HEX0 ///////// - output [ 6: 0] HEX0_D, - output HEX0_DP, - - ///////// HEX1 ///////// - output [ 6: 0] HEX1_D, - output HEX1_DP, - -`ifdef ENABLE_DDR4A - ///////// DDR4A ///////// - input DDR4A_REFCLK_p, - output [16: 0] DDR4A_A, - output [ 1: 0] DDR4A_BA, - output [ 1: 0] DDR4A_BG, - output DDR4A_CK, - output DDR4A_CK_n, - output DDR4A_CKE, - inout [ 8: 0] DDR4A_DQS, - inout [ 8: 0] DDR4A_DQS_n, - inout [71: 0] DDR4A_DQ, - inout [ 8: 0] DDR4A_DBI_n, - output DDR4A_CS_n, - output DDR4A_RESET_n, - output DDR4A_ODT, - output DDR4A_PAR, - input DDR4A_ALERT_n, - output DDR4A_ACT_n, - input DDR4A_EVENT_n, - output [ 1: 0] DDR4A_AC_R, - output [ 1: 0] DDR4A_C, - input DDR4A_RZQ, - inout DDR4A_SCL, - inout DDR4A_SDA, - -`endif /*ENABLE_DDR4A*/ - -`ifdef ENABLE_DDR4B - ///////// DDR4B ///////// - input DDR4B_REFCLK_p, - output [16: 0] DDR4B_A, - output [ 1: 0] DDR4B_BA, - output [ 1: 0] DDR4B_BG, - output DDR4B_CK, - output DDR4B_CK_n, - output DDR4B_CKE, - inout [ 3: 0] DDR4B_DQS, - inout [ 3: 0] DDR4B_DQS_n, - inout [31: 0] DDR4B_DQ, - inout [ 3: 0] DDR4B_DBI_n, - output DDR4B_CS_n, - output DDR4B_RESET_n, - output DDR4B_ODT, - output DDR4B_PAR, - input DDR4B_ALERT_n, - output DDR4B_ACT_n, - input DDR4B_RZQ, -`endif /*ENABLE_DDR4B*/ - -`ifdef ENABLE_DDR4H - ///////// DDR4H ///////// - input DDR4H_REFCLK_p, - output [16: 0] DDR4H_A, - output [ 1: 0] DDR4H_BA, - output [ 0: 0] DDR4H_BG, - output DDR4H_CK, - output DDR4H_CK_n, - output DDR4H_CKE, - inout [ 3: 0] DDR4H_DQS, - inout [ 3: 0] DDR4H_DQS_n, - inout [31: 0] DDR4H_DQ, - inout [ 3: 0] DDR4H_DBI_n, - output DDR4H_CS_n, - output DDR4H_RESET_n, - output DDR4H_ODT, - output DDR4H_PAR, - input DDR4H_ALERT_n, - output DDR4H_ACT_n, - input DDR4H_RZQ, -`endif /*ENABLE_DDR4H*/ - -`ifdef ENABLE_HDMI_TX - ///////// HDMI ///////// - input HDMI_REFCLK_p, - output HDMI_TX_CLK_p, - output [ 2: 0] HDMI_TX_D_p, - inout HDMI_TX_SCL, - inout HDMI_TX_SDA, - inout HDMI_TX_HPD, - inout HDMI_TX_CEC, -`endif /*ENABLE_HDMI*/ - - -`ifdef ENABLE_HDMI_RX - ///////// HDMI ///////// - input HDMI_RX_CLK_p, - input [ 2: 0] HDMI_RX_D_p, - inout HDMI_RX_SCL, - inout HDMI_RX_SDA, - inout HDMI_RX_HPD, - input HDMI_RX_5V_n, - inout HDMI_RX_CEC, - inout DDCSCL_RX, - inout DDCSDA_RX, -`endif /*ENABLE_HDMI*/ - - - - ///////// I2C ///////// - inout I2C_INT, - - ///////// I2Cs ///////// - inout FPGA_I2C_SCL, - inout FPGA_I2C_SDA, - inout REFCLK0_SCL, - inout REFCLK0_SDA, - inout REFCLK1_SCL, - inout REFCLK1_SDA, - inout CDCM6208_SCL, - inout CDCM6208_SDA, - input FAN_ALERT_n, - input PM_ALERT_n, - - ///////// FMC ///////// - inout FMC_CLK2_BIDIR_p, - inout FMC_CLK2_BIDIR_n, - inout FMC_CLK3_BIDIR_p, - inout FMC_CLK3_BIDIR_n, - input [ 1: 0] FMC_CLK_M2C_p, - input [ 1: 0] FMC_CLK_M2C_n, - inout [23: 0] FMC_HA_p, - inout [23: 0] FMC_HA_n, - inout [21: 0] FMC_HB_p, - inout [21: 0] FMC_HB_n, - inout [33: 0] FMC_LA_p, - inout [33: 0] FMC_LA_n, - input [ 1: 0] FMC_GBTCLK_M2C_p, - input FMC_REFCLK_p, - output [ 9: 0] FMC_DP_C2M_p, - input [ 9: 0] FMC_DP_M2C_p, - inout [ 1: 0] FMC_GA, - input FMC_RZQ, - inout FMC_SCL, - inout FMC_SDA, - - - -`ifdef ENABLE_PCIE - ///////// PCIE ///////// - input OB_PCIE_REFCLK_p, - input PCIE_REFCLK_p, - output [ 3: 0] PCIE_TX_p, - input [ 3: 0] PCIE_RX_p, - input PCIE_PERST_n, - output PCIE_WAKE_n, -`endif /*ENABLE_PCIE*/ - -`ifdef ENABLE_SATA - ///////// SATA ///////// - input SATA_HOST_REFCLK_p, - output [ 1: 0] SATA_HOST_TX_p, - input [ 1: 0] SATA_HOST_RX_p, - input SATA_DEVICE_REFCLK_p, - output [ 1: 0] SATA_DEVICE_TX_p, - input [ 1: 0] SATA_DEVICE_RX_p, -`endif /*ENABLE_SATA*/ - -`ifdef ENABLE_SFP - ///////// SFP+ x4 ///////// - output SFPA_TXDISABLE, - input SFPA_TXFAULT, - output SFPA_TX_p, - input SFPA_RX_p, - input SFPA_LOS, - input SFPA_MOD0_PRSNT_n, - inout SFPA_MOD1_SCL, - inout SFPA_MOD2_SDA, - output [ 1: 0] SFPA_RATESEL, - output SFPB_TXDISABLE, - input SFPB_TXFAULT, - output SFPB_TX_p, - input SFPB_RX_p, - input SFPB_LOS, - input SFPB_MOD0_PRSNT_n, - inout SFPB_MOD1_SCL, - inout SFPB_MOD2_SDA, - output [ 1: 0] SFPB_RATESEL, - output SFPC_TXDISABLE, - input SFPC_TXFAULT, - output SFPC_TX_p, - input SFPC_RX_p, - input SFPC_LOS, - input SFPC_MOD0_PRSNT_n, - inout SFPC_MOD1_SCL, - inout SFPC_MOD2_SDA, - output [ 1: 0] SFPC_RATESEL, - output SFPD_TXDISABLE, - input SFPD_TXFAULT, - output SFPD_TX_p, - input SFPD_RX_p, - input SFPD_LOS, - input SFPD_MOD0_PRSNT_n, - inout SFPD_MOD1_SCL, - inout SFPD_MOD2_SDA, - output [ 1: 0] SFPD_RATESEL, - input SFP_REFCLK_p, -`endif /*ENABLE_SFP*/ - - -`ifdef ENABLE_DP - ///////// DP ///////// - input DP_REFCLK_p, - output [ 3: 0] DP_TX_p, - inout DP_AUX_SEL, - output DP_AUX_p, - inout DP_DX_SEL, - input [ 3: 0] DP_RX_p, // Reserved for future -`endif /*ENABLE_DP*/ - - ///////// ETH ///////// - output ETH_TX_p, - input ETH_RX_p, - input ETH_INT_n, - output ETH_MDC, - inout ETH_MDIO, - output ETH_RST_n, - - -`ifdef ENABLE_HPS - ///////// HPS ///////// -// inout HPS_CLK_25, - inout [5: 0] HPS_DIO, - inout [3: 0] HPS_GPIO, - - output HPS_ENET_GTX_CLK, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [ 3: 0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [ 3: 0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - - inout HPS_I2C0_SCLK, - inout HPS_I2C0_SDAT, - - inout HPS_KEY, - inout HPS_LED, - -// inout HPS_RESET_n, - input HPS_RXD, - output HPS_TXD, - - input HPS_USB_CLKOUT, - inout [ 7: 0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -// inout HPS_WARM_RST_n, // note lowcase _n -`endif /*ENABLE_HPS*/ - - ///////// MPU ///////// - inout MPU_INT, - - ///////// SRC ///////// - inout SRC_DP_HPD, - -`ifdef ENABLE_TYPEC - ///////// TYPEC ///////// - input TYPEC_5V_EN, - inout TYPEC_PD_SLAVE_SCL, - inout TYPEC_PD_SLAVE_SDA, - inout TYPEC_PD_SCL, - inout TYPEC_PD_SDA, - - ///////// USB20 Switch Control ///////// - inout USB20_SW, - inout USB20_OE_n, - - ///////// DisplayPort CorssBar Setting ///////// - input [ 2: 0] USBDP_SW_CNF, -`endif /*ENABLE_TYPEC*/ - -`ifdef ENABLE_TYPEC_USB3_XCVR - ///////// USB3 ///////// - inout USB_HOST_DEV_OE_n, - inout USB_HOST_DEV_SEL_n, - inout USB_SSFX3_PATH_OE_n, - inout USB_SSFX3_PATH_SEL_n, - input USB_REFCLK_p, - output USB_TX_p, - input USB_RX_p, -`endif /*ENABLE_USB*/ - - - ///////// USBFX3 ///////// - inout USBFX3_RESET_n, - inout USBFX3_PCLK, - inout USBFX3_CTL0_SLCS_n, - inout USBFX3_UART_TX, - inout USBFX3_UART_RX, - inout USBFX3_CTL10, - input USBFX3_CTL11_A1, - inout USBFX3_CTL12_A0, - inout USBFX3_CTL15_INT_n, - inout USBFX3_CTL1_SLWR_n, - inout USBFX3_CTL2_SLOE_n, - inout USBFX3_CTL3_SLRD_n, - inout USBFX3_CTL4_FLAGA, - inout USBFX3_CTL5_FLAGB, - inout USBFX3_CTL6, - inout USBFX3_CTL7_PKTEND_n, - inout USBFX3_CTL8, - inout USBFX3_CTL9, - inout [31: 0] USBFX3_DQ, - inout USBFX3_OTG_ID, - - - ///////// SMA ///////// - input SMA_CLKIN_p, - output SMA_CLKOUT_p - -); - - -//======================================================= -// REG/WIRE declarations -//======================================================= - -// internal wires and registers declaration - wire [1:0] fpga_debounced_buttons; - wire [27:0] stm_hw_events; - wire hps_fpga_reset; - wire [2:0] hps_reset_req; - wire hps_cold_reset; - wire hps_warm_reset; - wire hps_debug_reset; - - -//======================================================= -// Structural coding -//======================================================= - -// connection of internal logics - assign stm_hw_events = {{24{1'b0}}, SW, fpga_debounced_buttons}; - -// fan control -assign RESET_N = fpga_debounced_buttons[0]; -assign MANU_AUTO_SW =0;// SW[0] ; // 1:Test,0:Auto by Temperature - - - a10s_ghrd u0 ( - .clk_100_clk (CLKUSR_100), - .clk_50_clk (CLK_50_B2H), // clk.clk - .reset_reset_n (CPU_RESET_n), // reset.reset_n - .hps_fpga_reset_reset (hps_fpga_reset), // hps_fpga_reset.reset - - // DDR4_H - .emif_a10_hps_pll_ref_clk_clock_sink_clk (DDR4H_REFCLK_p), // emif_a10_hps_pll_ref_clk_clock_sink.clk - .emif_a10_hps_oct_conduit_end_oct_rzqin (DDR4H_RZQ), // emif_a10_hps_oct_conduit_end.oct_rzqin - .emif_a10_hps_mem_conduit_end_mem_ck (DDR4H_CK), // emif_a10_hps_mem_conduit_end.mem_ck - .emif_a10_hps_mem_conduit_end_mem_ck_n (DDR4H_CK_n), // .mem_ck_n - .emif_a10_hps_mem_conduit_end_mem_a (DDR4H_A), // .mem_a - .emif_a10_hps_mem_conduit_end_mem_act_n (DDR4H_ACT_n), // .mem_act_n - .emif_a10_hps_mem_conduit_end_mem_ba (DDR4H_BA), // .mem_ba - .emif_a10_hps_mem_conduit_end_mem_bg (DDR4H_BG), // .mem_bg - .emif_a10_hps_mem_conduit_end_mem_cke (DDR4H_CKE), // .mem_cke - .emif_a10_hps_mem_conduit_end_mem_cs_n (DDR4H_CS_n), // .mem_cs_n - .emif_a10_hps_mem_conduit_end_mem_odt (DDR4H_ODT), // .mem_odt - .emif_a10_hps_mem_conduit_end_mem_reset_n (DDR4H_RESET_n), // .mem_reset_n - .emif_a10_hps_mem_conduit_end_mem_par (DDR4H_PAR), // .mem_par - .emif_a10_hps_mem_conduit_end_mem_alert_n (DDR4H_ALERT_n), // .mem_alert_n - .emif_a10_hps_mem_conduit_end_mem_dqs (DDR4H_DQS), // .mem_dqs - .emif_a10_hps_mem_conduit_end_mem_dqs_n (DDR4H_DQS_n), // .mem_dqs_n - .emif_a10_hps_mem_conduit_end_mem_dq (DDR4H_DQ), // .mem_dq - .emif_a10_hps_mem_conduit_end_mem_dbi_n (DDR4H_DBI_n), // .mem_dbi_n - - // ETHERNET - .hps_io_hps_io_phery_emac0_TX_CLK (HPS_ENET_GTX_CLK), // hps_io.hps_io_phery_emac0_TX_CLK - .hps_io_hps_io_phery_emac0_TXD0 (HPS_ENET_TX_DATA[0]), // .hps_io_phery_emac0_TXD0 - .hps_io_hps_io_phery_emac0_TXD1 (HPS_ENET_TX_DATA[1]), // .hps_io_phery_emac0_TXD1 - .hps_io_hps_io_phery_emac0_TXD2 (HPS_ENET_TX_DATA[2]), // .hps_io_phery_emac0_TXD2 - .hps_io_hps_io_phery_emac0_TXD3 (HPS_ENET_TX_DATA[3]), // .hps_io_phery_emac0_TXD3 - .hps_io_hps_io_phery_emac0_RX_CTL (HPS_ENET_RX_DV), // .hps_io_phery_emac0_RX_CTL - .hps_io_hps_io_phery_emac0_TX_CTL (HPS_ENET_TX_EN), // .hps_io_phery_emac0_TX_CTL - .hps_io_hps_io_phery_emac0_RX_CLK (HPS_ENET_RX_CLK), // .hps_io_phery_emac0_RX_CLK - .hps_io_hps_io_phery_emac0_RXD0 (HPS_ENET_RX_DATA[0]), // .hps_io_phery_emac0_RXD0 - .hps_io_hps_io_phery_emac0_RXD1 (HPS_ENET_RX_DATA[1]), // .hps_io_phery_emac0_RXD1 - .hps_io_hps_io_phery_emac0_RXD2 (HPS_ENET_RX_DATA[2]), // .hps_io_phery_emac0_RXD2 - .hps_io_hps_io_phery_emac0_RXD3 (HPS_ENET_RX_DATA[3]), // .hps_io_phery_emac0_RXD3 - .hps_io_hps_io_phery_emac0_MDIO (HPS_ENET_MDIO), // .hps_io_phery_emac0_MDIO - .hps_io_hps_io_phery_emac0_MDC (HPS_ENET_MDC), // .hps_io_phery_emac0_MDC - - // SD CARD - .hps_io_hps_io_phery_sdmmc_CMD (HPS_DIO[1]), // .hps_io_phery_sdmmc_CMD - .hps_io_hps_io_phery_sdmmc_D0 (HPS_DIO[0]), // .hps_io_phery_sdmmc_D0 - .hps_io_hps_io_phery_sdmmc_D1 (HPS_DIO[3]), // .hps_io_phery_sdmmc_D1 - .hps_io_hps_io_phery_sdmmc_D2 (HPS_DIO[4]), // .hps_io_phery_sdmmc_D2 - .hps_io_hps_io_phery_sdmmc_D3 (HPS_DIO[5]), // .hps_io_phery_sdmmc_D3 - .hps_io_hps_io_phery_sdmmc_CCLK (HPS_DIO[2]), // .hps_io_phery_sdmmc_CCLK - - // USB - .hps_io_hps_io_phery_usb0_DATA0 (HPS_USB_DATA[0]), // .hps_io_phery_usb0_DATA0 - .hps_io_hps_io_phery_usb0_DATA1 (HPS_USB_DATA[1]), // .hps_io_phery_usb0_DATA1 - .hps_io_hps_io_phery_usb0_DATA2 (HPS_USB_DATA[2]), // .hps_io_phery_usb0_DATA2 - .hps_io_hps_io_phery_usb0_DATA3 (HPS_USB_DATA[3]), // .hps_io_phery_usb0_DATA3 - .hps_io_hps_io_phery_usb0_DATA4 (HPS_USB_DATA[4]), // .hps_io_phery_usb0_DATA4 - .hps_io_hps_io_phery_usb0_DATA5 (HPS_USB_DATA[5]), // .hps_io_phery_usb0_DATA5 - .hps_io_hps_io_phery_usb0_DATA6 (HPS_USB_DATA[6]), // .hps_io_phery_usb0_DATA6 - .hps_io_hps_io_phery_usb0_DATA7 (HPS_USB_DATA[7]), // .hps_io_phery_usb0_DATA7 - .hps_io_hps_io_phery_usb0_CLK (HPS_USB_CLKOUT), // .hps_io_phery_usb0_CLK - .hps_io_hps_io_phery_usb0_STP (HPS_USB_STP), // .hps_io_phery_usb0_STP - .hps_io_hps_io_phery_usb0_DIR (HPS_USB_DIR), // .hps_io_phery_usb0_DIR - .hps_io_hps_io_phery_usb0_NXT (HPS_USB_NXT), // .hps_io_phery_usb0_NXT - - // UART - .hps_io_hps_io_phery_uart1_RX (HPS_RXD), // .hps_io_phery_uart1_RX - .hps_io_hps_io_phery_uart1_TX (HPS_TXD), // .hps_io_phery_uart1_TX - - // I2C - .hps_io_hps_io_phery_i2c0_SDA (HPS_I2C0_SDAT), // .hps_io_phery_i2c0_SDA - .hps_io_hps_io_phery_i2c0_SCL (HPS_I2C0_SCLK), // .hps_io_phery_i2c0_SCL - - // GPIO - .hps_io_hps_io_gpio_gpio1_io1 (HPS_LED), // .hps_io_gpio_gpio1_io1 - .hps_io_hps_io_gpio_gpio1_io4 (HPS_KEY), // .hps_io_gpio_gpio1_io4 - - .hps_io_hps_io_gpio_gpio2_io8 (HPS_GPIO[0]), // .hps_io_gpio_gpio2_io8 - .hps_io_hps_io_gpio_gpio2_io9 (HPS_GPIO[1]), // .hps_io_gpio_gpio2_io9 - .hps_io_hps_io_gpio_gpio2_io10 (HPS_GPIO[2]), // .hps_io_gpio_gpio2_io10 - .hps_io_hps_io_gpio_gpio2_io11 (HPS_GPIO[3]), // .hps_io_gpio_gpio2_io11 - - .led_pio_external_connection_export (LED), // led_pio_external_connection.export - .button_pio_external_connection_export (fpga_debounced_buttons), // button_pio_external_connection.export - .dipsw_pio_external_connection_export (SW), // dipsw_pio_external_connection.export - - .f2h_cold_reset_req_reset_n (~hps_cold_reset), // f2h_cold_reset_req.reset_n - .f2h_debug_reset_req_reset_n (~hps_debug_reset), // f2h_debug_reset_req.reset_n - .f2h_warm_reset_req_reset_n (~hps_warm_reset), // f2h_warm_reset_req.reset_n - .f2h_stm_hw_events_stm_hwevents (stm_hw_events), // f2h_stm_hw_events.stm_hwevents - .issp_hps_resets_source (hps_reset_req), // issp_hps_resets.source - - ///////////////////////////////////////// Seven Sig Display //////////////////////////////////////////// - - .sevensig_io_hex_d0_readdata (HEX0_D), // sevensig_io_hex_d0.readdata - .sevensig_io_hex_d1_readdata (HEX1_D), // sevensig_io_hex_d1.readdata - .sevensig_io_hex_dp0_writeresponsevalid_n (HEX0_DP), // sevensig_io_hex_dp0.writeresponsevalid_n - .sevensig_io_hex_dp1_writeresponsevalid_n (HEX1_DP), // - - ////////////////////////////////////////// FAN Controll //////////////////////////////////////////////// - - .fancmd_fan_alert_beginbursttransfer (FAN_ALERT_n), // fancmd_fan_alert.beginbursttransfer - .fancmd_io_i2c_scl_writeresponsevalid_n (FPGA_I2C_SCL), // fancmd_io_i2c_scl.writeresponsevalid_n - .fancmd_io_i2c_sda_export (FPGA_I2C_SDA), // fancmd_io_i2c_sda.export - .fancmd_status_led_writeresponsevalid_n (), // - - ); - - - - -// Debounce logic to clean out glitches within 1ms -debounce debounce_inst ( - .clk (CLKUSR_100), - .reset_n (~hps_fpga_reset), - .data_in (KEY), - .data_out (fpga_debounced_buttons) -); - defparam debounce_inst.WIDTH = 2; - defparam debounce_inst.POLARITY = "LOW"; - defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms - defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT)) - - -altera_edge_detector pulse_cold_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[0]), - .pulse_out (hps_cold_reset) -); - defparam pulse_cold_reset.PULSE_EXT = 6; - defparam pulse_cold_reset.EDGE_TYPE = 1; - defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1; - -altera_edge_detector pulse_warm_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[1]), - .pulse_out (hps_warm_reset) -); - defparam pulse_warm_reset.PULSE_EXT = 2; - defparam pulse_warm_reset.EDGE_TYPE = 1; - defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1; - -altera_edge_detector pulse_debug_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[2]), - .pulse_out (hps_debug_reset) -); - defparam pulse_debug_reset.PULSE_EXT = 32; - defparam pulse_debug_reset.EDGE_TYPE = 1; - defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1; - - -endmodule diff --git a/fpga/HAN_A10rsyocto/a10s.v.bak b/fpga/HAN_A10rsyocto/a10s.v.bak deleted file mode 100644 index ed9f416..0000000 --- a/fpga/HAN_A10rsyocto/a10s.v.bak +++ /dev/null @@ -1,595 +0,0 @@ -// ============================================================================ -// Copyright (c) 2018 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Sep 03 11:14:26 2018 -// ============================================================================ - -//`define ENABLE_DDR4A -//`define ENABLE_DDR4B -`define ENABLE_DDR4H -//`define ENABLE_HDMI_TX -//`define ENABLE_HDMI_RX -//`define ENABLE_PCIE -//`define ENABLE_SATA -//`define ENABLE_SFP -//`define ENABLE_DP -`define ENABLE_HPS -//`define ENABLE_TYPEC -//`define ENABLE_TYPEC_USB3_XCVR - -module a10s( - - ///////// CLOCK ///////// - input CLKUSR_100, - input CLK_50_B2H, - input CLK_50_B3H, - - ///////// Buttons ///////// - input CPU_RESET_n, - input [ 1: 0] KEY, //KEY is Low-Active - - ///////// Swtiches ///////// - input [ 1: 0] SW, - - ///////// LED ///////// - output [ 1: 0] LED, //LED is Low-Active - - ///////// HEX0 ///////// - output [ 6: 0] HEX0_D, - output HEX0_DP, - - ///////// HEX1 ///////// - output [ 6: 0] HEX1_D, - output HEX1_DP, - -`ifdef ENABLE_DDR4A - ///////// DDR4A ///////// - input DDR4A_REFCLK_p, - output [16: 0] DDR4A_A, - output [ 1: 0] DDR4A_BA, - output [ 1: 0] DDR4A_BG, - output DDR4A_CK, - output DDR4A_CK_n, - output DDR4A_CKE, - inout [ 8: 0] DDR4A_DQS, - inout [ 8: 0] DDR4A_DQS_n, - inout [71: 0] DDR4A_DQ, - inout [ 8: 0] DDR4A_DBI_n, - output DDR4A_CS_n, - output DDR4A_RESET_n, - output DDR4A_ODT, - output DDR4A_PAR, - input DDR4A_ALERT_n, - output DDR4A_ACT_n, - input DDR4A_EVENT_n, - output [ 1: 0] DDR4A_AC_R, - output [ 1: 0] DDR4A_C, - input DDR4A_RZQ, - inout DDR4A_SCL, - inout DDR4A_SDA, - -`endif /*ENABLE_DDR4A*/ - -`ifdef ENABLE_DDR4B - ///////// DDR4B ///////// - input DDR4B_REFCLK_p, - output [16: 0] DDR4B_A, - output [ 1: 0] DDR4B_BA, - output [ 1: 0] DDR4B_BG, - output DDR4B_CK, - output DDR4B_CK_n, - output DDR4B_CKE, - inout [ 3: 0] DDR4B_DQS, - inout [ 3: 0] DDR4B_DQS_n, - inout [31: 0] DDR4B_DQ, - inout [ 3: 0] DDR4B_DBI_n, - output DDR4B_CS_n, - output DDR4B_RESET_n, - output DDR4B_ODT, - output DDR4B_PAR, - input DDR4B_ALERT_n, - output DDR4B_ACT_n, - input DDR4B_RZQ, -`endif /*ENABLE_DDR4B*/ - -`ifdef ENABLE_DDR4H - ///////// DDR4H ///////// - input DDR4H_REFCLK_p, - output [16: 0] DDR4H_A, - output [ 1: 0] DDR4H_BA, - output [ 0: 0] DDR4H_BG, - output DDR4H_CK, - output DDR4H_CK_n, - output DDR4H_CKE, - inout [ 3: 0] DDR4H_DQS, - inout [ 3: 0] DDR4H_DQS_n, - inout [31: 0] DDR4H_DQ, - inout [ 3: 0] DDR4H_DBI_n, - output DDR4H_CS_n, - output DDR4H_RESET_n, - output DDR4H_ODT, - output DDR4H_PAR, - input DDR4H_ALERT_n, - output DDR4H_ACT_n, - input DDR4H_RZQ, -`endif /*ENABLE_DDR4H*/ - -`ifdef ENABLE_HDMI_TX - ///////// HDMI ///////// - input HDMI_REFCLK_p, - output HDMI_TX_CLK_p, - output [ 2: 0] HDMI_TX_D_p, - inout HDMI_TX_SCL, - inout HDMI_TX_SDA, - inout HDMI_TX_HPD, - inout HDMI_TX_CEC, -`endif /*ENABLE_HDMI*/ - - -`ifdef ENABLE_HDMI_RX - ///////// HDMI ///////// - input HDMI_RX_CLK_p, - input [ 2: 0] HDMI_RX_D_p, - inout HDMI_RX_SCL, - inout HDMI_RX_SDA, - inout HDMI_RX_HPD, - input HDMI_RX_5V_n, - inout HDMI_RX_CEC, - inout DDCSCL_RX, - inout DDCSDA_RX, -`endif /*ENABLE_HDMI*/ - - - - ///////// I2C ///////// - inout I2C_INT, - - ///////// I2Cs ///////// - inout FPGA_I2C_SCL, - inout FPGA_I2C_SDA, - inout REFCLK0_SCL, - inout REFCLK0_SDA, - inout REFCLK1_SCL, - inout REFCLK1_SDA, - inout CDCM6208_SCL, - inout CDCM6208_SDA, - input FAN_ALERT_n, - input PM_ALERT_n, - - ///////// FMC ///////// - inout FMC_CLK2_BIDIR_p, - inout FMC_CLK2_BIDIR_n, - inout FMC_CLK3_BIDIR_p, - inout FMC_CLK3_BIDIR_n, - input [ 1: 0] FMC_CLK_M2C_p, - input [ 1: 0] FMC_CLK_M2C_n, - inout [23: 0] FMC_HA_p, - inout [23: 0] FMC_HA_n, - inout [21: 0] FMC_HB_p, - inout [21: 0] FMC_HB_n, - inout [33: 0] FMC_LA_p, - inout [33: 0] FMC_LA_n, - input [ 1: 0] FMC_GBTCLK_M2C_p, - input FMC_REFCLK_p, - output [ 9: 0] FMC_DP_C2M_p, - input [ 9: 0] FMC_DP_M2C_p, - inout [ 1: 0] FMC_GA, - input FMC_RZQ, - inout FMC_SCL, - inout FMC_SDA, - - - -`ifdef ENABLE_PCIE - ///////// PCIE ///////// - input OB_PCIE_REFCLK_p, - input PCIE_REFCLK_p, - output [ 3: 0] PCIE_TX_p, - input [ 3: 0] PCIE_RX_p, - input PCIE_PERST_n, - output PCIE_WAKE_n, -`endif /*ENABLE_PCIE*/ - -`ifdef ENABLE_SATA - ///////// SATA ///////// - input SATA_HOST_REFCLK_p, - output [ 1: 0] SATA_HOST_TX_p, - input [ 1: 0] SATA_HOST_RX_p, - input SATA_DEVICE_REFCLK_p, - output [ 1: 0] SATA_DEVICE_TX_p, - input [ 1: 0] SATA_DEVICE_RX_p, -`endif /*ENABLE_SATA*/ - -`ifdef ENABLE_SFP - ///////// SFP+ x4 ///////// - output SFPA_TXDISABLE, - input SFPA_TXFAULT, - output SFPA_TX_p, - input SFPA_RX_p, - input SFPA_LOS, - input SFPA_MOD0_PRSNT_n, - inout SFPA_MOD1_SCL, - inout SFPA_MOD2_SDA, - output [ 1: 0] SFPA_RATESEL, - output SFPB_TXDISABLE, - input SFPB_TXFAULT, - output SFPB_TX_p, - input SFPB_RX_p, - input SFPB_LOS, - input SFPB_MOD0_PRSNT_n, - inout SFPB_MOD1_SCL, - inout SFPB_MOD2_SDA, - output [ 1: 0] SFPB_RATESEL, - output SFPC_TXDISABLE, - input SFPC_TXFAULT, - output SFPC_TX_p, - input SFPC_RX_p, - input SFPC_LOS, - input SFPC_MOD0_PRSNT_n, - inout SFPC_MOD1_SCL, - inout SFPC_MOD2_SDA, - output [ 1: 0] SFPC_RATESEL, - output SFPD_TXDISABLE, - input SFPD_TXFAULT, - output SFPD_TX_p, - input SFPD_RX_p, - input SFPD_LOS, - input SFPD_MOD0_PRSNT_n, - inout SFPD_MOD1_SCL, - inout SFPD_MOD2_SDA, - output [ 1: 0] SFPD_RATESEL, - input SFP_REFCLK_p, -`endif /*ENABLE_SFP*/ - - -`ifdef ENABLE_DP - ///////// DP ///////// - input DP_REFCLK_p, - output [ 3: 0] DP_TX_p, - inout DP_AUX_SEL, - output DP_AUX_p, - inout DP_DX_SEL, - input [ 3: 0] DP_RX_p, // Reserved for future -`endif /*ENABLE_DP*/ - - ///////// ETH ///////// - output ETH_TX_p, - input ETH_RX_p, - input ETH_INT_n, - output ETH_MDC, - inout ETH_MDIO, - output ETH_RST_n, - - -`ifdef ENABLE_HPS - ///////// HPS ///////// -// inout HPS_CLK_25, - inout [5: 0] HPS_DIO, - inout [3: 0] HPS_GPIO, - - output HPS_ENET_GTX_CLK, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [ 3: 0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [ 3: 0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - - inout HPS_I2C0_SCLK, - inout HPS_I2C0_SDAT, - - inout HPS_KEY, - inout HPS_LED, - -// inout HPS_RESET_n, - input HPS_RXD, - output HPS_TXD, - - input HPS_USB_CLKOUT, - inout [ 7: 0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -// inout HPS_WARM_RST_n, // note lowcase _n -`endif /*ENABLE_HPS*/ - - ///////// MPU ///////// - inout MPU_INT, - - ///////// SRC ///////// - inout SRC_DP_HPD, - -`ifdef ENABLE_TYPEC - ///////// TYPEC ///////// - input TYPEC_5V_EN, - inout TYPEC_PD_SLAVE_SCL, - inout TYPEC_PD_SLAVE_SDA, - inout TYPEC_PD_SCL, - inout TYPEC_PD_SDA, - - ///////// USB20 Switch Control ///////// - inout USB20_SW, - inout USB20_OE_n, - - ///////// DisplayPort CorssBar Setting ///////// - input [ 2: 0] USBDP_SW_CNF, -`endif /*ENABLE_TYPEC*/ - -`ifdef ENABLE_TYPEC_USB3_XCVR - ///////// USB3 ///////// - inout USB_HOST_DEV_OE_n, - inout USB_HOST_DEV_SEL_n, - inout USB_SSFX3_PATH_OE_n, - inout USB_SSFX3_PATH_SEL_n, - input USB_REFCLK_p, - output USB_TX_p, - input USB_RX_p, -`endif /*ENABLE_USB*/ - - - ///////// USBFX3 ///////// - inout USBFX3_RESET_n, - inout USBFX3_PCLK, - inout USBFX3_CTL0_SLCS_n, - inout USBFX3_UART_TX, - inout USBFX3_UART_RX, - inout USBFX3_CTL10, - input USBFX3_CTL11_A1, - inout USBFX3_CTL12_A0, - inout USBFX3_CTL15_INT_n, - inout USBFX3_CTL1_SLWR_n, - inout USBFX3_CTL2_SLOE_n, - inout USBFX3_CTL3_SLRD_n, - inout USBFX3_CTL4_FLAGA, - inout USBFX3_CTL5_FLAGB, - inout USBFX3_CTL6, - inout USBFX3_CTL7_PKTEND_n, - inout USBFX3_CTL8, - inout USBFX3_CTL9, - inout [31: 0] USBFX3_DQ, - inout USBFX3_OTG_ID, - - - ///////// SMA ///////// - input SMA_CLKIN_p, - output SMA_CLKOUT_p - -); - - -//======================================================= -// REG/WIRE declarations -//======================================================= - -// internal wires and registers declaration - wire [1:0] fpga_debounced_buttons; - wire [27:0] stm_hw_events; - wire hps_fpga_reset; - wire [2:0] hps_reset_req; - wire hps_cold_reset; - wire hps_warm_reset; - wire hps_debug_reset; - // for fan - wire TEMP_HI; - wire TEMP_OK; - wire TEMP_LO; - wire [7:0] FPGA_TEMP_C; - wire [7:0] BOARD_TEMP_C ; - wire [7:0] ALARM_STATUS ; - wire [7:0] FAN_DAC ; - wire [15:0]FAN_RPM; - wire RESET_N ; - wire BUSY_GO_HI; - wire BUSY ; - wire [7:0] FPGA_T_ISM; - wire MANU_AUTO_SW ; - wire [7:0] PRM ; - -//======================================================= -// Structural coding -//======================================================= - -// connection of internal logics - assign stm_hw_events = {{24{1'b0}}, SW, fpga_debounced_buttons}; - -// fan control -assign RESET_N = fpga_debounced_buttons[0]; -assign MANU_AUTO_SW =0;// SW[0] ; // 1:Test,0:Auto by Temperature - -//-------- FAN_IP EXAMPLE --- -TEMP_FAN_LOOP lp( - .OSC_50 ( CLK_50_B2H ), // 50MHZ CLOCK - .RESET_N ( RESET_N ) , // RESET - .I2C_SCL ( FPGA_I2C_SCL), // I2C SCLK ( FAN & TEMPERATURE IC ) - .I2C_SDA ( FPGA_I2C_SDA), // I2C SDA ( FAN & TEMPERATURE IC ) - - .MANU_AUTO_SW ( MANU_AUTO_SW ), // 1:Test,0:Auto by Temperature - .FPGA_T_ISM ( FPGA_T_ISM ) , - .FAN_ALERT_n ( FAN_ALERT_n ), // FAN ALARM PIN - .ALARM_STATUS ( ALARM_STATUS) , // FAN ALARM STATUS - .FAN_DAC ( FAN_DAC) , // FAN DAC - .FAN_RPM ( FAN_RPM) , // FAN RPM - .BUSY ( BUSY ), // GO HI , DATA is SAFE (READY ) - .TEMP_HI ( TEMP_HI) , // "1" FPGA TEMPERATURE IS HIGH >37 degree C - .TEMP_OK ( TEMP_OK) , // "1" FPGA TEMPERATURE IS SAFE 32~37 degree C - .TEMP_LO ( TEMP_LO) , // "1" FPGA TEMPERATURE IS LOW < 32 degree C - .FPGA_TEMP_C ( FPGA_TEMP_C ) , // FPGA TEMPERATURE degree C - .BOARD_TEMP_C ( BOARD_TEMP_C) , // BOARD TEMPERATURE degree C - //--test-- - .BUSY_GO_HI ( BUSY_GO_HI ) -); -//-------- FAN_IP EXAMPLE END -------- - -//---HEX Display SW 1= RPM*100 , 0= FPGA_Temperature -assign PRM =FAN_RPM/100 ; - -SEG7_LUT_V t1(.iDIG( (!SW[1]? FPGA_TEMP_C :PRM )%10), .oSEG(HEX0_D)); -SEG7_LUT_V t2(.iDIG( ((!SW[1]? FPGA_TEMP_C :PRM )/10)%10),.oSEG(HEX1_D)); - -assign { HEX1_DP , HEX0_DP } =2'b10 ; - - a10s_ghrd u0 ( - .clk_100_clk (CLKUSR_100), // clk.clk - .reset_reset_n (CPU_RESET_n), // reset.reset_n - .hps_fpga_reset_reset (hps_fpga_reset), // hps_fpga_reset.reset - - // DDR4_H - .emif_a10_hps_pll_ref_clk_clock_sink_clk (DDR4H_REFCLK_p), // emif_a10_hps_pll_ref_clk_clock_sink.clk - .emif_a10_hps_oct_conduit_end_oct_rzqin (DDR4H_RZQ), // emif_a10_hps_oct_conduit_end.oct_rzqin - .emif_a10_hps_mem_conduit_end_mem_ck (DDR4H_CK), // emif_a10_hps_mem_conduit_end.mem_ck - .emif_a10_hps_mem_conduit_end_mem_ck_n (DDR4H_CK_n), // .mem_ck_n - .emif_a10_hps_mem_conduit_end_mem_a (DDR4H_A), // .mem_a - .emif_a10_hps_mem_conduit_end_mem_act_n (DDR4H_ACT_n), // .mem_act_n - .emif_a10_hps_mem_conduit_end_mem_ba (DDR4H_BA), // .mem_ba - .emif_a10_hps_mem_conduit_end_mem_bg (DDR4H_BG), // .mem_bg - .emif_a10_hps_mem_conduit_end_mem_cke (DDR4H_CKE), // .mem_cke - .emif_a10_hps_mem_conduit_end_mem_cs_n (DDR4H_CS_n), // .mem_cs_n - .emif_a10_hps_mem_conduit_end_mem_odt (DDR4H_ODT), // .mem_odt - .emif_a10_hps_mem_conduit_end_mem_reset_n (DDR4H_RESET_n), // .mem_reset_n - .emif_a10_hps_mem_conduit_end_mem_par (DDR4H_PAR), // .mem_par - .emif_a10_hps_mem_conduit_end_mem_alert_n (DDR4H_ALERT_n), // .mem_alert_n - .emif_a10_hps_mem_conduit_end_mem_dqs (DDR4H_DQS), // .mem_dqs - .emif_a10_hps_mem_conduit_end_mem_dqs_n (DDR4H_DQS_n), // .mem_dqs_n - .emif_a10_hps_mem_conduit_end_mem_dq (DDR4H_DQ), // .mem_dq - .emif_a10_hps_mem_conduit_end_mem_dbi_n (DDR4H_DBI_n), // .mem_dbi_n - - // ETHERNET - .hps_io_hps_io_phery_emac0_TX_CLK (HPS_ENET_GTX_CLK), // hps_io.hps_io_phery_emac0_TX_CLK - .hps_io_hps_io_phery_emac0_TXD0 (HPS_ENET_TX_DATA[0]), // .hps_io_phery_emac0_TXD0 - .hps_io_hps_io_phery_emac0_TXD1 (HPS_ENET_TX_DATA[1]), // .hps_io_phery_emac0_TXD1 - .hps_io_hps_io_phery_emac0_TXD2 (HPS_ENET_TX_DATA[2]), // .hps_io_phery_emac0_TXD2 - .hps_io_hps_io_phery_emac0_TXD3 (HPS_ENET_TX_DATA[3]), // .hps_io_phery_emac0_TXD3 - .hps_io_hps_io_phery_emac0_RX_CTL (HPS_ENET_RX_DV), // .hps_io_phery_emac0_RX_CTL - .hps_io_hps_io_phery_emac0_TX_CTL (HPS_ENET_TX_EN), // .hps_io_phery_emac0_TX_CTL - .hps_io_hps_io_phery_emac0_RX_CLK (HPS_ENET_RX_CLK), // .hps_io_phery_emac0_RX_CLK - .hps_io_hps_io_phery_emac0_RXD0 (HPS_ENET_RX_DATA[0]), // .hps_io_phery_emac0_RXD0 - .hps_io_hps_io_phery_emac0_RXD1 (HPS_ENET_RX_DATA[1]), // .hps_io_phery_emac0_RXD1 - .hps_io_hps_io_phery_emac0_RXD2 (HPS_ENET_RX_DATA[2]), // .hps_io_phery_emac0_RXD2 - .hps_io_hps_io_phery_emac0_RXD3 (HPS_ENET_RX_DATA[3]), // .hps_io_phery_emac0_RXD3 - .hps_io_hps_io_phery_emac0_MDIO (HPS_ENET_MDIO), // .hps_io_phery_emac0_MDIO - .hps_io_hps_io_phery_emac0_MDC (HPS_ENET_MDC), // .hps_io_phery_emac0_MDC - - // SD CARD - .hps_io_hps_io_phery_sdmmc_CMD (HPS_DIO[1]), // .hps_io_phery_sdmmc_CMD - .hps_io_hps_io_phery_sdmmc_D0 (HPS_DIO[0]), // .hps_io_phery_sdmmc_D0 - .hps_io_hps_io_phery_sdmmc_D1 (HPS_DIO[3]), // .hps_io_phery_sdmmc_D1 - .hps_io_hps_io_phery_sdmmc_D2 (HPS_DIO[4]), // .hps_io_phery_sdmmc_D2 - .hps_io_hps_io_phery_sdmmc_D3 (HPS_DIO[5]), // .hps_io_phery_sdmmc_D3 - .hps_io_hps_io_phery_sdmmc_CCLK (HPS_DIO[2]), // .hps_io_phery_sdmmc_CCLK - - // USB - .hps_io_hps_io_phery_usb0_DATA0 (HPS_USB_DATA[0]), // .hps_io_phery_usb0_DATA0 - .hps_io_hps_io_phery_usb0_DATA1 (HPS_USB_DATA[1]), // .hps_io_phery_usb0_DATA1 - .hps_io_hps_io_phery_usb0_DATA2 (HPS_USB_DATA[2]), // .hps_io_phery_usb0_DATA2 - .hps_io_hps_io_phery_usb0_DATA3 (HPS_USB_DATA[3]), // .hps_io_phery_usb0_DATA3 - .hps_io_hps_io_phery_usb0_DATA4 (HPS_USB_DATA[4]), // .hps_io_phery_usb0_DATA4 - .hps_io_hps_io_phery_usb0_DATA5 (HPS_USB_DATA[5]), // .hps_io_phery_usb0_DATA5 - .hps_io_hps_io_phery_usb0_DATA6 (HPS_USB_DATA[6]), // .hps_io_phery_usb0_DATA6 - .hps_io_hps_io_phery_usb0_DATA7 (HPS_USB_DATA[7]), // .hps_io_phery_usb0_DATA7 - .hps_io_hps_io_phery_usb0_CLK (HPS_USB_CLKOUT), // .hps_io_phery_usb0_CLK - .hps_io_hps_io_phery_usb0_STP (HPS_USB_STP), // .hps_io_phery_usb0_STP - .hps_io_hps_io_phery_usb0_DIR (HPS_USB_DIR), // .hps_io_phery_usb0_DIR - .hps_io_hps_io_phery_usb0_NXT (HPS_USB_NXT), // .hps_io_phery_usb0_NXT - - // UART - .hps_io_hps_io_phery_uart1_RX (HPS_RXD), // .hps_io_phery_uart1_RX - .hps_io_hps_io_phery_uart1_TX (HPS_TXD), // .hps_io_phery_uart1_TX - - // I2C - .hps_io_hps_io_phery_i2c0_SDA (HPS_I2C0_SDAT), // .hps_io_phery_i2c0_SDA - .hps_io_hps_io_phery_i2c0_SCL (HPS_I2C0_SCLK), // .hps_io_phery_i2c0_SCL - - // GPIO - .hps_io_hps_io_gpio_gpio1_io1 (HPS_LED), // .hps_io_gpio_gpio1_io1 - .hps_io_hps_io_gpio_gpio1_io4 (HPS_KEY), // .hps_io_gpio_gpio1_io4 - - .hps_io_hps_io_gpio_gpio2_io8 (HPS_GPIO[0]), // .hps_io_gpio_gpio2_io8 - .hps_io_hps_io_gpio_gpio2_io9 (HPS_GPIO[1]), // .hps_io_gpio_gpio2_io9 - .hps_io_hps_io_gpio_gpio2_io10 (HPS_GPIO[2]), // .hps_io_gpio_gpio2_io10 - .hps_io_hps_io_gpio_gpio2_io11 (HPS_GPIO[3]), // .hps_io_gpio_gpio2_io11 - - .led_pio_external_connection_export (LED), // led_pio_external_connection.export - .button_pio_external_connection_export (fpga_debounced_buttons), // button_pio_external_connection.export - .dipsw_pio_external_connection_export (SW), // dipsw_pio_external_connection.export - - .f2h_cold_reset_req_reset_n (~hps_cold_reset), // f2h_cold_reset_req.reset_n - .f2h_debug_reset_req_reset_n (~hps_debug_reset), // f2h_debug_reset_req.reset_n - .f2h_warm_reset_req_reset_n (~hps_warm_reset), // f2h_warm_reset_req.reset_n - .f2h_stm_hw_events_stm_hwevents (stm_hw_events), // f2h_stm_hw_events.stm_hwevents - .issp_hps_resets_source (hps_reset_req) // issp_hps_resets.source - ); - - -// Debounce logic to clean out glitches within 1ms -debounce debounce_inst ( - .clk (CLKUSR_100), - .reset_n (~hps_fpga_reset), - .data_in (KEY), - .data_out (fpga_debounced_buttons) -); - defparam debounce_inst.WIDTH = 2; - defparam debounce_inst.POLARITY = "LOW"; - defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms - defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT)) - - -altera_edge_detector pulse_cold_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[0]), - .pulse_out (hps_cold_reset) -); - defparam pulse_cold_reset.PULSE_EXT = 6; - defparam pulse_cold_reset.EDGE_TYPE = 1; - defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1; - -altera_edge_detector pulse_warm_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[1]), - .pulse_out (hps_warm_reset) -); - defparam pulse_warm_reset.PULSE_EXT = 2; - defparam pulse_warm_reset.EDGE_TYPE = 1; - defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1; - -altera_edge_detector pulse_debug_reset ( - .clk (CLKUSR_100), - .rst_n (~hps_fpga_reset), - .signal_in (hps_reset_req[2]), - .pulse_out (hps_debug_reset) -); - defparam pulse_debug_reset.PULSE_EXT = 32; - defparam pulse_debug_reset.EDGE_TYPE = 1; - defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1; - - -endmodule diff --git a/fpga/HAN_A10rsyocto/a10s_ghrd.qsys b/fpga/HAN_A10rsyocto/a10s_ghrd.qsys deleted file mode 100644 index 76bada2..0000000 --- a/fpga/HAN_A10rsyocto/a10s_ghrd.qsys +++ /dev/null @@ -1,2212 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDMMC:D0,SDMMC:CMD,SDMMC:CCLK,SDMMC:D1,SDMMC:D2,SDMMC:D3,NONE,NONE,GPIO,GPIO,GPIO,GPIO,UART1:TX,UART1:RX,USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,NONE,GPIO,I2C0:SDA,I2C0:SCL,GPIO,NONE,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC,NONE,NONE,NONE,NONE,NONE,NONE,NONE,NONE,NONE,NONE,NONE,NONE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DDR3_CTRL_ADDR_ORDER_CS_R_B_C - - - - CTRL_AVL_PROTOCOL_ST - - - - - - - - - - - - - - - DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG - - - - CTRL_AVL_PROTOCOL_ST - - - - - - - - - - - - - - - LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C - - - - CTRL_AVL_PROTOCOL_ST - - - - - - - - - - - - - - - CTRL_AVL_PROTOCOL_MM - - - - - CTRL_AVL_PROTOCOL_MM - CTRL_AVL_PROTOCOL_MM - RLD3_CTRL_ADDR_ORDER_CS_R_B_C - CTRL_AVL_PROTOCOL_MM - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - - - - - - - - - FAST_SIM_OVERRIDE_DEFAULT - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - SOFT_NIOS_MODE_DISABLED - - - - - - - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - DDR3_ALERT_N_PLACEMENT_AC_LANES - - - - - - - - - - - - - - - - - - - - - - - - - DDR3_RTT_NOM_ODT_DISABLED - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - DDR4_AC_PARITY_LATENCY_DISABLE - - - - - DDR4_ALERT_N_PLACEMENT_DATA_LANES - - DDR4_ASR_MANUAL_NORMAL - - - - - - - - - - - DDR4_DB_DRV_STR_RZQ_7 - DDR4_DB_RTT_NOM_ODT_DISABLED - DDR4_DB_RTT_PARK_ODT_DISABLED - DDR4_DB_RTT_WR_RZQ_3 - - - - - - - - - DDR4_FINE_REFRESH_FIXED_1X - - - - - - - - - - DDR4_MPR_READ_FORMAT_SERIAL - - - - - - DDR4_RCD_CKE_IBT_100 - - DDR4_RCD_ODT_IBT_100 - - - - - - DDR4_RTT_PARK_ODT_DISABLED - DDR4_RTT_WR_ODT_DISABLED - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DDR4_TEMP_CONTROLLED_RFSH_NORMAL - - - - - - - - - - - - - - - - - - - - - - - - DDR4_VREFDQ_TRAINING_RANGE_1 - - - - - - - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - LPDDR3_DQODT_DISABLE - - LPDDR3_DRV_STR_40D_40U - LPDDR3_PDODT_DISABLED - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - LPDDR3_SPEEDBIN_1600 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - - - - - - - - - - - - - - - - - QDR4_OUTPUT_DRIVE_25_PCT - QDR4_OUTPUT_DRIVE_25_PCT - - - - - - - - - - - - - - RLD2_CONFIG_TRC_8_TRL_8_TWL_9 - - - RLD2_DRIVE_IMPEDENCE_INTERNAL_50 - - - - - - - - - - - - - - - - - - - - - - - - - RLD3_OUTPUT_DRIVE_40 - - - - - - - - - - - - - - - - - - - - - CONFIG_PHY_AND_HARD_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - CONFIG_PHY_AND_HARD_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - CONFIG_PHY_AND_HARD_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - CONFIG_PHY_AND_SOFT_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - CONFIG_PHY_AND_SOFT_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - CONFIG_PHY_AND_SOFT_CTRL - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - - CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - PERIODIC_OCT_RECAL_AUTO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_emif_a10_hps - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_onchip_memory2 - - - - - - ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/a10s_ghrd.sopcinfo b/fpga/HAN_A10rsyocto/a10s_ghrd.sopcinfo deleted file mode 100644 index bf9a206..0000000 --- a/fpga/HAN_A10rsyocto/a10s_ghrd.sopcinfo +++ /dev/null @@ -1,74083 +0,0 @@ - - - - - - - java.lang.Integer - 1576500538 - false - true - false - true - GENERATION_ID - - - java.lang.String - - false - true - false - true - UNIQUE_ID - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - clk_100 - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - clk_100 - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - clk_100 - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - clk_50 - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - clk_50 - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - clk_50 - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - emif_a10_hps_pll_ref_clk_clock_sink - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - emif_a10_hps_pll_ref_clk_clock_sink - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - emif_a10_hps_pll_ref_clk_clock_sink - - - java.lang.String - Arria 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - embeddedsw.dts.compatible - altr,ilc-1.0 - - - embeddedsw.dts.group - ilc - - - embeddedsw.dts.name - altera_ilc - - - embeddedsw.dts.params.altr,sw-fifo-depth - 32 - - - embeddedsw.dts.vendor - altr - - - int - 0 - false - true - true - true - - - int - 100000000 - false - true - true - true - CLOCK_RATE - clk - - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset_n - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq - Input - 2 - irq - - - false - button_pio - irq - button_pio.irq - 0 - - - false - dipsw_pio - irq - dipsw_pio.irq - 1 - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 256 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avmm_addr - Input - 6 - address - - - avmm_wrdata - Input - 32 - writedata - - - avmm_write - Input - 1 - write - - - avmm_read - Input - 1 - read - - - avmm_rddata - Output - 32 - readdata - - - - - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 1 - false - false - true - true - - - int - 6 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 6 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 4 - false - true - false - true - - - int - 32 - false - true - true - true - - - [Ljava.lang.String; - 0,1,2,3,4,5,6,7 - true - true - true - true - - - [Ljava.lang.String; - No,No,No,No,No,No,No,No - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - double - 25.0 - false - true - true - true - - - int - 0 - true - true - false - true - - - int - 60 - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 200 - false - false - true - true - - - int - 100000000 - false - true - false - true - CLOCK_RATE - f2h_axi_clock - - - int - 100000000 - false - true - false - true - CLOCK_RATE - h2f_axi_clock - - - int - 100000000 - false - true - false - true - CLOCK_RATE - h2f_lw_axi_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram0_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram1_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram2_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram3_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram4_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram5_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - h2f_cti_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - h2f_tpiu_clock_in - - - int - 100 - false - true - false - true - CLOCK_RATE - h2f_debug_apb_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - emac_ptp_ref_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - emac0_rx_clk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - emac0_tx_clk_in - - - double - 2.5 - false - false - true - true - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - emac1_rx_clk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - emac1_tx_clk_in - - - double - 2.5 - false - false - true - true - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - emac2_rx_clk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - emac2_tx_clk_in - - - double - 2.5 - false - false - true - true - - - int - 100 - false - false - true - true - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - sdmmc_clk_in - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - usb0_clk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - usb1_clk_in - - - int - 100 - false - false - true - true - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - spis0_sclk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - spis1_sclk_in - - - int - 100 - false - true - false - true - CLOCK_RATE - i2c0_scl_in - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - i2c1_scl_in - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - i2cemac0_scl_in - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - i2cemac1_scl_in - - - int - 100 - false - false - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - i2cemac2_scl_in - - - int - 100 - false - false - true - true - - - int - 1000 - true - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 800 - false - false - true - true - - - boolean - false - false - true - true - true - - - int - 400 - false - false - true - true - - - boolean - false - false - true - true - true - - - int - 400 - false - false - true - true - - - int - 800 - false - true - false - true - - - int - 100 - false - true - false - true - - - int - 200 - false - true - false - true - - - int - 4 - false - true - false - true - - - int - 200 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 125 - false - true - true - true - - - int - 32000 - true - true - false - true - - - int - 250 - false - true - true - true - - - int - 250 - false - false - true - true - - - int - 250 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 2000 - false - false - false - true - - - int - 1000 - true - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 159 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 9 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 159 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 7 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 19 - true - true - false - true - - - int - 499 - true - true - false - true - - - int - 9 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - int - 900 - true - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - int - 8 - false - false - false - true - - - int - 8 - false - false - false - true - - - int - 16 - false - false - false - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - [Ljava.lang.String; - - true - true - false - true - - - [Ljava.lang.String; - - true - true - false - true - - - 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Q2_1,F25,Q2_2,G25,Q2_3,K22,Q2_4,L22,Q2_5,H24,Q2_6,J24,Q2_7,H23,Q2_8,J23,Q2_10,M21,Q2_9,M22,Q2_11,F24,Q2_12,G24,D_4,J18,D_5,F22,D_6,K18,D_7,E23,D_8,G21,D_9,H21,Q3_1,C29,Q3_2,D29,Q3_3,A30,Q3_4,B30,Q3_5,A29,Q3_6,B29,Q3_7,C28,Q3_8,D28,D_10,H22,Q3_9,A28,D_11,H19,D_12,D23,D_13,C23,D_14,F23,D_15,G22,D_16,J19,D_17,L20,Q3_10,A27,Q4_1,B27,Q3_11,C24,Q4_2,C27,Q3_12,D24,Q4_3,D26,Q4_4,E26,Q4_5,D25,Q4_6,E25,Q4_7,A25,Q4_8,B25,Q4_9,A24,Q1_10,M24,Q1_1,L25,Q1_11,K23,Q1_2,M25,Q1_12,L23,Q1_3,J25,Q1_4,K25,Q1_5,G26,Q1_6,H26,Q1_7,E27,Q1_8,F27,Q1_9,L24,Q4_10,B24,Q4_11,B26,Q4_12,C26 - true - true - false - true - - - java.lang.String - ARRIA10 - true - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_enable_sdmmc_clk_in - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_enable_test_interface - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_enable_jtag - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_enable_a10_advanced_options - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_boot_from_fpga_ready - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_override_sdmmc_4bit - - - boolean - false - false - true - false - true - QUARTUS_INI - hps_ip_overide_f2sdram_delay - - - java.lang.String - DFT_IN_ADVANCE 1 input DFT_IN_ATPG_CLK_SEL_N 1 input DFT_IN_ATPG_MODE_N 1 input DFT_IN_BIST_CPU_SI 1 input DFT_IN_BIST_L2_SI 1 input DFT_IN_BIST_PERI_SI 3 input DFT_IN_BIST_RST_N 1 input DFT_IN_BIST_SE_N 1 input DFT_IN_BISTCLK 1 input DFT_IN_BISTEN_N 1 input DFT_IN_BWADJ 12 input DFT_IN_CLKF 13 input DFT_IN_CLKOD 11 input DFT_IN_CLKOD_CTL 1 input DFT_IN_CLKOD_SCANCLK 1 input DFT_IN_CLKOD_SCANIN 1 input DFT_IN_CLKR 6 input DFT_IN_COMPRESS_ENABLE_N 1 input DFT_IN_ECCBYP_N 1 input DFT_IN_ENSAT 1 input DFT_IN_FASTEN 1 input DFT_IN_FREECLK_EN_N 1 input DFT_IN_IO_CONTROL 20 input DFT_IN_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_IO_TEST_MODE_N 1 input DFT_IN_JTAG_MODE 1 input DFT_IN_JTAG_UPDATE_DR 1 input DFT_IN_JTGHIGHZ 1 input DFT_IN_L4MPCLK_DIV_CTL_N 1 input DFT_IN_MAINPLL_BG_PWRDN 1 input DFT_IN_MAINPLL_BG_RESET 1 input DFT_IN_MAINPLL_REG_PWRDN 1 input DFT_IN_MAINPLL_REG_RESET 1 input DFT_IN_MAINPLL_REG_TEST_SEL 1 input DFT_IN_MEM_CPU_SI 1 input DFT_IN_MEM_L2_SI 1 input DFT_IN_MEM_PERI_SI 3 input DFT_IN_MEM_SE_N 1 input DFT_IN_MPFE_ATPG_MODE_N 1 input DFT_IN_MPFE_CLK_SEL_N 1 input DFT_IN_MPFE_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_MPFE_OCC_BYPASS_N 1 input DFT_IN_MPFE_OCC_ENABLE_N 1 input DFT_IN_MPFE_OCC_SI 1 input DFT_IN_MPFE_PIPELINE_SCAN_EN_N 1 input DFT_IN_MPFE_SCANEN_N 1 input DFT_IN_MPFE_SCANIN 14 input DFT_IN_MPFE_TEST_CLK_0 1 input DFT_IN_MPFE_TEST_CLK_1 1 input DFT_IN_MPFE_TEST_CLK_2 1 input DFT_IN_MPFE_TEST_CLOCK_EN_N 1 input DFT_IN_MPFE_TEST_MODE_N 1 input DFT_IN_MTESTEN_N 1 input DFT_IN_NOC_LEFT_SCANIN 15 input DFT_IN_NOC_RIGHT_SCANIN 10 input DFT_IN_OCC_ENABLE_N 1 input DFT_IN_OUTRESET 1 input DFT_IN_OUTRESETALL 1 input DFT_IN_PERIPHPLL_BG_PWRDN 1 input DFT_IN_PERIPHPLL_BG_RESET 1 input DFT_IN_PERIPHPLL_REG_PWRDN 1 input DFT_IN_PERIPHPLL_REG_RESET 1 input DFT_IN_PERIPHPLL_REG_TEST_SEL 1 input DFT_IN_PINMUX_SCANEN 1 input DFT_IN_PINMUX_SCANIN 1 input DFT_IN_PIPELINE_SCAN_EN_N 1 input DFT_IN_PLL_CLK_TESTBUS_SEL 4 input DFT_IN_PLL_DEBUG_TESTBUS_SEL 4 input DFT_IN_PLL_REG_EXT_SEL 1 input DFT_IN_PLL_REG_TEST_DRV 1 input DFT_IN_PLL_REG_TEST_OUT 1 input DFT_IN_PLL_REG_TEST_REP 1 input DFT_IN_PLLBYPASS 1 input DFT_IN_PLLBYPASS_SEL_N 1 input DFT_IN_PLLTEST_INPUT_EN_N 1 input DFT_IN_PRBS_TEST_ENABLE_N 1 input DFT_IN_PWRDN 1 input DFT_IN_REG_TEST_INT_EN_N 1 input DFT_IN_RESET 1 input DFT_IN_SCANEN_N 1 input DFT_IN_STEP 1 input DFT_IN_TCK 1 input DFT_IN_TDI 1 input DFT_IN_TEST 1 input DFT_IN_TEST_CLOCK 1 input DFT_IN_TEST_CLOCK_EN_N 60 input DFT_IN_TEST_INIT_N 1 input DFT_IN_TEST_SI 50 input DFT_IN_TESTMODE_N 1 input DFX_IN_RINGO_DATAIN 1 input DFX_IN_RINGO_ENABLE_N 1 input DFX_IN_RINGO_SCAN_EN_N 1 input DFX_IN_T2_CLK 1 input DFX_IN_T2_DATAIN 1 input DFX_IN_T2_SCAN_EN_N 1 input DFT_OUT_BIST_CPU_SO 1 output DFT_OUT_BIST_L2_SO 1 output DFT_OUT_BIST_PERI_SO 3 output DFT_OUT_CLKOD_SCANOUT 1 output DFT_OUT_MAINPLL_CLKOUT_0_7 1 output DFT_OUT_MAINPLL_CLKOUT_8_15 1 output DFT_OUT_MAINPLL_DEBUGOUT 1 output DFT_OUT_MAINPLL_REG_TEST_INT 1 output DFT_OUT_MAINPLL_REG_TEST_SIG 1 output DFT_OUT_MEM_CPU_SO 1 output DFT_OUT_MEM_L2_SO 1 output DFT_OUT_MEM_PERI_SO 3 output DFT_OUT_MPFE_OCC_SO 1 output DFT_OUT_MPFE_SCANOUT 14 output DFT_OUT_NOC_LEFT_SCANOUT 15 output DFT_OUT_NOC_RIGHT_SCANOUT 10 output DFT_OUT_PERIPHPLL_CLKOUT_0_7 1 output DFT_OUT_PERIPHPLL_CLKOUT_8_15 1 output DFT_OUT_PERIPHPLL_DEBUGOUT 1 output DFT_OUT_PERIPHPLL_REG_TEST_INT 1 output DFT_OUT_PERIPHPLL_REG_TEST_SIG 1 output DFT_OUT_PINMUX_SCANOUT 1 output DFT_OUT_SECMGR_POR_RST_N 1 output DFT_OUT_TDO 1 output DFT_OUT_TEST_SO 50 output DFT_OUT_TESTMODE_STATUS 1 output DFX_OUT_DCLK 1 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_L4_SYS_FREE_CLK 1 output DFX_OUT_FPGA_S2F_NTRST 1 output DFX_OUT_PR_REQUEST 1 output DFX_OUT_RINGO_DATAOUT 1 output DFX_OUT_S2F_DATA 32 output DFX_OUT_T2_DATAOUT 4 output - true - true - false - true - - - java.lang.String - @orderednames {CM EMAC0 EMAC1 EMAC2 NAND QSPI SDMMC USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 TRACE UART0 UART1 I2C0 I2C1 I2CEMAC0 I2CEMAC1 I2CEMAC2} NAND {interfaces {nand {properties {} direction Input @no_export 0 type conduit} @orderednames nand} atom_name hps_interface_peripheral_nand} SPIM0 {interfaces {spim0_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim0 spim0_sclk_out} spim0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB0 {interfaces {usb0_clk_in {properties {} direction Input @no_export 0 type clock} @orderednames {usb0 usb0_clk_in} usb0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} SPIM1 {interfaces {spim1_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim1 spim1_sclk_out} spim1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB1 {interfaces {@orderednames {usb1 usb1_clk_in} usb1_clk_in {properties {} direction Input @no_export 0 type clock} usb1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} I2CEMAC0 {interfaces {i2cemac0 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac0_scl_in i2cemac0_clk i2cemac0} i2cemac0_clk {properties {} direction Output @no_export 0 type clock} i2cemac0_scl_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART0 {interfaces {uart0 {properties {} direction Input @no_export 0 type conduit} @orderednames uart0} atom_name hps_interface_peripheral_uart} I2CEMAC1 {interfaces {i2cemac1_scl_in {properties {} direction Input @no_export 0 type clock} i2cemac1 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac1_scl_in i2cemac1_clk i2cemac1} i2cemac1_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART1 {interfaces {uart1 {properties {} direction Input @no_export 0 type conduit} @orderednames uart1} atom_name hps_interface_peripheral_uart} QSPI {interfaces {qspi_sclk_out {properties {} direction Output @no_export 0 type clock} qspi_s2f_clk {properties {} direction Output @no_export 0 type clock} qspi {properties {} direction Input @no_export 0 type conduit} @orderednames {qspi_sclk_out qspi_s2f_clk qspi}} atom_name hps_interface_peripheral_qspi} I2CEMAC2 {interfaces {i2cemac2_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2cemac2_scl_in i2cemac2_clk i2cemac2} i2cemac2 {properties {} direction Input @no_export 0 type conduit} i2cemac2_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} EMAC0 {interfaces {emac0_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac0_rx_reset {properties {associatedClock emac0_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac0_gtx_clk {properties {} direction Output @no_export 0 type clock} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac0 {properties {} direction Input @no_export 0 type conduit} emac0_md_clk {properties {} direction Output @no_export 0 type clock} emac0_tx_reset {properties {associatedClock emac0_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset}} atom_name hps_interface_peripheral_emac} TRACE {interfaces {@orderednames {trace_s2f_clk trace} trace_s2f_clk {properties {} direction Output @no_export 0 type clock} trace {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_tpiu_trace} SPIS0 {interfaces {spis0_sclk_in {properties {} direction Input @no_export 0 type clock} @orderednames {spis0 spis0_sclk_in} spis0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_slave} EMAC1 {interfaces {emac1_md_clk {properties {} direction Output @no_export 0 type clock} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac1_gtx_clk {properties {} direction Output @no_export 0 type clock} emac1_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_emac} SPIS1 {interfaces {spis1 {properties {} direction Input @no_export 0 type conduit} @orderednames {spis1 spis1_sclk_in} spis1_sclk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_spi_slave} CM {interfaces {cm {properties {} direction Input @no_export 0 type conduit} @orderednames cm}} EMAC2 {interfaces {emac2_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac2 {properties {} direction Input @no_export 0 type conduit} @orderednames {emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} emac2_md_clk {properties {} direction Output @no_export 0 type clock} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_gtx_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_emac} SDMMC {interfaces {sdmmc_cclk {properties {} direction Output @no_export 0 type clock} sdmmc {properties {} direction Input @no_export 0 type conduit} @orderednames {sdmmc sdmmc_reset sdmmc_clk_in sdmmc_cclk} sdmmc_reset {properties {synchronousEdges none} direction Output @no_export 0 type reset} sdmmc_clk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_sdmmc} I2C0 {interfaces {i2c0_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0 {properties {} direction Input @no_export 0 type conduit} i2c0_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} I2C1 {interfaces {i2c1_clk {properties {} direction Output @no_export 0 type clock} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1_scl_in {properties {} direction Input @no_export 0 type clock} i2c1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_i2c} - true - true - false - true - - - java.lang.String - emac0_tx_clk_in {@orderednames emac0_clk_tx_i emac0_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} emac0_gtx_clk {emac0_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk} @orderednames emac0_phy_txclk_o} spim0 {spim0_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim0_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim0_mosi_o spim0_miso_i spim0_ss_in_n spim0_mosi_oe spim0_ss0_n_o spim0_ss1_n_o spim0_ss2_n_o spim0_ss3_n_o} spim0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim0_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim0_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim0_mosi_o {direction Output atom_signal_name mosi_o role mosi_o} spim0_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim0_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} spim1 {spim1_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim1_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o} spim1_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim1_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim1_mosi_o spim1_miso_i spim1_ss_in_n spim1_mosi_oe spim1_ss0_n_o spim1_ss1_n_o spim1_ss2_n_o spim1_ss3_n_o} spim1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim1_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim1_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim1_mosi_o {direction Output atom_signal_name mosi_o role mosi_o}} emac2_gtx_clk {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} sdmmc_clk_in {@orderednames sdmmc_clk_in sdmmc_clk_in {direction Input atom_signal_name clk_in role clk}} i2cemac1_scl_in {i2c_emac1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac1_scl_i} spim0_sclk_out {spim0_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim0_sclk_out} qspi {qspi_ss_o {direction Output atom_signal_name ss_o role ss_o} qspi_io0_i {direction Input atom_signal_name io0_i role io0_i} qspi_io2_wpn_o {direction Output atom_signal_name io2_wpn_o role io2_wpn_o} qspi_io1_i {direction Input atom_signal_name io1_i role io1_i} @orderednames {qspi_io0_i qspi_io1_i qspi_io2_i qspi_io3_i qspi_io0_o qspi_io1_o qspi_io2_wpn_o qspi_io3_hold_o qspi_mo_oe qspi_ss_o} qspi_io2_i {direction Input atom_signal_name io2_i role io2_i} qspi_io0_o {direction Output atom_signal_name io0_o role io0_o} qspi_io3_hold_o {direction Output atom_signal_name io3_hold_o role io3_hold_o} qspi_io1_o {direction Output atom_signal_name io1_o role io1_o} qspi_io3_i {direction Input atom_signal_name io3_i role io3_i} qspi_mo_oe {direction Output atom_signal_name mo_oe role mo_oe}} i2cemac1_clk {i2c_emac1_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac1_scl_oe} emac0 {emac0_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac0_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} @orderednames {emac0_phy_txd_o emac0_phy_mac_speed_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i emac0_ptp_tstmp_data emac0_ptp_tstmp_en} emac0_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac0_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac0_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac0_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac0_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac0_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac0_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac0_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac0_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac0_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac0_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac0_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac0_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac0_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o}} emac1 {emac1_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} @orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i emac1_ptp_tstmp_data emac1_ptp_tstmp_en} emac1_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac1_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac1_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac1_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac1_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac1_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac1_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac1_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac1_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} emac1_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac1_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac1_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac1_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac1_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac1_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i}} emac2 {emac2_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} @orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i emac2_ptp_tstmp_data emac2_ptp_tstmp_en} emac2_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac2_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac2_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac2_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac2_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac2_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac2_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac2_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac2_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac2_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac2_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac2_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac2_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac2_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac2_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i}} spis0_sclk_in {spis0_sclk_in {direction Input atom_signal_name clk role clk} @orderednames spis0_sclk_in} spis1_sclk_in {@orderednames spis1_sclk_in spis1_sclk_in {direction Input atom_signal_name clk role clk}} trace_s2f_clk {@orderednames trace_s2f_clk trace_s2f_clk {direction Output atom_signal_name s2f_clk role clk}} i2cemac0_scl_in {i2c_emac0_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac0_scl_i} emac0_tx_reset {emac0_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n} @orderednames emac0_rst_clk_tx_n_o} sdmmc {@orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_oe sdmmc_data_i sdmmc_data_o sdmmc_data_oe} sdmmc_cmd_oe {direction Output atom_signal_name cmd_oe role cmd_oe} sdmmc_pwr_ena_o {direction Output atom_signal_name pwr_ena_o role pwr_ena_o} sdmmc_card_intn_i {direction Input atom_signal_name card_intn_i role card_intn_i} sdmmc_cmd_o {direction Output atom_signal_name cmd_o role cmd_o} sdmmc_data_i {direction Input atom_signal_name data_i role data_i} sdmmc_cdn_i {direction Input atom_signal_name cdn_i role cdn_i} sdmmc_data_oe {direction Output atom_signal_name data_oe role data_oe} sdmmc_vs_o {direction Output atom_signal_name vs_o role vs_o} sdmmc_wp_i {direction Input atom_signal_name wp_i role wp_i} sdmmc_data_o {direction Output atom_signal_name data_o role data_o} sdmmc_cmd_i {direction Input atom_signal_name cmd_i role cmd_i}} spim1_sclk_out {spim1_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim1_sclk_out} emac1_rx_clk_in {emac1_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac1_clk_rx_i} i2c0_clk {@orderednames i2c0_scl_oe i2c0_scl_oe {direction Output atom_signal_name scl_oe role clk}} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} i2cemac0 {i2c_emac0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c_emac0_sda_i i2c_emac0_sda_oe} i2c_emac0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac1_tx_reset {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2cemac1 {@orderednames {i2c_emac1_sda_i i2c_emac1_sda_oe} i2c_emac1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} i2c_emac1_sda_i {direction Input atom_signal_name sda_i role sda_i}} i2cemac2 {i2c_emac2_sda_i {direction Input atom_signal_name sda_i role sda_i} @orderednames {i2c_emac2_sda_i i2c_emac2_sda_oe} i2c_emac2_sda_oe {direction Output atom_signal_name sda_oe role sda_oe}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n}} emac2_tx_reset {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2c1_scl_in {i2c1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c1_scl_i} emac2_rx_clk_in {@orderednames emac2_clk_rx_i emac2_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk}} sdmmc_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {direction Output atom_signal_name cclk_o role clk}} emac2_md_clk {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk}} emac1_rx_reset {emac1_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac1_rst_clk_rx_n_o} emac2_tx_clk_in {emac2_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk} @orderednames emac2_clk_tx_i} uart0 {uart0_out1_n {direction Output atom_signal_name out1_n role out1_n} uart0_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} @orderednames {uart0_cts_n uart0_dsr_n uart0_dcd_n uart0_ri_n uart0_rx uart0_dtr_n uart0_rts_n uart0_out1_n uart0_out2_n uart0_tx} uart0_rx {direction Input atom_signal_name rx role rx} uart0_rts_n {direction Output atom_signal_name rts_n role rts_n} uart0_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart0_cts_n {direction Input atom_signal_name cts_n role cts_n} uart0_out2_n {direction Output atom_signal_name out2_n role out2_n} uart0_tx {direction Output atom_signal_name tx role tx} uart0_ri_n {direction Input atom_signal_name ri_n role ri_n} uart0_dcd_n {direction Input atom_signal_name dcd_n role dcd_n}} i2cemac0_clk {@orderednames i2c_emac0_scl_oe i2c_emac0_scl_oe {direction Output atom_signal_name scl_oe role clk}} uart1 {uart1_tx {direction Output atom_signal_name tx role tx} uart1_ri_n {direction Input atom_signal_name ri_n role ri_n} uart1_dcd_n {direction Input atom_signal_name dcd_n role dcd_n} @orderednames {uart1_cts_n uart1_dsr_n uart1_dcd_n uart1_ri_n uart1_rx uart1_dtr_n uart1_rts_n uart1_out1_n uart1_out2_n uart1_tx} uart1_out1_n {direction Output atom_signal_name out1_n role out1_n} uart1_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} uart1_rx {direction Input atom_signal_name rx role rx} uart1_rts_n {direction Output atom_signal_name rts_n role rts_n} uart1_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart1_cts_n {direction Input atom_signal_name cts_n role cts_n} uart1_out2_n {direction Output atom_signal_name out2_n role out2_n}} i2c0_scl_in {@orderednames i2c0_scl_i i2c0_scl_i {direction Input atom_signal_name scl_i role clk}} i2cemac2_clk {i2c_emac2_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac2_scl_oe} trace {trace_data {direction Output atom_signal_name data role data} @orderednames {trace_clk_ctl trace_clkin trace_data} trace_clk_ctl {direction Input atom_signal_name clk_ctl role clk_ctl} trace_clkin {direction Input atom_signal_name clkin role clkin}} emac1_md_clk {emac1_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac1_gmii_mdc_o} cm {@orderednames {}} qspi_sclk_out {qspi_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames qspi_sclk_out} qspi_s2f_clk {qspi_s2f_clk {direction Output atom_signal_name s2f_clk role clk} @orderednames qspi_s2f_clk} emac2_rx_reset {emac2_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac2_rst_clk_rx_n_o} emac0_md_clk {emac0_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac0_gmii_mdc_o} i2c1_clk {@orderednames i2c1_scl_oe i2c1_scl_oe {direction Output atom_signal_name scl_oe role clk}} nand {nand_ale_o {direction Output atom_signal_name ale_o role ale_o} nand_adq_o {direction Output atom_signal_name adq_o role adq_o} nand_wp_o {direction Output atom_signal_name wp_n_o role wp_n_o} nand_rdy_busy_i {direction Input atom_signal_name rdy_busy_i role rdy_busy_i} nand_adq_oe {direction Output atom_signal_name adq_oe role adq_oe} @orderednames {nand_adq_i nand_adq_oe nand_adq_o nand_ale_o nand_ce_o nand_cle_o nand_re_o nand_rdy_busy_i nand_we_o nand_wp_o} nand_re_o {direction Output atom_signal_name re_n_o role re_n_o} nand_cle_o {direction Output atom_signal_name cle_o role cle_o} nand_adq_i {direction Input atom_signal_name adq_i role adq_i} nand_ce_o {direction Output atom_signal_name ce_n_o role ce_n_o} nand_we_o {direction Output atom_signal_name we_n_o role we_n_o}} usb0 {usb0_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} usb0_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb0_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_data_i usb0_ulpi_stp usb0_ulpi_data_o usb0_ulpi_data_oe} usb0_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb0_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o} usb0_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe}} usb1_clk_in {usb1_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb1_ulpi_clk} usb1 {usb1_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe} usb1_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_data_i usb1_ulpi_stp usb1_ulpi_data_o usb1_ulpi_data_oe} usb1_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb1_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} usb1_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb1_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o}} sdmmc_reset {sdmmc_rstn_o {direction Output atom_signal_name rstn_o role reset} @orderednames sdmmc_rstn_o} spis0 {spis0_miso_o {direction Output atom_signal_name miso_o role miso_o} spis0_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} @orderednames {spis0_mosi_i spis0_ss_in_n spis0_miso_o spis0_miso_oe} spis0_mosi_i {direction Input atom_signal_name mosi_i role mosi_i} spis0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n}} spis1 {spis1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} @orderednames {spis1_mosi_i spis1_ss_in_n spis1_miso_o spis1_miso_oe} spis1_miso_o {direction Output atom_signal_name miso_o role miso_o} spis1_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} spis1_mosi_i {direction Input atom_signal_name mosi_i role mosi_i}} usb0_clk_in {usb0_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb0_ulpi_clk} i2cemac2_scl_in {@orderednames i2c_emac2_scl_i i2c_emac2_scl_i {direction Input atom_signal_name scl_i role clk}} i2c0 {i2c0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c0_sda_i i2c0_sda_oe} i2c0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac0_rx_clk_in {emac0_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac0_clk_rx_i} i2c1 {i2c1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c1_sda_i i2c1_sda_oe} i2c1_sda_i {direction Input atom_signal_name sda_i role sda_i}} - true - true - false - true - - - java.lang.String - spim0_miso_i {0 rxd} usb0_ulpi_stp {0 ulpi_stp} emac0_ptp_aux_ts_trig_i {0 ts_trig} uart1_dsr_n {0 dsr_n} spim0_ss1_n_o {0 ss_cs1} qspi_io0_o {0 mo0} emac1_ptp_pps_o {0 ptp_pps} emac1_phy_txclk_o {0 tx_clk_o} spim1_ss1_n_o {0 ss_cs1} sdmmc_clk_in {0 clk_in} emac0_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_ptp_tstmp_en {0 ptp_tstmp_en} emac1_clk_tx_i {0 tx_clk_i} uart1_dcd_n {0 dcd_n} spim0_ss3_n_o {0 ss_cs3} spim0_sclk_out {0 sclk_out} spis1_miso_o {0 txd} spim1_ss3_n_o {0 ss_cs3} emac1_gmii_mdi_i {0 mdi} emac0_phy_rxer_i {0 rxer} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} emac0_clk_rx_i {0 rx_clk} uart0_rts_n {0 rts_n} spis0_sclk_in {0 sclk_in} trace_s2f_clk {0 s2f_clk} i2c_emac0_sda_i {0 ic_data_in_a} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} emac2_gmii_mdo_o {0 mdo} emac1_phy_rxdv_i {0 rxdv} i2c1_scl_oe {0 ic_clk_oe} uart1_cts_n {0 cts_n} emac0_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} uart1_ri_n {0 ri_n} spis0_miso_o {0 txd} emac2_clk_tx_i {0 tx_clk_i} emac0_gmii_mdc_o {0 mdc} emac1_phy_col_i {0 col} emac2_phy_txen_o {0 txen} uart0_rx {0 sin} spim1_sclk_out {0 sclk_out} qspi_io1_i {0 mi1} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} i2c_emac2_scl_i {0 ic_clk_in_a} i2c1_sda_i {0 ic_data_in_a} emac1_phy_crs_i {0 crs} usb0_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} sdmmc_cmd_i {0 ccmd_i} emac2_phy_txer_o {0 txer} uart0_dsr_n {0 dsr_n} spis0_miso_oe {0 ssi_oe_n} emac1_clk_rx_i {0 rx_clk} i2c0_scl_oe {0 ic_clk_oe} spis1_miso_oe {0 ssi_oe_n} emac1_ptp_aux_ts_trig_i {0 ts_trig} uart0_dcd_n {0 dcd_n} qspi_io1_o {0 mo1} emac2_ptp_pps_o {0 ptp_pps} usb0_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} usb0_ulpi_nxt {0 ulpi_nxt} emac0_gmii_mdo_o_e {0 mdo_en} emac0_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac1_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} sdmmc_cmd_o {0 ccmd_o} sdmmc_card_intn_i {0 card_int_n} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac2_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} sdmmc_cclk_out {0 cclk_out} sdmmc_rstn_o {0 rst_out_n} sdmmc_cdn_i {0 cd_i_n} emac0_gmii_mdo_o {0 mdo} i2c_emac2_scl_oe {0 ic_clk_oe} i2c1_sda_oe {0 ic_data_oe} uart0_cts_n {0 cts_n} usb0_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} sdmmc_vs_o {0 vs_o} emac2_clk_rx_i {0 rx_clk} emac0_phy_txen_o {0 txen} emac0_ptp_tstmp_en {0 ptp_tstmp_en} uart1_dtr_n {0 dtr_n} emac1_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_scl_i {0 ic_clk_in_a} i2c0_sda_i {0 ic_data_in_a} usb1_ulpi_nxt {0 ulpi_nxt} emac2_phy_col_i {0 col} qspi_io2_i {0 mi2} nand_adq_i {0 adq_in0 1 adq_in1 2 adq_in2 3 adq_in3 4 adq_in4 5 adq_in5 6 adq_in6 7 adq_in7 8 adq_in8 10 adq_in10 9 adq_in9 11 adq_in11 12 adq_in12 13 adq_in13 14 adq_in14 15 adq_in15} emac2_gmii_mdi_i {0 mdi} emac0_phy_txer_o {0 txer} uart0_tx {0 sout} spis1_mosi_i {0 rxd} spis0_ss_in_n {0 ss_in_n} spim1_mosi_o {0 txd} emac2_phy_crs_i {0 crs} emac1_phy_rxer_i {0 rxer} i2c_emac1_scl_oe {0 ic_clk_oe} i2c0_sda_oe {0 ic_data_oe} spis1_ss_in_n {0 ss_in_n} nand_ale_o {0 ale_out} spim0_ss0_n_o {0 ss_cs0} usb0_ulpi_dir {0 ulpi_dir} emac0_phy_txclk_o {0 tx_clk_o} uart1_out1_n {0 out1_n} spim1_ss0_n_o {0 ss_cs0} sdmmc_cmd_oe {0 ccmd_en} nand_cle_o {0 cle_out} uart0_ri_n {0 ri_n} spim0_ss2_n_o {0 ss_cs2} qspi_io3_hold_o {0 mo3_hold} emac2_phy_txclk_o {0 tx_clk_o} emac2_ptp_aux_ts_trig_i {0 ts_trig} emac2_phy_rxdv_i {0 rxdv} spim1_ss2_n_o {0 ss_cs2} usb0_ulpi_clk {0 ulpi_clk} nand_adq_o {0 adq_out0 1 adq_out1 2 adq_out2 3 adq_out3 4 adq_out4 5 adq_out5 6 adq_out6 7 adq_out7 8 adq_out8 10 adq_out10 9 adq_out9 11 adq_out11 12 adq_out12 13 adq_out13 14 adq_out14 15 adq_out15} sdmmc_data_i {0 cdata_in0 4 cdata_in4 5 cdata_in5 1 cdata_in1 2 cdata_in2 6 cdata_in6 7 cdata_in7 3 cdata_in3} emac2_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_gmii_mdc_o {0 mdc} uart1_rx {0 sin} spis0_mosi_i {0 rxd} spim0_mosi_o {0 txd} emac2_gmii_mdo_o_e {0 mdo_en} i2c_emac2_sda_oe {0 ic_data_oe} i2c_emac0_scl_oe {0 ic_clk_oe} trace_data {17 d17 0 d0 18 d18 1 d1 20 d20 19 d19 2 d2 21 d21 3 d3 22 d22 4 d4 23 d23 5 d5 6 d6 24 d24 25 d25 7 d7 8 d8 26 d26 27 d27 9 d9 10 d10 11 d11 28 d28 29 d29 12 d12 30 d30 31 d31 13 d13 14 d14 15 d15 16 d16} sdmmc_data_oe {0 cdata_out_en0 4 cdata_out_en4 5 cdata_out_en5 1 cdata_out_en1 2 cdata_out_en2 6 cdata_out_en6 7 cdata_out_en7 3 cdata_out_en3} qspi_s2f_clk {0 s2f_clk} qspi_sclk_out {0 sck_out} uart0_out1_n {0 out1_n} spim0_ss_in_n {0 ss_in_n} nand_rdy_busy_i {0 rdy_bsy_in0 1 rdy_bsy_in1 2 rdy_bsy_in2 3 rdy_bsy_in3} nand_adq_oe {0 adq_oe0} uart0_dtr_n {0 dtr_n} spim1_ss_in_n {0 ss_in_n} usb1_ulpi_dir {0 ulpi_dir} sdmmc_data_o {0 cdata_out0 4 cdata_out4 5 cdata_out5 1 cdata_out1 2 cdata_out2 6 cdata_out6 7 cdata_out7 3 cdata_out3} qspi_mo_oe {0 n_mo_en0 1 n_mo_en1 2 n_mo_en2 3 n_mo_en3} emac2_ptp_tstmp_data {0 ptp_tstmp_data} i2c_emac2_sda_i {0 ic_data_in_a} i2c_emac0_scl_i {0 ic_clk_in_a} emac2_ptp_tstmp_en {0 ptp_tstmp_en} emac0_gmii_mdi_i {0 mdi} usb1_ulpi_clk {0 ulpi_clk} nand_wp_o {0 wp_outn} emac2_rst_clk_rx_n_o {0 rst_clk_rx_n_o} emac2_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_sda_oe {0 ic_data_oe} qspi_io3_i {0 mi3} i2c1_scl_i {0 ic_clk_in_a} qspi_ss_o {0 n_ss_out0 1 n_ss_out1 2 n_ss_out2 3 n_ss_out3} qspi_io2_wpn_o {0 mo2_wpn} emac0_phy_rxdv_i {0 rxdv} emac0_ptp_pps_o {0 ptp_pps} emac1_gmii_mdo_o {0 mdo} trace_clk_ctl {0 clk_ctl} nand_we_o {0 we_outn} emac1_ptp_tstmp_data {0 ptp_tstmp_data} uart1_out2_n {0 out2_n} emac1_phy_txen_o {0 txen} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} i2c_emac0_sda_oe {0 ic_data_oe} usb1_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} nand_re_o {0 re_outn} trace_clkin {0 clkin} emac1_phy_txer_o {0 txer} uart1_tx {0 sout} usb1_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} emac2_phy_rxer_i {0 rxer} spim1_miso_i {0 rxd} emac0_ptp_tstmp_data {0 ptp_tstmp_data} uart1_rts_n {0 rts_n} uart0_out2_n {0 out2_n} sdmmc_wp_i {0 wp_i} emac0_clk_tx_i {0 tx_clk_i} i2c_emac1_sda_i {0 ic_data_in_a} spim0_mosi_oe {0 ssi_oe_n} usb1_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} emac0_phy_col_i {0 col} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim1_mosi_oe {0 ssi_oe_n} qspi_io0_i {0 mi0} emac0_phy_crs_i {0 crs} emac1_gmii_mdo_o_e {0 mdo_en} nand_ce_o {0 ce_outn0 1 ce_outn1 2 ce_outn2 3 ce_outn3} emac2_gmii_mdc_o {0 mdc} i2c0_scl_i {0 ic_clk_in_a} emac2_rst_clk_tx_n_o {0 rst_clk_tx_n_o} - true - true - false - true - - - java.lang.String - - true - true - false - true - - - java.lang.String - - true - true - false - true - - - java.lang.String - - true - true - false - true - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_cold_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_dbg_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_warm_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - f2h_stm_hwevents - Input - 28 - stm_hwevents - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - emif_emif_to_hps - Input - 4096 - emif_to_hps - - - emif_hps_to_emif - Output - 4096 - hps_to_emif - - - emif_emif_to_gp - Input - 1 - emif_to_gp - - - emif_gp_to_emif - Output - 2 - gp_to_emif - - - - - - qsys.ui.export_name - hps_io - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - hps_io_phery_emac0_TX_CLK - Output - 1 - hps_io_phery_emac0_TX_CLK - - - hps_io_phery_emac0_TXD0 - Output - 1 - hps_io_phery_emac0_TXD0 - - - hps_io_phery_emac0_TXD1 - Output - 1 - hps_io_phery_emac0_TXD1 - - - hps_io_phery_emac0_TXD2 - Output - 1 - hps_io_phery_emac0_TXD2 - - - hps_io_phery_emac0_TXD3 - Output - 1 - hps_io_phery_emac0_TXD3 - - - hps_io_phery_emac0_RX_CTL - Input - 1 - hps_io_phery_emac0_RX_CTL - - - hps_io_phery_emac0_TX_CTL - Output - 1 - hps_io_phery_emac0_TX_CTL - - - hps_io_phery_emac0_RX_CLK - Input - 1 - hps_io_phery_emac0_RX_CLK - - - hps_io_phery_emac0_RXD0 - Input - 1 - hps_io_phery_emac0_RXD0 - - - hps_io_phery_emac0_RXD1 - Input - 1 - hps_io_phery_emac0_RXD1 - - - hps_io_phery_emac0_RXD2 - Input - 1 - hps_io_phery_emac0_RXD2 - - - hps_io_phery_emac0_RXD3 - Input - 1 - hps_io_phery_emac0_RXD3 - - - hps_io_phery_emac0_MDIO - Bidir - 1 - hps_io_phery_emac0_MDIO - - - hps_io_phery_emac0_MDC - Output - 1 - hps_io_phery_emac0_MDC - - - hps_io_phery_sdmmc_CMD - Bidir - 1 - hps_io_phery_sdmmc_CMD - - - hps_io_phery_sdmmc_D0 - Bidir - 1 - hps_io_phery_sdmmc_D0 - - - hps_io_phery_sdmmc_D1 - Bidir - 1 - hps_io_phery_sdmmc_D1 - - - hps_io_phery_sdmmc_D2 - Bidir - 1 - hps_io_phery_sdmmc_D2 - - - hps_io_phery_sdmmc_D3 - Bidir - 1 - hps_io_phery_sdmmc_D3 - - - hps_io_phery_sdmmc_CCLK - Output - 1 - hps_io_phery_sdmmc_CCLK - - - hps_io_phery_usb0_DATA0 - Bidir - 1 - hps_io_phery_usb0_DATA0 - - - hps_io_phery_usb0_DATA1 - Bidir - 1 - hps_io_phery_usb0_DATA1 - - - hps_io_phery_usb0_DATA2 - Bidir - 1 - hps_io_phery_usb0_DATA2 - - - hps_io_phery_usb0_DATA3 - Bidir - 1 - hps_io_phery_usb0_DATA3 - - - hps_io_phery_usb0_DATA4 - Bidir - 1 - hps_io_phery_usb0_DATA4 - - - hps_io_phery_usb0_DATA5 - Bidir - 1 - hps_io_phery_usb0_DATA5 - - - hps_io_phery_usb0_DATA6 - Bidir - 1 - hps_io_phery_usb0_DATA6 - - - hps_io_phery_usb0_DATA7 - Bidir - 1 - hps_io_phery_usb0_DATA7 - - - hps_io_phery_usb0_CLK - Input - 1 - hps_io_phery_usb0_CLK - - - hps_io_phery_usb0_STP - Output - 1 - hps_io_phery_usb0_STP - - - hps_io_phery_usb0_DIR - Input - 1 - hps_io_phery_usb0_DIR - - - hps_io_phery_usb0_NXT - Input - 1 - hps_io_phery_usb0_NXT - - - hps_io_phery_uart1_RX - Input - 1 - hps_io_phery_uart1_RX - - - hps_io_phery_uart1_TX - Output - 1 - hps_io_phery_uart1_TX - - - hps_io_phery_i2c0_SDA - Bidir - 1 - hps_io_phery_i2c0_SDA - - - hps_io_phery_i2c0_SCL - Bidir - 1 - hps_io_phery_i2c0_SCL - - - hps_io_gpio_gpio2_io8 - Bidir - 1 - hps_io_gpio_gpio2_io8 - - - hps_io_gpio_gpio2_io9 - Bidir - 1 - hps_io_gpio_gpio2_io9 - - - hps_io_gpio_gpio2_io10 - Bidir - 1 - hps_io_gpio_gpio2_io10 - - - hps_io_gpio_gpio2_io11 - Bidir - 1 - hps_io_gpio_gpio2_io11 - - - hps_io_gpio_gpio1_io1 - Bidir - 1 - hps_io_gpio_gpio1_io1 - - - hps_io_gpio_gpio1_io4 - Bidir - 1 - hps_io_gpio_gpio1_io4 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - h2f_rst_n - Output - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - f2sdram0_clk - Input - 1 - clk - - - - - - java.lang.String - f2sdram0_clock - false - true - true - true - - - java.lang.String - f2sdram0_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4294967296 - true - true - false - true - - axi - false - - f2sdram0_AWID - Input - 4 - awid - - - f2sdram0_AWADDR - Input - 32 - awaddr - - - f2sdram0_AWLEN - Input - 4 - awlen - - - f2sdram0_AWSIZE - Input - 3 - awsize - - - f2sdram0_AWBURST - Input - 2 - awburst - - - f2sdram0_AWLOCK - Input - 2 - awlock - - - f2sdram0_AWCACHE - Input - 4 - awcache - - - f2sdram0_AWPROT - Input - 3 - awprot - - - f2sdram0_AWVALID - Input - 1 - awvalid - - - f2sdram0_AWREADY - Output - 1 - awready - - - f2sdram0_AWUSER - Input - 5 - awuser - - - f2sdram0_WID - Input - 4 - wid - - - f2sdram0_WDATA - Input - 128 - wdata - - - f2sdram0_WSTRB - Input - 16 - wstrb - - - f2sdram0_WLAST - Input - 1 - wlast - - - f2sdram0_WVALID - Input - 1 - wvalid - - - f2sdram0_WREADY - Output - 1 - wready - - - f2sdram0_BID - Output - 4 - bid - - - f2sdram0_BRESP - Output - 2 - bresp - - - f2sdram0_BVALID - Output - 1 - bvalid - - - f2sdram0_BREADY - Input - 1 - bready - - - f2sdram0_ARID - Input - 4 - arid - - - f2sdram0_ARADDR - Input - 32 - araddr - - - f2sdram0_ARLEN - Input - 4 - arlen - - - f2sdram0_ARSIZE - Input - 3 - arsize - - - f2sdram0_ARBURST - Input - 2 - arburst - - - f2sdram0_ARLOCK - Input - 2 - arlock - - - f2sdram0_ARCACHE - Input - 4 - arcache - - - f2sdram0_ARPROT - Input - 3 - arprot - - - f2sdram0_ARVALID - Input - 1 - arvalid - - - f2sdram0_ARREADY - Output - 1 - arready - - - f2sdram0_ARUSER - Input - 5 - aruser - - - f2sdram0_RID - Output - 4 - rid - - - f2sdram0_RDATA - Output - 128 - rdata - - - f2sdram0_RRESP - Output - 2 - rresp - - - f2sdram0_RLAST - Output - 1 - rlast - - - f2sdram0_RVALID - Output - 1 - rvalid - - - f2sdram0_RREADY - Input - 1 - rready - - - - - - java.lang.String - f2sdram0_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2sdram0_reset_reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - h2f_axi_clk - Input - 1 - clk - - - - - - java.lang.String - h2f_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - h2f_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - h2f_axi_clock - false - true - true - true - - - java.lang.String - h2f_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - h2f_AWID - Output - 4 - awid - - - h2f_AWADDR - Output - 32 - awaddr - - - h2f_AWLEN - Output - 4 - awlen - - - h2f_AWSIZE - Output - 3 - awsize - - - h2f_AWBURST - Output - 2 - awburst - - - h2f_AWLOCK - Output - 2 - awlock - - - h2f_AWCACHE - Output - 4 - awcache - - - h2f_AWPROT - Output - 3 - awprot - - - h2f_AWVALID - Output - 1 - awvalid - - - h2f_AWREADY - Input - 1 - awready - - - h2f_AWUSER - Output - 5 - awuser - - - h2f_WID - Output - 4 - wid - - - h2f_WDATA - Output - 64 - wdata - - - h2f_WSTRB - Output - 8 - wstrb - - - h2f_WLAST - Output - 1 - wlast - - - h2f_WVALID - Output - 1 - wvalid - - - h2f_WREADY - Input - 1 - wready - - - h2f_BID - Input - 4 - bid - - - h2f_BRESP - Input - 2 - bresp - - - h2f_BVALID - Input - 1 - bvalid - - - h2f_BREADY - Output - 1 - bready - - - h2f_ARID - Output - 4 - arid - - - h2f_ARADDR - Output - 32 - araddr - - - h2f_ARLEN - Output - 4 - arlen - - - h2f_ARSIZE - Output - 3 - arsize - - - h2f_ARBURST - Output - 2 - arburst - - - h2f_ARLOCK - Output - 2 - arlock - - - h2f_ARCACHE - Output - 4 - arcache - - - h2f_ARPROT - Output - 3 - arprot - - - h2f_ARVALID - Output - 1 - arvalid - - - h2f_ARREADY - Input - 1 - arready - - - h2f_ARUSER - Output - 5 - aruser - - - h2f_RID - Input - 4 - rid - - - h2f_RDATA - Input - 64 - rdata - - - h2f_RRESP - Input - 2 - rresp - - - h2f_RLAST - Input - 1 - rlast - - - h2f_RVALID - Input - 1 - rvalid - - - h2f_RREADY - Output - 1 - rready - - - true - h2fw_ClockBridge - s0 - h2fw_ClockBridge.s0 - 0 - 1024 - - - false - sevensig - avalon_slave_0 - sevensig.avalon_slave_0 - 0 - 8 - - - false - fancmd - avalon_slave_0_1 - fancmd.avalon_slave_0_1 - 8 - 8 - - - false - onchip_memory2 - s1 - onchip_memory2.s1 - 16777216 - 262144 - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - f2h_axi_clk - Input - 1 - clk - - - - - - java.lang.String - f2h_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - f2h_axi_clock - false - true - true - true - - - java.lang.String - f2h_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4294967296 - true - true - false - true - - axi - false - - f2h_AWID - Input - 4 - awid - - - f2h_AWADDR - Input - 32 - awaddr - - - f2h_AWLEN - Input - 4 - awlen - - - f2h_AWSIZE - Input - 3 - awsize - - - f2h_AWBURST - Input - 2 - awburst - - - f2h_AWLOCK - Input - 2 - awlock - - - f2h_AWCACHE - Input - 4 - awcache - - - f2h_AWPROT - Input - 3 - awprot - - - f2h_AWVALID - Input - 1 - awvalid - - - f2h_AWREADY - Output - 1 - awready - - - f2h_AWUSER - Input - 5 - awuser - - - f2h_WID - Input - 4 - wid - - - f2h_WDATA - Input - 128 - wdata - - - f2h_WSTRB - Input - 16 - wstrb - - - f2h_WLAST - Input - 1 - wlast - - - f2h_WVALID - Input - 1 - wvalid - - - f2h_WREADY - Output - 1 - wready - - - f2h_BID - Output - 4 - bid - - - f2h_BRESP - Output - 2 - bresp - - - f2h_BVALID - Output - 1 - bvalid - - - f2h_BREADY - Input - 1 - bready - - - f2h_ARID - Input - 4 - arid - - - f2h_ARADDR - Input - 32 - araddr - - - f2h_ARLEN - Input - 4 - arlen - - - f2h_ARSIZE - Input - 3 - arsize - - - f2h_ARBURST - Input - 2 - arburst - - - f2h_ARLOCK - Input - 2 - arlock - - - f2h_ARCACHE - Input - 4 - arcache - - - f2h_ARPROT - Input - 3 - arprot - - - f2h_ARVALID - Input - 1 - arvalid - - - f2h_ARREADY - Output - 1 - arready - - - f2h_ARUSER - Input - 5 - aruser - - - f2h_RID - Output - 4 - rid - - - f2h_RDATA - Output - 128 - rdata - - - f2h_RRESP - Output - 2 - rresp - - - f2h_RLAST - Output - 1 - rlast - - - f2h_RVALID - Output - 1 - rvalid - - - f2h_RREADY - Input - 1 - rready - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - h2f_lw_axi_clk - Input - 1 - clk - - - - - - java.lang.String - h2f_lw_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - h2f_lw_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - h2f_lw_axi_clock - false - true - true - true - - - java.lang.String - h2f_lw_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - h2f_lw_AWID - Output - 4 - awid - - - h2f_lw_AWADDR - Output - 21 - awaddr - - - h2f_lw_AWLEN - Output - 4 - awlen - - - h2f_lw_AWSIZE - Output - 3 - awsize - - - h2f_lw_AWBURST - Output - 2 - awburst - - - h2f_lw_AWLOCK - Output - 2 - awlock - - - h2f_lw_AWCACHE - Output - 4 - awcache - - - h2f_lw_AWPROT - Output - 3 - awprot - - - h2f_lw_AWVALID - Output - 1 - awvalid - - - h2f_lw_AWREADY - Input - 1 - awready - - - h2f_lw_AWUSER - Output - 5 - awuser - - - h2f_lw_WID - Output - 4 - wid - - - h2f_lw_WDATA - Output - 32 - wdata - - - h2f_lw_WSTRB - Output - 4 - wstrb - - - h2f_lw_WLAST - Output - 1 - wlast - - - h2f_lw_WVALID - Output - 1 - wvalid - - - h2f_lw_WREADY - Input - 1 - wready - - - h2f_lw_BID - Input - 4 - bid - - - h2f_lw_BRESP - Input - 2 - bresp - - - h2f_lw_BVALID - Input - 1 - bvalid - - - h2f_lw_BREADY - Output - 1 - bready - - - h2f_lw_ARID - Output - 4 - arid - - - h2f_lw_ARADDR - Output - 21 - araddr - - - h2f_lw_ARLEN - Output - 4 - arlen - - - h2f_lw_ARSIZE - Output - 3 - arsize - - - h2f_lw_ARBURST - Output - 2 - arburst - - - h2f_lw_ARLOCK - Output - 2 - arlock - - - h2f_lw_ARCACHE - Output - 4 - arcache - - - h2f_lw_ARPROT - Output - 3 - arprot - - - h2f_lw_ARVALID - Output - 1 - arvalid - - - h2f_lw_ARREADY - Input - 1 - arready - - - h2f_lw_ARUSER - Output - 5 - aruser - - - h2f_lw_RID - Input - 4 - rid - - - h2f_lw_RDATA - Input - 32 - rdata - - - h2f_lw_RRESP - Input - 2 - rresp - - - h2f_lw_RLAST - Input - 1 - rlast - - - h2f_lw_RVALID - Input - 1 - rvalid - - - h2f_lw_RREADY - Output - 1 - rready - - - true - pb_lwh2f - s0 - pb_lwh2f.s0 - 0 - 512 - - - false - ILC - avalon_slave - ILC.avalon_slave - 0 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 304 - 8 - - - false - led_pio - s1 - led_pio.s1 - 288 - 16 - - - false - button_pio - s1 - button_pio.s1 - 272 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 256 - 16 - - - - - - embeddedsw.dts.irq.rx_offset - 19 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - f2h_irq_p0 - Input - 32 - irq - - - false - button_pio - irq - button_pio.irq - 0 - - - false - dipsw_pio - irq - dipsw_pio.irq - 1 - - - - - - embeddedsw.dts.irq.rx_offset - 51 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - f2h_irq1_irq - Input - 32 - irq - - - - - - - java.lang.String - constraints {} instances {interrupts {signal_widths {} parameters {} location HPSINTERFACEINTERRUPTS_X78_Y180_N96 entity_name twentynm_hps_interface_interrupts signal_default_terminations {} signal_terminations {}} boot_from_fpga {signal_widths {f2s_bsel 3 f2s_boot_from_fpga_on_failure 1 f2s_bsel_en 1 f2s_boot_from_fpga_ready 1} parameters {} location HPSINTERFACEBOOTFROMFPGA_X79_Y172_N96 entity_name twentynm_hps_interface_boot_from_fpga signal_default_terminations {f2s_bsel 0 f2s_boot_from_fpga_on_failure 0 f2s_bsel_en 0 f2s_boot_from_fpga_ready 0} signal_terminations {f2s_bsel {2:0 1} f2s_boot_from_fpga_on_failure {0:0 0} f2s_bsel_en {0:0 0} f2s_boot_from_fpga_ready {0:0 0}}} clocks_resets {signal_widths {f2s_free_clk 1 f2s_pending_rst_ack 1} parameters {} location HPSINTERFACECLOCKSRESETS_X78_Y168_N96 entity_name twentynm_hps_interface_clocks_resets signal_default_terminations {f2s_free_clk 1 f2s_pending_rst_ack 1} signal_terminations {f2s_free_clk {0:0 0} f2s_pending_rst_ack {0:0 1}}} emif_interface {signal_widths {} parameters {} location HPSINTERFACEDDR_X78_Y171_N96 entity_name a10_hps_emif_interface signal_default_terminations {} signal_terminations {}} stm_event {signal_widths {} parameters {} location HPSINTERFACESTMEVENT_X78_Y204_N96 entity_name twentynm_hps_interface_stm_event signal_default_terminations {} signal_terminations {}} debug_apb {signal_widths {F2S_PCLKENDBG 1 F2S_DBGAPB_DISABLE 1} parameters {} location HPSINTERFACEDBGAPB_X78_Y170_N96 entity_name twentynm_hps_interface_dbg_apb signal_default_terminations {F2S_PCLKENDBG 0 F2S_DBGAPB_DISABLE 0} signal_terminations {F2S_PCLKENDBG {0:0 0} F2S_DBGAPB_DISABLE {0:0 0}}} @orderednames {clocks_resets debug_apb stm_event boot_from_fpga emif_interface interrupts}} interfaces {@orderednames {h2f_reset f2h_cold_reset_req f2h_debug_reset_req f2h_warm_reset_req f2h_stm_hw_events emif} h2f_reset {properties {associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req} synchronousEdges none} direction Output type reset signals {@orderednames h2f_rst_n h2f_rst_n {width 1 properties {} instance_name clocks_resets internal_name s2f_user3_clk direction Output role reset_n fragments {}}}} f2h_cold_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_cold_rst_req_n f2h_cold_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_cold_rst_req_n direction Input role reset_n fragments {}}}} f2h_debug_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_dbg_rst_req_n f2h_dbg_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_dbg_rst_req_n direction Input role reset_n fragments {}}}} f2h_warm_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_warm_rst_req_n f2h_warm_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_warm_rst_req_n direction Input role reset_n fragments {}}}} f2h_stm_hw_events {properties {} direction Input type conduit signals {@orderednames f2h_stm_hwevents f2h_stm_hwevents {width 28 properties {} instance_name stm_event internal_name f2s_stm_event direction Input role stm_hwevents fragments {}}}} emif {properties {} direction Output type conduit signals {@orderednames {emif_emif_to_hps emif_hps_to_emif emif_emif_to_gp emif_gp_to_emif} emif_emif_to_hps {width 4096 properties {} instance_name emif_interface internal_name emif_to_hps direction Input role emif_to_hps fragments {}} emif_hps_to_emif {width 4096 properties {} instance_name emif_interface internal_name hps_to_emif direction Output role hps_to_emif fragments {}} emif_emif_to_gp {width 1 properties {} instance_name emif internal_name emif_emif_to_gp direction Input role emif_to_gp fragments {}} emif_gp_to_emif {width 2 properties {} instance_name emif internal_name emif_gp_to_emif direction Output role gp_to_emif fragments {}}}}} properties {} interface_sim_style {} raw_assigns {} intermediate_wire_count 0 raw_assign_sim_style {} wires_to_fragments {} wire_sim_style {} - false - true - true - true - - - java.lang.String - - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - f2h_warm_reset_req,f2h_cold_reset_req - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - h2f_rst_n - Output - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_cold_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_dbg_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_warm_rst_req_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - f2h_stm_hwevents - Input - 28 - stm_hwevents - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - emif_emif_to_hps - Input - 4096 - emif_to_hps - - - emif_hps_to_emif - Output - 4096 - hps_to_emif - - - emif_emif_to_gp - Input - 1 - emif_to_gp - - - emif_gp_to_emif - Output - 2 - gp_to_emif - - - - - - - java.lang.String - constraints {} instances {phery_uart1 {signal_widths {} parameters {} location HPSPERIPHERALUART_X79_Y169_N96 entity_name twentynm_hps_peripheral_uart signal_default_terminations {} signal_terminations {}} phery_i2c0 {signal_widths {} parameters {} location HPSPERIPHERALI2C_X78_Y211_N96 entity_name twentynm_hps_peripheral_i2c signal_default_terminations {} signal_terminations {}} phery_usb0 {signal_widths {} parameters {} location HPSPERIPHERALUSB_X79_Y170_N96 entity_name twentynm_hps_peripheral_usb signal_default_terminations {} signal_terminations {}} phery_emac0 {signal_widths {} parameters {} location HPSPERIPHERALEMAC_X78_Y207_N96 entity_name twentynm_hps_peripheral_emac signal_default_terminations {} signal_terminations {}} @orderednames {phery_emac0 phery_sdmmc phery_usb0 phery_uart1 phery_i2c0 gpio} gpio {signal_widths {} parameters {} location HPSPERIPHERALGPIO_X78_Y210_N96 entity_name twentynm_hps_peripheral_gpio signal_default_terminations {} signal_terminations {}} phery_sdmmc {signal_widths {} parameters {} location HPSPERIPHERALSDMMC_X78_Y219_N96 entity_name twentynm_hps_peripheral_sdmmc signal_default_terminations {} signal_terminations {}}} interfaces {@orderednames hps_io hps_io {properties {} direction input type conduit signals {@orderednames {hps_io_phery_emac0_TX_CLK hps_io_phery_emac0_TXD0 hps_io_phery_emac0_TXD1 hps_io_phery_emac0_TXD2 hps_io_phery_emac0_TXD3 hps_io_phery_emac0_RX_CTL hps_io_phery_emac0_TX_CTL hps_io_phery_emac0_RX_CLK hps_io_phery_emac0_RXD0 hps_io_phery_emac0_RXD1 hps_io_phery_emac0_RXD2 hps_io_phery_emac0_RXD3 hps_io_phery_emac0_MDIO hps_io_phery_emac0_MDC hps_io_phery_sdmmc_CMD hps_io_phery_sdmmc_D0 hps_io_phery_sdmmc_D1 hps_io_phery_sdmmc_D2 hps_io_phery_sdmmc_D3 hps_io_phery_sdmmc_CCLK hps_io_phery_usb0_DATA0 hps_io_phery_usb0_DATA1 hps_io_phery_usb0_DATA2 hps_io_phery_usb0_DATA3 hps_io_phery_usb0_DATA4 hps_io_phery_usb0_DATA5 hps_io_phery_usb0_DATA6 hps_io_phery_usb0_DATA7 hps_io_phery_usb0_CLK hps_io_phery_usb0_STP hps_io_phery_usb0_DIR hps_io_phery_usb0_NXT hps_io_phery_uart1_RX hps_io_phery_uart1_TX hps_io_phery_i2c0_SDA hps_io_phery_i2c0_SCL hps_io_gpio_gpio2_io8 hps_io_gpio_gpio2_io9 hps_io_gpio_gpio2_io10 hps_io_gpio_gpio2_io11 hps_io_gpio_gpio1_io1 hps_io_gpio_gpio1_io4} hps_io_phery_emac0_TX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CLK direction output role hps_io_phery_emac0_TX_CLK fragments phery_emac0:EMAC_CLK_TX(0:0)} hps_io_phery_emac0_TXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD0 direction output role hps_io_phery_emac0_TXD0 fragments phery_emac0:EMAC_PHY_TXD(0:0)} hps_io_phery_emac0_TXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD1 direction output role hps_io_phery_emac0_TXD1 fragments phery_emac0:EMAC_PHY_TXD(1:1)} hps_io_phery_emac0_TXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD2 direction output role hps_io_phery_emac0_TXD2 fragments phery_emac0:EMAC_PHY_TXD(2:2)} hps_io_phery_emac0_TXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD3 direction output role hps_io_phery_emac0_TXD3 fragments phery_emac0:EMAC_PHY_TXD(3:3)} hps_io_phery_emac0_RX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CTL direction input role hps_io_phery_emac0_RX_CTL fragments phery_emac0:EMAC_PHY_RXDV(0:0)} hps_io_phery_emac0_TX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CTL direction output role hps_io_phery_emac0_TX_CTL fragments phery_emac0:EMAC_PHY_TX_OE(0:0)} hps_io_phery_emac0_RX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CLK direction input role hps_io_phery_emac0_RX_CLK fragments phery_emac0:EMAC_CLK_RX(0:0)} hps_io_phery_emac0_RXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD0 direction input role hps_io_phery_emac0_RXD0 fragments phery_emac0:EMAC_PHY_RXD(0:0)} hps_io_phery_emac0_RXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD1 direction input role hps_io_phery_emac0_RXD1 fragments phery_emac0:EMAC_PHY_RXD(1:1)} hps_io_phery_emac0_RXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD2 direction input role hps_io_phery_emac0_RXD2 fragments phery_emac0:EMAC_PHY_RXD(2:2)} hps_io_phery_emac0_RXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD3 direction input role hps_io_phery_emac0_RXD3 fragments phery_emac0:EMAC_PHY_RXD(3:3)} hps_io_phery_emac0_MDIO {tristate_output {{intermediate 1} {intermediate 0}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDIO direction bidir role hps_io_phery_emac0_MDIO fragments phery_emac0:EMAC_GMII_MDO_I(0:0)} hps_io_phery_emac0_MDC {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDC direction output role hps_io_phery_emac0_MDC fragments phery_emac0:EMAC_GMII_MDC(0:0)} hps_io_phery_sdmmc_CMD {tristate_output {{intermediate 3} {intermediate 2}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_CMD direction bidir role hps_io_phery_sdmmc_CMD fragments phery_sdmmc:SDMMC_CMD_I(0:0)} hps_io_phery_sdmmc_D0 {tristate_output {{intermediate 5} {intermediate 4}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D0 direction bidir role hps_io_phery_sdmmc_D0 fragments phery_sdmmc:SDMMC_DATA_I(0:0)} hps_io_phery_sdmmc_D1 {tristate_output {{intermediate 7} {intermediate 6}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D1 direction bidir role hps_io_phery_sdmmc_D1 fragments phery_sdmmc:SDMMC_DATA_I(1:1)} hps_io_phery_sdmmc_D2 {tristate_output {{intermediate 9} {intermediate 8}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D2 direction bidir role hps_io_phery_sdmmc_D2 fragments phery_sdmmc:SDMMC_DATA_I(2:2)} hps_io_phery_sdmmc_D3 {tristate_output {{intermediate 11} {intermediate 10}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D3 direction bidir role hps_io_phery_sdmmc_D3 fragments phery_sdmmc:SDMMC_DATA_I(3:3)} hps_io_phery_sdmmc_CCLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_CCLK direction output role hps_io_phery_sdmmc_CCLK fragments phery_sdmmc:SDMMC_CCLK(0:0)} hps_io_phery_usb0_DATA0 {tristate_output {{intermediate 13} {intermediate 12}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA0 direction bidir role hps_io_phery_usb0_DATA0 fragments phery_usb0:USB_ULPI_DATA_I(0:0)} hps_io_phery_usb0_DATA1 {tristate_output {{intermediate 15} {intermediate 14}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA1 direction bidir role hps_io_phery_usb0_DATA1 fragments phery_usb0:USB_ULPI_DATA_I(1:1)} hps_io_phery_usb0_DATA2 {tristate_output {{intermediate 17} {intermediate 16}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA2 direction bidir role hps_io_phery_usb0_DATA2 fragments phery_usb0:USB_ULPI_DATA_I(2:2)} hps_io_phery_usb0_DATA3 {tristate_output {{intermediate 19} {intermediate 18}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA3 direction bidir role hps_io_phery_usb0_DATA3 fragments phery_usb0:USB_ULPI_DATA_I(3:3)} hps_io_phery_usb0_DATA4 {tristate_output {{intermediate 21} {intermediate 20}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA4 direction bidir role hps_io_phery_usb0_DATA4 fragments phery_usb0:USB_ULPI_DATA_I(4:4)} hps_io_phery_usb0_DATA5 {tristate_output {{intermediate 23} {intermediate 22}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA5 direction bidir role hps_io_phery_usb0_DATA5 fragments phery_usb0:USB_ULPI_DATA_I(5:5)} hps_io_phery_usb0_DATA6 {tristate_output {{intermediate 25} {intermediate 24}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA6 direction bidir role hps_io_phery_usb0_DATA6 fragments phery_usb0:USB_ULPI_DATA_I(6:6)} hps_io_phery_usb0_DATA7 {tristate_output {{intermediate 27} {intermediate 26}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA7 direction bidir role hps_io_phery_usb0_DATA7 fragments phery_usb0:USB_ULPI_DATA_I(7:7)} hps_io_phery_usb0_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_CLK direction input role hps_io_phery_usb0_CLK fragments phery_usb0:USB_ULPI_CLK(0:0)} hps_io_phery_usb0_STP {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_STP direction output role hps_io_phery_usb0_STP fragments phery_usb0:USB_ULPI_STP(0:0)} hps_io_phery_usb0_DIR {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DIR direction input role hps_io_phery_usb0_DIR fragments phery_usb0:USB_ULPI_DIR(0:0)} hps_io_phery_usb0_NXT {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_NXT direction input role hps_io_phery_usb0_NXT fragments phery_usb0:USB_ULPI_NXT(0:0)} hps_io_phery_uart1_RX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart1_RX direction input role hps_io_phery_uart1_RX fragments phery_uart1:UART_RXD(0:0)} hps_io_phery_uart1_TX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart1_TX direction output role hps_io_phery_uart1_TX fragments phery_uart1:UART_TXD(0:0)} hps_io_phery_i2c0_SDA {tristate_output {{intermediate 28} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c0_SDA direction bidir role hps_io_phery_i2c0_SDA fragments phery_i2c0:I2C_DATA(0:0)} hps_io_phery_i2c0_SCL {tristate_output {{intermediate 29} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c0_SCL direction bidir role hps_io_phery_i2c0_SCL fragments phery_i2c0:I2C_CLK(0:0)} hps_io_gpio_gpio2_io8 {tristate_output {{intermediate 31} {intermediate 30}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio2_io8 direction bidir role hps_io_gpio_gpio2_io8 fragments gpio:GPIO2_PORTA_I(8:8)} hps_io_gpio_gpio2_io9 {tristate_output {{intermediate 33} {intermediate 32}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio2_io9 direction bidir role hps_io_gpio_gpio2_io9 fragments gpio:GPIO2_PORTA_I(9:9)} hps_io_gpio_gpio2_io10 {tristate_output {{intermediate 35} {intermediate 34}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio2_io10 direction bidir role hps_io_gpio_gpio2_io10 fragments gpio:GPIO2_PORTA_I(10:10)} hps_io_gpio_gpio2_io11 {tristate_output {{intermediate 37} {intermediate 36}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio2_io11 direction bidir role hps_io_gpio_gpio2_io11 fragments gpio:GPIO2_PORTA_I(11:11)} hps_io_gpio_gpio1_io1 {tristate_output {{intermediate 39} {intermediate 38}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io1 direction bidir role hps_io_gpio_gpio1_io1 fragments gpio:GPIO1_PORTA_I(1:1)} hps_io_gpio_gpio1_io4 {tristate_output {{intermediate 41} {intermediate 40}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io4 direction bidir role hps_io_gpio_gpio1_io4 fragments gpio:GPIO1_PORTA_I(4:4)}}}} properties {GENERATE_ISW 1} interface_sim_style {} raw_assigns {} intermediate_wire_count 42 raw_assign_sim_style {} wires_to_fragments {{intermediate 41} {output gpio:GPIO1_PORTA_OE(4:4)} {intermediate 23} {output phery_usb0:USB_ULPI_DATA_OE(5:5)} {intermediate 24} {output phery_usb0:USB_ULPI_DATA_O(6:6)} {intermediate 25} {output phery_usb0:USB_ULPI_DATA_OE(6:6)} {intermediate 26} {output phery_usb0:USB_ULPI_DATA_O(7:7)} {intermediate 0} {output phery_emac0:EMAC_GMII_MDO_O(0:0)} {intermediate 27} {output phery_usb0:USB_ULPI_DATA_OE(7:7)} {intermediate 1} {output phery_emac0:EMAC_GMII_MDO_OE(0:0)} {intermediate 10} {output phery_sdmmc:SDMMC_DATA_O(3:3)} {intermediate 28} {output phery_i2c0:I2C_DATA_OE(0:0)} {intermediate 2} {output phery_sdmmc:SDMMC_CMD_O(0:0)} {intermediate 11} {output phery_sdmmc:SDMMC_DATA_OE(3:3)} {intermediate 30} {output gpio:GPIO2_PORTA_O(8:8)} {intermediate 29} {output phery_i2c0:I2C_CLK_OE(0:0)} {intermediate 12} {output phery_usb0:USB_ULPI_DATA_O(0:0)} {intermediate 3} {output phery_sdmmc:SDMMC_CMD_OE(0:0)} {intermediate 31} {output gpio:GPIO2_PORTA_OE(8:8)} {intermediate 13} {output phery_usb0:USB_ULPI_DATA_OE(0:0)} {intermediate 4} {output phery_sdmmc:SDMMC_DATA_O(0:0)} {intermediate 32} {output gpio:GPIO2_PORTA_O(9:9)} {intermediate 14} {output phery_usb0:USB_ULPI_DATA_O(1:1)} {intermediate 5} {output phery_sdmmc:SDMMC_DATA_OE(0:0)} {intermediate 33} {output gpio:GPIO2_PORTA_OE(9:9)} {intermediate 15} {output phery_usb0:USB_ULPI_DATA_OE(1:1)} {intermediate 6} {output phery_sdmmc:SDMMC_DATA_O(1:1)} {intermediate 34} {output gpio:GPIO2_PORTA_O(10:10)} {intermediate 16} {output phery_usb0:USB_ULPI_DATA_O(2:2)} {intermediate 7} {output phery_sdmmc:SDMMC_DATA_OE(1:1)} {intermediate 35} {output gpio:GPIO2_PORTA_OE(10:10)} {intermediate 17} {output phery_usb0:USB_ULPI_DATA_OE(2:2)} {intermediate 8} {output phery_sdmmc:SDMMC_DATA_O(2:2)} {intermediate 36} {output gpio:GPIO2_PORTA_O(11:11)} {intermediate 18} {output phery_usb0:USB_ULPI_DATA_O(3:3)} {intermediate 9} {output phery_sdmmc:SDMMC_DATA_OE(2:2)} {intermediate 37} {output gpio:GPIO2_PORTA_OE(11:11)} {intermediate 20} {output phery_usb0:USB_ULPI_DATA_O(4:4)} {intermediate 19} {output phery_usb0:USB_ULPI_DATA_OE(3:3)} {intermediate 38} {output gpio:GPIO1_PORTA_O(1:1)} {intermediate 21} {output phery_usb0:USB_ULPI_DATA_OE(4:4)} {intermediate 40} {output gpio:GPIO1_PORTA_O(4:4)} {intermediate 39} {output gpio:GPIO1_PORTA_OE(1:1)} {intermediate 22} {output phery_usb0:USB_ULPI_DATA_O(5:5)}} wire_sim_style {} - false - true - true - true - - - java.lang.String - H2F_DEBUG_APB_CLOCK_FREQ 100 quartus_ini_hps_ip_enable_jtag false MAINPLLGRP_NOC_CNT 9 SPIS1_Mode N/A MAINPLLGRP_SDMMC_CNT 900 test_iface_definition {DFT_IN_ADVANCE 1 input DFT_IN_ATPG_CLK_SEL_N 1 input DFT_IN_ATPG_MODE_N 1 input DFT_IN_BIST_CPU_SI 1 input DFT_IN_BIST_L2_SI 1 input DFT_IN_BIST_PERI_SI 3 input DFT_IN_BIST_RST_N 1 input DFT_IN_BIST_SE_N 1 input DFT_IN_BISTCLK 1 input DFT_IN_BISTEN_N 1 input DFT_IN_BWADJ 12 input DFT_IN_CLKF 13 input DFT_IN_CLKOD 11 input DFT_IN_CLKOD_CTL 1 input DFT_IN_CLKOD_SCANCLK 1 input DFT_IN_CLKOD_SCANIN 1 input DFT_IN_CLKR 6 input DFT_IN_COMPRESS_ENABLE_N 1 input DFT_IN_ECCBYP_N 1 input DFT_IN_ENSAT 1 input DFT_IN_FASTEN 1 input DFT_IN_FREECLK_EN_N 1 input DFT_IN_IO_CONTROL 20 input DFT_IN_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_IO_TEST_MODE_N 1 input DFT_IN_JTAG_MODE 1 input DFT_IN_JTAG_UPDATE_DR 1 input DFT_IN_JTGHIGHZ 1 input DFT_IN_L4MPCLK_DIV_CTL_N 1 input DFT_IN_MAINPLL_BG_PWRDN 1 input DFT_IN_MAINPLL_BG_RESET 1 input DFT_IN_MAINPLL_REG_PWRDN 1 input DFT_IN_MAINPLL_REG_RESET 1 input DFT_IN_MAINPLL_REG_TEST_SEL 1 input DFT_IN_MEM_CPU_SI 1 input DFT_IN_MEM_L2_SI 1 input DFT_IN_MEM_PERI_SI 3 input DFT_IN_MEM_SE_N 1 input DFT_IN_MPFE_ATPG_MODE_N 1 input DFT_IN_MPFE_CLK_SEL_N 1 input DFT_IN_MPFE_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_MPFE_OCC_BYPASS_N 1 input DFT_IN_MPFE_OCC_ENABLE_N 1 input DFT_IN_MPFE_OCC_SI 1 input DFT_IN_MPFE_PIPELINE_SCAN_EN_N 1 input DFT_IN_MPFE_SCANEN_N 1 input DFT_IN_MPFE_SCANIN 14 input DFT_IN_MPFE_TEST_CLK_0 1 input DFT_IN_MPFE_TEST_CLK_1 1 input DFT_IN_MPFE_TEST_CLK_2 1 input DFT_IN_MPFE_TEST_CLOCK_EN_N 1 input DFT_IN_MPFE_TEST_MODE_N 1 input DFT_IN_MTESTEN_N 1 input DFT_IN_NOC_LEFT_SCANIN 15 input DFT_IN_NOC_RIGHT_SCANIN 10 input DFT_IN_OCC_ENABLE_N 1 input DFT_IN_OUTRESET 1 input DFT_IN_OUTRESETALL 1 input DFT_IN_PERIPHPLL_BG_PWRDN 1 input DFT_IN_PERIPHPLL_BG_RESET 1 input DFT_IN_PERIPHPLL_REG_PWRDN 1 input DFT_IN_PERIPHPLL_REG_RESET 1 input DFT_IN_PERIPHPLL_REG_TEST_SEL 1 input DFT_IN_PINMUX_SCANEN 1 input DFT_IN_PINMUX_SCANIN 1 input DFT_IN_PIPELINE_SCAN_EN_N 1 input DFT_IN_PLL_CLK_TESTBUS_SEL 4 input DFT_IN_PLL_DEBUG_TESTBUS_SEL 4 input DFT_IN_PLL_REG_EXT_SEL 1 input DFT_IN_PLL_REG_TEST_DRV 1 input DFT_IN_PLL_REG_TEST_OUT 1 input DFT_IN_PLL_REG_TEST_REP 1 input DFT_IN_PLLBYPASS 1 input DFT_IN_PLLBYPASS_SEL_N 1 input DFT_IN_PLLTEST_INPUT_EN_N 1 input DFT_IN_PRBS_TEST_ENABLE_N 1 input DFT_IN_PWRDN 1 input DFT_IN_REG_TEST_INT_EN_N 1 input DFT_IN_RESET 1 input DFT_IN_SCANEN_N 1 input DFT_IN_STEP 1 input DFT_IN_TCK 1 input DFT_IN_TDI 1 input DFT_IN_TEST 1 input DFT_IN_TEST_CLOCK 1 input DFT_IN_TEST_CLOCK_EN_N 60 input DFT_IN_TEST_INIT_N 1 input DFT_IN_TEST_SI 50 input DFT_IN_TESTMODE_N 1 input DFX_IN_RINGO_DATAIN 1 input DFX_IN_RINGO_ENABLE_N 1 input DFX_IN_RINGO_SCAN_EN_N 1 input DFX_IN_T2_CLK 1 input DFX_IN_T2_DATAIN 1 input DFX_IN_T2_SCAN_EN_N 1 input DFT_OUT_BIST_CPU_SO 1 output DFT_OUT_BIST_L2_SO 1 output DFT_OUT_BIST_PERI_SO 3 output DFT_OUT_CLKOD_SCANOUT 1 output DFT_OUT_MAINPLL_CLKOUT_0_7 1 output DFT_OUT_MAINPLL_CLKOUT_8_15 1 output DFT_OUT_MAINPLL_DEBUGOUT 1 output DFT_OUT_MAINPLL_REG_TEST_INT 1 output DFT_OUT_MAINPLL_REG_TEST_SIG 1 output DFT_OUT_MEM_CPU_SO 1 output DFT_OUT_MEM_L2_SO 1 output DFT_OUT_MEM_PERI_SO 3 output DFT_OUT_MPFE_OCC_SO 1 output DFT_OUT_MPFE_SCANOUT 14 output DFT_OUT_NOC_LEFT_SCANOUT 15 output DFT_OUT_NOC_RIGHT_SCANOUT 10 output DFT_OUT_PERIPHPLL_CLKOUT_0_7 1 output DFT_OUT_PERIPHPLL_CLKOUT_8_15 1 output DFT_OUT_PERIPHPLL_DEBUGOUT 1 output DFT_OUT_PERIPHPLL_REG_TEST_INT 1 output DFT_OUT_PERIPHPLL_REG_TEST_SIG 1 output DFT_OUT_PINMUX_SCANOUT 1 output DFT_OUT_SECMGR_POR_RST_N 1 output DFT_OUT_TDO 1 output DFT_OUT_TEST_SO 50 output DFT_OUT_TESTMODE_STATUS 1 output DFX_OUT_DCLK 1 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_L4_SYS_FREE_CLK 1 output DFX_OUT_FPGA_S2F_NTRST 1 output DFX_OUT_PR_REQUEST 1 output DFX_OUT_RINGO_DATAOUT 1 output DFX_OUT_S2F_DATA 32 output DFX_OUT_T2_DATAOUT 4 output} H2F_AXI_CLOCK_FREQ 100000000 I2CEMAC0_PinMuxing Unused QSPI_PinMuxing Unused MAINPLLGRP_MPU_CNT 1 quartus_ini_hps_ip_enable_a10_advanced_options false CLK_SDMMC_SOURCE 1 JAVA_WARNING_MSG {} S2FINTERRUPT_NAND_Enable false JAVA_ERROR_MSG {} I2CEMAC2_Mode N/A CLK_EMAC_PTP_SOURCE 1 DB_iface_ports {emac0_tx_clk_in {@orderednames emac0_clk_tx_i emac0_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} emac0_gtx_clk {emac0_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk} @orderednames emac0_phy_txclk_o} spim0 {spim0_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim0_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim0_mosi_o spim0_miso_i spim0_ss_in_n spim0_mosi_oe spim0_ss0_n_o spim0_ss1_n_o spim0_ss2_n_o spim0_ss3_n_o} spim0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim0_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim0_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim0_mosi_o {direction Output atom_signal_name mosi_o role mosi_o} spim0_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim0_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} spim1 {spim1_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim1_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o} spim1_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim1_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim1_mosi_o spim1_miso_i spim1_ss_in_n spim1_mosi_oe spim1_ss0_n_o spim1_ss1_n_o spim1_ss2_n_o spim1_ss3_n_o} spim1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim1_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim1_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim1_mosi_o {direction Output atom_signal_name mosi_o role mosi_o}} emac2_gtx_clk {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} sdmmc_clk_in {@orderednames sdmmc_clk_in sdmmc_clk_in {direction Input atom_signal_name clk_in role clk}} i2cemac1_scl_in {i2c_emac1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac1_scl_i} spim0_sclk_out {spim0_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim0_sclk_out} qspi {qspi_ss_o {direction Output atom_signal_name ss_o role ss_o} qspi_io0_i {direction Input atom_signal_name io0_i role io0_i} qspi_io2_wpn_o {direction Output atom_signal_name io2_wpn_o role io2_wpn_o} qspi_io1_i {direction Input atom_signal_name io1_i role io1_i} @orderednames {qspi_io0_i qspi_io1_i qspi_io2_i qspi_io3_i qspi_io0_o qspi_io1_o qspi_io2_wpn_o qspi_io3_hold_o qspi_mo_oe qspi_ss_o} qspi_io2_i {direction Input atom_signal_name io2_i role io2_i} qspi_io0_o {direction Output atom_signal_name io0_o role io0_o} qspi_io3_hold_o {direction Output atom_signal_name io3_hold_o role io3_hold_o} qspi_io1_o {direction Output atom_signal_name io1_o role io1_o} qspi_io3_i {direction Input atom_signal_name io3_i role io3_i} qspi_mo_oe {direction Output atom_signal_name mo_oe role mo_oe}} i2cemac1_clk {i2c_emac1_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac1_scl_oe} emac0 {emac0_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac0_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} @orderednames {emac0_phy_txd_o emac0_phy_mac_speed_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i emac0_ptp_tstmp_data emac0_ptp_tstmp_en} emac0_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac0_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac0_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac0_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac0_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac0_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac0_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac0_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac0_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac0_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac0_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac0_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac0_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac0_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o}} emac1 {emac1_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} @orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i emac1_ptp_tstmp_data emac1_ptp_tstmp_en} emac1_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac1_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac1_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac1_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac1_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac1_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac1_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac1_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac1_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} emac1_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac1_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac1_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac1_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac1_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac1_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i}} emac2 {emac2_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} @orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i emac2_ptp_tstmp_data emac2_ptp_tstmp_en} emac2_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac2_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac2_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac2_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac2_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac2_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac2_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac2_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac2_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac2_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac2_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac2_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac2_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac2_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac2_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i}} spis0_sclk_in {spis0_sclk_in {direction Input atom_signal_name clk role clk} @orderednames spis0_sclk_in} spis1_sclk_in {@orderednames spis1_sclk_in spis1_sclk_in {direction Input atom_signal_name clk role clk}} trace_s2f_clk {@orderednames trace_s2f_clk trace_s2f_clk {direction Output atom_signal_name s2f_clk role clk}} i2cemac0_scl_in {i2c_emac0_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac0_scl_i} emac0_tx_reset {emac0_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n} @orderednames emac0_rst_clk_tx_n_o} sdmmc {@orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_oe sdmmc_data_i sdmmc_data_o sdmmc_data_oe} sdmmc_cmd_oe {direction Output atom_signal_name cmd_oe role cmd_oe} sdmmc_pwr_ena_o {direction Output atom_signal_name pwr_ena_o role pwr_ena_o} sdmmc_card_intn_i {direction Input atom_signal_name card_intn_i role card_intn_i} sdmmc_cmd_o {direction Output atom_signal_name cmd_o role cmd_o} sdmmc_data_i {direction Input atom_signal_name data_i role data_i} sdmmc_cdn_i {direction Input atom_signal_name cdn_i role cdn_i} sdmmc_data_oe {direction Output atom_signal_name data_oe role data_oe} sdmmc_vs_o {direction Output atom_signal_name vs_o role vs_o} sdmmc_wp_i {direction Input atom_signal_name wp_i role wp_i} sdmmc_data_o {direction Output atom_signal_name data_o role data_o} sdmmc_cmd_i {direction Input atom_signal_name cmd_i role cmd_i}} spim1_sclk_out {spim1_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim1_sclk_out} emac1_rx_clk_in {emac1_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac1_clk_rx_i} i2c0_clk {@orderednames i2c0_scl_oe i2c0_scl_oe {direction Output atom_signal_name scl_oe role clk}} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} i2cemac0 {i2c_emac0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c_emac0_sda_i i2c_emac0_sda_oe} i2c_emac0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac1_tx_reset {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2cemac1 {@orderednames {i2c_emac1_sda_i i2c_emac1_sda_oe} i2c_emac1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} i2c_emac1_sda_i {direction Input atom_signal_name sda_i role sda_i}} i2cemac2 {i2c_emac2_sda_i {direction Input atom_signal_name sda_i role sda_i} @orderednames {i2c_emac2_sda_i i2c_emac2_sda_oe} i2c_emac2_sda_oe {direction Output atom_signal_name sda_oe role sda_oe}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n}} emac2_tx_reset {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2c1_scl_in {i2c1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c1_scl_i} emac2_rx_clk_in {@orderednames emac2_clk_rx_i emac2_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk}} sdmmc_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {direction Output atom_signal_name cclk_o role clk}} emac2_md_clk {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk}} emac1_rx_reset {emac1_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac1_rst_clk_rx_n_o} emac2_tx_clk_in {emac2_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk} @orderednames emac2_clk_tx_i} uart0 {uart0_out1_n {direction Output atom_signal_name out1_n role out1_n} uart0_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} @orderednames {uart0_cts_n uart0_dsr_n uart0_dcd_n uart0_ri_n uart0_rx uart0_dtr_n uart0_rts_n uart0_out1_n uart0_out2_n uart0_tx} uart0_rx {direction Input atom_signal_name rx role rx} uart0_rts_n {direction Output atom_signal_name rts_n role rts_n} uart0_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart0_cts_n {direction Input atom_signal_name cts_n role cts_n} uart0_out2_n {direction Output atom_signal_name out2_n role out2_n} uart0_tx {direction Output atom_signal_name tx role tx} uart0_ri_n {direction Input atom_signal_name ri_n role ri_n} uart0_dcd_n {direction Input atom_signal_name dcd_n role dcd_n}} i2cemac0_clk {@orderednames i2c_emac0_scl_oe i2c_emac0_scl_oe {direction Output atom_signal_name scl_oe role clk}} uart1 {uart1_tx {direction Output atom_signal_name tx role tx} uart1_ri_n {direction Input atom_signal_name ri_n role ri_n} uart1_dcd_n {direction Input atom_signal_name dcd_n role dcd_n} @orderednames {uart1_cts_n uart1_dsr_n uart1_dcd_n uart1_ri_n uart1_rx uart1_dtr_n uart1_rts_n uart1_out1_n uart1_out2_n uart1_tx} uart1_out1_n {direction Output atom_signal_name out1_n role out1_n} uart1_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} uart1_rx {direction Input atom_signal_name rx role rx} uart1_rts_n {direction Output atom_signal_name rts_n role rts_n} uart1_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart1_cts_n {direction Input atom_signal_name cts_n role cts_n} uart1_out2_n {direction Output atom_signal_name out2_n role out2_n}} i2c0_scl_in {@orderednames i2c0_scl_i i2c0_scl_i {direction Input atom_signal_name scl_i role clk}} i2cemac2_clk {i2c_emac2_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac2_scl_oe} trace {trace_data {direction Output atom_signal_name data role data} @orderednames {trace_clk_ctl trace_clkin trace_data} trace_clk_ctl {direction Input atom_signal_name clk_ctl role clk_ctl} trace_clkin {direction Input atom_signal_name clkin role clkin}} emac1_md_clk {emac1_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac1_gmii_mdc_o} cm {@orderednames {}} qspi_sclk_out {qspi_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames qspi_sclk_out} qspi_s2f_clk {qspi_s2f_clk {direction Output atom_signal_name s2f_clk role clk} @orderednames qspi_s2f_clk} emac2_rx_reset {emac2_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac2_rst_clk_rx_n_o} emac0_md_clk {emac0_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac0_gmii_mdc_o} i2c1_clk {@orderednames i2c1_scl_oe i2c1_scl_oe {direction Output atom_signal_name scl_oe role clk}} nand {nand_ale_o {direction Output atom_signal_name ale_o role ale_o} nand_adq_o {direction Output atom_signal_name adq_o role adq_o} nand_wp_o {direction Output atom_signal_name wp_n_o role wp_n_o} nand_rdy_busy_i {direction Input atom_signal_name rdy_busy_i role rdy_busy_i} nand_adq_oe {direction Output atom_signal_name adq_oe role adq_oe} @orderednames {nand_adq_i nand_adq_oe nand_adq_o nand_ale_o nand_ce_o nand_cle_o nand_re_o nand_rdy_busy_i nand_we_o nand_wp_o} nand_re_o {direction Output atom_signal_name re_n_o role re_n_o} nand_cle_o {direction Output atom_signal_name cle_o role cle_o} nand_adq_i {direction Input atom_signal_name adq_i role adq_i} nand_ce_o {direction Output atom_signal_name ce_n_o role ce_n_o} nand_we_o {direction Output atom_signal_name we_n_o role we_n_o}} usb0 {usb0_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} usb0_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb0_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_data_i usb0_ulpi_stp usb0_ulpi_data_o usb0_ulpi_data_oe} usb0_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb0_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o} usb0_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe}} usb1_clk_in {usb1_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb1_ulpi_clk} usb1 {usb1_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe} usb1_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_data_i usb1_ulpi_stp usb1_ulpi_data_o usb1_ulpi_data_oe} usb1_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb1_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} usb1_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb1_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o}} sdmmc_reset {sdmmc_rstn_o {direction Output atom_signal_name rstn_o role reset} @orderednames sdmmc_rstn_o} spis0 {spis0_miso_o {direction Output atom_signal_name miso_o role miso_o} spis0_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} @orderednames {spis0_mosi_i spis0_ss_in_n spis0_miso_o spis0_miso_oe} spis0_mosi_i {direction Input atom_signal_name mosi_i role mosi_i} spis0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n}} spis1 {spis1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} @orderednames {spis1_mosi_i spis1_ss_in_n spis1_miso_o spis1_miso_oe} spis1_miso_o {direction Output atom_signal_name miso_o role miso_o} spis1_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} spis1_mosi_i {direction Input atom_signal_name mosi_i role mosi_i}} usb0_clk_in {usb0_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb0_ulpi_clk} i2cemac2_scl_in {@orderednames i2c_emac2_scl_i i2c_emac2_scl_i {direction Input atom_signal_name scl_i role clk}} i2c0 {i2c0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c0_sda_i i2c0_sda_oe} i2c0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac0_rx_clk_in {emac0_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac0_clk_rx_i} i2c1 {i2c1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c1_sda_i i2c1_sda_oe} i2c1_sda_i {direction Input atom_signal_name sda_i role sda_i}}} EMAC2_Mode N/A CLK_NOC_CNT 0 DB_periph_ifaces {@orderednames {CM EMAC0 EMAC1 EMAC2 NAND QSPI SDMMC USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 TRACE UART0 UART1 I2C0 I2C1 I2CEMAC0 I2CEMAC1 I2CEMAC2} NAND {interfaces {nand {properties {} direction Input @no_export 0 type conduit} @orderednames nand} atom_name hps_interface_peripheral_nand} SPIM0 {interfaces {spim0_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim0 spim0_sclk_out} spim0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB0 {interfaces {usb0_clk_in {properties {} direction Input @no_export 0 type clock} @orderednames {usb0 usb0_clk_in} usb0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} SPIM1 {interfaces {spim1_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim1 spim1_sclk_out} spim1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB1 {interfaces {@orderednames {usb1 usb1_clk_in} usb1_clk_in {properties {} direction Input @no_export 0 type clock} usb1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} I2CEMAC0 {interfaces {i2cemac0 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac0_scl_in i2cemac0_clk i2cemac0} i2cemac0_clk {properties {} direction Output @no_export 0 type clock} i2cemac0_scl_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART0 {interfaces {uart0 {properties {} direction Input @no_export 0 type conduit} @orderednames uart0} atom_name hps_interface_peripheral_uart} I2CEMAC1 {interfaces {i2cemac1_scl_in {properties {} direction Input @no_export 0 type clock} i2cemac1 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac1_scl_in i2cemac1_clk i2cemac1} i2cemac1_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART1 {interfaces {uart1 {properties {} direction Input @no_export 0 type conduit} @orderednames uart1} atom_name hps_interface_peripheral_uart} QSPI {interfaces {qspi_sclk_out {properties {} direction Output @no_export 0 type clock} qspi_s2f_clk {properties {} direction Output @no_export 0 type clock} qspi {properties {} direction Input @no_export 0 type conduit} @orderednames {qspi_sclk_out qspi_s2f_clk qspi}} atom_name hps_interface_peripheral_qspi} I2CEMAC2 {interfaces {i2cemac2_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2cemac2_scl_in i2cemac2_clk i2cemac2} i2cemac2 {properties {} direction Input @no_export 0 type conduit} i2cemac2_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} EMAC0 {interfaces {emac0_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac0_rx_reset {properties {associatedClock emac0_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac0_gtx_clk {properties {} direction Output @no_export 0 type clock} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac0 {properties {} direction Input @no_export 0 type conduit} emac0_md_clk {properties {} direction Output @no_export 0 type clock} emac0_tx_reset {properties {associatedClock emac0_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset}} atom_name hps_interface_peripheral_emac} TRACE {interfaces {@orderednames {trace_s2f_clk trace} trace_s2f_clk {properties {} direction Output @no_export 0 type clock} trace {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_tpiu_trace} SPIS0 {interfaces {spis0_sclk_in {properties {} direction Input @no_export 0 type clock} @orderednames {spis0 spis0_sclk_in} spis0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_slave} EMAC1 {interfaces {emac1_md_clk {properties {} direction Output @no_export 0 type clock} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac1_gtx_clk {properties {} direction Output @no_export 0 type clock} emac1_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_emac} SPIS1 {interfaces {spis1 {properties {} direction Input @no_export 0 type conduit} @orderednames {spis1 spis1_sclk_in} spis1_sclk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_spi_slave} CM {interfaces {cm {properties {} direction Input @no_export 0 type conduit} @orderednames cm}} EMAC2 {interfaces {emac2_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac2 {properties {} direction Input @no_export 0 type conduit} @orderednames {emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} emac2_md_clk {properties {} direction Output @no_export 0 type clock} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_gtx_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_emac} SDMMC {interfaces {sdmmc_cclk {properties {} direction Output @no_export 0 type clock} sdmmc {properties {} direction Input @no_export 0 type conduit} @orderednames {sdmmc sdmmc_reset sdmmc_clk_in sdmmc_cclk} sdmmc_reset {properties {synchronousEdges none} direction Output @no_export 0 type reset} sdmmc_clk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_sdmmc} I2C0 {interfaces {i2c0_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0 {properties {} direction Input @no_export 0 type conduit} i2c0_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} I2C1 {interfaces {i2c1_clk {properties {} direction Output @no_export 0 type clock} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1_scl_in {properties {} direction Input @no_export 0 type clock} i2c1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_i2c}} NOCDIV_L4SPCLK 2 SDMMC_Mode 4-bit UART0_PinMuxing Unused F2S_Width 6 dev_database {} FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 S2FINTERRUPT_FPGAMANAGER_Enable false F2H_SDRAM0_CLOCK_FREQ 100 NOCDIV_CS_ATCLK 0 EMAC2_SWITCH_Enable false CLK_MPU_CNT 0 S2FINTERRUPT_USB1_Enable false SDMMC_PinMuxing IO CLK_S2F_USER0_SOURCE 0 MAINPLLGRP_S2F_USER0_CNT 900 DB_port_pins {spim0_miso_i {0 rxd} usb0_ulpi_stp {0 ulpi_stp} emac0_ptp_aux_ts_trig_i {0 ts_trig} uart1_dsr_n {0 dsr_n} spim0_ss1_n_o {0 ss_cs1} qspi_io0_o {0 mo0} emac1_ptp_pps_o {0 ptp_pps} emac1_phy_txclk_o {0 tx_clk_o} spim1_ss1_n_o {0 ss_cs1} sdmmc_clk_in {0 clk_in} emac0_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_ptp_tstmp_en {0 ptp_tstmp_en} emac1_clk_tx_i {0 tx_clk_i} uart1_dcd_n {0 dcd_n} spim0_ss3_n_o {0 ss_cs3} spim0_sclk_out {0 sclk_out} spis1_miso_o {0 txd} spim1_ss3_n_o {0 ss_cs3} emac1_gmii_mdi_i {0 mdi} emac0_phy_rxer_i {0 rxer} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} emac0_clk_rx_i {0 rx_clk} uart0_rts_n {0 rts_n} spis0_sclk_in {0 sclk_in} trace_s2f_clk {0 s2f_clk} i2c_emac0_sda_i {0 ic_data_in_a} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} emac2_gmii_mdo_o {0 mdo} emac1_phy_rxdv_i {0 rxdv} i2c1_scl_oe {0 ic_clk_oe} uart1_cts_n {0 cts_n} emac0_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} uart1_ri_n {0 ri_n} spis0_miso_o {0 txd} emac2_clk_tx_i {0 tx_clk_i} emac0_gmii_mdc_o {0 mdc} emac1_phy_col_i {0 col} emac2_phy_txen_o {0 txen} uart0_rx {0 sin} spim1_sclk_out {0 sclk_out} qspi_io1_i {0 mi1} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} i2c_emac2_scl_i {0 ic_clk_in_a} i2c1_sda_i {0 ic_data_in_a} emac1_phy_crs_i {0 crs} usb0_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} sdmmc_cmd_i {0 ccmd_i} emac2_phy_txer_o {0 txer} uart0_dsr_n {0 dsr_n} spis0_miso_oe {0 ssi_oe_n} emac1_clk_rx_i {0 rx_clk} i2c0_scl_oe {0 ic_clk_oe} spis1_miso_oe {0 ssi_oe_n} emac1_ptp_aux_ts_trig_i {0 ts_trig} uart0_dcd_n {0 dcd_n} qspi_io1_o {0 mo1} emac2_ptp_pps_o {0 ptp_pps} usb0_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} usb0_ulpi_nxt {0 ulpi_nxt} emac0_gmii_mdo_o_e {0 mdo_en} emac0_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac1_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} sdmmc_cmd_o {0 ccmd_o} sdmmc_card_intn_i {0 card_int_n} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac2_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} sdmmc_cclk_out {0 cclk_out} sdmmc_rstn_o {0 rst_out_n} sdmmc_cdn_i {0 cd_i_n} emac0_gmii_mdo_o {0 mdo} i2c_emac2_scl_oe {0 ic_clk_oe} i2c1_sda_oe {0 ic_data_oe} uart0_cts_n {0 cts_n} usb0_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} sdmmc_vs_o {0 vs_o} emac2_clk_rx_i {0 rx_clk} emac0_phy_txen_o {0 txen} emac0_ptp_tstmp_en {0 ptp_tstmp_en} uart1_dtr_n {0 dtr_n} emac1_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_scl_i {0 ic_clk_in_a} i2c0_sda_i {0 ic_data_in_a} usb1_ulpi_nxt {0 ulpi_nxt} emac2_phy_col_i {0 col} qspi_io2_i {0 mi2} nand_adq_i {0 adq_in0 1 adq_in1 2 adq_in2 3 adq_in3 4 adq_in4 5 adq_in5 6 adq_in6 7 adq_in7 8 adq_in8 10 adq_in10 9 adq_in9 11 adq_in11 12 adq_in12 13 adq_in13 14 adq_in14 15 adq_in15} emac2_gmii_mdi_i {0 mdi} emac0_phy_txer_o {0 txer} uart0_tx {0 sout} spis1_mosi_i {0 rxd} spis0_ss_in_n {0 ss_in_n} spim1_mosi_o {0 txd} emac2_phy_crs_i {0 crs} emac1_phy_rxer_i {0 rxer} i2c_emac1_scl_oe {0 ic_clk_oe} i2c0_sda_oe {0 ic_data_oe} spis1_ss_in_n {0 ss_in_n} nand_ale_o {0 ale_out} spim0_ss0_n_o {0 ss_cs0} usb0_ulpi_dir {0 ulpi_dir} emac0_phy_txclk_o {0 tx_clk_o} uart1_out1_n {0 out1_n} spim1_ss0_n_o {0 ss_cs0} sdmmc_cmd_oe {0 ccmd_en} nand_cle_o {0 cle_out} uart0_ri_n {0 ri_n} spim0_ss2_n_o {0 ss_cs2} qspi_io3_hold_o {0 mo3_hold} emac2_phy_txclk_o {0 tx_clk_o} emac2_ptp_aux_ts_trig_i {0 ts_trig} emac2_phy_rxdv_i {0 rxdv} spim1_ss2_n_o {0 ss_cs2} usb0_ulpi_clk {0 ulpi_clk} nand_adq_o {0 adq_out0 1 adq_out1 2 adq_out2 3 adq_out3 4 adq_out4 5 adq_out5 6 adq_out6 7 adq_out7 8 adq_out8 10 adq_out10 9 adq_out9 11 adq_out11 12 adq_out12 13 adq_out13 14 adq_out14 15 adq_out15} sdmmc_data_i {0 cdata_in0 4 cdata_in4 5 cdata_in5 1 cdata_in1 2 cdata_in2 6 cdata_in6 7 cdata_in7 3 cdata_in3} emac2_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_gmii_mdc_o {0 mdc} uart1_rx {0 sin} spis0_mosi_i {0 rxd} spim0_mosi_o {0 txd} emac2_gmii_mdo_o_e {0 mdo_en} i2c_emac2_sda_oe {0 ic_data_oe} i2c_emac0_scl_oe {0 ic_clk_oe} trace_data {17 d17 0 d0 18 d18 1 d1 20 d20 19 d19 2 d2 21 d21 3 d3 22 d22 4 d4 23 d23 5 d5 6 d6 24 d24 25 d25 7 d7 8 d8 26 d26 27 d27 9 d9 10 d10 11 d11 28 d28 29 d29 12 d12 30 d30 31 d31 13 d13 14 d14 15 d15 16 d16} sdmmc_data_oe {0 cdata_out_en0 4 cdata_out_en4 5 cdata_out_en5 1 cdata_out_en1 2 cdata_out_en2 6 cdata_out_en6 7 cdata_out_en7 3 cdata_out_en3} qspi_s2f_clk {0 s2f_clk} qspi_sclk_out {0 sck_out} uart0_out1_n {0 out1_n} spim0_ss_in_n {0 ss_in_n} nand_rdy_busy_i {0 rdy_bsy_in0 1 rdy_bsy_in1 2 rdy_bsy_in2 3 rdy_bsy_in3} nand_adq_oe {0 adq_oe0} uart0_dtr_n {0 dtr_n} spim1_ss_in_n {0 ss_in_n} usb1_ulpi_dir {0 ulpi_dir} sdmmc_data_o {0 cdata_out0 4 cdata_out4 5 cdata_out5 1 cdata_out1 2 cdata_out2 6 cdata_out6 7 cdata_out7 3 cdata_out3} qspi_mo_oe {0 n_mo_en0 1 n_mo_en1 2 n_mo_en2 3 n_mo_en3} emac2_ptp_tstmp_data {0 ptp_tstmp_data} i2c_emac2_sda_i {0 ic_data_in_a} i2c_emac0_scl_i {0 ic_clk_in_a} emac2_ptp_tstmp_en {0 ptp_tstmp_en} emac0_gmii_mdi_i {0 mdi} usb1_ulpi_clk {0 ulpi_clk} nand_wp_o {0 wp_outn} emac2_rst_clk_rx_n_o {0 rst_clk_rx_n_o} emac2_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_sda_oe {0 ic_data_oe} qspi_io3_i {0 mi3} i2c1_scl_i {0 ic_clk_in_a} qspi_ss_o {0 n_ss_out0 1 n_ss_out1 2 n_ss_out2 3 n_ss_out3} qspi_io2_wpn_o {0 mo2_wpn} emac0_phy_rxdv_i {0 rxdv} emac0_ptp_pps_o {0 ptp_pps} emac1_gmii_mdo_o {0 mdo} trace_clk_ctl {0 clk_ctl} nand_we_o {0 we_outn} emac1_ptp_tstmp_data {0 ptp_tstmp_data} uart1_out2_n {0 out2_n} emac1_phy_txen_o {0 txen} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} i2c_emac0_sda_oe {0 ic_data_oe} usb1_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} nand_re_o {0 re_outn} trace_clkin {0 clkin} emac1_phy_txer_o {0 txer} uart1_tx {0 sout} usb1_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} emac2_phy_rxer_i {0 rxer} spim1_miso_i {0 rxd} emac0_ptp_tstmp_data {0 ptp_tstmp_data} uart1_rts_n {0 rts_n} uart0_out2_n {0 out2_n} sdmmc_wp_i {0 wp_i} emac0_clk_tx_i {0 tx_clk_i} i2c_emac1_sda_i {0 ic_data_in_a} spim0_mosi_oe {0 ssi_oe_n} usb1_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} emac0_phy_col_i {0 col} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim1_mosi_oe {0 ssi_oe_n} qspi_io0_i {0 mi0} emac0_phy_crs_i {0 crs} emac1_gmii_mdo_o_e {0 mdo_en} nand_ce_o {0 ce_outn0 1 ce_outn1 2 ce_outn2 3 ce_outn3} emac2_gmii_mdc_o {0 mdc} i2c0_scl_i {0 ic_clk_in_a} emac2_rst_clk_tx_n_o {0 rst_clk_tx_n_o}} quartus_ini_hps_ip_boot_from_fpga_ready false MAINPLLGRP_GPIO_DB_CNT 900 MAINPLLGRP_VCO_DENOM 1 USB0_PinMuxing IO S2F_Width 2 TRACE_Mode N/A I2CEMAC2_PinMuxing Unused S2FINTERRUPT_I2C1_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN 100 S2FINTERRUPT_CLOCKPERIPHERAL_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 DEFAULT_MPU_CLK 1000 H2F_COLD_RST_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5 MAINPLLGRP_EMACB_CNT 900 S2FINTERRUPT_I2CEMAC1_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 100 MAINPLLGRP_EMAC_PTP_CNT 900 PERI_PLL_AUTO_VCO_FREQ 1000 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 F2H_SDRAM1_CLOCK_FREQ 100 EMAC0_CLK 250 DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} BOOT_FROM_FPGA_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN 100 PERPLLGRP_NOC_CNT 900 Quad_4_Save {} PERPLLGRP_HMC_PLL_REF_CNT 900 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 DMA_Enable {No No No No No No No No} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 Quad_1_Save {} EMAC1_PTP false eosc1_clk_mhz 25.0 F2H_DBG_RST_Enable true PERPLLGRP_MPU_CNT 900 F2SDRAM2_DELAY 4 S2FINTERRUPT_GPIO_Enable false H2F_USER0_CLK_FREQ 400 H2F_USER0_CLK_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN 100 UART0_Mode N/A F2H_SDRAM2_CLOCK_FREQ 100 NOCDIV_L4MPCLK 0 H2F_PENDING_RST_Enable false I2C0_PinMuxing IO S2FINTERRUPT_SPIS1_Enable false S2FINTERRUPT_SPIM0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 100 USB1_Mode N/A S2FINTERRUPT_DMA_Enable false H2F_CTI_CLOCK_FREQ 100 SPIM1_PinMuxing Unused QSPI_Mode N/A F2SDRAM0_ENABLED true CLK_EMACB_SOURCE 1 SPIS0_Mode N/A MAINPLLGRP_VCO_NUMER 159 EMAC0_PinMuxing IO SPIS0_PinMuxing Unused PERPLLGRP_S2F_USER1_CNT 900 CM_PinMuxing Unused SPIM1_Mode N/A FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 PERPLLGRP_SDMMC_CNT 9 S2FINTERRUPT_UART0_Enable false TESTIOCTRL_PERICLKSEL 8 pin_muxing_check {} SECURITY_MODULE_Enable false S2FINTERRUPT_SYSTIMER_Enable false S2FINTERRUPT_EMAC2_Enable false quartus_ini_hps_ip_enable_sdmmc_clk_in false H2F_USER1_CLK_Enable false RUN_INTERNAL_BUILD_CHECKS 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 I2CEMAC1_Mode N/A F2H_AXI_CLOCK_FREQ 100000000 F2H_SDRAM3_CLOCK_FREQ 100 CLK_NOC_SOURCE 0 TESTIOCTRL_DEBUGCLKSEL 16 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDMMC_CLK_IN 100 MPU_CLK_VCCL 0 EMAC1_Mode N/A USE_DEFAULT_MPU_CLK false S2FINTERRUPT_HMC_Enable false GP_Enable false eosc1_clk_hz 0 S2FINTERRUPT_EMAC0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 100 MAINPLLGRP_PERIPH_REF_CNT 900 quartus_ini_hps_ip_overide_f2sdram_delay false NAND_PinMuxing Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 EMAC2_CLK 250 GPIO_REF_CLK 4 OVERIDE_PERI_PLL false PERPLLGRP_EMAC_PTP_CNT 19 EMAC2_PinMuxing Unused DEBUG_APB_Enable false EMIF_BYPASS_CHECK false F2SDRAM_PORT_CONFIG 6 F2H_FREE_CLK_Enable false PERPLLGRP_VCO_DENOM 1 F2H_SDRAM4_CLOCK_FREQ 100 JTAG_Enable false EMAC2SEL 0 MAINPLLGRP_HMC_PLL_REF_CNT 900 CTI_Enable false BSEL_EN false SDMMC_REF_CLK 200 H2F_LW_AXI_CLOCK_FREQ 100000000 PERPLLGRP_EMACB_CNT 900 F2H_FREE_CLK_FREQ 200 F2H_COLD_RST_Enable true MAINPLLGRP_EMACA_CNT 900 Quad_3_Save {} H2F_USER1_CLK_FREQ 400 L4_SYS_FREE_CLK 1 LWH2F_Enable 2 F2SDRAM1_ENABLED false I2CEMAC1_PinMuxing Unused F2H_SDRAM5_CLOCK_FREQ 100 CLK_S2F_USER1_SOURCE 0 S2FINTERRUPT_CTI_Enable false TEST_Enable false NOCDIV_CS_PDBGCLK 1 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 PERPLLGRP_GPIO_DB_CNT 499 NOCDIV_CS_TRACECLK 0 HPS_DIV_GPIO_FREQ 125 CLK_GPIO_SOURCE 1 EMAC0_PTP false NOCDIV_L4MAINCLK 0 I2C1_Mode N/A S2FINTERRUPT_SYSTEMMANAGER_Enable false S2FINTERRUPT_USB0_Enable false PIN_TO_BALL_MAP {Q2_1 F25 Q2_2 G25 Q2_3 K22 Q2_4 L22 Q2_5 H24 Q2_6 J24 Q2_7 H23 Q2_8 J23 Q2_10 M21 Q2_9 M22 Q2_11 F24 Q2_12 G24 D_4 J18 D_5 F22 D_6 K18 D_7 E23 D_8 G21 D_9 H21 Q3_1 C29 Q3_2 D29 Q3_3 A30 Q3_4 B30 Q3_5 A29 Q3_6 B29 Q3_7 C28 Q3_8 D28 D_10 H22 Q3_9 A28 D_11 H19 D_12 D23 D_13 C23 D_14 F23 D_15 G22 D_16 J19 D_17 L20 Q3_10 A27 Q4_1 B27 Q3_11 C24 Q4_2 C27 Q3_12 D24 Q4_3 D26 Q4_4 E26 Q4_5 D25 Q4_6 E25 Q4_7 A25 Q4_8 B25 Q4_9 A24 Q1_10 M24 Q1_1 L25 Q1_11 K23 Q1_2 M25 Q1_12 L23 Q1_3 J25 Q1_4 K25 Q1_5 G26 Q1_6 H26 Q1_7 E27 Q1_8 F27 Q1_9 L24 Q4_10 B24 Q4_11 B26 Q4_12 C26} HPS_IO_Enable {SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 NONE NONE GPIO GPIO GPIO GPIO UART1:TX UART1:RX USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 NONE GPIO I2C0:SDA I2C0:SCL GPIO NONE NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE} CLK_HMC_PLL_SOURCE 0 S2FINTERRUPT_SDMMC_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 UART1_PinMuxing IO S2FINTERRUPT_I2CEMAC2_Enable false F2SDRAM_ADDRESS_WIDTH 32 EMAC1SEL 0 HMC_PLL_REF_CLK 800 TRACE_PinMuxing Unused FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 USB0_Mode default FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 100 DISABLE_PERI_PLL false CLK_PERI_PLL_SOURCE2 0 S2FINTERRUPT_I2C0_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN 100 EMIF_CONDUIT_Enable true SPIM0_Mode N/A FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 100 PERPLLGRP_VCO_NUMER 159 S2FINTERRUPT_L4TIMER_Enable false H2F_TPIU_CLOCK_IN_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 USB1_PinMuxing Unused S2FINTERRUPT_I2CEMAC0_Enable false F2SDRAM_READY_LATENCY false PERPLLGRP_S2F_USER0_CNT 900 EMAC0_SWITCH_Enable false S2FINTERRUPT_WATCHDOG_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 I2CEMAC0_Mode N/A EMAC0_Mode RGMII_with_MDIO S2FINTERRUPT_QSPI_Enable false MAINPLLGRP_S2F_USER1_CNT 900 pin_muxing {} INTERNAL_OSCILLATOR_ENABLE 60 SPIM0_PinMuxing Unused PERI_PLL_MANUAL_VCO_FREQ 2000 F2H_WARM_RST_Enable true CUSTOM_MPU_CLK 800 L3_MAIN_FREE_CLK 200 F2SINTERRUPT_Enable true S2FINTERRUPT_SPIM1_Enable false device_name 10AS066K3F40E2SG FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN 100 EMAC0SEL 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 CONFIG_HPS_DIV_GPIO 32000 EMAC1_CLK 250 S2FINTERRUPT_UART1_Enable false F2SDRAM2_ENABLED false MPU_EVENTS_Enable false S2FINTERRUPT_SPIS0_Enable false EMAC_PTP_REF_CLK 100 CLK_EMACA_SOURCE 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 hps_device_family {Arria 10} EMAC2_PTP false CLK_MPU_SOURCE 0 I2C1_PinMuxing Unused NAND_Mode N/A quartus_ini_hps_ip_override_sdmmc_4bit false PERPLLGRP_EMACA_CNT 7 Quad_2_Save {} S2FINTERRUPT_EMAC1_Enable false EMAC1_PinMuxing Unused SPIS1_PinMuxing Unused EMAC1_SWITCH_Enable false BSEL 1 PLL_CLK0 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100 PLL_CLK1 Unused quartus_ini_hps_ip_enable_test_interface false PLL_CLK2 Unused PLL_CLK3 Unused CM_Mode N/A PLL_CLK4 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 100 CLK_MAIN_PLL_SOURCE2 0 TESTIOCTRL_MAINCLKSEL 8 UART1_Mode No_flow_control I2C0_Mode default STM_Enable true - false - true - true - true - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - Arria 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - hps_io_phery_emac0_TX_CLK - Output - 1 - hps_io_phery_emac0_TX_CLK - - - hps_io_phery_emac0_TXD0 - Output - 1 - hps_io_phery_emac0_TXD0 - - - hps_io_phery_emac0_TXD1 - Output - 1 - hps_io_phery_emac0_TXD1 - - - hps_io_phery_emac0_TXD2 - Output - 1 - hps_io_phery_emac0_TXD2 - - - hps_io_phery_emac0_TXD3 - Output - 1 - hps_io_phery_emac0_TXD3 - - - hps_io_phery_emac0_RX_CTL - Input - 1 - hps_io_phery_emac0_RX_CTL - - - hps_io_phery_emac0_TX_CTL - Output - 1 - hps_io_phery_emac0_TX_CTL - - - hps_io_phery_emac0_RX_CLK - Input - 1 - hps_io_phery_emac0_RX_CLK - - - hps_io_phery_emac0_RXD0 - Input - 1 - hps_io_phery_emac0_RXD0 - - - hps_io_phery_emac0_RXD1 - Input - 1 - hps_io_phery_emac0_RXD1 - - - hps_io_phery_emac0_RXD2 - Input - 1 - hps_io_phery_emac0_RXD2 - - - hps_io_phery_emac0_RXD3 - Input - 1 - hps_io_phery_emac0_RXD3 - - - hps_io_phery_emac0_MDIO - Bidir - 1 - hps_io_phery_emac0_MDIO - - - hps_io_phery_emac0_MDC - Output - 1 - hps_io_phery_emac0_MDC - - - hps_io_phery_sdmmc_CMD - Bidir - 1 - hps_io_phery_sdmmc_CMD - - - hps_io_phery_sdmmc_D0 - Bidir - 1 - hps_io_phery_sdmmc_D0 - - - hps_io_phery_sdmmc_D1 - Bidir - 1 - hps_io_phery_sdmmc_D1 - - - hps_io_phery_sdmmc_D2 - Bidir - 1 - hps_io_phery_sdmmc_D2 - - - hps_io_phery_sdmmc_D3 - Bidir - 1 - hps_io_phery_sdmmc_D3 - - - hps_io_phery_sdmmc_CCLK - Output - 1 - hps_io_phery_sdmmc_CCLK - - - hps_io_phery_usb0_DATA0 - Bidir - 1 - hps_io_phery_usb0_DATA0 - - - hps_io_phery_usb0_DATA1 - Bidir - 1 - hps_io_phery_usb0_DATA1 - - - hps_io_phery_usb0_DATA2 - Bidir - 1 - hps_io_phery_usb0_DATA2 - - - hps_io_phery_usb0_DATA3 - Bidir - 1 - hps_io_phery_usb0_DATA3 - - - hps_io_phery_usb0_DATA4 - Bidir - 1 - hps_io_phery_usb0_DATA4 - - - hps_io_phery_usb0_DATA5 - Bidir - 1 - hps_io_phery_usb0_DATA5 - - - hps_io_phery_usb0_DATA6 - Bidir - 1 - hps_io_phery_usb0_DATA6 - - - hps_io_phery_usb0_DATA7 - Bidir - 1 - hps_io_phery_usb0_DATA7 - - - hps_io_phery_usb0_CLK - Input - 1 - hps_io_phery_usb0_CLK - - - hps_io_phery_usb0_STP - Output - 1 - hps_io_phery_usb0_STP - - - hps_io_phery_usb0_DIR - Input - 1 - hps_io_phery_usb0_DIR - - - hps_io_phery_usb0_NXT - Input - 1 - hps_io_phery_usb0_NXT - - - hps_io_phery_uart1_RX - Input - 1 - hps_io_phery_uart1_RX - - - hps_io_phery_uart1_TX - Output - 1 - hps_io_phery_uart1_TX - - - hps_io_phery_i2c0_SDA - Bidir - 1 - hps_io_phery_i2c0_SDA - - - hps_io_phery_i2c0_SCL - Bidir - 1 - hps_io_phery_i2c0_SCL - - - hps_io_gpio_gpio2_io8 - Bidir - 1 - hps_io_gpio_gpio2_io8 - - - hps_io_gpio_gpio2_io9 - Bidir - 1 - hps_io_gpio_gpio2_io9 - - - hps_io_gpio_gpio2_io10 - Bidir - 1 - hps_io_gpio_gpio2_io10 - - - hps_io_gpio_gpio2_io11 - Bidir - 1 - hps_io_gpio_gpio2_io11 - - - hps_io_gpio_gpio1_io1 - Bidir - 1 - hps_io_gpio_gpio1_io1 - - - hps_io_gpio_gpio1_io4 - Bidir - 1 - hps_io_gpio_gpio1_io4 - - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - new_signal_13 - Output - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - new_signal_14 - Output - 1 - clk - - - false - arria10_hps_bridges - clock_sink - arria10_hps_bridges.clock_sink - - - false - arria10_hps_arm_a9_0 - clock_sink - arria10_hps_arm_a9_0.clock_sink - - - false - arria10_hps_arm_a9_1 - clock_sink - arria10_hps_arm_a9_1.clock_sink - - - false - arria10_hps_arm_gic_0 - clock_sink - arria10_hps_arm_gic_0.clock_sink - - - false - arria10_hps_mpu_reg_l2_MPUL2 - clock_sink - arria10_hps_mpu_reg_l2_MPUL2.clock_sink - - - false - arria10_hps_i_sys_mgr_core - clock_sink - arria10_hps_i_sys_mgr_core.clock_sink - - - false - arria10_hps_i_rst_mgr_rstmgr - clock_sink - arria10_hps_i_rst_mgr_rstmgr.clock_sink - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - clock_sink - arria10_hps_i_fpga_mgr_fpgamgrregs.clock_sink - - - false - arria10_hps_scu - clock_sink - arria10_hps_scu.clock_sink - - - - - - - embeddedsw.dts.compatible - simple-bus - - - embeddedsw.dts.group - bridge - - - embeddedsw.dts.name - bridge - - - embeddedsw.dts.vendor - altr - - - java.lang.String - ]]> - false - true - true - true - ADDRESS_MAP - axi_f2h - - - int - 6 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 6 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram0_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram1_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram2_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram3_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram4_clock - - - int - 100 - false - true - false - true - CLOCK_RATE - f2h_sdram5_clock - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - addressSpan - 536870912 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - bridges.h2f - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 536870912 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 29 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 29 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - addressSpan - 2097152 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - bridges.h2f_lw - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 2097152 - true - true - false - true - - axi - false - - axi_sig1_40 - Input - 1 - awvalid - - - axi_sig1_41 - Output - 1 - awready - - - axi_sig1_42 - Input - 12 - awid - - - axi_sig1_43 - Input - 21 - awaddr - - - axi_sig1_44 - Input - 4 - awlen - - - axi_sig1_45 - Input - 3 - awsize - - - axi_sig1_46 - Input - 2 - awburst - - - axi_sig1_47 - Input - 2 - awlock - - - axi_sig1_48 - Input - 4 - awcache - - - axi_sig1_49 - Input - 3 - awprot - - - axi_sig1_50 - Input - 1 - awuser - - - axi_sig1_51 - Input - 1 - arvalid - - - axi_sig1_52 - Output - 1 - arready - - - axi_sig1_53 - Input - 12 - arid - - - axi_sig1_54 - Input - 21 - araddr - - - axi_sig1_55 - Input - 4 - arlen - - - axi_sig1_56 - Input - 3 - arsize - - - axi_sig1_57 - Input - 2 - arburst - - - axi_sig1_58 - Input - 2 - arlock - - - axi_sig1_59 - Input - 4 - arcache - - - axi_sig1_60 - Input - 3 - arprot - - - axi_sig1_61 - Input - 1 - aruser - - - axi_sig1_62 - Input - 1 - wvalid - - - axi_sig1_63 - Output - 1 - wready - - - axi_sig1_64 - Input - 12 - wid - - - axi_sig1_65 - Input - 1 - wlast - - - axi_sig1_66 - Input - 32 - wdata - - - axi_sig1_67 - Input - 4 - wstrb - - - axi_sig1_68 - Output - 1 - rvalid - - - axi_sig1_69 - Input - 1 - rready - - - axi_sig1_70 - Output - 12 - rid - - - axi_sig1_71 - Output - 1 - rlast - - - axi_sig1_72 - Output - 2 - rresp - - - axi_sig1_73 - Output - 32 - rdata - - - axi_sig1_74 - Output - 1 - bvalid - - - axi_sig1_75 - Input - 1 - bready - - - axi_sig1_76 - Output - 12 - bid - - - axi_sig1_77 - Output - 2 - bresp - - - - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - axi_master_sig - Output - 1 - awvalid - - - axi_master_sig_1 - Input - 1 - awready - - - axi_master_sig_2 - Output - 1 - awid - - - axi_master_sig_3 - Output - 32 - awaddr - - - axi_master_sig_4 - Output - 4 - awlen - - - axi_master_sig_5 - Output - 3 - awsize - - - axi_master_sig_6 - Output - 2 - awburst - - - axi_master_sig_7 - Output - 2 - awlock - - - axi_master_sig_8 - Output - 4 - awcache - - - axi_master_sig_9 - Output - 3 - awprot - - - axi_master_sig_10 - Output - 1 - awuser - - - axi_master_sig_11 - Output - 1 - arvalid - - - axi_master_sig_12 - Input - 1 - arready - - - axi_master_sig_14 - Output - 32 - araddr - - - axi_master_sig_15 - Output - 4 - arlen - - - axi_master_sig_16 - Output - 3 - arsize - - - axi_master_sig_17 - Output - 2 - arburst - - - axi_master_sig_18 - Output - 2 - arlock - - - axi_master_sig_19 - Output - 4 - arcache - - - axi_master_sig_20 - Output - 3 - arprot - - - axi_master_sig_21 - Output - 1 - aruser - - - axi_master_sig_13 - Output - 1 - arid - - - axi_master_sig_24 - Input - 1 - bid - - - axi_master_sig_25 - Input - 1 - rid - - - axi_master_sig_26 - Output - 1 - wid - - - axi_master_sig_27 - Output - 1 - wvalid - - - axi_master_sig_28 - Input - 1 - wready - - - axi_master_sig_29 - Output - 1 - wlast - - - axi_master_sig_30 - Output - 32 - wdata - - - axi_master_sig_31 - Output - 4 - wstrb - - - axi_master_sig_32 - Input - 1 - rvalid - - - axi_master_sig_33 - Output - 1 - rready - - - axi_master_sig_34 - Input - 1 - rlast - - - axi_master_sig_35 - Input - 2 - rresp - - - axi_master_sig_36 - Input - 32 - rdata - - - axi_master_sig_37 - Input - 1 - bvalid - - - axi_master_sig_38 - Output - 1 - bready - - - axi_master_sig_39 - Input - 2 - bresp - - - false - arria10_hps_baum_clkmgr - axi_slave0 - arria10_hps_baum_clkmgr.axi_slave0 - 4291837952 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave0 - arria10_hps_arm_gic_0.axi_slave0 - 4294955008 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave1 - arria10_hps_arm_gic_0.axi_slave1 - 4294951168 - 256 - - - false - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - arria10_hps_mpu_reg_l2_MPUL2.axi_slave0 - 4294963200 - 4096 - - - false - arria10_hps_i_dma_DMASECURE - axi_slave0 - arria10_hps_i_dma_DMASECURE.axi_slave0 - 4292481024 - 4096 - - - false - arria10_hps_i_sys_mgr_core - axi_slave0 - arria10_hps_i_sys_mgr_core.axi_slave0 - 4291846144 - 1024 - - - false - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - arria10_hps_i_rst_mgr_rstmgr.axi_slave0 - 4291842048 - 256 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0 - 4291833856 - 4096 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1 - 4291814400 - 256 - - - false - arria10_hps_i_uart_0_uart - axi_slave0 - arria10_hps_i_uart_0_uart.axi_slave0 - 4290781184 - 256 - - - false - arria10_hps_i_uart_1_uart - axi_slave0 - arria10_hps_i_uart_1_uart.axi_slave0 - 4290781440 - 256 - - - false - arria10_hps_i_timer_sp_0_timer - axi_slave0 - arria10_hps_i_timer_sp_0_timer.axi_slave0 - 4290782976 - 256 - - - false - arria10_hps_i_timer_sp_1_timer - axi_slave0 - arria10_hps_i_timer_sp_1_timer.axi_slave0 - 4290783232 - 256 - - - false - arria10_hps_i_timer_sys_0_timer - axi_slave0 - arria10_hps_i_timer_sys_0_timer.axi_slave0 - 4291821568 - 256 - - - false - arria10_hps_i_timer_sys_1_timer - axi_slave0 - arria10_hps_i_timer_sys_1_timer.axi_slave0 - 4291821824 - 256 - - - false - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - arria10_hps_i_watchdog_0_l4wd.axi_slave0 - 4291822080 - 256 - - - false - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - arria10_hps_i_watchdog_1_l4wd.axi_slave0 - 4291822336 - 256 - - - false - arria10_hps_i_gpio_0_gpio - axi_slave0 - arria10_hps_i_gpio_0_gpio.axi_slave0 - 4290783488 - 256 - - - false - arria10_hps_i_gpio_1_gpio - axi_slave0 - arria10_hps_i_gpio_1_gpio.axi_slave0 - 4290783744 - 256 - - - false - arria10_hps_i_gpio_2_gpio - axi_slave0 - arria10_hps_i_gpio_2_gpio.axi_slave0 - 4290784000 - 256 - - - false - arria10_hps_i_i2c_0_i2c - axi_slave0 - arria10_hps_i_i2c_0_i2c.axi_slave0 - 4290781696 - 256 - - - false - arria10_hps_i_i2c_1_i2c - axi_slave0 - arria10_hps_i_i2c_1_i2c.axi_slave0 - 4290781952 - 256 - - - false - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - arria10_hps_i_i2c_emac_0_i2c.axi_slave0 - 4290782208 - 256 - - - false - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - arria10_hps_i_i2c_emac_1_i2c.axi_slave0 - 4290782464 - 256 - - - false - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - arria10_hps_i_i2c_emac_2_i2c.axi_slave0 - 4290782720 - 256 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave0 - arria10_hps_i_nand_NANDDATA.axi_slave0 - 4290314240 - 65536 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave1 - arria10_hps_i_nand_NANDDATA.axi_slave1 - 4290248704 - 65536 - - - false - arria10_hps_i_spim_0_spim - axi_slave0 - arria10_hps_i_spim_0_spim.axi_slave0 - 4292493312 - 256 - - - false - arria10_hps_i_spim_1_spim - axi_slave0 - arria10_hps_i_spim_1_spim.axi_slave0 - 4292497408 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - arria10_hps_i_qspi_QSPIDATA.axi_slave0 - 4286615552 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - arria10_hps_i_qspi_QSPIDATA.axi_slave1 - 4288675840 - 256 - - - false - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - arria10_hps_i_sdmmc_sdmmc.axi_slave0 - 4286611456 - 4096 - - - false - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - arria10_hps_i_usbotg_0_globgrp.axi_slave0 - 4289724416 - 262144 - - - false - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - arria10_hps_i_usbotg_1_globgrp.axi_slave0 - 4289986560 - 262144 - - - false - arria10_hps_i_emac_emac0 - axi_slave0 - arria10_hps_i_emac_emac0.axi_slave0 - 4286578688 - 8192 - - - false - arria10_hps_i_emac_emac1 - axi_slave0 - arria10_hps_i_emac_emac1.axi_slave0 - 4286586880 - 8192 - - - false - arria10_hps_i_emac_emac2 - axi_slave0 - arria10_hps_i_emac_emac2.axi_slave0 - 4286595072 - 8192 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - h2f_rst_n - Output - 1 - reset_n - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - new_signal_13 - Input - 1 - reset - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - new_signal_14 - Input - 1 - clk - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - h2f_axi_clk - Input - 1 - clk - - - - - - java.lang.String - h2f_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - h2f_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - h2f_axi_clock - false - true - true - true - - - java.lang.String - h2f_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - h2f_AWID - Output - 4 - awid - - - h2f_AWADDR - Output - 32 - awaddr - - - h2f_AWLEN - Output - 4 - awlen - - - h2f_AWSIZE - Output - 3 - awsize - - - h2f_AWBURST - Output - 2 - awburst - - - h2f_AWLOCK - Output - 2 - awlock - - - h2f_AWCACHE - Output - 4 - awcache - - - h2f_AWPROT - Output - 3 - awprot - - - h2f_AWVALID - Output - 1 - awvalid - - - h2f_AWREADY - Input - 1 - awready - - - h2f_AWUSER - Output - 5 - awuser - - - h2f_WID - Output - 4 - wid - - - h2f_WDATA - Output - 64 - wdata - - - h2f_WSTRB - Output - 8 - wstrb - - - h2f_WLAST - Output - 1 - wlast - - - h2f_WVALID - Output - 1 - wvalid - - - h2f_WREADY - Input - 1 - wready - - - h2f_BID - Input - 4 - bid - - - h2f_BRESP - Input - 2 - bresp - - - h2f_BVALID - Input - 1 - bvalid - - - h2f_BREADY - Output - 1 - bready - - - h2f_ARID - Output - 4 - arid - - - h2f_ARADDR - Output - 32 - araddr - - - h2f_ARLEN - Output - 4 - arlen - - - h2f_ARSIZE - Output - 3 - arsize - - - h2f_ARBURST - Output - 2 - arburst - - - h2f_ARLOCK - Output - 2 - arlock - - - h2f_ARCACHE - Output - 4 - arcache - - - h2f_ARPROT - Output - 3 - arprot - - - h2f_ARVALID - Output - 1 - arvalid - - - h2f_ARREADY - Input - 1 - arready - - - h2f_ARUSER - Output - 5 - aruser - - - h2f_RID - Input - 4 - rid - - - h2f_RDATA - Input - 64 - rdata - - - h2f_RRESP - Input - 2 - rresp - - - h2f_RLAST - Input - 1 - rlast - - - h2f_RVALID - Input - 1 - rvalid - - - h2f_RREADY - Output - 1 - rready - - - true - h2fw_ClockBridge - s0 - h2fw_ClockBridge.s0 - 0 - 1024 - - - false - sevensig - avalon_slave_0 - sevensig.avalon_slave_0 - 0 - 8 - - - false - fancmd - avalon_slave_0_1 - fancmd.avalon_slave_0_1 - 8 - 8 - - - false - onchip_memory2 - s1 - onchip_memory2.s1 - 16777216 - 262144 - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - h2f_lw_axi_clk - Input - 1 - clk - - - - - - java.lang.String - h2f_lw_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - h2f_lw_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - h2f_lw_axi_clock - false - true - true - true - - - java.lang.String - h2f_lw_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - h2f_lw_AWID - Output - 4 - awid - - - h2f_lw_AWADDR - Output - 21 - awaddr - - - h2f_lw_AWLEN - Output - 4 - awlen - - - h2f_lw_AWSIZE - Output - 3 - awsize - - - h2f_lw_AWBURST - Output - 2 - awburst - - - h2f_lw_AWLOCK - Output - 2 - awlock - - - h2f_lw_AWCACHE - Output - 4 - awcache - - - h2f_lw_AWPROT - Output - 3 - awprot - - - h2f_lw_AWVALID - Output - 1 - awvalid - - - h2f_lw_AWREADY - Input - 1 - awready - - - h2f_lw_AWUSER - Output - 5 - awuser - - - h2f_lw_WID - Output - 4 - wid - - - h2f_lw_WDATA - Output - 32 - wdata - - - h2f_lw_WSTRB - Output - 4 - wstrb - - - h2f_lw_WLAST - Output - 1 - wlast - - - h2f_lw_WVALID - Output - 1 - wvalid - - - h2f_lw_WREADY - Input - 1 - wready - - - h2f_lw_BID - Input - 4 - bid - - - h2f_lw_BRESP - Input - 2 - bresp - - - h2f_lw_BVALID - Input - 1 - bvalid - - - h2f_lw_BREADY - Output - 1 - bready - - - h2f_lw_ARID - Output - 4 - arid - - - h2f_lw_ARADDR - Output - 21 - araddr - - - h2f_lw_ARLEN - Output - 4 - arlen - - - h2f_lw_ARSIZE - Output - 3 - arsize - - - h2f_lw_ARBURST - Output - 2 - arburst - - - h2f_lw_ARLOCK - Output - 2 - arlock - - - h2f_lw_ARCACHE - Output - 4 - arcache - - - h2f_lw_ARPROT - Output - 3 - arprot - - - h2f_lw_ARVALID - Output - 1 - arvalid - - - h2f_lw_ARREADY - Input - 1 - arready - - - h2f_lw_ARUSER - Output - 5 - aruser - - - h2f_lw_RID - Input - 4 - rid - - - h2f_lw_RDATA - Input - 32 - rdata - - - h2f_lw_RRESP - Input - 2 - rresp - - - h2f_lw_RLAST - Input - 1 - rlast - - - h2f_lw_RVALID - Input - 1 - rvalid - - - h2f_lw_RREADY - Output - 1 - rready - - - true - pb_lwh2f - s0 - pb_lwh2f.s0 - 0 - 512 - - - false - ILC - avalon_slave - ILC.avalon_slave - 0 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 304 - 8 - - - false - led_pio - s1 - led_pio.s1 - 288 - 16 - - - false - button_pio - s1 - button_pio.s1 - 272 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 256 - 16 - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - f2h_axi_clk - Input - 1 - clk - - - - - - java.lang.String - f2h_axi_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2h_axi_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - f2h_axi_clock - false - true - true - true - - - java.lang.String - f2h_axi_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - bridges.axi_f2h - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4294967296 - true - true - false - true - - axi - false - - f2h_AWID - Input - 4 - awid - - - f2h_AWADDR - Input - 32 - awaddr - - - f2h_AWLEN - Input - 4 - awlen - - - f2h_AWSIZE - Input - 3 - awsize - - - f2h_AWBURST - Input - 2 - awburst - - - f2h_AWLOCK - Input - 2 - awlock - - - f2h_AWCACHE - Input - 4 - awcache - - - f2h_AWPROT - Input - 3 - awprot - - - f2h_AWVALID - Input - 1 - awvalid - - - f2h_AWREADY - Output - 1 - awready - - - f2h_AWUSER - Input - 5 - awuser - - - f2h_WID - Input - 4 - wid - - - f2h_WDATA - Input - 128 - wdata - - - f2h_WSTRB - Input - 16 - wstrb - - - f2h_WLAST - Input - 1 - wlast - - - f2h_WVALID - Input - 1 - wvalid - - - f2h_WREADY - Output - 1 - wready - - - f2h_BID - Output - 4 - bid - - - f2h_BRESP - Output - 2 - bresp - - - f2h_BVALID - Output - 1 - bvalid - - - f2h_BREADY - Input - 1 - bready - - - f2h_ARID - Input - 4 - arid - - - f2h_ARADDR - Input - 32 - araddr - - - f2h_ARLEN - Input - 4 - arlen - - - f2h_ARSIZE - Input - 3 - arsize - - - f2h_ARBURST - Input - 2 - arburst - - - f2h_ARLOCK - Input - 2 - arlock - - - f2h_ARCACHE - Input - 4 - arcache - - - f2h_ARPROT - Input - 3 - arprot - - - f2h_ARVALID - Input - 1 - arvalid - - - f2h_ARREADY - Output - 1 - arready - - - f2h_ARUSER - Input - 5 - aruser - - - f2h_RID - Output - 4 - rid - - - f2h_RDATA - Output - 128 - rdata - - - f2h_RRESP - Output - 2 - rresp - - - f2h_RLAST - Output - 1 - rlast - - - f2h_RVALID - Output - 1 - rvalid - - - f2h_RREADY - Input - 1 - rready - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - f2sdram0_clk - Input - 1 - clk - - - - - - java.lang.String - f2sdram0_clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - f2s_sdram0_rst_n - Input - 1 - reset_n - - - - - - java.lang.String - f2sdram0_clock - false - true - true - true - - - java.lang.String - f2sdram0_reset - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 8 - false - true - true - true - - - java.lang.Integer - 16 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - axi_f2sdram0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4294967296 - true - true - false - true - - axi - false - - f2sdram0_AWID - Input - 4 - awid - - - f2sdram0_AWADDR - Input - 32 - awaddr - - - f2sdram0_AWLEN - Input - 4 - awlen - - - f2sdram0_AWSIZE - Input - 3 - awsize - - - f2sdram0_AWBURST - Input - 2 - awburst - - - f2sdram0_AWLOCK - Input - 2 - awlock - - - f2sdram0_AWCACHE - Input - 4 - awcache - - - f2sdram0_AWPROT - Input - 3 - awprot - - - f2sdram0_AWVALID - Input - 1 - awvalid - - - f2sdram0_AWREADY - Output - 1 - awready - - - f2sdram0_AWUSER - Input - 5 - awuser - - - f2sdram0_WID - Input - 4 - wid - - - f2sdram0_WDATA - Input - 128 - wdata - - - f2sdram0_WSTRB - Input - 16 - wstrb - - - f2sdram0_WLAST - Input - 1 - wlast - - - f2sdram0_WVALID - Input - 1 - wvalid - - - f2sdram0_WREADY - Output - 1 - wready - - - f2sdram0_BID - Output - 4 - bid - - - f2sdram0_BRESP - Output - 2 - bresp - - - f2sdram0_BVALID - Output - 1 - bvalid - - - f2sdram0_BREADY - Input - 1 - bready - - - f2sdram0_ARID - Input - 4 - arid - - - f2sdram0_ARADDR - Input - 32 - araddr - - - f2sdram0_ARLEN - Input - 4 - arlen - - - f2sdram0_ARSIZE - Input - 3 - arsize - - - f2sdram0_ARBURST - Input - 2 - arburst - - - f2sdram0_ARLOCK - Input - 2 - arlock - - - f2sdram0_ARCACHE - Input - 4 - arcache - - - f2sdram0_ARPROT - Input - 3 - arprot - - - f2sdram0_ARVALID - Input - 1 - arvalid - - - f2sdram0_ARREADY - Output - 1 - arready - - - f2sdram0_ARUSER - Input - 5 - aruser - - - f2sdram0_RID - Output - 4 - rid - - - f2sdram0_RDATA - Output - 128 - rdata - - - f2sdram0_RRESP - Output - 2 - rresp - - - f2sdram0_RLAST - Output - 1 - rlast - - - f2sdram0_RVALID - Output - 1 - rvalid - - - f2sdram0_RREADY - Input - 1 - rready - - - - - - - embeddedsw.dts.compatible - fixed-clock - - - embeddedsw.dts.group - clock - - - embeddedsw.dts.vendor - altr - - - long - 25000000 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - new_signal_13 - Output - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 25000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - new_signal_14 - Output - 1 - clk - - - false - arria10_hps_baum_clkmgr - eosc1 - arria10_hps_baum_clkmgr.eosc1 - - - - - - - embeddedsw.dts.compatible - fixed-clock - - - embeddedsw.dts.group - clock - - - embeddedsw.dts.vendor - altr - - - long - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - new_signal_13 - Output - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - new_signal_14 - Output - 1 - clk - - - false - arria10_hps_baum_clkmgr - cb_intosc_hs_div2_clk - arria10_hps_baum_clkmgr.cb_intosc_hs_div2_clk - - - - - - - embeddedsw.dts.compatible - fixed-clock - - - embeddedsw.dts.group - clock - - - embeddedsw.dts.vendor - altr - - - long - 60000000 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - new_signal_13 - Output - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 60000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - new_signal_14 - Output - 1 - clk - - - false - arria10_hps_baum_clkmgr - cb_intosc_ls_clk - arria10_hps_baum_clkmgr.cb_intosc_ls_clk - - - - - - - embeddedsw.dts.compatible - fixed-clock - - - embeddedsw.dts.group - clock - - - embeddedsw.dts.vendor - altr - - - long - 200000000 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - new_signal_13 - Output - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 200000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - new_signal_14 - Output - 1 - clk - - - false - arria10_hps_baum_clkmgr - f2s_free_clk - arria10_hps_baum_clkmgr.f2s_free_clk - - - - - - - embeddedsw.dts.compatible - arm,cortex-a9 - - - embeddedsw.dts.group - cpu - - - embeddedsw.dts.name - cortex-a9 - - - embeddedsw.dts.vendor - arm - - - java.lang.String - ]]> - false - true - true - true - ADDRESS_MAP - altera_axi_master - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - new_signal - Output - 1 - awvalid - - - new_signal_1 - Input - 1 - awready - - - new_signal_2 - Output - 1 - awid - - - new_signal_3 - Output - 32 - awaddr - - - new_signal_4 - Output - 4 - awlen - - - new_signal_5 - Output - 3 - awsize - - - new_signal_6 - Output - 2 - awburst - - - new_signal_7 - Output - 2 - awlock - - - new_signal_8 - Output - 4 - awcache - - - new_signal_9 - Output - 3 - awprot - - - new_signal_10 - Output - 1 - awuser - - - new_signal_11 - Output - 1 - arvalid - - - new_signal_12 - Input - 1 - arready - - - new_signal_14 - Output - 32 - araddr - - - new_signal_15 - Output - 4 - arlen - - - new_signal_16 - Output - 3 - arsize - - - new_signal_17 - Output - 2 - arburst - - - new_signal_18 - Output - 2 - arlock - - - new_signal_19 - Output - 4 - arcache - - - new_signal_20 - Output - 3 - arprot - - - new_signal_21 - Output - 1 - aruser - - - new_signal_13 - Output - 1 - arid - - - new_signal_24 - Input - 1 - bid - - - new_signal_25 - Input - 1 - rid - - - new_signal_26 - Output - 1 - wid - - - new_signal_27 - Output - 1 - wvalid - - - new_signal_28 - Input - 1 - wready - - - new_signal_29 - Output - 1 - wlast - - - new_signal_30 - Output - 32 - wdata - - - new_signal_31 - Output - 4 - wstrb - - - new_signal_32 - Input - 1 - rvalid - - - new_signal_33 - Output - 1 - rready - - - new_signal_34 - Input - 1 - rlast - - - new_signal_35 - Input - 2 - rresp - - - new_signal_36 - Input - 32 - rdata - - - new_signal_37 - Input - 1 - bvalid - - - new_signal_38 - Output - 1 - bready - - - new_signal_39 - Input - 2 - bresp - - - true - arria10_hps_bridges - axi_h2f - arria10_hps_bridges.axi_h2f - 3221225472 - 536870912 - - - true - h2fw_ClockBridge - s0 - h2fw_ClockBridge.s0 - 3221225472 - 1024 - - - false - sevensig - avalon_slave_0 - sevensig.avalon_slave_0 - 3221225472 - 8 - - - false - fancmd - avalon_slave_0_1 - fancmd.avalon_slave_0_1 - 3221225480 - 8 - - - false - onchip_memory2 - s1 - onchip_memory2.s1 - 3238002688 - 262144 - - - true - arria10_hps_bridges - axi_h2f_lw - arria10_hps_bridges.axi_h2f_lw - 4280287232 - 2097152 - - - true - pb_lwh2f - s0 - pb_lwh2f.s0 - 4280287232 - 512 - - - false - ILC - avalon_slave - ILC.avalon_slave - 4280287232 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 4280287536 - 8 - - - false - led_pio - s1 - led_pio.s1 - 4280287520 - 16 - - - false - button_pio - s1 - button_pio.s1 - 4280287504 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 4280287488 - 16 - - - false - arria10_hps_arm_gic_0 - axi_slave0 - arria10_hps_arm_gic_0.axi_slave0 - 4294955008 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave1 - arria10_hps_arm_gic_0.axi_slave1 - 4294951168 - 256 - - - false - arria10_hps_baum_clkmgr - axi_slave0 - arria10_hps_baum_clkmgr.axi_slave0 - 4291837952 - 4096 - - - false - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - arria10_hps_mpu_reg_l2_MPUL2.axi_slave0 - 4294963200 - 4096 - - - false - arria10_hps_i_dma_DMASECURE - axi_slave0 - arria10_hps_i_dma_DMASECURE.axi_slave0 - 4292481024 - 4096 - - - false - arria10_hps_i_sys_mgr_core - axi_slave0 - arria10_hps_i_sys_mgr_core.axi_slave0 - 4291846144 - 1024 - - - false - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - arria10_hps_i_rst_mgr_rstmgr.axi_slave0 - 4291842048 - 256 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0 - 4291833856 - 4096 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1 - 4291814400 - 256 - - - false - arria10_hps_timer - axi_slave0 - arria10_hps_timer.axi_slave0 - 4294952448 - 256 - - - false - arria10_hps_i_timer_sp_0_timer - axi_slave0 - arria10_hps_i_timer_sp_0_timer.axi_slave0 - 4290782976 - 256 - - - false - arria10_hps_i_timer_sp_1_timer - axi_slave0 - arria10_hps_i_timer_sp_1_timer.axi_slave0 - 4290783232 - 256 - - - false - arria10_hps_i_timer_sys_0_timer - axi_slave0 - arria10_hps_i_timer_sys_0_timer.axi_slave0 - 4291821568 - 256 - - - false - arria10_hps_i_timer_sys_1_timer - axi_slave0 - arria10_hps_i_timer_sys_1_timer.axi_slave0 - 4291821824 - 256 - - - false - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - arria10_hps_i_watchdog_0_l4wd.axi_slave0 - 4291822080 - 256 - - - false - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - arria10_hps_i_watchdog_1_l4wd.axi_slave0 - 4291822336 - 256 - - - false - arria10_hps_i_gpio_0_gpio - axi_slave0 - arria10_hps_i_gpio_0_gpio.axi_slave0 - 4290783488 - 256 - - - false - arria10_hps_i_gpio_1_gpio - axi_slave0 - arria10_hps_i_gpio_1_gpio.axi_slave0 - 4290783744 - 256 - - - false - arria10_hps_i_gpio_2_gpio - axi_slave0 - arria10_hps_i_gpio_2_gpio.axi_slave0 - 4290784000 - 256 - - - false - arria10_hps_i_uart_0_uart - axi_slave0 - arria10_hps_i_uart_0_uart.axi_slave0 - 4290781184 - 256 - - - false - arria10_hps_i_uart_1_uart - axi_slave0 - arria10_hps_i_uart_1_uart.axi_slave0 - 4290781440 - 256 - - - false - arria10_hps_i_emac_emac0 - axi_slave0 - arria10_hps_i_emac_emac0.axi_slave0 - 4286578688 - 8192 - - - false - arria10_hps_i_emac_emac1 - axi_slave0 - arria10_hps_i_emac_emac1.axi_slave0 - 4286586880 - 8192 - - - false - arria10_hps_i_emac_emac2 - axi_slave0 - arria10_hps_i_emac_emac2.axi_slave0 - 4286595072 - 8192 - - - false - arria10_hps_i_spim_0_spim - axi_slave0 - arria10_hps_i_spim_0_spim.axi_slave0 - 4292493312 - 256 - - - false - arria10_hps_i_spim_1_spim - axi_slave0 - arria10_hps_i_spim_1_spim.axi_slave0 - 4292497408 - 256 - - - false - arria10_hps_i_spis_0_spis - axi_slave0 - arria10_hps_i_spis_0_spis.axi_slave0 - 4292485120 - 256 - - - false - arria10_hps_i_spis_1_spis - axi_slave0 - arria10_hps_i_spis_1_spis.axi_slave0 - 4292489216 - 256 - - - false - arria10_hps_i_i2c_0_i2c - axi_slave0 - arria10_hps_i_i2c_0_i2c.axi_slave0 - 4290781696 - 256 - - - false - arria10_hps_i_i2c_1_i2c - axi_slave0 - arria10_hps_i_i2c_1_i2c.axi_slave0 - 4290781952 - 256 - - - false - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - arria10_hps_i_i2c_emac_0_i2c.axi_slave0 - 4290782208 - 256 - - - false - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - arria10_hps_i_i2c_emac_1_i2c.axi_slave0 - 4290782464 - 256 - - - false - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - arria10_hps_i_i2c_emac_2_i2c.axi_slave0 - 4290782720 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - arria10_hps_i_qspi_QSPIDATA.axi_slave0 - 4286615552 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - arria10_hps_i_qspi_QSPIDATA.axi_slave1 - 4288675840 - 256 - - - false - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - arria10_hps_i_sdmmc_sdmmc.axi_slave0 - 4286611456 - 4096 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave0 - arria10_hps_i_nand_NANDDATA.axi_slave0 - 4290314240 - 65536 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave1 - arria10_hps_i_nand_NANDDATA.axi_slave1 - 4290248704 - 65536 - - - false - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - arria10_hps_i_usbotg_0_globgrp.axi_slave0 - 4289724416 - 262144 - - - false - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - arria10_hps_i_usbotg_1_globgrp.axi_slave0 - 4289986560 - 262144 - - - false - arria10_hps_scu - axi_slave0 - arria10_hps_scu.axi_slave0 - 4294950912 - 256 - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - new_signal_22 - Input - 1 - reset - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - new_signal_23 - Input - 1 - clk - - - - - - - embeddedsw.dts.compatible - arm,cortex-a9 - - - embeddedsw.dts.group - cpu - - - embeddedsw.dts.name - cortex-a9 - - - embeddedsw.dts.vendor - arm - - - java.lang.String - ]]> - false - true - true - true - ADDRESS_MAP - altera_axi_master - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - axi - true - - new_signal - Output - 1 - awvalid - - - new_signal_1 - Input - 1 - awready - - - new_signal_2 - Output - 1 - awid - - - new_signal_3 - Output - 32 - awaddr - - - new_signal_4 - Output - 4 - awlen - - - new_signal_5 - Output - 3 - awsize - - - new_signal_6 - Output - 2 - awburst - - - new_signal_7 - Output - 2 - awlock - - - new_signal_8 - Output - 4 - awcache - - - new_signal_9 - Output - 3 - awprot - - - new_signal_10 - Output - 1 - awuser - - - new_signal_11 - Output - 1 - arvalid - - - new_signal_12 - Input - 1 - arready - - - new_signal_14 - Output - 32 - araddr - - - new_signal_15 - Output - 4 - arlen - - - new_signal_16 - Output - 3 - arsize - - - new_signal_17 - Output - 2 - arburst - - - new_signal_18 - Output - 2 - arlock - - - new_signal_19 - Output - 4 - arcache - - - new_signal_20 - Output - 3 - arprot - - - new_signal_21 - Output - 1 - aruser - - - new_signal_13 - Output - 1 - arid - - - new_signal_24 - Input - 1 - bid - - - new_signal_25 - Input - 1 - rid - - - new_signal_26 - Output - 1 - wid - - - new_signal_27 - Output - 1 - wvalid - - - new_signal_28 - Input - 1 - wready - - - new_signal_29 - Output - 1 - wlast - - - new_signal_30 - Output - 32 - wdata - - - new_signal_31 - Output - 4 - wstrb - - - new_signal_32 - Input - 1 - rvalid - - - new_signal_33 - Output - 1 - rready - - - new_signal_34 - Input - 1 - rlast - - - new_signal_35 - Input - 2 - rresp - - - new_signal_36 - Input - 32 - rdata - - - new_signal_37 - Input - 1 - bvalid - - - new_signal_38 - Output - 1 - bready - - - new_signal_39 - Input - 2 - bresp - - - true - arria10_hps_bridges - axi_h2f - arria10_hps_bridges.axi_h2f - 3221225472 - 536870912 - - - true - h2fw_ClockBridge - s0 - h2fw_ClockBridge.s0 - 3221225472 - 1024 - - - false - sevensig - avalon_slave_0 - sevensig.avalon_slave_0 - 3221225472 - 8 - - - false - fancmd - avalon_slave_0_1 - fancmd.avalon_slave_0_1 - 3221225480 - 8 - - - false - onchip_memory2 - s1 - onchip_memory2.s1 - 3238002688 - 262144 - - - true - arria10_hps_bridges - axi_h2f_lw - arria10_hps_bridges.axi_h2f_lw - 4280287232 - 2097152 - - - true - pb_lwh2f - s0 - pb_lwh2f.s0 - 4280287232 - 512 - - - false - ILC - avalon_slave - ILC.avalon_slave - 4280287232 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 4280287536 - 8 - - - false - led_pio - s1 - led_pio.s1 - 4280287520 - 16 - - - false - button_pio - s1 - button_pio.s1 - 4280287504 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 4280287488 - 16 - - - false - arria10_hps_arm_gic_0 - axi_slave0 - arria10_hps_arm_gic_0.axi_slave0 - 4294955008 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave1 - arria10_hps_arm_gic_0.axi_slave1 - 4294951168 - 256 - - - false - arria10_hps_baum_clkmgr - axi_slave0 - arria10_hps_baum_clkmgr.axi_slave0 - 4291837952 - 4096 - - - false - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - arria10_hps_mpu_reg_l2_MPUL2.axi_slave0 - 4294963200 - 4096 - - - false - arria10_hps_i_dma_DMASECURE - axi_slave0 - arria10_hps_i_dma_DMASECURE.axi_slave0 - 4292481024 - 4096 - - - false - arria10_hps_i_sys_mgr_core - axi_slave0 - arria10_hps_i_sys_mgr_core.axi_slave0 - 4291846144 - 1024 - - - false - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - arria10_hps_i_rst_mgr_rstmgr.axi_slave0 - 4291842048 - 256 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0 - 4291833856 - 4096 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1 - 4291814400 - 256 - - - false - arria10_hps_timer - axi_slave0 - arria10_hps_timer.axi_slave0 - 4294952448 - 256 - - - false - arria10_hps_i_timer_sp_0_timer - axi_slave0 - arria10_hps_i_timer_sp_0_timer.axi_slave0 - 4290782976 - 256 - - - false - arria10_hps_i_timer_sp_1_timer - axi_slave0 - arria10_hps_i_timer_sp_1_timer.axi_slave0 - 4290783232 - 256 - - - false - arria10_hps_i_timer_sys_0_timer - axi_slave0 - arria10_hps_i_timer_sys_0_timer.axi_slave0 - 4291821568 - 256 - - - false - arria10_hps_i_timer_sys_1_timer - axi_slave0 - arria10_hps_i_timer_sys_1_timer.axi_slave0 - 4291821824 - 256 - - - false - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - arria10_hps_i_watchdog_0_l4wd.axi_slave0 - 4291822080 - 256 - - - false - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - arria10_hps_i_watchdog_1_l4wd.axi_slave0 - 4291822336 - 256 - - - false - arria10_hps_i_gpio_0_gpio - axi_slave0 - arria10_hps_i_gpio_0_gpio.axi_slave0 - 4290783488 - 256 - - - false - arria10_hps_i_gpio_1_gpio - axi_slave0 - arria10_hps_i_gpio_1_gpio.axi_slave0 - 4290783744 - 256 - - - false - arria10_hps_i_gpio_2_gpio - axi_slave0 - arria10_hps_i_gpio_2_gpio.axi_slave0 - 4290784000 - 256 - - - false - arria10_hps_i_uart_0_uart - axi_slave0 - arria10_hps_i_uart_0_uart.axi_slave0 - 4290781184 - 256 - - - false - arria10_hps_i_uart_1_uart - axi_slave0 - arria10_hps_i_uart_1_uart.axi_slave0 - 4290781440 - 256 - - - false - arria10_hps_i_emac_emac0 - axi_slave0 - arria10_hps_i_emac_emac0.axi_slave0 - 4286578688 - 8192 - - - false - arria10_hps_i_emac_emac1 - axi_slave0 - arria10_hps_i_emac_emac1.axi_slave0 - 4286586880 - 8192 - - - false - arria10_hps_i_emac_emac2 - axi_slave0 - arria10_hps_i_emac_emac2.axi_slave0 - 4286595072 - 8192 - - - false - arria10_hps_i_spim_0_spim - axi_slave0 - arria10_hps_i_spim_0_spim.axi_slave0 - 4292493312 - 256 - - - false - arria10_hps_i_spim_1_spim - axi_slave0 - arria10_hps_i_spim_1_spim.axi_slave0 - 4292497408 - 256 - - - false - arria10_hps_i_spis_0_spis - axi_slave0 - arria10_hps_i_spis_0_spis.axi_slave0 - 4292485120 - 256 - - - false - arria10_hps_i_spis_1_spis - axi_slave0 - arria10_hps_i_spis_1_spis.axi_slave0 - 4292489216 - 256 - - - false - arria10_hps_i_i2c_0_i2c - axi_slave0 - arria10_hps_i_i2c_0_i2c.axi_slave0 - 4290781696 - 256 - - - false - arria10_hps_i_i2c_1_i2c - axi_slave0 - arria10_hps_i_i2c_1_i2c.axi_slave0 - 4290781952 - 256 - - - false - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - arria10_hps_i_i2c_emac_0_i2c.axi_slave0 - 4290782208 - 256 - - - false - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - arria10_hps_i_i2c_emac_1_i2c.axi_slave0 - 4290782464 - 256 - - - false - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - arria10_hps_i_i2c_emac_2_i2c.axi_slave0 - 4290782720 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - arria10_hps_i_qspi_QSPIDATA.axi_slave0 - 4286615552 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - arria10_hps_i_qspi_QSPIDATA.axi_slave1 - 4288675840 - 256 - - - false - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - arria10_hps_i_sdmmc_sdmmc.axi_slave0 - 4286611456 - 4096 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave0 - arria10_hps_i_nand_NANDDATA.axi_slave0 - 4290314240 - 65536 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave1 - arria10_hps_i_nand_NANDDATA.axi_slave1 - 4290248704 - 65536 - - - false - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - arria10_hps_i_usbotg_0_globgrp.axi_slave0 - 4289724416 - 262144 - - - false - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - arria10_hps_i_usbotg_1_globgrp.axi_slave0 - 4289986560 - 262144 - - - false - arria10_hps_scu - axi_slave0 - arria10_hps_scu.axi_slave0 - 4294950912 - 256 - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - new_signal_22 - Input - 1 - reset - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - new_signal_23 - Input - 1 - clk - - - - - - - embeddedsw.dts.compatible - arm,cortex-a9-gic - - - embeddedsw.dts.group - intc - - - embeddedsw.dts.name - cortex-a9-gic - - - embeddedsw.dts.vendor - arm - - - java.math.BigInteger - 8192 - false - true - false - true - INTERRUPTS_USED - arm_gic_ppi - - - java.math.BigInteger - 262144 - false - true - false - true - INTERRUPTS_USED - irq_rx_offset_0 - - - java.math.BigInteger - 0 - false - true - false - true - INTERRUPTS_USED - f2h_irq_0_irq_rx_offset_19 - - - java.math.BigInteger - 0 - false - true - false - true - INTERRUPTS_USED - f2h_irq_32_irq_rx_offset_51 - - - java.math.BigInteger - 4294950401 - false - true - false - true - INTERRUPTS_USED - irq_rx_offset_83 - - - java.math.BigInteger - 319 - false - true - false - true - INTERRUPTS_USED - irq_rx_offset_115 - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - new_signal_2 - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - new_signal_3 - Input - 1 - reset - - - - - - embeddedsw.dts.irq.rx_offset - 0 - - - embeddedsw.dts.irq.rx_type - arm_gic_ppi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - ppi_irq_siq - Input - 19 - irq - - - false - arria10_hps_timer - interrupt_sender - arria10_hps_timer.interrupt_sender - 13 - - - - - - embeddedsw.dts.irq.rx_offset - 0 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_siq_0 - Input - 19 - irq - - - false - arria10_hps_mpu_reg_l2_MPUL2 - interrupt_sender - arria10_hps_mpu_reg_l2_MPUL2.interrupt_sender - 18 - - - - - - embeddedsw.dts.irq.rx_offset - 19 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_siq_19 - Input - 32 - irq - - - false - button_pio - irq - button_pio.irq - 0 - - - false - dipsw_pio - irq - dipsw_pio.irq - 1 - - - - - - embeddedsw.dts.irq.rx_offset - 51 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_siq_10 - Input - 32 - irq - - - - - - embeddedsw.dts.irq.rx_offset - 83 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_siq_83 - Input - 32 - irq - - - false - arria10_hps_i_dma_DMASECURE - interrupt_sender - arria10_hps_i_dma_DMASECURE.interrupt_sender - 0 - - - false - arria10_hps_i_gpio_0_gpio - interrupt_sender - arria10_hps_i_gpio_0_gpio.interrupt_sender - 29 - - - false - arria10_hps_i_gpio_1_gpio - interrupt_sender - arria10_hps_i_gpio_1_gpio.interrupt_sender - 30 - - - false - arria10_hps_i_gpio_2_gpio - interrupt_sender - arria10_hps_i_gpio_2_gpio.interrupt_sender - 31 - - - false - arria10_hps_i_uart_0_uart - interrupt_sender - arria10_hps_i_uart_0_uart.interrupt_sender - 27 - - - false - arria10_hps_i_uart_1_uart - interrupt_sender - arria10_hps_i_uart_1_uart.interrupt_sender - 28 - - - false - arria10_hps_i_emac_emac0 - interrupt_sender - arria10_hps_i_emac_emac0.interrupt_sender - 9 - - - false - arria10_hps_i_emac_emac1 - interrupt_sender - arria10_hps_i_emac_emac1.interrupt_sender - 10 - - - false - arria10_hps_i_emac_emac2 - interrupt_sender - arria10_hps_i_emac_emac2.interrupt_sender - 11 - - - false - arria10_hps_i_spim_0_spim - interrupt_sender - arria10_hps_i_spim_0_spim.interrupt_sender - 20 - - - false - arria10_hps_i_spim_1_spim - interrupt_sender - arria10_hps_i_spim_1_spim.interrupt_sender - 21 - - - false - arria10_hps_i_spis_0_spis - interrupt_sender - arria10_hps_i_spis_0_spis.interrupt_sender - 18 - - - false - arria10_hps_i_spis_1_spis - interrupt_sender - arria10_hps_i_spis_1_spis.interrupt_sender - 19 - - - false - arria10_hps_i_i2c_0_i2c - interrupt_sender - arria10_hps_i_i2c_0_i2c.interrupt_sender - 22 - - - false - arria10_hps_i_i2c_1_i2c - interrupt_sender - arria10_hps_i_i2c_1_i2c.interrupt_sender - 23 - - - false - arria10_hps_i_i2c_emac_0_i2c - interrupt_sender - arria10_hps_i_i2c_emac_0_i2c.interrupt_sender - 24 - - - false - arria10_hps_i_i2c_emac_1_i2c - interrupt_sender - arria10_hps_i_i2c_emac_1_i2c.interrupt_sender - 25 - - - false - arria10_hps_i_i2c_emac_2_i2c - interrupt_sender - arria10_hps_i_i2c_emac_2_i2c.interrupt_sender - 26 - - - false - arria10_hps_i_qspi_QSPIDATA - interrupt_sender - arria10_hps_i_qspi_QSPIDATA.interrupt_sender - 17 - - - false - arria10_hps_i_sdmmc_sdmmc - interrupt_sender - arria10_hps_i_sdmmc_sdmmc.interrupt_sender - 15 - - - false - arria10_hps_i_nand_NANDDATA - interrupt_sender - arria10_hps_i_nand_NANDDATA.interrupt_sender - 16 - - - false - arria10_hps_i_usbotg_0_globgrp - interrupt_sender - arria10_hps_i_usbotg_0_globgrp.interrupt_sender - 12 - - - false - arria10_hps_i_usbotg_1_globgrp - interrupt_sender - arria10_hps_i_usbotg_1_globgrp.interrupt_sender - 13 - - - - - - embeddedsw.dts.irq.rx_offset - 115 - - - embeddedsw.dts.irq.rx_type - arm_gic_spi - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_siq_115 - Input - 12 - irq - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - interrupt_sender - arria10_hps_i_fpga_mgr_fpgamgrregs.interrupt_sender - 8 - - - false - arria10_hps_i_timer_sp_0_timer - interrupt_sender - arria10_hps_i_timer_sp_0_timer.interrupt_sender - 0 - - - false - arria10_hps_i_timer_sp_1_timer - interrupt_sender - arria10_hps_i_timer_sp_1_timer.interrupt_sender - 1 - - - false - arria10_hps_i_timer_sys_0_timer - interrupt_sender - arria10_hps_i_timer_sys_0_timer.interrupt_sender - 2 - - - false - arria10_hps_i_timer_sys_1_timer - interrupt_sender - arria10_hps_i_timer_sys_1_timer.interrupt_sender - 3 - - - false - arria10_hps_i_watchdog_0_l4wd - interrupt_sender - arria10_hps_i_watchdog_0_l4wd.interrupt_sender - 4 - - - false - arria10_hps_i_watchdog_1_l4wd - interrupt_sender - arria10_hps_i_watchdog_1_l4wd.interrupt_sender - 5 - - - - - - addressSpan - 4096 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_slave0_signal_40 - Input - 1 - awvalid - - - axi_slave0_signal_41 - Output - 1 - awready - - - axi_slave0_signal_42 - Input - 12 - awid - - - axi_slave0_signal_43 - Input - 12 - awaddr - - - axi_slave0_signal_44 - Input - 4 - awlen - - - axi_slave0_signal_45 - Input - 3 - awsize - - - axi_slave0_signal_46 - Input - 2 - awburst - - - axi_slave0_signal_47 - Input - 2 - awlock - - - axi_slave0_signal_48 - Input - 4 - awcache - - - axi_slave0_signal_49 - Input - 3 - awprot - - - axi_slave0_signal_50 - Input - 1 - awuser - - - axi_slave0_signal_51 - Input - 1 - arvalid - - - axi_slave0_signal_52 - Output - 1 - arready - - - axi_slave0_signal_53 - Input - 12 - arid - - - axi_slave0_signal_54 - Input - 12 - araddr - - - axi_slave0_signal_55 - Input - 4 - arlen - - - axi_slave0_signal_56 - Input - 3 - arsize - - - axi_slave0_signal_57 - Input - 2 - arburst - - - axi_slave0_signal_58 - Input - 2 - arlock - - - axi_slave0_signal_59 - Input - 4 - arcache - - - axi_slave0_signal_60 - Input - 3 - arprot - - - axi_slave0_signal_61 - Input - 1 - aruser - - - axi_slave0_signal_62 - Input - 1 - wvalid - - - axi_slave0_signal_63 - Output - 1 - wready - - - axi_slave0_signal_64 - Input - 12 - wid - - - axi_slave0_signal_65 - Input - 1 - wlast - - - axi_slave0_signal_66 - Input - 32 - wdata - - - axi_slave0_signal_67 - Input - 4 - wstrb - - - axi_slave0_signal_68 - Output - 1 - rvalid - - - axi_slave0_signal_69 - Input - 1 - rready - - - axi_slave0_signal_70 - Output - 12 - rid - - - axi_slave0_signal_71 - Output - 1 - rlast - - - axi_slave0_signal_72 - Output - 2 - rresp - - - axi_slave0_signal_73 - Output - 32 - rdata - - - axi_slave0_signal_74 - Output - 1 - bvalid - - - axi_slave0_signal_75 - Input - 1 - bready - - - axi_slave0_signal_76 - Output - 12 - bid - - - axi_slave0_signal_77 - Output - 2 - bresp - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_slave1_signal_40 - Input - 1 - awvalid - - - axi_slave1_signal_41 - Output - 1 - awready - - - axi_slave1_signal_42 - Input - 12 - awid - - - axi_slave1_signal_43 - Input - 8 - awaddr - - - axi_slave1_signal_44 - Input - 4 - awlen - - - axi_slave1_signal_45 - Input - 3 - awsize - - - axi_slave1_signal_46 - Input - 2 - awburst - - - axi_slave1_signal_47 - Input - 2 - awlock - - - axi_slave1_signal_48 - Input - 4 - awcache - - - axi_slave1_signal_49 - Input - 3 - awprot - - - axi_slave1_signal_50 - Input - 1 - awuser - - - axi_slave1_signal_51 - Input - 1 - arvalid - - - axi_slave1_signal_52 - Output - 1 - arready - - - axi_slave1_signal_53 - Input - 12 - arid - - - axi_slave1_signal_54 - Input - 8 - araddr - - - axi_slave1_signal_55 - Input - 4 - arlen - - - axi_slave1_signal_56 - Input - 3 - arsize - - - axi_slave1_signal_57 - Input - 2 - arburst - - - axi_slave1_signal_58 - Input - 2 - arlock - - - axi_slave1_signal_59 - Input - 4 - arcache - - - axi_slave1_signal_60 - Input - 3 - arprot - - - axi_slave1_signal_61 - Input - 1 - aruser - - - axi_slave1_signal_62 - Input - 1 - wvalid - - - axi_slave1_signal_63 - Output - 1 - wready - - - axi_slave1_signal_64 - Input - 12 - wid - - - axi_slave1_signal_65 - Input - 1 - wlast - - - axi_slave1_signal_66 - Input - 32 - wdata - - - axi_slave1_signal_67 - Input - 4 - wstrb - - - axi_slave1_signal_68 - Output - 1 - rvalid - - - axi_slave1_signal_69 - Input - 1 - rready - - - axi_slave1_signal_70 - Output - 12 - rid - - - axi_slave1_signal_71 - Output - 1 - rlast - - - axi_slave1_signal_72 - Output - 2 - rresp - - - axi_slave1_signal_73 - Output - 32 - rdata - - - axi_slave1_signal_74 - Output - 1 - bvalid - - - axi_slave1_signal_75 - Input - 1 - bready - - - axi_slave1_signal_76 - Output - 12 - bid - - - axi_slave1_signal_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,clk-mgr - - - embeddedsw.dts.group - clkmgr - - - embeddedsw.dts.name - clk-mgr - - - embeddedsw.dts.vendor - altr - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - eosc1_clk - Input - 1 - clk - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - cb_intosc_hs_div2_clk_clk - Input - 1 - clk - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - cb_intosc_ls_clk_clk - Input - 1 - clk - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - f2s_free_clk_clk - Input - 1 - clk - - - - - - java.lang.String - eosc1 - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - l4_sys_free_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_timer_sys_0_timer - clock_sink - arria10_hps_i_timer_sys_0_timer.clock_sink - - - false - arria10_hps_i_timer_sys_1_timer - clock_sink - arria10_hps_i_timer_sys_1_timer.clock_sink - - - false - arria10_hps_i_watchdog_0_l4wd - clock_sink - arria10_hps_i_watchdog_0_l4wd.clock_sink - - - false - arria10_hps_i_watchdog_1_l4wd - clock_sink - arria10_hps_i_watchdog_1_l4wd.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - mpu_free_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - l3_main_free_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - cs_at_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - cs_pdbg_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - cs_trace_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - cs_timer_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - emac0_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_emac_emac0 - clock_sink - arria10_hps_i_emac_emac0.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - emac1_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_emac_emac1 - clock_sink - arria10_hps_i_emac_emac1.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - emac2_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_emac_emac2 - clock_sink - arria10_hps_i_emac_emac2.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - usb_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_usbotg_0_globgrp - clock_sink - arria10_hps_i_usbotg_0_globgrp.clock_sink - - - false - arria10_hps_i_usbotg_1_globgrp - clock_sink - arria10_hps_i_usbotg_1_globgrp.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - emac_ptp_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - gpio_db_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - l4_sp_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_timer_sp_0_timer - clock_sink - arria10_hps_i_timer_sp_0_timer.clock_sink - - - false - arria10_hps_i_timer_sp_1_timer - clock_sink - arria10_hps_i_timer_sp_1_timer.clock_sink - - - false - arria10_hps_i_uart_0_uart - clock_sink - arria10_hps_i_uart_0_uart.clock_sink - - - false - arria10_hps_i_uart_1_uart - clock_sink - arria10_hps_i_uart_1_uart.clock_sink - - - false - arria10_hps_i_i2c_0_i2c - clock_sink - arria10_hps_i_i2c_0_i2c.clock_sink - - - false - arria10_hps_i_i2c_1_i2c - clock_sink - arria10_hps_i_i2c_1_i2c.clock_sink - - - false - arria10_hps_i_i2c_emac_0_i2c - clock_sink - arria10_hps_i_i2c_emac_0_i2c.clock_sink - - - false - arria10_hps_i_i2c_emac_1_i2c - clock_sink - arria10_hps_i_i2c_emac_1_i2c.clock_sink - - - false - arria10_hps_i_i2c_emac_2_i2c - clock_sink - arria10_hps_i_i2c_emac_2_i2c.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - l4_mp_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_gpio_0_gpio - clock_sink - arria10_hps_i_gpio_0_gpio.clock_sink - - - false - arria10_hps_i_gpio_1_gpio - clock_sink - arria10_hps_i_gpio_1_gpio.clock_sink - - - false - arria10_hps_i_gpio_2_gpio - clock_sink - arria10_hps_i_gpio_2_gpio.clock_sink - - - false - arria10_hps_i_spis_0_spis - clock_sink - arria10_hps_i_spis_0_spis.clock_sink - - - false - arria10_hps_i_spis_1_spis - clock_sink - arria10_hps_i_spis_1_spis.clock_sink - - - false - arria10_hps_i_qspi_QSPIDATA - clock_sink - arria10_hps_i_qspi_QSPIDATA.clock_sink - - - false - arria10_hps_i_sdmmc_sdmmc - biu - arria10_hps_i_sdmmc_sdmmc.biu - - - false - arria10_hps_i_nand_NANDDATA - clock_sink - arria10_hps_i_nand_NANDDATA.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - l4_main_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_dma_DMASECURE - apb_pclk - arria10_hps_i_dma_DMASECURE.apb_pclk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - mpu_periph_clk_clk - Output - 1 - clk - - - false - arria10_hps_timer - clock_sink - arria10_hps_timer.clock_sink - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - sdmmc_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_sdmmc_sdmmc - ciu - arria10_hps_i_sdmmc_sdmmc.ciu - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - qspi_sclk_out_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - s2f_free_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - s2f_user_clk0_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - s2f_user_clk1_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - s2f_user0_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - s2f_user1_clk_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - spim0_sclk_out_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - spim1_sclk_out_clk - Output - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - spi_m_clk_clk - Output - 1 - clk - - - false - arria10_hps_i_spim_0_spim - clock_sink - arria10_hps_i_spim_0_spim.clock_sink - - - false - arria10_hps_i_spim_1_spim - clock_sink - arria10_hps_i_spim_1_spim.clock_sink - - - - - - addressSpan - 4096 - - - java.lang.String - eosc1 - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 12 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 12 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - arm,pl310-cache - - - embeddedsw.dts.group - L2-cache - - - embeddedsw.dts.name - pl310-cache - - - embeddedsw.dts.params.cache-level - 2 - - - embeddedsw.dts.vendor - arm - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 4096 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 12 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 12 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - arm,pl330 arm,primecell - - - embeddedsw.dts.group - dma - - - embeddedsw.dts.name - pl330 - - - embeddedsw.dts.params.#dma-cells - 1 - - - embeddedsw.dts.params.#dma-channels - 8 - - - embeddedsw.dts.params.#dma-requests - 32 - - - embeddedsw.dts.params.clock-names - apb_pclk - - - embeddedsw.dts.params.copy-align - 3 - - - embeddedsw.dts.params.nr-irqs - 9 - - - embeddedsw.dts.params.nr-valid-peri - 9 - - - embeddedsw.dts.vendor - arm - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - apb_pclk_clk - Input - 1 - clk - - - - - - java.lang.String - apb_pclk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 4096 - - - java.lang.String - apb_pclk - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 12 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 12 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,sys-mgr syscon - - - embeddedsw.dts.group - sysmgr - - - embeddedsw.dts.name - sys-mgr - - - embeddedsw.dts.params.cpu1-start-addr - 4291846704 - - - embeddedsw.dts.vendor - altr - - - long - 4291846704 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - addressSpan - 1024 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 1024 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 10 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 10 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,rst-mgr syscon - - - embeddedsw.dts.group - rstmgr - - - embeddedsw.dts.name - rst-mgr - - - embeddedsw.dts.params.#reset-cells - 1 - - - embeddedsw.dts.params.altr,modrst-offset - 32 - - - embeddedsw.dts.vendor - altr - - - int - 32 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,socfpga-a10-fpga-mgr - - - embeddedsw.dts.group - fpgamgr - - - embeddedsw.dts.name - fpga-mgr - - - embeddedsw.dts.params.transport - mmio - - - embeddedsw.dts.vendor - altr - - - java.lang.String - altr,socfpga-a10-fpga-mgr - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 4096 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 12 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 12 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig1_40 - Input - 1 - awvalid - - - axi_sig1_41 - Output - 1 - awready - - - axi_sig1_42 - Input - 12 - awid - - - axi_sig1_43 - Input - 8 - awaddr - - - axi_sig1_44 - Input - 4 - awlen - - - axi_sig1_45 - Input - 3 - awsize - - - axi_sig1_46 - Input - 2 - awburst - - - axi_sig1_47 - Input - 2 - awlock - - - axi_sig1_48 - Input - 4 - awcache - - - axi_sig1_49 - Input - 3 - awprot - - - axi_sig1_50 - Input - 1 - awuser - - - axi_sig1_51 - Input - 1 - arvalid - - - axi_sig1_52 - Output - 1 - arready - - - axi_sig1_53 - Input - 12 - arid - - - axi_sig1_54 - Input - 8 - araddr - - - axi_sig1_55 - Input - 4 - arlen - - - axi_sig1_56 - Input - 3 - arsize - - - axi_sig1_57 - Input - 2 - arburst - - - axi_sig1_58 - Input - 2 - arlock - - - axi_sig1_59 - Input - 4 - arcache - - - axi_sig1_60 - Input - 3 - arprot - - - axi_sig1_61 - Input - 1 - aruser - - - axi_sig1_62 - Input - 1 - wvalid - - - axi_sig1_63 - Output - 1 - wready - - - axi_sig1_64 - Input - 12 - wid - - - axi_sig1_65 - Input - 1 - wlast - - - axi_sig1_66 - Input - 32 - wdata - - - axi_sig1_67 - Input - 4 - wstrb - - - axi_sig1_68 - Output - 1 - rvalid - - - axi_sig1_69 - Input - 1 - rready - - - axi_sig1_70 - Output - 12 - rid - - - axi_sig1_71 - Output - 1 - rlast - - - axi_sig1_72 - Output - 2 - rresp - - - axi_sig1_73 - Output - 32 - rdata - - - axi_sig1_74 - Output - 1 - bvalid - - - axi_sig1_75 - Input - 1 - bready - - - axi_sig1_76 - Output - 12 - bid - - - axi_sig1_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - arm,cortex-a9-twd-timer - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - cortex-a9-twd-timer - - - embeddedsw.dts.vendor - arm - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - embeddedsw.dts.irq.tx_mask - 0xf00 - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-apb-timer-sp - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-apb-timer-sp - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-apb-timer-sp - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-apb-timer-sp - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-apb-timer-osc - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-apb-timer-osc - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-apb-timer-osc - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-apb-timer-osc - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-wdt - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-wdt - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-wdt - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - dw-wdt - - - embeddedsw.dts.params.clock-names - timer - - - embeddedsw.dts.vendor - snps - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-gpio - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - dw-gpio - - - embeddedsw.dts.vendor - snps - - - int - 1 - false - true - true - true - - - int - 24 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-gpio - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - dw-gpio - - - embeddedsw.dts.vendor - snps - - - int - 1 - false - true - true - true - - - int - 24 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-gpio - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - dw-gpio - - - embeddedsw.dts.vendor - snps - - - int - 1 - false - true - true - true - - - int - 14 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.CMacro.FIFO_DEPTH - 128 - - - embeddedsw.CMacro.FIFO_HWFC - 0 - - - embeddedsw.CMacro.FIFO_MODE - 1 - - - embeddedsw.CMacro.FIFO_SWFC - 0 - - - embeddedsw.CMacro.FREQ - 0 - - - embeddedsw.dts.compatible - snps,dw-apb-uart - - - embeddedsw.dts.group - serial - - - embeddedsw.dts.name - dw-apb-uart - - - embeddedsw.dts.params.reg-io-width - 4 - - - embeddedsw.dts.params.reg-shift - 2 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - double - 0.0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - embeddedsw.configuration.isPrintableDevice - 1 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.CMacro.FIFO_DEPTH - 128 - - - embeddedsw.CMacro.FIFO_HWFC - 0 - - - embeddedsw.CMacro.FIFO_MODE - 1 - - - embeddedsw.CMacro.FIFO_SWFC - 0 - - - embeddedsw.CMacro.FREQ - 0 - - - embeddedsw.dts.compatible - snps,dw-apb-uart - - - embeddedsw.dts.group - serial - - - embeddedsw.dts.name - dw-apb-uart - - - embeddedsw.dts.params.reg-io-width - 4 - - - embeddedsw.dts.params.reg-shift - 2 - - - embeddedsw.dts.params.status - okay - - - embeddedsw.dts.vendor - snps - - - boolean - true - false - true - true - true - - - double - 0.0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - embeddedsw.configuration.isPrintableDevice - 1 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - - - embeddedsw.dts.group - ethernet - - - embeddedsw.dts.name - dwmac - - - embeddedsw.dts.params.clock-names - stmmaceth - - - embeddedsw.dts.params.interrupt-names - macirq - - - embeddedsw.dts.params.rx-fifo-depth - 16384 - - - embeddedsw.dts.params.snps,multicast-filter-bins - 256 - - - embeddedsw.dts.params.snps,perfect-filter-entries - 128 - - - embeddedsw.dts.params.status - okay - - - embeddedsw.dts.params.tx-fifo-depth - 4096 - - - embeddedsw.dts.vendor - synopsys - - - boolean - true - false - true - true - true - - - java.lang.String - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - false - true - true - true - - - int - 16384 - false - true - true - true - - - int - 4096 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 8192 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 8192 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 13 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 13 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - - - embeddedsw.dts.group - ethernet - - - embeddedsw.dts.name - dwmac - - - embeddedsw.dts.params.clock-names - stmmaceth - - - embeddedsw.dts.params.interrupt-names - macirq - - - embeddedsw.dts.params.rx-fifo-depth - 16384 - - - embeddedsw.dts.params.snps,multicast-filter-bins - 256 - - - embeddedsw.dts.params.snps,perfect-filter-entries - 128 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.params.tx-fifo-depth - 4096 - - - embeddedsw.dts.vendor - synopsys - - - boolean - false - false - true - true - true - - - java.lang.String - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - false - true - true - true - - - int - 16384 - false - true - true - true - - - int - 4096 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 8192 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 8192 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 13 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 13 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - - - embeddedsw.dts.group - ethernet - - - embeddedsw.dts.name - dwmac - - - embeddedsw.dts.params.clock-names - stmmaceth - - - embeddedsw.dts.params.interrupt-names - macirq - - - embeddedsw.dts.params.rx-fifo-depth - 16384 - - - embeddedsw.dts.params.snps,multicast-filter-bins - 256 - - - embeddedsw.dts.params.snps,perfect-filter-entries - 128 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.params.tx-fifo-depth - 4096 - - - embeddedsw.dts.vendor - synopsys - - - boolean - false - false - true - true - true - - - java.lang.String - altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac - false - true - true - true - - - int - 16384 - false - true - true - true - - - int - 4096 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 8192 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 8192 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 13 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 13 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-spi-mmio snps,dw-apb-ssi - - - embeddedsw.dts.group - spi - - - embeddedsw.dts.name - dw-spi-mmio - - - embeddedsw.dts.params.#address-cells - 1 - - - embeddedsw.dts.params.#size-cells - 0 - - - embeddedsw.dts.params.bus-num - 0 - - - embeddedsw.dts.params.num-chipselect - 4 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-spi-mmio snps,dw-apb-ssi - - - embeddedsw.dts.group - spi - - - embeddedsw.dts.name - dw-spi-mmio - - - embeddedsw.dts.params.#address-cells - 1 - - - embeddedsw.dts.params.#size-cells - 0 - - - embeddedsw.dts.params.bus-num - 0 - - - embeddedsw.dts.params.num-chipselect - 4 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-spi-mmio snps,dw-apb-ssi - - - embeddedsw.dts.group - spi - - - embeddedsw.dts.name - dw-spi-mmio - - - embeddedsw.dts.params.#address-cells - 1 - - - embeddedsw.dts.params.#size-cells - 0 - - - embeddedsw.dts.params.bus-num - 0 - - - embeddedsw.dts.params.num-chipselect - 4 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dw-spi-mmio snps,dw-apb-ssi - - - embeddedsw.dts.group - spi - - - embeddedsw.dts.name - dw-spi-mmio - - - embeddedsw.dts.params.#address-cells - 1 - - - embeddedsw.dts.params.#size-cells - 0 - - - embeddedsw.dts.params.bus-num - 0 - - - embeddedsw.dts.params.num-chipselect - 4 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,designware-i2c - - - embeddedsw.dts.group - i2c - - - embeddedsw.dts.name - designware-i2c - - - embeddedsw.dts.params.emptyfifo_hold_master - 1 - - - embeddedsw.dts.params.status - okay - - - embeddedsw.dts.vendor - snps - - - boolean - true - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,designware-i2c - - - embeddedsw.dts.group - i2c - - - embeddedsw.dts.name - designware-i2c - - - embeddedsw.dts.params.emptyfifo_hold_master - 1 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,designware-i2c - - - embeddedsw.dts.group - i2c - - - embeddedsw.dts.name - designware-i2c - - - embeddedsw.dts.params.emptyfifo_hold_master - 1 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,designware-i2c - - - embeddedsw.dts.group - i2c - - - embeddedsw.dts.name - designware-i2c - - - embeddedsw.dts.params.emptyfifo_hold_master - 1 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,designware-i2c - - - embeddedsw.dts.group - i2c - - - embeddedsw.dts.name - designware-i2c - - - embeddedsw.dts.params.emptyfifo_hold_master - 1 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - cadence,qspi cdns,qspi-nor - - - embeddedsw.dts.group - flash - - - embeddedsw.dts.name - qspi - - - embeddedsw.dts.params.bus-num - 2 - - - embeddedsw.dts.params.fifo-depth - 128 - - - embeddedsw.dts.params.num-chipselect - 4 - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - cadence - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig1_40 - Input - 1 - awvalid - - - axi_sig1_41 - Output - 1 - awready - - - axi_sig1_42 - Input - 12 - awid - - - axi_sig1_43 - Input - 8 - awaddr - - - axi_sig1_44 - Input - 4 - awlen - - - axi_sig1_45 - Input - 3 - awsize - - - axi_sig1_46 - Input - 2 - awburst - - - axi_sig1_47 - Input - 2 - awlock - - - axi_sig1_48 - Input - 4 - awcache - - - axi_sig1_49 - Input - 3 - awprot - - - axi_sig1_50 - Input - 1 - awuser - - - axi_sig1_51 - Input - 1 - arvalid - - - axi_sig1_52 - Output - 1 - arready - - - axi_sig1_53 - Input - 12 - arid - - - axi_sig1_54 - Input - 8 - araddr - - - axi_sig1_55 - Input - 4 - arlen - - - axi_sig1_56 - Input - 3 - arsize - - - axi_sig1_57 - Input - 2 - arburst - - - axi_sig1_58 - Input - 2 - arlock - - - axi_sig1_59 - Input - 4 - arcache - - - axi_sig1_60 - Input - 3 - arprot - - - axi_sig1_61 - Input - 1 - aruser - - - axi_sig1_62 - Input - 1 - wvalid - - - axi_sig1_63 - Output - 1 - wready - - - axi_sig1_64 - Input - 12 - wid - - - axi_sig1_65 - Input - 1 - wlast - - - axi_sig1_66 - Input - 32 - wdata - - - axi_sig1_67 - Input - 4 - wstrb - - - axi_sig1_68 - Output - 1 - rvalid - - - axi_sig1_69 - Input - 1 - rready - - - axi_sig1_70 - Output - 12 - rid - - - axi_sig1_71 - Output - 1 - rlast - - - axi_sig1_72 - Output - 2 - rresp - - - axi_sig1_73 - Output - 32 - rdata - - - axi_sig1_74 - Output - 1 - bvalid - - - axi_sig1_75 - Input - 1 - bready - - - axi_sig1_76 - Output - 12 - bid - - - axi_sig1_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - altr,socfpga-dw-mshc - - - embeddedsw.dts.group - flash - - - embeddedsw.dts.name - mmc - - - embeddedsw.dts.params.fifo-depth - 1024 - - - embeddedsw.dts.params.num-slots - 1 - - - embeddedsw.dts.params.status - okay - - - embeddedsw.dts.vendor - snps - - - boolean - true - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - biu_clk - Input - 1 - clk - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - ciu_clk - Input - 1 - clk - - - - - - java.lang.String - biu - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 4096 - - - java.lang.String - biu - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 4096 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 12 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 12 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - denali,denali-nand-dt - - - embeddedsw.dts.group - flash - - - embeddedsw.dts.name - nand - - - embeddedsw.dts.params.#address-cells - 1 - - - embeddedsw.dts.params.#size-cells - 1 - - - embeddedsw.dts.params.reg-names - "nand_data", "denali_reg" - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.vendor - denali - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 65536 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 65536 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 16 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 16 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - addressSpan - 65536 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 65536 - true - true - false - true - - axi - false - - axi_sig1_40 - Input - 1 - awvalid - - - axi_sig1_41 - Output - 1 - awready - - - axi_sig1_42 - Input - 12 - awid - - - axi_sig1_43 - Input - 16 - awaddr - - - axi_sig1_44 - Input - 4 - awlen - - - axi_sig1_45 - Input - 3 - awsize - - - axi_sig1_46 - Input - 2 - awburst - - - axi_sig1_47 - Input - 2 - awlock - - - axi_sig1_48 - Input - 4 - awcache - - - axi_sig1_49 - Input - 3 - awprot - - - axi_sig1_50 - Input - 1 - awuser - - - axi_sig1_51 - Input - 1 - arvalid - - - axi_sig1_52 - Output - 1 - arready - - - axi_sig1_53 - Input - 12 - arid - - - axi_sig1_54 - Input - 16 - araddr - - - axi_sig1_55 - Input - 4 - arlen - - - axi_sig1_56 - Input - 3 - arsize - - - axi_sig1_57 - Input - 2 - arburst - - - axi_sig1_58 - Input - 2 - arlock - - - axi_sig1_59 - Input - 4 - arcache - - - axi_sig1_60 - Input - 3 - arprot - - - axi_sig1_61 - Input - 1 - aruser - - - axi_sig1_62 - Input - 1 - wvalid - - - axi_sig1_63 - Output - 1 - wready - - - axi_sig1_64 - Input - 12 - wid - - - axi_sig1_65 - Input - 1 - wlast - - - axi_sig1_66 - Input - 32 - wdata - - - axi_sig1_67 - Input - 4 - wstrb - - - axi_sig1_68 - Output - 1 - rvalid - - - axi_sig1_69 - Input - 1 - rready - - - axi_sig1_70 - Output - 12 - rid - - - axi_sig1_71 - Output - 1 - rlast - - - axi_sig1_72 - Output - 2 - rresp - - - axi_sig1_73 - Output - 32 - rdata - - - axi_sig1_74 - Output - 1 - bvalid - - - axi_sig1_75 - Input - 1 - bready - - - axi_sig1_76 - Output - 12 - bid - - - axi_sig1_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dwc-otg snps,dwc2 - - - embeddedsw.dts.group - usb - - - embeddedsw.dts.name - dwc-otg - - - embeddedsw.dts.params.clock-names - otg - - - embeddedsw.dts.params.dev-nperio-tx-fifo-size - 4096 - - - embeddedsw.dts.params.dev-perio-tx-fifo-size - ]]> - - - embeddedsw.dts.params.dev-rx-fifo-size - 512 - - - embeddedsw.dts.params.dev-tx-fifo-size - ]]> - - - embeddedsw.dts.params.dma-mask - 268435455 - - - embeddedsw.dts.params.enable-dynamic-fifo - 1 - - - embeddedsw.dts.params.host-nperio-tx-fifo-size - 0xa00 - - - embeddedsw.dts.params.host-perio-tx-fifo-size - 0xa00 - - - embeddedsw.dts.params.host-rx-fifo-size - 0xa00 - - - embeddedsw.dts.params.phy-names - usb2-phy - - - embeddedsw.dts.params.status - okay - - - embeddedsw.dts.params.ulpi-ddr - 0 - - - embeddedsw.dts.params.voltage-switch - 0 - - - embeddedsw.dts.vendor - snps - - - boolean - true - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 262144 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 262144 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 18 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 18 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - snps,dwc-otg snps,dwc2 - - - embeddedsw.dts.group - usb - - - embeddedsw.dts.name - dwc-otg - - - embeddedsw.dts.params.clock-names - otg - - - embeddedsw.dts.params.dev-nperio-tx-fifo-size - 4096 - - - embeddedsw.dts.params.dev-perio-tx-fifo-size - ]]> - - - embeddedsw.dts.params.dev-rx-fifo-size - 512 - - - embeddedsw.dts.params.dev-tx-fifo-size - ]]> - - - embeddedsw.dts.params.dma-mask - 268435455 - - - embeddedsw.dts.params.enable-dynamic-fifo - 1 - - - embeddedsw.dts.params.host-nperio-tx-fifo-size - 0xa00 - - - embeddedsw.dts.params.host-perio-tx-fifo-size - 0xa00 - - - embeddedsw.dts.params.host-rx-fifo-size - 0xa00 - - - embeddedsw.dts.params.phy-names - usb2-phy - - - embeddedsw.dts.params.status - disabled - - - embeddedsw.dts.params.ulpi-ddr - 0 - - - embeddedsw.dts.params.voltage-switch - 0 - - - embeddedsw.dts.vendor - snps - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - interrupt_sender - Output - 1 - irq - - - - - - addressSpan - 262144 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 262144 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 18 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 18 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.dts.compatible - arm,cortex-a9-scu - - - embeddedsw.dts.group - scu - - - embeddedsw.dts.name - corex-a9-scu - - - embeddedsw.dts.vendor - arm - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_sink_clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_sink_rst - Input - 1 - reset - - - - - - addressSpan - 256 - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - false - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - java.lang.Integer - 1 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.math.BigInteger - 256 - true - true - false - true - - axi - false - - axi_sig0_40 - Input - 1 - awvalid - - - axi_sig0_41 - Output - 1 - awready - - - axi_sig0_42 - Input - 12 - awid - - - axi_sig0_43 - Input - 8 - awaddr - - - axi_sig0_44 - Input - 4 - awlen - - - axi_sig0_45 - Input - 3 - awsize - - - axi_sig0_46 - Input - 2 - awburst - - - axi_sig0_47 - Input - 2 - awlock - - - axi_sig0_48 - Input - 4 - awcache - - - axi_sig0_49 - Input - 3 - awprot - - - axi_sig0_50 - Input - 1 - awuser - - - axi_sig0_51 - Input - 1 - arvalid - - - axi_sig0_52 - Output - 1 - arready - - - axi_sig0_53 - Input - 12 - arid - - - axi_sig0_54 - Input - 8 - araddr - - - axi_sig0_55 - Input - 4 - arlen - - - axi_sig0_56 - Input - 3 - arsize - - - axi_sig0_57 - Input - 2 - arburst - - - axi_sig0_58 - Input - 2 - arlock - - - axi_sig0_59 - Input - 4 - arcache - - - axi_sig0_60 - Input - 3 - arprot - - - axi_sig0_61 - Input - 1 - aruser - - - axi_sig0_62 - Input - 1 - wvalid - - - axi_sig0_63 - Output - 1 - wready - - - axi_sig0_64 - Input - 12 - wid - - - axi_sig0_65 - Input - 1 - wlast - - - axi_sig0_66 - Input - 32 - wdata - - - axi_sig0_67 - Input - 4 - wstrb - - - axi_sig0_68 - Output - 1 - rvalid - - - axi_sig0_69 - Input - 1 - rready - - - axi_sig0_70 - Output - 12 - rid - - - axi_sig0_71 - Output - 1 - rlast - - - axi_sig0_72 - Output - 2 - rresp - - - axi_sig0_73 - Output - 32 - rdata - - - axi_sig0_74 - Output - 1 - bvalid - - - axi_sig0_75 - Input - 1 - bready - - - axi_sig0_76 - Output - 12 - bid - - - axi_sig0_77 - Output - 2 - bresp - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 1 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 1 - - - embeddedsw.CMacro.DATA_WIDTH - 2 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - FALLING - - - embeddedsw.CMacro.FREQ - 100000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - EDGE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 2 - - - embeddedsw.dts.params.altr,interrupt-type - 2 - - - embeddedsw.dts.params.altr,interrupt_type - 2 - - - embeddedsw.dts.params.edge_type - 1 - - - embeddedsw.dts.params.level_trigger - 0 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - true - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - FALLING - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - EDGE - false - true - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 2 - false - true - true - true - - - long - 100000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - FALLING - true - true - false - true - - - java.lang.String - EDGE - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 2 - export - - - - - - embeddedsw.dts.irq.tx_type - RISING_EDGE - - - com.altera.entityinterfaces.IConnectionPoint - button_pio.s1 - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - - long - 100000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - long - 0 - false - true - false - true - CLOCK_RATE - clk_in - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - qsys.ui.export_name - clk - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - in_clk - Input - 1 - clk - - - - - - qsys.ui.export_name - reset - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_in - false - true - true - true - - - long - 100000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - clk_out - Output - 1 - clk - - - false - reset_bridge - clk - reset_bridge.clk - - - false - hps_m - clk - hps_m.clk - - - false - f2sdram_m - clk - f2sdram_m.clk - - - false - fpga_m - clk - fpga_m.clk - - - false - pb_lwh2f - clk - pb_lwh2f.clk - - - false - sysid_qsys - clk - sysid_qsys.clk - - - false - led_pio - clk - led_pio.clk - - - false - button_pio - clk - button_pio.clk - - - false - dipsw_pio - clk - dipsw_pio.clk - - - false - ILC - clk - ILC.clk - - - false - onchip_memory2 - clk1 - onchip_memory2.clk1 - - - false - arria10_hps_bridges - f2h_axi_clock - arria10_hps_bridges.f2h_axi_clock - - - false - arria10_hps_bridges - f2sdram0_clock - arria10_hps_bridges.f2sdram0_clock - - - false - arria10_hps_bridges - h2f_axi_clock - arria10_hps_bridges.h2f_axi_clock - - - false - arria10_hps_bridges - h2f_lw_axi_clock - arria10_hps_bridges.h2f_lw_axi_clock - - - false - h2fw_ClockBridge - m0_clk - h2fw_ClockBridge.m0_clk - - - false - issp - source_clk - issp.source_clk - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - clk_in_reset - false - true - true - true - - - [Ljava.lang.String; - clk_in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - reset_n_out - Output - 1 - reset_n - - - - - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - long - 0 - false - true - false - true - CLOCK_RATE - clk_in - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - qsys.ui.export_name - clk - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - in_clk - Input - 1 - clk - - - - - - qsys.ui.export_name - reset - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_in - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - clk_out - Output - 1 - clk - - - false - sevensig - clock50 - sevensig.clock50 - - - false - fancmd - clock50Mhz - fancmd.clock50Mhz - - - false - h2fw_ClockBridge - s0_clk - h2fw_ClockBridge.s0_clk - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - clk_in_reset - false - true - true - true - - - [Ljava.lang.String; - clk_in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - reset_n_out - Output - 1 - reset_n - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 1 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 1 - - - embeddedsw.CMacro.DATA_WIDTH - 2 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - ANY - - - embeddedsw.CMacro.FREQ - 100000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - EDGE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 2 - - - embeddedsw.dts.params.altr,interrupt-type - 3 - - - embeddedsw.dts.params.altr,interrupt_type - 3 - - - embeddedsw.dts.params.edge_type - 2 - - - embeddedsw.dts.params.level_trigger - 0 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - true - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - ANY - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - EDGE - false - true - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 2 - false - true - true - true - - - long - 100000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - ANY - true - true - false - true - - - java.lang.String - EDGE - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 2 - export - - - - - - embeddedsw.dts.irq.tx_type - RISING_EDGE - - - com.altera.entityinterfaces.IConnectionPoint - dipsw_pio.s1 - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - FAMILY_ARRIA10_HPS - true - true - false - true - - - java.lang.String - 0 - false - true - false - true - PART_TRAIT - SUPPORTS_VID - - - java.lang.String - PROTOCOL_DDR4 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 50000000 - false - true - false - true - CLOCK_RATE - cal_debug_clk_clock_sink - - - java.lang.String - a10s_ghrd_emif_a10_hps - false - true - false - true - UNIQUE_ID - - - java.lang.String - PROTOCOL_DDR4 - true - true - false - true - - - java.lang.String - E2 (Production) - change device under 'View'->'Device Family' - true - true - true - true - - - java.lang.String - E2 - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - CONFIG_PHY_AND_HARD_CTRL - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - RATE_HALF - true - true - false - true - - - double - 1066.666 - true - true - false - true - - - double - 266.667 - true - true - false - true - - - double - 10.0 - true - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - int - 240 - true - true - true - true - - - boolean - true - true - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - true - true - false - true - - - java.lang.String - 1066.666 - true - true - false - true - - - java.lang.String - 2 - true - true - false - true - - - java.lang.String - true - true - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - Arria 10 - true - true - false - true - - - java.lang.String - 10AS066K3F40E2SG - true - true - false - true - - - java.lang.String - 2 - true - true - false - true - - - java.lang.String - 266.667 - true - true - false - true - - - java.lang.String - 1066.668 MHz - true - true - false - true - - - java.lang.String - true - true - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - emif - true - true - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 533.333 - true - false - false - true - - - java.lang.String - 533.333 - true - false - false - true - - - java.lang.String - 533.334 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 117.0 - true - false - false - true - - - java.lang.String - 117 - true - false - false - true - - - java.lang.String - 22.5 - true - false - false - true - - - java.lang.String - 117.18735351580811 - true - false - false - true - - - double - 50.0 - true - false - false - true - - - java.lang.String - 50 - true - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 533.333 - true - false - false - true - - - java.lang.String - 533.333 - true - false - false - true - - - java.lang.String - 533.334 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 117.0 - true - false - false - true - - - java.lang.String - 117 - true - false - false - true - - - java.lang.String - 22.5 - true - false - false - true - - - java.lang.String - 117.18735351580811 - true - false - false - true - - - double - 50.0 - true - false - false - true - - - java.lang.String - 50 - true - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 533.333 - true - false - false - true - - - java.lang.String - 533.333 - true - false - false - true - - - java.lang.String - 533.334 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 117.0 - true - false - false - true - - - java.lang.String - 117 - true - false - false - true - - - java.lang.String - 22.5 - true - false - false - true - - - java.lang.String - 117.18735351580811 - true - false - false - true - - - double - 50.0 - true - false - false - true - - - java.lang.String - 50 - true - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 152.38085714285714 - true - false - false - true - - - java.lang.String - 152.38085714285714 - true - false - false - true - - - java.lang.String - 152.38114285714283 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - true - false - false - true - - - java.lang.String - 0 - true - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - true - false - false - true - - - java.lang.String - 50 - true - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 152.38085714285714 - true - false - false - true - - - java.lang.String - 152.38085714285714 - true - false - false - true - - - java.lang.String - 152.38114285714283 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - true - false - false - true - - - java.lang.String - 0 - true - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - true - false - false - true - - - java.lang.String - 50 - true - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - double - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - false - false - false - true - - - java.lang.String - 100.0 - true - false - false - true - - - java.lang.String - 0 - false - false - false - true - - - double - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - false - false - false - true - - - java.lang.String - 0.0 - true - false - false - true - - - double - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - false - false - false - true - - - java.lang.String - 50.0 - true - false - false - true - - - java.lang.String - CONFIG_PHY_AND_HARD_CTRL - false - true - false - true - - - boolean - false - false - true - false - true - - - double - 1066.667 - false - true - false - true - - - boolean - true - false - true - false - true - - - double - -1.0 - false - true - false - true - - - double - 10.0 - false - true - false - true - - - java.lang.String - RATE_HALF - false - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.5 - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - -1.0 - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - boolean - true - false - true - false - true - - - double - 70.0 - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - boolean - true - true - true - false - true - - - double - 70.0 - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - int - 0 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - CONFIG_PHY_AND_HARD_CTRL - false - true - true - true - - - boolean - false - false - true - false - true - - - double - 1066.666 - false - true - true - true - - - boolean - true - false - true - true - true - - - double - 266.667 - false - true - false - true - - - double - 10.0 - false - true - true - true - - - java.lang.String - RATE_HALF - false - true - true - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.2 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - 266.667 - true - true - true - true - - - boolean - false - true - true - false - true - - - java.lang.String - IO_STD_SSTL_12 - false - true - true - true - - - java.lang.String - OUT_OCT_40_CAL - false - true - true - true - - - java.lang.String - SLEW_RATE_FAST - false - true - true - true - - - java.lang.String - IO_STD_SSTL_12 - false - true - true - true - - - java.lang.String - OUT_OCT_40_CAL - false - true - true - true - - - java.lang.String - SLEW_RATE_FAST - false - true - true - true - - - java.lang.String - IO_STD_POD_12 - false - true - true - true - - - java.lang.String - OUT_OCT_48_CAL - false - true - true - true - - - java.lang.String - IN_OCT_60_CAL - false - true - true - true - - - boolean - true - false - true - true - true - - - double - 70.0 - false - true - false - true - - - java.lang.String - IO_STD_LVDS - false - true - true - true - - - java.lang.String - IO_STD_CMOS_12 - false - true - true - true - - - java.lang.String - IO_STD_SSTL_12 - true - true - false - true - - - java.lang.String - OUT_OCT_40_CAL - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - IO_STD_SSTL_12 - true - true - false - true - - - java.lang.String - OUT_OCT_40_CAL - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - IO_STD_POD_12 - true - true - false - true - - - java.lang.String - OUT_OCT_48_CAL - true - true - false - true - - - java.lang.String - IN_OCT_60_CAL - true - true - false - true - - - boolean - true - true - true - false - true - - - double - 68.0 - true - true - true - true - - - java.lang.String - IO_STD_LVDS - true - true - false - true - - - java.lang.String - IO_STD_CMOS_12 - true - true - false - true - - - java.lang.String - CONFIG_PHY_AND_SOFT_CTRL - false - true - false - true - - - boolean - false - false - true - false - true - - - double - 633.333 - false - true - false - true - - - boolean - true - false - true - false - true - - - double - -1.0 - false - true - false - true - - - double - 10.0 - false - true - false - true - - - java.lang.String - RATE_HALF - false - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.5 - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - -1.0 - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - boolean - true - false - true - false - true - - - double - 70.0 - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - boolean - true - true - true - false - true - - - double - 70.0 - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - CONFIG_PHY_AND_SOFT_CTRL - false - true - false - true - - - boolean - false - false - true - false - true - - - double - 1066.667 - false - true - false - true - - - boolean - true - false - true - false - true - - - double - -1.0 - false - true - false - true - - - double - 10.0 - false - true - false - true - - - java.lang.String - RATE_QUARTER - false - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.2 - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - -1.0 - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - boolean - true - false - true - false - true - - - double - 70.0 - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - SLEW_RATE_FAST - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - boolean - true - true - true - false - true - - - double - 70.0 - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - CONFIG_PHY_AND_SOFT_CTRL - false - true - false - true - - - boolean - false - false - true - false - true - - - double - 533.333 - false - true - false - true - - - boolean - true - false - true - false - true - - - double - -1.0 - false - true - false - true - - - double - 10.0 - false - true - false - true - - - java.lang.String - RATE_HALF - false - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.8 - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - -1.0 - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - unset - false - true - false - true - - - java.lang.String - SLEW_RATE_FAST - false - true - false - true - - - java.lang.String - unset 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70.0 - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - unset - true - true - false - true - - - java.lang.String - CONFIG_PHY_ONLY - false - true - false - true - - - boolean - false - false - true - false - true - - - double - 1066.667 - false - true - false - true - - - boolean - true - false - true - false - true - - - double - -1.0 - false - true - false - true - - - double - 10.0 - false - true - false - true - - - java.lang.String - RATE_QUARTER - false - true - false - true - - - java.lang.String - CORE_CLKS_SHARING_DISABLED - false - true - false - true - - - double - 1.2 - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - PERIODIC_OCT_RECAL_AUTO - false - true - false - true - - - double - -1.0 - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - unset - 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false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - 0000000000000000 - false - true - false - true - - - java.lang.String - 000000000000000000 - false - true - false - true - - - java.lang.String - DDR3_ALERT_N_PLACEMENT_AC_LANES - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 8 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 0 - true - true - false - true - - - boolean - false - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 8 - true - true - false - true - - - int - 72 - true - true - false - true - - - int - 1 - true - true - false - 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false - false - false - true - - - [Ljava.lang.String; - on,off - false - true - false - true - - - [Ljava.lang.String; - off,on - false - true - false - true - - - [Ljava.lang.String; - Rank 0,Rank 1,Rank 2,Rank 3 - false - false - false - true - - - [Ljava.lang.String; - off,off,on,on - false - true - false - true - - - [Ljava.lang.String; - on,on,off,off - false - true - false - true - - - [Ljava.lang.String; - Rank 0,Rank 1,Rank 2,Rank 3 - false - false - false - true - - - [Ljava.lang.String; - off,off,on,on - false - true - false - true - - - [Ljava.lang.String; - on,on,off,off - false - true - false - true - - - [Ljava.lang.String; - Rank 0,Rank 1,Rank 2,Rank 3 - false - false - false - true - - - [Ljava.lang.String; - off,off,off,off - false - true - false - true - - - [Ljava.lang.String; - off,off,on,on - false - true - false - true - - - [Ljava.lang.String; - off,off,off,off - false - true - false - true - - - [Ljava.lang.String; - on,on,off,off - false - true - false - true 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true - false - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - DDR3_SPEEDBIN_2133 - false - true - false - true - - - int - 60 - false - true - false - true - - - int - 135 - false - true - false - true - - - int - 95 - false - true - false - true - - - int - 100 - false - true - false - true - - - int - 53 - false - true - false - true - - - int - 135 - false - true - false - true - - - int - 55 - false - true - false - true - - - int - 100 - false - true - false - true - - - int - 75 - false - true - false - true - - - double - 0.38 - false - true - false - true - - - int - 180 - false - true - false - true - - - double - 0.27 - false - true - false - true - - - double - 0.4 - false - true - false - true - - - double - 0.18 - false - true - false - true - - - double - 125.0 - false - true - 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- true - false - true - - - java.lang.String - DDR4_ALERT_N_PLACEMENT_DATA_LANES - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - true - true - - - java.lang.String - DDR4_BL_BL8 - false - true - true - true - - - java.lang.String - DDR4_BT_SEQUENTIAL - false - true - true - true - - - int - 20 - false - true - true - true - - - java.lang.String - DDR4_RTT_NOM_RZQ_4 - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - DDR4_ATCL_DISABLED - false - true - true - true - - - java.lang.String - DDR4_DRV_STR_RZQ_7 - false - true - true - true - - - java.lang.String - DDR4_ASR_MANUAL_NORMAL - false - true - false - true - - - java.lang.String - DDR4_RTT_WR_ODT_DISABLED - false - true - true - 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- true - false - true - - - java.lang.String - DDR4_DB_DRV_STR_RZQ_7 - false - true - false - true - - - int - 101 - false - true - false - true - - - int - 5 - false - true - false - true - - - int - 29 - false - true - false - true - - - int - 29 - false - true - false - true - - - int - 29 - false - true - false - true - - - int - 29 - false - true - false - true - - - int - 37 - false - true - false - true - - - int - 21 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 20 - false - true - false - true - - - int - 39 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 240 - false - true - false - true - - - int - 4 - true - true - true - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - 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true - false - true - - - int - 1 - true - true - false - true - - - int - 1604 - true - true - false - true - - - int - 65793 - true - true - false - true - - - int - 131112 - true - true - false - true - - - int - 197120 - true - true - false - true - - - int - 264192 - true - true - false - true - - - int - 332832 - true - true - false - true - - - int - 395363 - true - true - false - true - - - java.lang.String - - true - true - false - true - - - java.lang.String - - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 13 - true - true - false - true - - - int - 1 - true - true - false - true - - - boolean - true - false - true - true - true - - - [Ljava.lang.String; - Rank 0 - false - false - true - true - - - [Ljava.lang.String; - off - false - true - true - true - - - [Ljava.lang.String; - Rank 0 - false - false - true - true - - - [Ljava.lang.String; - on - false - true - true - true - - - [Ljava.lang.String; - Rank 0,Rank 1 - false - false - true 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boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - SOFT_NIOS_MODE_DISABLED - false - false - true - true - - - int - 100 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 57600 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - boolean - false - false - false - true - true - - - int - 0 - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - true - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - true - true - false - true - - - boolean - false - true - true - false - true - - - int - 1 - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - EFFMON_MODE_DISABLED - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - int - 8 - true - true - false - true - - - int - 8 - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false 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true - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - true - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false - false - true - true - - - boolean - false - false - false - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - java.lang.String - EFFMON_MODE_DISABLED - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - true - false - false - true - true - - - boolean - true - false - false - true - true - - - boolean - true - false - false - true - true - - - int - 8 - false - false - false - true - - - int - 8 - false - false - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - EFFMON_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 8 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - EFFMON_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false 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- - - int - 8 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - EFFMON_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 8 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - SIM_CAL_MODE_SKIP - false - true - false - true - - - java.lang.String - CAL_DEBUG_EXPORT_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - EFFMON_MODE_DISABLED - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 8 - false - true - false - true - - - int - 8 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - true - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - true - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - true - true - - - boolean - true - false - false - true - true - - - boolean - true - false - false - true - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - true - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - false - true - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - AVAIL_EX_DESIGNS_GEN_DESIGN - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - HDL_FORMAT_VERILOG - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - TARGET_DEV_KIT_NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - global_reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - pll_ref_clk - Input - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - oct_rzqin - Input - 1 - oct_rzqin - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - mem_ck - Output - 1 - mem_ck - - - mem_ck_n - Output - 1 - mem_ck_n - - - mem_a - Output - 17 - mem_a - - - mem_act_n - Output - 1 - mem_act_n - - - mem_ba - Output - 2 - mem_ba - - - mem_bg - Output - 1 - mem_bg - - - mem_cke - Output - 1 - mem_cke - - - mem_cs_n - Output - 1 - mem_cs_n - - - mem_odt - Output - 1 - mem_odt - - - mem_reset_n - Output - 1 - mem_reset_n - - - mem_par - Output - 1 - mem_par - - - mem_alert_n - Input - 1 - mem_alert_n - - - mem_dqs - Bidir - 4 - mem_dqs - - - mem_dqs_n - Bidir - 4 - mem_dqs_n - - - mem_dq - Bidir - 32 - mem_dq - - - mem_dbi_n - Bidir - 4 - mem_dbi_n - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - hps_to_emif - Input - 4096 - hps_to_emif - - - emif_to_hps - Output - 4096 - emif_to_hps - - - hps_to_emif_gp - Input - 2 - gp_to_emif - - - emif_to_hps_gp - Output - 1 - emif_to_gp - - - - - - - debug.hostConnection - type jtag id 110:132 - - - int - 0 - false - true - true - true - - - int - 50000 - false - false - true - true - - - int - 0 - false - true - false - true - CLOCK_RATE - clock - - - int - 0 - false - true - true - true - - - int - 2 - false - false - true - true - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - Arria 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk_clk - Input - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - clk_reset_reset - Input - 1 - reset - - - - - - debug.providesServices - master - - - debug.visible - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - clk_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - master_address - Output - 32 - address - - - master_readdata - Input - 32 - readdata - - - master_read - Output - 1 - read - - - master_write - Output - 1 - write - - - master_writedata - Output - 32 - writedata - - - master_waitrequest - Input - 1 - waitrequest - - - master_readdatavalid - Input - 1 - readdatavalid - - - master_byteenable - Output - 4 - byteenable - - - false - arria10_hps_bridges - f2sdram0_data - arria10_hps_bridges.f2sdram0_data - 0 - 4294967296 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - master_reset_reset - Output - 1 - reset - - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk_50Mhz - Input - 1 - clk - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - I2C_SDA_TempFan - Bidir - 1 - export - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - I2C_SCL_TempFan - Output - 1 - writeresponsevalid_n - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - FAN_ALERT_n - Input - 1 - beginbursttransfer - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - Temp_LED - Output - 1 - writeresponsevalid_n - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - Temp_OK - Output - 1 - writeresponsevalid_n - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - Temp_LOW - Output - 1 - writeresponsevalid_n - - - - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - Temp_HI - Output - 1 - writeresponsevalid_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock50Mhz - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - read - Input - 1 - read - - - address - Input - 1 - address - - - readdata - Output - 32 - readdata - - - - - - - debug.hostConnection - type jtag id 110:132 - - - int - 0 - false - true - true - true - - - int - 50000 - false - false - true - true - - - int - 0 - false - true - false - true - CLOCK_RATE - clock - - - int - 0 - false - true - true - true - - - int - 2 - false - false - true - true - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - Arria 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk_clk - Input - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - clk_reset_reset - Input - 1 - reset - - - - - - debug.providesServices - master - - - debug.visible - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - clk_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - master_address - Output - 32 - address - - - master_readdata - Input - 32 - readdata - - - master_read - Output - 1 - read - - - master_write - Output - 1 - write - - - master_writedata - Output - 32 - writedata - - - master_waitrequest - Input - 1 - waitrequest - - - master_readdatavalid - Input - 1 - readdatavalid - - - master_byteenable - Output - 4 - byteenable - - - true - pb_lwh2f - s0 - pb_lwh2f.s0 - 0 - 512 - - - false - ILC - avalon_slave - ILC.avalon_slave - 0 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 304 - 8 - - - false - led_pio - s1 - led_pio.s1 - 288 - 16 - - - false - button_pio - s1 - button_pio.s1 - 272 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 256 - 16 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - master_reset_reset - Output - 1 - reset - - - - - - - int - 32 - false - true - true - true - - - int - 8 - false - true - true - true - - - int - 10 - false - true - true - true - - - int - 4 - false - true - false - true - ADDRESS_WIDTH - m0 - - - int - 0 - false - true - true - true - - - int - 4 - true - true - true - true - - - int - 10 - true - true - false - true - - - java.lang.String - SYMBOLS - false - true - true - true - - - int - 1 - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 4 - false - true - true - true - - - int - 4 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - m0_clk - Input - 1 - clk - - - - - - java.lang.String - m0_clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - m0_reset - Input - 1 - reset - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - s0_clk - Input - 1 - clk - - - - - - java.lang.String - s0_clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - s0_reset - Input - 1 - reset - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 1024 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - s0_clk - false - true - true - true - - - java.lang.String - s0_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - h2fw_ClockBridge.m0 - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 8 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - s0_waitrequest - Output - 1 - waitrequest - - - s0_readdata - Output - 32 - readdata - - - s0_readdatavalid - Output - 1 - readdatavalid - - - s0_burstcount - Input - 1 - burstcount - - - s0_writedata - Input - 32 - writedata - - - s0_address - Input - 10 - address - - - s0_write - Input - 1 - write - - - s0_read - Input - 1 - read - - - s0_byteenable - Input - 4 - byteenable - - - s0_debugaccess - Input - 1 - debugaccess - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - m0_clk - false - true - true - true - - - java.lang.String - m0_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - m0_waitrequest - Input - 1 - waitrequest - - - m0_readdata - Input - 32 - readdata - - - m0_readdatavalid - Input - 1 - readdatavalid - - - m0_burstcount - Output - 1 - burstcount - - - m0_writedata - Output - 32 - writedata - - - m0_address - Output - 10 - address - - - m0_write - Output - 1 - write - - - m0_read - Output - 1 - read - - - m0_byteenable - Output - 4 - byteenable - - - m0_debugaccess - Output - 1 - debugaccess - - - false - sevensig - avalon_slave_0 - sevensig.avalon_slave_0 - 0 - 8 - - - false - fancmd - avalon_slave_0_1 - fancmd.avalon_slave_0_1 - 8 - 8 - - - - - - - debug.hostConnection - type jtag id 110:132 - - - int - 0 - false - true - true - true - - - int - 50000 - false - false - true - true - - - int - 0 - false - true - false - true - CLOCK_RATE - clock - - - int - 0 - false - true - true - true - - - int - 2 - false - false - true - true - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10AS066K3F40E2SG - false - true - false - true - DEVICE - - - java.lang.String - 2 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - Arria 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk_clk - Input - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - clk_reset_reset - Input - 1 - reset - - - - - - debug.providesServices - master - - - debug.visible - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - clk_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - master_address - Output - 32 - address - - - master_readdata - Input - 32 - readdata - - - master_read - Output - 1 - read - - - master_write - Output - 1 - write - - - master_writedata - Output - 32 - writedata - - - master_waitrequest - Input - 1 - waitrequest - - - master_readdatavalid - Input - 1 - readdatavalid - - - master_byteenable - Output - 4 - byteenable - - - true - arria10_hps_bridges - f2h - arria10_hps_bridges.f2h - 0 - 4294967296 - - - false - arria10_hps_baum_clkmgr - axi_slave0 - arria10_hps_baum_clkmgr.axi_slave0 - 4291837952 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave0 - arria10_hps_arm_gic_0.axi_slave0 - 4294955008 - 4096 - - - false - arria10_hps_arm_gic_0 - axi_slave1 - arria10_hps_arm_gic_0.axi_slave1 - 4294951168 - 256 - - - false - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - arria10_hps_mpu_reg_l2_MPUL2.axi_slave0 - 4294963200 - 4096 - - - false - arria10_hps_i_dma_DMASECURE - axi_slave0 - arria10_hps_i_dma_DMASECURE.axi_slave0 - 4292481024 - 4096 - - - false - arria10_hps_i_sys_mgr_core - axi_slave0 - arria10_hps_i_sys_mgr_core.axi_slave0 - 4291846144 - 1024 - - - false - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - arria10_hps_i_rst_mgr_rstmgr.axi_slave0 - 4291842048 - 256 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0 - 4291833856 - 4096 - - - false - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - arria10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1 - 4291814400 - 256 - - - false - arria10_hps_i_uart_0_uart - axi_slave0 - arria10_hps_i_uart_0_uart.axi_slave0 - 4290781184 - 256 - - - false - arria10_hps_i_uart_1_uart - axi_slave0 - arria10_hps_i_uart_1_uart.axi_slave0 - 4290781440 - 256 - - - false - arria10_hps_i_timer_sp_0_timer - axi_slave0 - arria10_hps_i_timer_sp_0_timer.axi_slave0 - 4290782976 - 256 - - - false - arria10_hps_i_timer_sp_1_timer - axi_slave0 - arria10_hps_i_timer_sp_1_timer.axi_slave0 - 4290783232 - 256 - - - false - arria10_hps_i_timer_sys_0_timer - axi_slave0 - arria10_hps_i_timer_sys_0_timer.axi_slave0 - 4291821568 - 256 - - - false - arria10_hps_i_timer_sys_1_timer - axi_slave0 - arria10_hps_i_timer_sys_1_timer.axi_slave0 - 4291821824 - 256 - - - false - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - arria10_hps_i_watchdog_0_l4wd.axi_slave0 - 4291822080 - 256 - - - false - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - arria10_hps_i_watchdog_1_l4wd.axi_slave0 - 4291822336 - 256 - - - false - arria10_hps_i_gpio_0_gpio - axi_slave0 - arria10_hps_i_gpio_0_gpio.axi_slave0 - 4290783488 - 256 - - - false - arria10_hps_i_gpio_1_gpio - axi_slave0 - arria10_hps_i_gpio_1_gpio.axi_slave0 - 4290783744 - 256 - - - false - arria10_hps_i_gpio_2_gpio - axi_slave0 - arria10_hps_i_gpio_2_gpio.axi_slave0 - 4290784000 - 256 - - - false - arria10_hps_i_i2c_0_i2c - axi_slave0 - arria10_hps_i_i2c_0_i2c.axi_slave0 - 4290781696 - 256 - - - false - arria10_hps_i_i2c_1_i2c - axi_slave0 - arria10_hps_i_i2c_1_i2c.axi_slave0 - 4290781952 - 256 - - - false - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - arria10_hps_i_i2c_emac_0_i2c.axi_slave0 - 4290782208 - 256 - - - false - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - arria10_hps_i_i2c_emac_1_i2c.axi_slave0 - 4290782464 - 256 - - - false - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - arria10_hps_i_i2c_emac_2_i2c.axi_slave0 - 4290782720 - 256 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave0 - arria10_hps_i_nand_NANDDATA.axi_slave0 - 4290314240 - 65536 - - - false - arria10_hps_i_nand_NANDDATA - axi_slave1 - arria10_hps_i_nand_NANDDATA.axi_slave1 - 4290248704 - 65536 - - - false - arria10_hps_i_spim_0_spim - axi_slave0 - arria10_hps_i_spim_0_spim.axi_slave0 - 4292493312 - 256 - - - false - arria10_hps_i_spim_1_spim - axi_slave0 - arria10_hps_i_spim_1_spim.axi_slave0 - 4292497408 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - arria10_hps_i_qspi_QSPIDATA.axi_slave0 - 4286615552 - 256 - - - false - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - arria10_hps_i_qspi_QSPIDATA.axi_slave1 - 4288675840 - 256 - - - false - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - arria10_hps_i_sdmmc_sdmmc.axi_slave0 - 4286611456 - 4096 - - - false - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - arria10_hps_i_usbotg_0_globgrp.axi_slave0 - 4289724416 - 262144 - - - false - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - arria10_hps_i_usbotg_1_globgrp.axi_slave0 - 4289986560 - 262144 - - - false - arria10_hps_i_emac_emac0 - axi_slave0 - arria10_hps_i_emac_emac0.axi_slave0 - 4286578688 - 8192 - - - false - arria10_hps_i_emac_emac1 - axi_slave0 - arria10_hps_i_emac_emac1.axi_slave0 - 4286586880 - 8192 - - - false - arria10_hps_i_emac_emac2 - axi_slave0 - arria10_hps_i_emac_emac2.axi_slave0 - 4286595072 - 8192 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - master_reset_reset - Output - 1 - reset - - - - - - - embeddedsw.dts.group - ignore - - - embeddedsw.dts.name - debug - - - embeddedsw.dts.vendor - altr - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - boolean - true - false - true - true - true - - - java.lang.String - YES - true - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - RST - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 3 - false - true - true - true - - - java.lang.String - 0 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - YES - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - source_clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - source - Output - 3 - source - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - source_clk - Input - 1 - clk - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 2 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 100000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 2 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 2 - false - true - true - true - - - long - 100000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 2 - export - - - - - - - embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR - 0 - - - embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE - 0 - - - embeddedsw.CMacro.CONTENTS_INFO - "" - - - embeddedsw.CMacro.DUAL_PORT - 0 - - - embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.INIT_CONTENTS_FILE - a10s_ghrd_onchip_memory2 - - - embeddedsw.CMacro.INIT_MEM_CONTENT - 1 - - - embeddedsw.CMacro.INSTANCE_ID - NONE - - - embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED - 0 - - - embeddedsw.CMacro.RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.READ_DURING_WRITE_MODE - DONT_CARE - - - embeddedsw.CMacro.SINGLE_CLOCK_OP - 0 - - - embeddedsw.CMacro.SIZE_MULTIPLE - 1 - - - embeddedsw.CMacro.SIZE_VALUE - 262144 - - - embeddedsw.CMacro.WRITABLE - 1 - - - embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR - SIM_DIR - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 1 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HAS_BYTE_LANE - 0 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 8 - - - embeddedsw.memoryInfo.MEM_INIT_FILENAME - a10s_ghrd_onchip_memory2 - - - postgeneration.simulation.init_file.param_name - INIT_FILE - - - postgeneration.simulation.init_file.type - MEM_INIT - - - boolean - false - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - int - 8 - false - true - true - true - - - int - 32 - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - true - true - false - true - - - boolean - true - false - true - true - true - - - java.lang.String - onchip_mem.hex - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - NONE - false - false - true - true - - - long - 262144 - false - true - true - true - - - java.lang.String - DONT_CARE - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - false - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - a10s_ghrd_onchip_memory2 - false - true - false - true - UNIQUE_ID - - - java.lang.String - ARRIA10 - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 - false - true - false - true - DEVICE_FEATURES - - - int - 18 - true - true - false - true - - - int - 18 - true - true - false - true - - - int - 8 - true - true - false - true - - - int - 8 - true - true - false - true - - - java.lang.String - Automatic - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - a10s_ghrd_onchip_memory2.hex - true - true - false - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 262144 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk1 - false - true - true - true - - - java.lang.String - reset1 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 262144 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 18 - address - - - clken - Input - 1 - clken - - - chipselect - Input - 1 - chipselect - - - write - Input - 1 - write - - - readdata - Output - 8 - readdata - - - writedata - Input - 8 - writedata - - - - - - java.lang.String - clk1 - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - reset_req - Input - 1 - reset_req - - - - - - - int - 32 - false - true - true - true - - - int - 8 - false - true - true - true - - - int - 10 - false - false - true - true - - - int - 9 - false - true - false - true - ADDRESS_WIDTH - m0 - - - int - 1 - false - true - true - true - - - int - 9 - true - true - true - true - - - int - 9 - true - true - false - true - - - java.lang.String - SYMBOLS - false - true - true - true - - - int - 1 - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 512 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - pb_lwh2f.m0 - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - s0_waitrequest - Output - 1 - waitrequest - - - s0_readdata - Output - 32 - readdata - - - s0_readdatavalid - Output - 1 - readdatavalid - - - s0_burstcount - Input - 1 - burstcount - - - s0_writedata - Input - 32 - writedata - - - s0_address - Input - 9 - address - - - s0_write - Input - 1 - write - - - s0_read - Input - 1 - read - - - s0_byteenable - Input - 4 - byteenable - - - s0_debugaccess - Input - 1 - debugaccess - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - m0_waitrequest - Input - 1 - waitrequest - - - m0_readdata - Input - 32 - readdata - - - m0_readdatavalid - Input - 1 - readdatavalid - - - m0_burstcount - Output - 1 - burstcount - - - m0_writedata - Output - 32 - writedata - - - m0_address - Output - 9 - address - - - m0_write - Output - 1 - write - - - m0_read - Output - 1 - read - - - m0_byteenable - Output - 4 - byteenable - - - m0_debugaccess - Output - 1 - debugaccess - - - false - ILC - avalon_slave - ILC.avalon_slave - 0 - 256 - - - false - sysid_qsys - control_slave - sysid_qsys.control_slave - 304 - 8 - - - false - led_pio - s1 - led_pio.s1 - 288 - 16 - - - false - button_pio - s1 - button_pio.s1 - 272 - 16 - - - false - dipsw_pio - s1 - dipsw_pio.s1 - 256 - 16 - - - - - - - int - 0 - false - true - true - true - - - java.lang.String - deassert - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.Long - 100000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 100000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - in_reset - Input - 1 - reset - - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - in_reset - false - true - true - true - - - [Ljava.lang.String; - in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - out_reset - Output - 1 - reset - - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock50 - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - write - Input - 1 - write - - - address - Input - 1 - address - - - writedata - Input - 32 - writedata - - - - - - java.lang.String - clock50 - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk_50Mhz - Input - 1 - clk - - - - - - java.lang.String - clock50 - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - HEX0_D - Output - 7 - readdata - - - - - - java.lang.String - clock50 - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - HEX1_D - Output - 7 - readdata - - - - - - java.lang.String - clock50 - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - HEX0_DP - Output - 1 - writeresponsevalid_n - - - - - - java.lang.String - clock50 - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - HEX1_DP - Output - 1 - writeresponsevalid_n - - - - - - - embeddedsw.CMacro.ID - 0 - - - embeddedsw.CMacro.TIMESTAMP - 1576500538 - - - embeddedsw.dts.compatible - altr,sysid-1.0 - - - embeddedsw.dts.group - sysid - - - embeddedsw.dts.name - sysid - - - embeddedsw.dts.params.id - 0 - - - embeddedsw.dts.params.timestamp - 1576500538 - - - embeddedsw.dts.vendor - altr - - - int - 0 - false - true - true - true - - - int - 1576500538 - true - false - false - true - GENERATION_ID - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - readdata - Output - 32 - readdata - - - address - Input - 1 - address - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_bridges - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_bridges - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xc0000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_bridges - axi_h2f - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xc0000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_bridges - axi_h2f - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff200000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_bridges - axi_h2f_lw - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff200000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_bridges - axi_h2f_lw - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_arm_a9_0 - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_arm_a9_0 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_arm_a9_1 - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_arm_a9_1 - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd04000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_baum_clkmgr - axi_slave0 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_arm_gic_0 - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_arm_gic_0 - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffd000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_arm_gic_0 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffd000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_arm_gic_0 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_arm_gic_0 - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_arm_gic_0 - axi_slave1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_baum_clkmgr - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_cb_intosc_hs_div2_clk - clk - arria10_hps_baum_clkmgr - cb_intosc_hs_div2_clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_cb_intosc_ls_clk - clk - arria10_hps_baum_clkmgr - cb_intosc_ls_clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_f2s_free_clk - clk - arria10_hps_baum_clkmgr - f2s_free_clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_eosc1 - clk - arria10_hps_baum_clkmgr - eosc1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd04000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_baum_clkmgr - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd04000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_baum_clkmgr - axi_slave0 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_mpu_reg_l2_MPUL2 - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_mpu_reg_l2_MPUL2 - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xfffff000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xfffff000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - - - - int - 18 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_0 - arria10_hps_mpu_reg_l2_MPUL2 - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_dma_DMASECURE - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_main_clk - arria10_hps_i_dma_DMASECURE - apb_pclk - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda1000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_dma_DMASECURE - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda1000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_dma_DMASECURE - axi_slave0 - - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_dma_DMASECURE - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_i_sys_mgr_core - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_sys_mgr_core - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd06000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_sys_mgr_core - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd06000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_sys_mgr_core - axi_slave0 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_i_rst_mgr_rstmgr - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_rst_mgr_rstmgr - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd05000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd05000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_i_fpga_mgr_fpgamgrregs - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_fpga_mgr_fpgamgrregs - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd03000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd03000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffcfe400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffcfe400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - - - - int - 8 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_fpga_mgr_fpgamgrregs - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_timer - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - mpu_periph_clk - arria10_hps_timer - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc600 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc600 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_timer - axi_slave0 - - - - int - 13 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - arm_gic_ppi - arria10_hps_timer - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_timer_sp_0_timer - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_timer_sp_0_timer - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02700 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_timer_sp_0_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02700 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_timer_sp_0_timer - axi_slave0 - - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_timer_sp_0_timer - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_timer_sp_1_timer - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_timer_sp_1_timer - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_timer_sp_1_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_timer_sp_1_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_timer_sp_1_timer - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_timer_sys_0_timer - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sys_free_clk - arria10_hps_i_timer_sys_0_timer - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_timer_sys_0_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_timer_sys_0_timer - axi_slave0 - - - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_timer_sys_0_timer - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_timer_sys_1_timer - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sys_free_clk - arria10_hps_i_timer_sys_1_timer - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_timer_sys_1_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_timer_sys_1_timer - axi_slave0 - - - - int - 3 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_timer_sys_1_timer - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_watchdog_0_l4wd - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sys_free_clk - arria10_hps_i_watchdog_0_l4wd - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - - - - int - 4 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_watchdog_0_l4wd - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_watchdog_1_l4wd - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sys_free_clk - arria10_hps_i_watchdog_1_l4wd - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - - - - int - 5 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_115 - arria10_hps_i_watchdog_1_l4wd - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_gpio_0_gpio - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_gpio_0_gpio - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02900 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_gpio_0_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02900 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_gpio_0_gpio - axi_slave0 - - - - int - 29 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_gpio_0_gpio - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_gpio_1_gpio - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_gpio_1_gpio - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02a00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_gpio_1_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02a00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_gpio_1_gpio - axi_slave0 - - - - int - 30 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_gpio_1_gpio - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_gpio_2_gpio - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_gpio_2_gpio - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02b00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_gpio_2_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02b00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_gpio_2_gpio - axi_slave0 - - - - int - 31 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_gpio_2_gpio - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_uart_0_uart - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_uart_0_uart - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_uart_0_uart - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_uart_0_uart - axi_slave0 - - - - int - 27 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_uart_0_uart - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_uart_1_uart - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_uart_1_uart - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_uart_1_uart - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_uart_1_uart - axi_slave0 - - - - int - 28 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_uart_1_uart - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_emac_emac0 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - emac0_clk - arria10_hps_i_emac_emac0 - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff800000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_emac_emac0 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff800000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_emac_emac0 - axi_slave0 - - - - int - 9 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_emac_emac0 - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_emac_emac1 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - emac1_clk - arria10_hps_i_emac_emac1 - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff802000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_emac_emac1 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff802000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_emac_emac1 - axi_slave0 - - - - int - 10 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_emac_emac1 - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_emac_emac2 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - emac2_clk - arria10_hps_i_emac_emac2 - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff804000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_emac_emac2 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff804000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_emac_emac2 - axi_slave0 - - - - int - 11 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_emac_emac2 - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_spim_0_spim - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - spi_m_clk - arria10_hps_i_spim_0_spim - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda4000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_spim_0_spim - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda4000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_spim_0_spim - axi_slave0 - - - - int - 20 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_spim_0_spim - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_spim_1_spim - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - spi_m_clk - arria10_hps_i_spim_1_spim - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda5000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_spim_1_spim - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda5000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_spim_1_spim - axi_slave0 - - - - int - 21 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_spim_1_spim - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_spis_0_spis - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_spis_0_spis - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda2000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_spis_0_spis - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda2000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_spis_0_spis - axi_slave0 - - - - int - 18 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_spis_0_spis - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_spis_1_spis - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_spis_1_spis - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda3000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_spis_1_spis - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda3000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_spis_1_spis - axi_slave0 - - - - int - 19 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_spis_1_spis - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_i2c_0_i2c - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_i2c_0_i2c - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_i2c_0_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_i2c_0_i2c - axi_slave0 - - - - int - 22 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_i2c_0_i2c - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_i2c_1_i2c - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_i2c_1_i2c - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_i2c_1_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_i2c_1_i2c - axi_slave0 - - - - int - 23 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_i2c_1_i2c - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_i2c_emac_0_i2c - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_i2c_emac_0_i2c - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - - - - int - 24 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_i2c_emac_0_i2c - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_i2c_emac_1_i2c - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_i2c_emac_1_i2c - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02500 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02500 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - - - - int - 25 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_i2c_emac_1_i2c - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_i2c_emac_2_i2c - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_sp_clk - arria10_hps_i_i2c_emac_2_i2c - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02600 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02600 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - - - - int - 26 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_i2c_emac_2_i2c - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_qspi_QSPIDATA - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_qspi_QSPIDATA - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff809000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff809000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffa00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffa00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - - - - int - 17 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_qspi_QSPIDATA - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_sdmmc_sdmmc - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_sdmmc_sdmmc - biu - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - sdmmc_clk - arria10_hps_i_sdmmc_sdmmc - ciu - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff808000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff808000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - - - - int - 15 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_sdmmc_sdmmc - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_nand_NANDDATA - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - l4_mp_clk - arria10_hps_i_nand_NANDDATA - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb90000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_nand_NANDDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb90000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_nand_NANDDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb80000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_nand_NANDDATA - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb80000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_nand_NANDDATA - axi_slave1 - - - - int - 16 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_nand_NANDDATA - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_usbotg_0_globgrp - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - usb_clk - arria10_hps_i_usbotg_0_globgrp - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - - - - int - 12 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_usbotg_0_globgrp - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_i_usbotg_1_globgrp - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_baum_clkmgr - usb_clk - arria10_hps_i_usbotg_1_globgrp - clock_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb40000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb40000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - - - - int - 13 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - irq_rx_offset_83 - arria10_hps_i_usbotg_1_globgrp - interrupt_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk - arria10_hps_scu - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_clk_0 - clk_reset - arria10_hps_scu - reset_sink - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_0 - altera_axi_master - arria10_hps_scu - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_a9_1 - altera_axi_master - arria10_hps_scu - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffd000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_arm_gic_0 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffffc100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_arm_gic_0 - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xfffff000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_mpu_reg_l2_MPUL2 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda1000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_dma_DMASECURE - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd06000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_sys_mgr_core - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd05000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_rst_mgr_rstmgr - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd03000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffcfe400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_fpga_mgr_fpgamgrregs - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_uart_0_uart - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_uart_1_uart - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02700 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_timer_sp_0_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_timer_sp_1_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_timer_sys_0_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_timer_sys_1_timer - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_watchdog_0_l4wd - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffd00300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_watchdog_1_l4wd - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02900 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_gpio_0_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02a00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_gpio_1_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02b00 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_gpio_2_gpio - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_i2c_0_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_i2c_1_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02400 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_i2c_emac_0_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02500 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_i2c_emac_1_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffc02600 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_i2c_emac_2_i2c - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb90000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_nand_NANDDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb80000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_nand_NANDDATA - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda4000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_spim_0_spim - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffda5000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_spim_1_spim - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff809000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_qspi_QSPIDATA - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffa00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_qspi_QSPIDATA - axi_slave1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff808000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_sdmmc_sdmmc - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb00000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_usbotg_0_globgrp - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xffb40000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_usbotg_1_globgrp - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff800000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_emac_emac0 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff802000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_emac_emac1 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0xff804000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - axi_f2h - arria10_hps_i_emac_emac2 - axi_slave0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f - h2fw_ClockBridge - s0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x01000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f - onchip_memory2 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_lw - pb_lwh2f - s0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pb_lwh2f - m0 - ILC - avalon_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - h2fw_ClockBridge - m0 - sevensig - avalon_slave_0 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0008 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - h2fw_ClockBridge - m0 - fancmd - avalon_slave_0_1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0130 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pb_lwh2f - m0 - sysid_qsys - control_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0120 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pb_lwh2f - m0 - led_pio - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0110 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pb_lwh2f - m0 - button_pio - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pb_lwh2f - m0 - dipsw_pio - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - hps_m - master - arria10_hps_bridges - f2h - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - f2sdram_m - master - arria10_hps_bridges - f2sdram0_data - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - fpga_m - master - pb_lwh2f - s0 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - reset_bridge - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - hps_m - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - f2sdram_m - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - fpga_m - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - pb_lwh2f - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - sysid_qsys - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - led_pio - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - button_pio - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - dipsw_pio - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - ILC - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - onchip_memory2 - clk1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk - sevensig - clock50 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk - fancmd - clock50Mhz - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - arria10_hps_bridges - f2h_axi_clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - arria10_hps_bridges - f2sdram0_clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - arria10_hps_bridges - h2f_axi_clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - arria10_hps_bridges - h2f_lw_axi_clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - h2fw_ClockBridge - m0_clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk - h2fw_ClockBridge - s0_clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk - issp - source_clk - - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - emif_a10_hps - hps_emif_conduit_end - arria10_hps_fpga_interfaces - emif - - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - f2h_irq_0_irq_rx_offset_19 - button_pio - irq - - - - int - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_arm_gic_0 - f2h_irq_0_irq_rx_offset_19 - dipsw_pio - irq - - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - ILC - irq - button_pio - irq - - - - int - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - ILC - irq - dipsw_pio - irq - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - clk_50 - clk_in_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - hps_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - f2sdram_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - fpga_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - arria10_hps_bridges - f2h_axi_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - arria10_hps_bridges - f2sdram0_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - emif_a10_hps - global_reset_reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - arria10_hps_bridges - h2f_axi_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - arria10_hps_bridges - h2f_lw_axi_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - reset_bridge - in_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - h2fw_ClockBridge - m0_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - pb_lwh2f - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - sysid_qsys - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - led_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - button_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - dipsw_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk_reset - fancmd - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk_reset - sevensig - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - onchip_memory2 - reset1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_100 - clk_reset - ILC - reset_n - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_50 - clk_reset - h2fw_ClockBridge - s0_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - hps_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - f2sdram_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - fpga_m - clk_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - arria10_hps_bridges - f2h_axi_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - arria10_hps_bridges - h2f_lw_axi_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - reset_bridge - in_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - pb_lwh2f - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - sysid_qsys - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - led_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - button_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - dipsw_pio - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - onchip_memory2 - reset1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - arria10_hps_bridges - h2f_reset - ILC - reset_n - - - 1 - interrupt_latency_counter - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Interrupt Latency Counter Intel FPGA IP - 18.1 - - - 70 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 69 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 9 - interrupt_receiver - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 18.1 - - - 10 - avalon_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 18.1 - - - 1 - altera_arria10_hps - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Arria 10 Hard Processor System - 18.1 - - - 24 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - - 12 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 18.1 - - - 47 - altera_axi_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - AXI Slave - 18.1 - - - 7 - altera_axi_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - AXI Master - 18.1 - - - 1 - altera_arria10_interface_generator - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - altera_arria10_interface_generator - 14.0 - - - 1 - altera_arria10_hps_io - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - altera_arria10_hps_io - 18.1 - - - 1 - hps_clk_src - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - HPS clk src - 18.1 - - - 32 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 18.1 - - - 1 - arria10_hps_bridge_avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - HPS Bridge Avalon - 18.1 - - - 4 - hps_virt_clk - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - HPS Virtual Clock - 18.1 - - - 2 - arm_a9 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM A9 - 18.1 - - - 1 - arria10_arm_gic - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM GIC - 18.1 - - - 1 - baum_clkmgr - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Clock Manager - 18.1 - - - 1 - arm_pl310_L2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM pl310 cache - 18.1 - - - 34 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 18.1 - - - 1 - arm_pl330_dma - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM pl330 dma - 18.1 - - - 1 - altera_sysmgr - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera System Manager - 18.1 - - - 1 - altera_rstmgr - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Reset Manager - 18.1 - - - 1 - altera_fpgamgr - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera FPGA Manager - 18.1 - - - 1 - arm_internal_timer - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM internal timer - 18.1 - - - 2 - dw_apb_timer_sp - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys SP Timer - 18.1 - - - 2 - dw_apb_timer_osc - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys OCS Timer - 18.1 - - - 2 - dw_wd_timer - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys WatchDog Timer - 18.1 - - - 3 - dw_gpio - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys GPIO - 18.1 - - - 2 - snps_uart - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys UART - 18.1 - - - 3 - stmmac - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys GMAC - 18.1 - - - 4 - spi - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys SPI - 18.1 - - - 5 - designware_i2c - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys I2C - 18.1 - - - 1 - cadence_qspi - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Cadence QSPI - 18.1 - - - 1 - sdmmc - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys SDMMC - 18.1 - - - 1 - denali_nand - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Denali NAND - 18.1 - - - 2 - usb - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Synopsys USB - 18.1 - - - 1 - scu - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ARM Snoop Control Unit - 18.1 - - - 3 - altera_avalon_pio - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - PIO (Parallel I/O) Intel FPGA IP - 18.1 - - - 2 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Clock Source - 18.1 - - - 2 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 2 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 2 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 18.1 - - - 2 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 18.1 - - - 1 - altera_emif_a10_hps - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Arria 10 External Memory Interfaces for HPS - 18.1 - - - 3 - altera_jtag_avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG to Avalon Master Bridge - 18.1 - - - 5 - avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 18.1 - - - 1 - HAN_FanControll - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - HAN_FanControll - 1.0 - - - 1 - altera_avalon_mm_clock_crossing_bridge - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Avalon-MM Clock Crossing Bridge - 18.1 - - - 1 - altera_in_system_sources_probes - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - - 18.1 - - - 1 - altera_avalon_onchip_memory2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) Intel FPGA IP - 18.1 - - - 1 - altera_avalon_mm_bridge - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Avalon-MM Pipeline Bridge - 18.1 - - - 1 - altera_reset_bridge - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Reset Bridge - 18.1 - - - 1 - SevenSigmentDisplay - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - SevenSigmentDisplay - 1.0 - - - 1 - altera_avalon_sysid_qsys - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - System ID Peripheral Intel FPGA IP - 18.1 - - - 64 - clock - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection - 18.1 - - - 74 - reset - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection - 18.1 - - - 136 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 18.1 - - - 36 - interrupt - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Interrupt Connection - 18.1 - - - 1 - conduit - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Conduit Connection - 18.1 - - 18.1 625 - - diff --git a/fpga/HAN_A10rsyocto/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_summary.csv b/fpga/HAN_A10rsyocto/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_summary.csv deleted file mode 100644 index e951385..0000000 --- a/fpga/HAN_A10rsyocto/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_summary.csv +++ /dev/null @@ -1,30 +0,0 @@ -Core: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq - Instance: u0|emif_a10_hps -Path, Setup Margin, Hold Margin -"Address/Command (Slow 900mV 100C Model)",0.206,0.206 -"Core (Slow 900mV 100C Model)",--,-- -"Core Recovery/Removal (Slow 900mV 100C Model)",--,-- -"DQS Gating (Slow 900mV 100C Model)",0.62,0.62 -"Read Capture (Slow 900mV 100C Model)",0.043,0.043 -"Write (Slow 900mV 100C Model)",0.043,0.043 -"Write Levelling (Slow 900mV 100C Model)",0.158,0.158 -"Address/Command (Slow 900mV 0C Model)",0.206,0.206 -"Core (Slow 900mV 0C Model)",--,-- -"Core Recovery/Removal (Slow 900mV 0C Model)",--,-- -"DQS Gating (Slow 900mV 0C Model)",0.62,0.62 -"Read Capture (Slow 900mV 0C Model)",0.043,0.043 -"Write (Slow 900mV 0C Model)",0.043,0.043 -"Write Levelling (Slow 900mV 0C Model)",0.158,0.158 -"Address/Command (Fast 900mV 100C Model)",0.206,0.206 -"Core (Fast 900mV 100C Model)",--,-- -"Core Recovery/Removal (Fast 900mV 100C Model)",--,-- -"DQS Gating (Fast 900mV 100C Model)",0.62,0.62 -"Read Capture (Fast 900mV 100C Model)",0.043,0.043 -"Write (Fast 900mV 100C Model)",0.043,0.043 -"Write Levelling (Fast 900mV 100C Model)",0.158,0.158 -"Address/Command (Fast 900mV 0C Model)",0.206,0.206 -"Core (Fast 900mV 0C Model)",--,-- -"Core Recovery/Removal (Fast 900mV 0C Model)",--,-- -"DQS Gating (Fast 900mV 0C Model)",0.62,0.62 -"Read Capture (Fast 900mV 0C Model)",0.043,0.043 -"Write (Fast 900mV 0C Model)",0.043,0.043 -"Write Levelling (Fast 900mV 0C Model)",0.158,0.158 diff --git a/fpga/HAN_A10rsyocto/hps_isw_handoff/emif.xml b/fpga/HAN_A10rsyocto/hps_isw_handoff/emif.xml deleted file mode 100644 index 6088421..0000000 --- a/fpga/HAN_A10rsyocto/hps_isw_handoff/emif.xml +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/hps_isw_handoff/hps.xml b/fpga/HAN_A10rsyocto/hps_isw_handoff/hps.xml deleted file mode 100644 index 267da0e..0000000 --- a/fpga/HAN_A10rsyocto/hps_isw_handoff/hps.xml +++ /dev/null @@ -1,351 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/hps_isw_handoff/id b/fpga/HAN_A10rsyocto/hps_isw_handoff/id deleted file mode 100644 index 1f09541..0000000 --- a/fpga/HAN_A10rsyocto/hps_isw_handoff/id +++ /dev/null @@ -1,3 +0,0 @@ -Do not change the content of this file -MD5 : d357a1f667346be7717a8d9f10858cd3 -CRC32 : 0x99C78065 diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.asm.rpt b/fpga/HAN_A10rsyocto/output_files/a10s.asm.rpt deleted file mode 100644 index ae91b83..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.asm.rpt +++ /dev/null @@ -1,113 +0,0 @@ -Assembler report for a10s -Mon Dec 16 14:06:50 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Encrypted IP Cores Summary - 5. Assembler Generated Files - 6. Assembler Device Options: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.sof - 7. Assembler Device Options: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.pof - 8. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Dec 16 14:06:50 2019 ; -; Revision Name ; a10s ; -; Top-level Entity Name ; a10s ; -; Family ; Arria 10 ; -; Device ; 10AS066K3F40E2SG ; -+-----------------------+---------------------------------------+ - - -+----------------------------------+ -; Assembler Settings ; -+--------+---------+---------------+ -; Option ; Setting ; Default Value ; -+--------+---------+---------------+ - - -+------------------------------------------------+ -; Assembler Encrypted IP Cores Summary ; -+--------+------------------------+--------------+ -; Vendor ; IP Core Name ; License Type ; -+--------+------------------------+--------------+ -; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; -; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; -+--------+------------------------+--------------+ - - -+---------------------------------------------------------------------------------------+ -; Assembler Generated Files ; -+---------------------------------------------------------------------------------------+ -; File Name ; -+---------------------------------------------------------------------------------------+ -; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.sof ; -; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.pof ; -+---------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.sof ; -+----------------+------------------------------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+------------------------------------------------------------------------------------------------+ -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x1CF9F750 ; -+----------------+------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.pof ; -+--------------------+--------------------------------------------------------------------------------------------+ -; Option ; Setting ; -+--------------------+--------------------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x5CBE8278 ; -; Compression Ratio ; 2 ; -+--------------------+--------------------------------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Assembler - Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - Info: Processing started: Mon Dec 16 14:05:50 2019 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off a10s -c a10s -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 10175 megabytes - Info: Processing ended: Mon Dec 16 14:06:51 2019 - Info: Elapsed time: 00:01:01 - Info: Total CPU time (on all processors): 00:01:12 - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.done b/fpga/HAN_A10rsyocto/output_files/a10s.done deleted file mode 100644 index 712533b..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.done +++ /dev/null @@ -1 +0,0 @@ -Mon Dec 16 18:03:00 2019 diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.fit.rpt b/fpga/HAN_A10rsyocto/output_files/a10s.fit.rpt deleted file mode 100644 index 7595ded..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.fit.rpt +++ /dev/null @@ -1,9201 +0,0 @@ -Fitter report for a10s -Mon Dec 16 14:05:43 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Fitter Netlist Optimizations - 6. Estimated Delay Added for Hold Timing Summary - 7. Estimated Delay Added for Hold Timing Details - 8. Ignored Assignments - 9. Incremental Compilation Preservation Summary - 10. Incremental Compilation Partition Settings - 11. Incremental Compilation Placement Preservation - 12. Pin-Out File - 13. Fitter Resource Usage Summary - 14. Fitter Partition Statistics - 15. Input Pins - 16. Output Pins - 17. Bidir Pins - 18. I/O Bank Usage - 19. All Package Pins - 20. I/O Assignment Warnings - 21. PLL Usage Summary - 22. Fitter Resource Utilization by Entity - 23. Delay Chain Summary - 24. Control Signals - 25. Global & Other Fast Signals Summary - 26. Global & Other Fast Signals Details - 27. Non-Global High Fan-Out Signals - 28. Fitter RAM Summary - 29. Routing Usage Summary - 30. Fitter HSLP Summary - 31. Fitter Device Options - 32. Operating Settings and Conditions - 33. Fitter Messages - 34. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+-------------------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Mon Dec 16 14:05:42 2019 ; -; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; -; Revision Name ; a10s ; -; Top-level Entity Name ; a10s ; -; Family ; Arria 10 ; -; Device ; 10AS066K3F40E2SG ; -; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 5,726 / 251,680 ( 2 % ) ; -; Total registers ; 10270 ; -; Total pins ; 439 / 864 ( 51 % ) ; -; Total virtual pins ; 0 ; -; Total block memory bits ; 2,099,384 / 43,642,880 ( 5 % ) ; -; Total RAM Blocks ; 134 / 2,131 ( 6 % ) ; -; Total DSP Blocks ; 0 / 1,687 ( 0 % ) ; -; Total HSSI RX channels ; 0 / 36 ( 0 % ) ; -; Total HSSI TX channels ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 12 / 80 ( 15 % ) ; -+-----------------------------+-------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; 10AS066K3F40E2SG ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 100 ; ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Optimization Mode ; Balanced ; Balanced ; -; Allow Register Merging ; On ; On ; -; Allow Register Duplication ; On ; On ; -; Allow Register Retiming ; On ; On ; -; Disable the Legacy Timing Analyzer and use the latest version of the Timing Analyzer instead ; On ; On ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Perform Clocking Topology Analysis During Routing ; Off ; Off ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Physical Synthesis ; Off ; Off ; -; Enable unused RX clock workaround ; Off ; Off ; -; Preserve unused RX/TX channels ; Off ; Off ; -; Ignore the power supply of HSSI column when preserving unused RX/TX channels ; On ; On ; -; Automatically reserve CLKUSR pin for calibration purposes ; On ; On ; -; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; On ; On ; -; Auto RAM to MLAB Conversion ; On ; On ; -; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; -; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; -; Programmable Power Technology Optimization ; Automatic ; Automatic ; -; Programmable Power Maximum High-Speed Fraction of Used LAB Tiles ; 1.0 ; 1.0 ; -; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; Periphery to Core Placement and Routing Optimization ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Synchronizer Identification ; Auto ; Auto ; -; Optimize Design for Metastability ; On ; On ; -; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; -; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; -; Advanced Physical Optimization ; On ; On ; -+----------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 6 ; -; ; ; -; Average used ; 1.35 ; -; Maximum used ; 6 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 9.0% ; -; Processor 3 ; 6.9% ; -; Processor 4 ; 6.6% ; -; Processor 5 ; 6.5% ; -; Processor 6 ; 6.4% ; -+----------------------------+-------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+--------------------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+--------------------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+-----------------------+ -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a8 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a9 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a10 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a11 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a12 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a13 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a14 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a15 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a16 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a17 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a18 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a19 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a20 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a21 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a22 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a23 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a24 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a25 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a26 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a27 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a28 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a29 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a30 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|out_payload[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ram_block1a31 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a8 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a9 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[37] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a10 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[38] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a11 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[42] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a13 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|out_payload[43] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ram_block1a14 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a0 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a1 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a2 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a3 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a4 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a5 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a6 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a7 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a8 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a9 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a10 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a11 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a12 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a13 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a14 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a15 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a16 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a17 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a18 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a19 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a20 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a21 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a22 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a23 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a24 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a25 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a26 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a27 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a28 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a29 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a30 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|out_payload[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ram_block1a31 ; PORTBDATAOUT ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CK_1HZ ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CK_1HZ~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CLK_DELAY[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CLK_DELAY[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CLK_DELAY[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|CLK_DELAY[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[4]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[9]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[17]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|CNT[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|CNT[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|ST[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|ST[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|A[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|A[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|ST[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|ST[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|ST[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|ST[4]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|END_OK ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|END_OK~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|W_POINTER_REG[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|W_POINTER_REG[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|W_WORD_GO ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|W_WORD_GO~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|getptr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|getptr[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[22]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[48] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[48]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[61] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|r_data_init_r[61]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|getptr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|getptr[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|getptr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|getptr[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b|free ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b|free~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|ar_data_init_r[32] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|ar_data_init_r[32]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|aw_data_init_r[41] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|aw_data_init_r[41]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|getptr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|getptr[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|w_data_init_r[36] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|w_data_init_r[36]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|w_data_init_r[38] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|w_data_init_r[38]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio|edge_capture[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio|edge_capture[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[9]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[16]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[6]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.0000 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.0000~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|internal_out_valid ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|internal_out_valid~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|wr_ptr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|wr_ptr[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[15]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[12]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_HEADER_1 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_HEADER_1~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[4]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[14]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_SIZE1 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_SIZE1~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_WRITE_DATA ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_WRITE_DATA~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|wr_ptr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|wr_ptr[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_toggle ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_toggle~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_HEADER ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_HEADER~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[18]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_BYPASS ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_BYPASS~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[14]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[24]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[28]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[29]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[15]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_WRITE_DATA ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_WRITE_DATA~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_ISSUE ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_ISSUE~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.WRITE_WAIT ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.WRITE_WAIT~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|wr_ptr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|wr_ptr[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[4]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[14]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|sent_channel_char ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|sent_channel_char~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo|mem_used[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo|mem_used[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent|hold_waitrequest ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent|hold_waitrequest~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator|read_latency_shift_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator|read_latency_shift_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator|read_latency_shift_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator|read_latency_shift_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator|read_latency_shift_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator|read_latency_shift_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][135] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][135]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][142] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][142]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][128]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][136]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][137] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][137]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][143]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][132] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][132]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][135] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][135]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][136]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][137] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem[0][137]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][129]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][130] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][130]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][132] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][132]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][136]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][139]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][141] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem[0][141]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter|pending_response_count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter|pending_response_count[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo|mem_used[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo|mem_used[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator|av_readdata_pre[26] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator|av_readdata_pre[26]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|saved_grant[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|saved_grant[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|saved_grant[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|saved_grant[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|wr_ptr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|wr_ptr[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][4]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|mem[0][6]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[13]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[16]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator|read_latency_shift_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator|read_latency_shift_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|count[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|cmd_address[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|cmd_address[7]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|cmd_read ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|cmd_read~DUPLICATE ; ; ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller|r_sync_rst_chain[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altera_reset_controller:rst_controller|r_sync_rst_chain[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|hold_reg[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|hold_reg[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[0]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[2]~DUPLICATE ; ; ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[3]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][12]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][15]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][16]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][18]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[0][20]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][15]~DUPLICATE ; ; ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|interrupt_latency_counter:ilc|count_reg[1][29]~DUPLICATE ; ; ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[1]~DUPLICATE ; ; ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[10]~DUPLICATE ; ; ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[11]~DUPLICATE ; ; ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[14]~DUPLICATE ; ; ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[5]~DUPLICATE ; ; ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[3]~DUPLICATE ; ; ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0]~DUPLICATE ; ; ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[5]~DUPLICATE ; ; ; -; ALTERA_RESERVED_FITTER_INSERTED_PMA_AUX0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; ALTERA_RESERVED_FITTER_INSERTED_PMA_AUX1 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; ALTERA_RESERVED_FITTER_INSERTED_PMA_UC0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; CLKUSR_100~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; CLK_50_B2H~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[0]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[1]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[2]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[3]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[4]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[5]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[6]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[7]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[8]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_C2M_p[9]~output_PMA_TX_BUF_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[0]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[1]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[2]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[3]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[4]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[5]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[6]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[7]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[8]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_DP_M2C_p[9]~input_PMA_RX_BUF_RARP_FITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_GBTCLK_M2C_p[0]~inputFITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_GBTCLK_M2C_p[1]~inputFITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; FMC_REFCLK_p~inputFITTER_INSERTED ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL1 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL2 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL3 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL4 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL5 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL6 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL7 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL8 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_PLL9 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX1 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX2 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX3 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX4 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX5 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX6 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX7 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX8 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; RARP_FITTER_INSERTED_PMA_CDR_REFCLK_SELECT_MUX9 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|all_tiles_core_clks_out[0][0] ; Duplicated ; Placement ; Fitter Periphery Placement ; PA_CORE_CLK_OUT ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|all_tiles_core_clks_out[0][0]~_Duplicate ; PA_CORE_CLK_OUT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|all_tiles_core_clks_out[1][0] ; Deleted ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_1 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_2 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_3 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_4 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_5 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_6 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_7 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_8 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_9 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_10 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_11 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_12 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_13 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_14 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_15 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_16 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_17 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_18 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_19 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_20 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_21 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_22 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_23 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_24 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_25 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_26 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_27 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_28 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_29 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_30 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_31 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_32 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_33 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_34 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_35 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_36 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_37 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_38 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_39 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_40 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_41 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_42 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_43 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_44 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_45 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_46 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_47 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_48 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_49 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_50 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_51 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_52 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_53 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_54 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_55 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_56 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_57 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_58 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_59 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_60 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_61 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_62 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_63 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_64 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_65 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_66 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_67 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_68 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_69 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Duplicated ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_70 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0] ; Deleted ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_1 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_3 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_2 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_5 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_4 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_7 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_6 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_9 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_8 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_11 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_10 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_14 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_13 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_16 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_15 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_19 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_18 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_21 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_20 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_26 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_23 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_31 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_27 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_32 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_28 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_33 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_29 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_34 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_30 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_37 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_36 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_39 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_35 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_42 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_40 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_45 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_43 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_48 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_44 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_49 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_47 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_53 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_51 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_54 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_52 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_57 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_55 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_62 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_59 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_63 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_60 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_65 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_61 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_67 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_41 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_68 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_46 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_69 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_58 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_70 ; Merged ; Placement ; Fitter Periphery Placement ; SERIESTERMINATIONCONTROL ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|oct_stc[0]~_Duplicate_66 ; SERIESTERMINATIONCONTROL ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~O_BLOCK_SELECT ; Duplicated ; Placement ; Fitter Periphery Placement ; BLOCK_SELECT ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~O_BLOCK_SELECT_Duplicate ; BLOCK_SELECT ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~refclk ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~refclk ; Duplicated ; Placement ; Fitter Periphery Placement ; CLK_OUT ; ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~refclk_Duplicate ; CLK_OUT ; ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+--------------------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+-----------------------+ - - -+----------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Summary ; -+---------------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+---------------------+----------------------+-------------------+ -; altera_reserved_tck ; altera_reserved_tck ; 1782.9 ; -; CLKUSR_100 ; CLKUSR_100 ; 944.6 ; -; CLK_50_B2H ; CLK_50_B2H ; 83.2 ; -+---------------------+----------------------+-------------------+ -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.306 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 2.299 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.281 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 2.260 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 2.254 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 2.244 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[7] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.222 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.190 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.166 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|received_esc ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.152 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.126 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.123 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[1] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[1] ; 2.092 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.086 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.086 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 2.061 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.059 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 2.039 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 2.035 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 2.024 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 2.010 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.997 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 1.997 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.984 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.977 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.977 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[7] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.974 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.969 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.962 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[7] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.946 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_READ_DATA ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.926 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_BYPASS ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[1] ; 1.923 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[0] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[3] ; 1.920 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.917 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[6] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[0] ; 1.908 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[1] ; 1.894 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[8] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.868 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.865 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.859 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.858 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[8] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[4][0] ; 1.857 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_HEADER ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.851 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.843 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|received_esc ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.834 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.834 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.834 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[7] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.829 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.804 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[2][2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED ; 1.790 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1] ; 1.787 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[2][1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED ; 1.784 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.738 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[2][0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED ; 1.730 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA ; 1.729 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[3][1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; 1.687 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[7] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[0] ; 1.677 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA ; 1.675 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA ; 1.654 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|received_esc ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.649 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[3][2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; 1.648 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA ; 1.630 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[3][0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; 1.615 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_valid ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[8] ; 1.551 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.538 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.519 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.515 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.510 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.498 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_valid ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[18] ; 1.492 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.492 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.491 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_scan_reg ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; 1.490 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.482 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[8] ; 1.482 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[8] ; 1.481 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0] ; 1.472 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[4] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED ; 1.468 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.467 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][0] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0] ; 1.460 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[8] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.455 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[5] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18] ; 1.440 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[1] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[8] ; 1.436 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[1][0] ; 1.434 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[9] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.423 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[12] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.423 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][2] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0] ; 1.420 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|splitter_nodes_receive_2[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready ; 1.415 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4] ; 1.403 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[13] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.397 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[7] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18] ; 1.393 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[14] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 1.380 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18] ; 1.375 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|splitter_nodes_receive_0[3] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0] ; 1.369 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[12] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 1.366 ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[1][0] ; 1.362 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[8] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[7] ; 1.356 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[13] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3] ; 1.346 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[14] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.345 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[11] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.343 ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[16] ; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0] ; 1.341 ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -Note: This table only shows the top 100 path(s) that have the largest delay added for hold. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Ignored Assignments ; -+--------------+-------------------------------------------+--------------+----------------------+-------------------------+----------------------------+ -; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; -+--------------+-------------------------------------------+--------------+----------------------+-------------------------+----------------------------+ -; Location ; ; ; CLK_50_B2A ; PIN_AW16 ; QSF Assignment ; -; Location ; ; ; CLK_50_B3F ; PIN_F3 ; QSF Assignment ; -; Location ; ; ; DDCSCL_RX ; PIN_AN27 ; QSF Assignment ; -; Location ; ; ; DDCSDA_RX ; PIN_AJ26 ; QSF Assignment ; -; Location ; ; ; DDR4A_ACT_n ; PIN_AD1 ; QSF Assignment ; -; Location ; ; ; DDR4A_AC_R[0] ; PIN_AD5 ; QSF Assignment ; -; Location ; ; ; DDR4A_AC_R[1] ; PIN_Y6 ; QSF Assignment ; -; Location ; ; ; DDR4A_ALERT_n ; PIN_AC12 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[0] ; PIN_AC1 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[10] ; PIN_W5 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[11] ; PIN_Y5 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[12] ; PIN_AA9 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[13] ; PIN_AB7 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[14] ; PIN_AA7 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[15] ; PIN_AB10 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[16] ; PIN_AB11 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[1] ; PIN_AB1 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[2] ; PIN_AB4 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[3] ; PIN_AA5 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[4] ; PIN_AA3 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[5] ; PIN_AA4 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[6] ; PIN_Y2 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[7] ; PIN_AA2 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[8] ; PIN_AB5 ; QSF Assignment ; -; Location ; ; ; DDR4A_A[9] ; PIN_AB6 ; QSF Assignment ; -; Location ; ; ; DDR4A_BA[0] ; PIN_Y7 ; QSF Assignment ; -; Location ; ; ; DDR4A_BA[1] ; PIN_AB9 ; QSF Assignment ; -; Location ; ; ; DDR4A_BG[0] ; PIN_AA10 ; QSF Assignment ; -; Location ; ; ; DDR4A_BG[1] ; PIN_AE2 ; QSF Assignment ; -; Location ; ; ; DDR4A_CK ; PIN_AD3 ; QSF Assignment ; -; Location ; ; ; DDR4A_CKE ; PIN_AC2 ; QSF Assignment ; -; Location ; ; ; DDR4A_CK_n ; PIN_AD4 ; QSF Assignment ; -; Location ; ; ; DDR4A_CS_n ; PIN_AE1 ; QSF Assignment ; -; Location ; ; ; DDR4A_C[0] ; PIN_AC4 ; QSF Assignment ; -; Location ; ; ; DDR4A_C[1] ; PIN_AB2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[0] ; PIN_AD9 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[1] ; PIN_AJ5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[2] ; PIN_AK2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[3] ; PIN_AG2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[4] ; PIN_L2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[5] ; PIN_L3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[6] ; PIN_U4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[7] ; PIN_V8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DBI_n[8] ; PIN_V4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[0] ; PIN_AE8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[1] ; PIN_AF7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[2] ; PIN_AN1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[3] ; PIN_AH2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[4] ; PIN_P1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[5] ; PIN_J3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[6] ; PIN_R5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[7] ; PIN_V9 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS[8] ; PIN_V2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[0] ; PIN_AD8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[1] ; PIN_AE7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[2] ; PIN_AN2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[3] ; PIN_AH3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[4] ; PIN_R1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[5] ; PIN_K3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[6] ; PIN_R6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[7] ; PIN_W9 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQS_n[8] ; PIN_V3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[0] ; PIN_AC11 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[10] ; PIN_AG6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[11] ; PIN_AD6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[12] ; PIN_AG5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[13] ; PIN_AK5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[14] ; PIN_AC7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[15] ; PIN_AH6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[16] ; PIN_AK1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[17] ; PIN_AL4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[18] ; PIN_AJ4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[19] ; PIN_AM1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[1] ; PIN_AD10 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[20] ; PIN_AK3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[21] ; PIN_AL2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[22] ; PIN_AJ3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[23] ; PIN_AM2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[24] ; PIN_AF2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[25] ; PIN_AH1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[26] ; PIN_AG4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[27] ; PIN_AE5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[28] ; PIN_AF3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[29] ; PIN_AH4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[2] ; PIN_AC9 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[30] ; PIN_AG1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[31] ; PIN_AF4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[32] ; PIN_K1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[33] ; PIN_P4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[34] ; PIN_N2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[35] ; PIN_K2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[36] ; PIN_M2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[37] ; PIN_P3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[38] ; PIN_N1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[39] ; PIN_J1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[3] ; PIN_AG7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[40] ; PIN_N3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[41] ; PIN_P5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[42] ; PIN_M5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[43] ; PIN_R2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[44] ; PIN_N4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[45] ; PIN_P6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[46] ; PIN_L4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[47] ; PIN_R3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[48] ; PIN_V6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[49] ; PIN_T7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[4] ; PIN_AD13 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[50] ; PIN_U5 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[51] ; PIN_U7 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[52] ; PIN_T4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[53] ; PIN_W6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[54] ; PIN_T3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[55] ; PIN_U6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[56] ; PIN_W8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[57] ; PIN_Y12 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[58] ; PIN_Y11 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[59] ; PIN_W10 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[5] ; PIN_AD11 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[60] ; PIN_Y13 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[61] ; PIN_Y8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[62] ; PIN_Y10 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[63] ; PIN_W11 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[64] ; PIN_V1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[65] ; PIN_Y1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[66] ; PIN_W3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[67] ; PIN_W1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[68] ; PIN_Y3 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[69] ; PIN_W4 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[6] ; PIN_AC8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[70] ; PIN_U1 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[71] ; PIN_U2 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[7] ; PIN_AF8 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[8] ; PIN_AE6 ; QSF Assignment ; -; Location ; ; ; DDR4A_DQ[9] ; PIN_AJ6 ; QSF Assignment ; -; Location ; ; ; DDR4A_EVENT_n ; PIN_T5 ; QSF Assignment ; -; Location ; ; ; DDR4A_ODT ; PIN_AC3 ; QSF Assignment ; -; Location ; ; ; DDR4A_PAR ; PIN_AC6 ; QSF Assignment ; -; Location ; ; ; DDR4A_REFCLK_p ; PIN_AB12 ; QSF Assignment ; -; Location ; ; ; DDR4A_RESET_n ; PIN_AE3 ; QSF Assignment ; -; Location ; ; ; DDR4A_RZQ ; PIN_AA8 ; QSF Assignment ; -; Location ; ; ; DDR4A_SCL ; PIN_AF5 ; QSF Assignment ; -; Location ; ; ; DDR4A_SDA ; PIN_AJ1 ; QSF Assignment ; -; Location ; ; ; DDR4B_ACT_n ; PIN_AH13 ; QSF Assignment ; -; Location ; ; ; DDR4B_ALERT_n ; PIN_AH11 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[0] ; PIN_AJ11 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[10] ; PIN_AM9 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[11] ; PIN_AL10 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[12] ; PIN_AV8 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[13] ; PIN_AT8 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[14] ; PIN_AT9 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[15] ; PIN_AR7 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[16] ; PIN_AR8 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[1] ; PIN_AH12 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[2] ; PIN_AP11 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[3] ; PIN_AN11 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[4] ; PIN_AM10 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[5] ; PIN_AM11 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[6] ; PIN_AP9 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[7] ; PIN_AN9 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[8] ; PIN_AR10 ; QSF Assignment ; -; Location ; ; ; DDR4B_A[9] ; PIN_AP10 ; QSF Assignment ; -; Location ; ; ; DDR4B_BA[0] ; PIN_AU6 ; QSF Assignment ; -; Location ; ; ; DDR4B_BA[1] ; PIN_AP8 ; QSF Assignment ; -; Location ; ; ; DDR4B_BG[0] ; PIN_AN8 ; QSF Assignment ; -; Location ; ; ; DDR4B_BG[1] ; PIN_AJ14 ; QSF Assignment ; -; Location ; ; ; DDR4B_CK ; PIN_AL13 ; QSF Assignment ; -; Location ; ; ; DDR4B_CKE ; PIN_AK10 ; QSF Assignment ; -; Location ; ; ; DDR4B_CK_n ; PIN_AK13 ; QSF Assignment ; -; Location ; ; ; DDR4B_CS_n ; PIN_AJ13 ; QSF Assignment ; -; Location ; ; ; DDR4B_DBI_n[0] ; PIN_AF10 ; QSF Assignment ; -; Location ; ; ; DDR4B_DBI_n[1] ; PIN_AL8 ; QSF Assignment ; -; Location ; ; ; DDR4B_DBI_n[2] ; PIN_AN7 ; QSF Assignment ; -; Location ; ; ; DDR4B_DBI_n[3] ; PIN_AN4 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS[0] ; PIN_AE12 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS[1] ; PIN_AL7 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS[2] ; PIN_AR6 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS[3] ; PIN_AT2 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS_n[0] ; PIN_AF13 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS_n[1] ; PIN_AK8 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS_n[2] ; PIN_AP6 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQS_n[3] ; PIN_AT3 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[0] ; PIN_AJ9 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[10] ; PIN_AK6 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[11] ; PIN_AK7 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[12] ; PIN_AH8 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[13] ; PIN_AH7 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[14] ; PIN_AJ8 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[15] ; PIN_AE11 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[16] ; PIN_AT4 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[17] ; PIN_AM7 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[18] ; PIN_AP5 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[19] ; PIN_AL5 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[1] ; PIN_AG11 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[20] ; PIN_AM5 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[21] ; PIN_AM6 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[22] ; PIN_AM4 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[23] ; PIN_AR5 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[24] ; PIN_AP1 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[25] ; PIN_AR3 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[26] ; PIN_AN3 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[27] ; PIN_AR1 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[28] ; PIN_AU2 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[29] ; PIN_AP4 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[2] ; PIN_AF9 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[30] ; PIN_AR2 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[31] ; PIN_AU1 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[3] ; PIN_AG12 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[4] ; PIN_AG9 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[5] ; PIN_AF12 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[6] ; PIN_AJ10 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[7] ; PIN_AG10 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[8] ; PIN_AL9 ; QSF Assignment ; -; Location ; ; ; DDR4B_DQ[9] ; PIN_AH9 ; QSF Assignment ; -; Location ; ; ; DDR4B_ODT ; PIN_AL12 ; QSF Assignment ; -; Location ; ; ; DDR4B_PAR ; PIN_AM12 ; QSF Assignment ; -; Location ; ; ; DDR4B_REFCLK_p ; PIN_AU7 ; QSF Assignment ; -; Location ; ; ; DDR4B_RESET_n ; PIN_AH14 ; QSF Assignment ; -; Location ; ; ; DDR4B_RZQ ; PIN_AW8 ; QSF Assignment ; -; Location ; ; ; DDR4H_BG[1] ; PIN_W26 ; QSF Assignment ; -; Location ; ; ; DP_AUX_SEL ; PIN_AC28 ; QSF Assignment ; -; Location ; ; ; DP_AUX_p ; PIN_AM22 ; QSF Assignment ; -; Location ; ; ; DP_DX_SEL ; PIN_AB27 ; QSF Assignment ; -; Location ; ; ; DP_REFCLK_p ; PIN_AM31 ; QSF Assignment ; -; Location ; ; ; DP_RX_p[0] ; PIN_AV35 ; QSF Assignment ; -; Location ; ; ; DP_RX_p[1] ; PIN_AT35 ; QSF Assignment ; -; Location ; ; ; DP_RX_p[2] ; PIN_AN33 ; QSF Assignment ; -; Location ; ; ; DP_RX_p[3] ; PIN_AP35 ; QSF Assignment ; -; Location ; ; ; DP_TX_p[0] ; PIN_AW37 ; QSF Assignment ; -; Location ; ; ; DP_TX_p[1] ; PIN_AV39 ; QSF Assignment ; -; Location ; ; ; DP_TX_p[2] ; PIN_AU37 ; QSF Assignment ; -; Location ; ; ; DP_TX_p[3] ; PIN_AT39 ; QSF Assignment ; -; Location ; ; ; HDMI_REFCLK_p ; PIN_V31 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_5V_n ; PIN_C29 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_CEC ; PIN_AP29 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_CLK_p ; PIN_Y31 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_D_p[0] ; PIN_Y35 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_D_p[1] ; PIN_W37 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_D_p[2] ; PIN_W33 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_HPD ; PIN_AG27 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_SCL ; PIN_V7 ; QSF Assignment ; -; Location ; ; ; HDMI_RX_SDA ; PIN_T2 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_CEC ; PIN_AK26 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_CLK_p ; PIN_V39 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_D_p[0] ; PIN_U37 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_D_p[1] ; PIN_T39 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_D_p[2] ; PIN_R37 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_HPD ; PIN_AF28 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_SCL ; PIN_A25 ; QSF Assignment ; -; Location ; ; ; HDMI_TX_SDA ; PIN_B25 ; QSF Assignment ; -; Location ; ; ; HPS_CLK_25 ; PIN_E22 ; QSF Assignment ; -; Location ; ; ; HPS_DIO[6] ; PIN_H22 ; QSF Assignment ; -; Location ; ; ; HPS_DIO[7] ; PIN_H19 ; QSF Assignment ; -; Location ; ; ; HPS_RESET_n ; PIN_K21 ; QSF Assignment ; -; Location ; ; ; HPS_WARM_RST_n ; PIN_J21 ; QSF Assignment ; -; Location ; ; ; OB_PCIE_REFCLK_p ; PIN_AK31 ; QSF Assignment ; -; Location ; ; ; PCIE_PERST_n ; PIN_AW20 ; QSF Assignment ; -; Location ; ; ; PCIE_REFCLK_p ; PIN_AH31 ; QSF Assignment ; -; Location ; ; ; PCIE_RX_p[0] ; PIN_AL33 ; QSF Assignment ; -; Location ; ; ; PCIE_RX_p[1] ; PIN_AM35 ; QSF Assignment ; -; Location ; ; ; PCIE_RX_p[2] ; PIN_AJ33 ; QSF Assignment ; -; Location ; ; ; PCIE_RX_p[3] ; PIN_AK35 ; QSF Assignment ; -; Location ; ; ; PCIE_TX_p[0] ; PIN_AR37 ; QSF Assignment ; -; Location ; ; ; PCIE_TX_p[1] ; PIN_AP39 ; QSF Assignment ; -; Location ; ; ; PCIE_TX_p[2] ; PIN_AN37 ; QSF Assignment ; -; Location ; ; ; PCIE_TX_p[3] ; PIN_AM39 ; QSF Assignment ; -; Location ; ; ; PCIE_WAKE_n ; PIN_AL19 ; QSF Assignment ; -; Location ; ; ; RX_SENSE_n ; PIN_AC26 ; QSF Assignment ; -; Location ; ; ; RX_SENSE_p ; PIN_AC27 ; QSF Assignment ; -; Location ; ; ; SATA_DEVICE_REFCLK_p ; PIN_M31 ; QSF Assignment ; -; Location ; ; ; SATA_DEVICE_RX_p[0] ; PIN_D35 ; QSF Assignment ; -; Location ; ; ; SATA_DEVICE_RX_p[1] ; PIN_B35 ; QSF Assignment ; -; Location ; ; ; SATA_DEVICE_TX_p[0] ; PIN_B39 ; QSF Assignment ; -; Location ; ; ; SATA_DEVICE_TX_p[1] ; PIN_A37 ; QSF Assignment ; -; Location ; ; ; SATA_HOST_REFCLK_p ; PIN_AF31 ; QSF Assignment ; -; Location ; ; ; SATA_HOST_RX_p[0] ; PIN_AE33 ; QSF Assignment ; -; Location ; ; ; SATA_HOST_RX_p[1] ; PIN_AF35 ; QSF Assignment ; -; Location ; ; ; SATA_HOST_TX_p[0] ; PIN_AJ37 ; QSF Assignment ; -; Location ; ; ; SATA_HOST_TX_p[1] ; PIN_AH39 ; QSF Assignment ; -; Location ; ; ; SFPA_LOS ; PIN_AN6 ; QSF Assignment ; -; Location ; ; ; SFPA_MOD0_PRSNT_n ; PIN_AU4 ; QSF Assignment ; -; Location ; ; ; SFPA_MOD1_SCL ; PIN_AW6 ; QSF Assignment ; -; Location ; ; ; SFPA_MOD2_SDA ; PIN_AW5 ; QSF Assignment ; -; Location ; ; ; SFPA_RATESEL[0] ; PIN_AM19 ; QSF Assignment ; -; Location ; ; ; SFPA_RATESEL[1] ; PIN_AN17 ; QSF Assignment ; -; Location ; ; ; SFPA_RX_p ; PIN_AD35 ; QSF Assignment ; -; Location ; ; ; SFPA_TXDISABLE ; PIN_AV6 ; QSF Assignment ; -; Location ; ; ; SFPA_TXFAULT ; PIN_AP3 ; QSF Assignment ; -; Location ; ; ; SFPA_TX_p ; PIN_AG37 ; QSF Assignment ; -; Location ; ; ; SFPB_LOS ; PIN_AN12 ; QSF Assignment ; -; Location ; ; ; SFPB_MOD0_PRSNT_n ; PIN_AT5 ; QSF Assignment ; -; Location ; ; ; SFPB_MOD1_SCL ; PIN_AW4 ; QSF Assignment ; -; Location ; ; ; SFPB_MOD2_SDA ; PIN_AV4 ; QSF Assignment ; -; Location ; ; ; SFPB_RATESEL[0] ; PIN_AR18 ; QSF Assignment ; -; Location ; ; ; SFPB_RATESEL[1] ; PIN_AP18 ; QSF Assignment ; -; Location ; ; ; SFPB_RX_p ; PIN_AC37 ; QSF Assignment ; -; Location ; ; ; SFPB_TXDISABLE ; PIN_AU5 ; QSF Assignment ; -; Location ; ; ; SFPB_TXFAULT ; PIN_AE10 ; QSF Assignment ; -; Location ; ; ; SFPB_TX_p ; PIN_AF39 ; QSF Assignment ; -; Location ; ; ; SFPC_LOS ; PIN_AN28 ; QSF Assignment ; -; Location ; ; ; SFPC_MOD0_PRSNT_n ; PIN_B27 ; QSF Assignment ; -; Location ; ; ; SFPC_MOD1_SCL ; PIN_AV3 ; QSF Assignment ; -; Location ; ; ; SFPC_MOD2_SDA ; PIN_AW3 ; QSF Assignment ; -; Location ; ; ; SFPC_RATESEL[0] ; PIN_AK18 ; QSF Assignment ; -; Location ; ; ; SFPC_RATESEL[1] ; PIN_AR17 ; QSF Assignment ; -; Location ; ; ; SFPC_RX_p ; PIN_AC33 ; QSF Assignment ; -; Location ; ; ; SFPC_TXDISABLE ; PIN_AP30 ; QSF Assignment ; -; Location ; ; ; SFPC_TXFAULT ; PIN_AP28 ; QSF Assignment ; -; Location ; ; ; SFPC_TX_p ; PIN_AE37 ; QSF Assignment ; -; Location ; ; ; SFPD_LOS ; PIN_D26 ; QSF Assignment ; -; Location ; ; ; SFPD_MOD0_PRSNT_n ; PIN_AL28 ; QSF Assignment ; -; Location ; ; ; SFPD_MOD1_SCL ; PIN_AV2 ; QSF Assignment ; -; Location ; ; ; SFPD_MOD2_SDA ; PIN_AV1 ; QSF Assignment ; -; Location ; ; ; SFPD_RATESEL[0] ; PIN_AH18 ; QSF Assignment ; -; Location ; ; ; SFPD_RATESEL[1] ; PIN_AW19 ; QSF Assignment ; -; Location ; ; ; SFPD_RX_p ; PIN_AB35 ; QSF Assignment ; -; Location ; ; ; SFPD_TXDISABLE ; PIN_AR28 ; QSF Assignment ; -; Location ; ; ; SFPD_TXFAULT ; PIN_AP21 ; QSF Assignment ; -; Location ; ; ; SFPD_TX_p ; PIN_AD39 ; QSF Assignment ; -; Location ; ; ; SFP_REFCLK_p ; PIN_AD31 ; QSF Assignment ; -; Location ; ; ; SINK_DP_HPD ; PIN_AD28 ; QSF Assignment ; -; Location ; ; ; TYPEC_5V_EN ; PIN_AT15 ; QSF Assignment ; -; Location ; ; ; TYPEC_PD_SCL ; PIN_AF27 ; QSF Assignment ; -; Location ; ; ; TYPEC_PD_SDA ; PIN_AE26 ; QSF Assignment ; -; Location ; ; ; TYPEC_PD_SLAVE_SCL ; PIN_AG25 ; QSF Assignment ; -; Location ; ; ; TYPEC_PD_SLAVE_SDA ; PIN_AH28 ; QSF Assignment ; -; Location ; ; ; USB20_OE_n ; PIN_A24 ; QSF Assignment ; -; Location ; ; ; USB20_SW ; PIN_C27 ; QSF Assignment ; -; Location ; ; ; USBDP_SW_CNF[0] ; PIN_AA27 ; QSF Assignment ; -; Location ; ; ; USBDP_SW_CNF[1] ; PIN_AB26 ; QSF Assignment ; -; Location ; ; ; USBDP_SW_CNF[2] ; PIN_AB25 ; QSF Assignment ; -; Location ; ; ; USB_HOST_DEV_OE_n ; PIN_AE27 ; QSF Assignment ; -; Location ; ; ; USB_HOST_DEV_SEL_n ; PIN_AD26 ; QSF Assignment ; -; Location ; ; ; USB_REFCLK_p ; PIN_AB31 ; QSF Assignment ; -; Location ; ; ; USB_RX_p ; PIN_AA37 ; QSF Assignment ; -; Location ; ; ; USB_SSFX3_PATH_OE_n ; PIN_AF25 ; QSF Assignment ; -; Location ; ; ; USB_SSFX3_PATH_SEL_n ; PIN_AE25 ; QSF Assignment ; -; Location ; ; ; USB_TX_p ; PIN_AB39 ; QSF Assignment ; -; I/O Standard ; a10s ; ; CLK_50_B2A ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; CLK_50_B3F ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDCSCL_RX ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDCSDA_RX ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_ACT_n ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_AC_R[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_AC_R[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_ALERT_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[10] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[11] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[12] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[13] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[14] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[15] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[16] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[2] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[3] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[4] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[5] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[6] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[7] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[8] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_A[9] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_BA[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_BA[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_BG[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_BG[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_CK ; DIFFERENTIAL 1.2-V SSTL ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_CKE ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_CK_n ; DIFFERENTIAL 1.2-V SSTL ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_CS_n ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_C[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_C[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[0] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[1] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[2] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[3] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[4] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[5] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[6] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[7] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DBI_n[8] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[0] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[1] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[2] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[3] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[4] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[5] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[6] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[7] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS[8] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[0] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[1] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[2] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[3] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[4] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[5] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[6] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[7] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQS_n[8] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[0] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[10] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[11] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[12] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[13] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[14] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[15] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[16] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[17] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[18] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[19] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[1] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[20] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[21] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[22] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[23] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[24] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[25] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[26] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[27] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[28] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[29] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[2] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[30] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[31] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[32] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[33] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[34] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[35] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[36] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[37] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[38] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[39] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[3] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[40] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[41] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[42] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[43] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[44] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[45] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[46] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[47] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[48] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[49] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[4] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[50] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[51] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[52] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[53] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[54] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[55] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[56] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[57] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[58] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[59] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[5] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[60] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[61] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[62] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[63] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[64] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[65] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[66] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[67] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[68] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[69] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[6] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[70] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[71] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[7] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[8] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_DQ[9] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_EVENT_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_ODT ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_PAR ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_RESET_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_RZQ ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4A_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_ACT_n ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_ALERT_n ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[10] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[11] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[12] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[13] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[14] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[15] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[16] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[2] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[3] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[4] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[5] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[6] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[7] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[8] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_A[9] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_BA[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_BA[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_BG[0] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_BG[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_CK ; DIFFERENTIAL 1.2-V SSTL ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_CKE ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_CK_n ; DIFFERENTIAL 1.2-V SSTL ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_CS_n ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DBI_n[0] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DBI_n[1] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DBI_n[2] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DBI_n[3] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS[0] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS[1] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS[2] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS[3] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS_n[0] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS_n[1] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS_n[2] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQS_n[3] ; DIFFERENTIAL 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[0] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[10] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[11] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[12] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[13] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[14] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[15] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[16] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[17] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[18] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[19] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[1] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[20] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[21] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[22] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[23] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[24] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[25] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[26] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[27] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[28] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[29] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[2] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[30] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[31] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[3] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[4] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[5] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[6] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[7] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[8] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_DQ[9] ; 1.2-V POD ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_ODT ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_PAR ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_RESET_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4B_RZQ ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DDR4H_BG[1] ; SSTL-12 ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_AUX_SEL ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_AUX_p ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_DX_SEL ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_RX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_RX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_RX_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_RX_p[3] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_TX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_TX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_TX_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; DP_TX_p[3] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_5V_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_CEC ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_CLK_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_D_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_D_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_D_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_HPD ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_RX_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_CEC ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_CLK_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_D_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_D_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_D_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_HPD ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_SCL ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HDMI_TX_SDA ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HPS_CLK_25 ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HPS_DIO[6] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HPS_DIO[7] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HPS_RESET_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; HPS_WARM_RST_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; OB_PCIE_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_PERST_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_RX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_RX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_RX_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_RX_p[3] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_TX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_TX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_TX_p[2] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_TX_p[3] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; PCIE_WAKE_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; RX_SENSE_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; RX_SENSE_p ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_DEVICE_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_DEVICE_RX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_DEVICE_RX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_DEVICE_TX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_DEVICE_TX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_HOST_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_HOST_RX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_HOST_RX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_HOST_TX_p[0] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SATA_HOST_TX_p[1] ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_LOS ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_MOD0_PRSNT_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_MOD1_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_MOD2_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_RATESEL[0] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_RATESEL[1] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_RX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_TXDISABLE ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_TXFAULT ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPA_TX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_LOS ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_MOD0_PRSNT_n ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_MOD1_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_MOD2_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_RATESEL[0] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_RATESEL[1] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_RX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_TXDISABLE ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_TXFAULT ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPB_TX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_LOS ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_MOD0_PRSNT_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_MOD1_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_MOD2_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_RATESEL[0] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_RATESEL[1] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_RX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_TXDISABLE ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_TXFAULT ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPC_TX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_LOS ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_MOD0_PRSNT_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_MOD1_SCL ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_MOD2_SDA ; 1.2 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_RATESEL[0] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_RATESEL[1] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_RX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_TXDISABLE ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_TXFAULT ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFPD_TX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; SFP_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; SINK_DP_HPD ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; TYPEC_5V_EN ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; TYPEC_PD_SCL ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; TYPEC_PD_SDA ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; TYPEC_PD_SLAVE_SCL ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; TYPEC_PD_SLAVE_SDA ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB20_OE_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB20_SW ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USBDP_SW_CNF[0] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USBDP_SW_CNF[1] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USBDP_SW_CNF[2] ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_HOST_DEV_OE_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_HOST_DEV_SEL_n ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_REFCLK_p ; LVDS ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_RX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_SSFX3_PATH_OEN ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_SSFX3_PATH_SELN ; 1.8 V ; QSF Assignment ; -; I/O Standard ; a10s ; ; USB_TX_p ; HSSI DIFFERENTIAL I/O ; QSF Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[10] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[11] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[12] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[13] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[14] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[15] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[16] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[1] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[2] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[3] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[4] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[5] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[6] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[7] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[8] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_a[9] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_act_n[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_alert_n[0] ; 1.2-V ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_ba[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_ba[1] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_bg[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_ck[0] ; DIFFERENTIAL 1.2-V SSTL ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_ck_n[0] ; DIFFERENTIAL 1.2-V SSTL ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_cke[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_cs_n[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dbi_n[0] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dbi_n[1] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dbi_n[2] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dbi_n[3] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[0] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[10] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[11] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[12] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[13] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[14] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[15] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[16] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[17] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[18] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[19] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[1] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[20] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[21] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[22] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[23] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[24] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[25] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[26] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[27] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[28] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[29] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[2] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[30] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[31] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[3] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[4] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[5] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[6] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[7] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[8] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dq[9] ; 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs[0] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs[1] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs[2] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs[3] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs_n[0] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs_n[1] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs_n[2] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_dqs_n[3] ; DIFFERENTIAL 1.2-V POD ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_odt[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_par[0] ; SSTL-12 ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; mem_reset_n[0] ; 1.2-V ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; oct_rzqin ; 1.2-V ; Compiler or HDL Assignment ; -; I/O Standard ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; ; pll_ref_clk ; LVDS ; Compiler or HDL Assignment ; -+--------------+-------------------------------------------+--------------+----------------------+-------------------------+----------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+--------------------------------------+----------------------+----------------------------+--------------------------+ -; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; -+--------------------------------------+----------------------+----------------------------+--------------------------+ -; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 20723 ) ; 0.00 % ( 0 / 20723 ) ; 0.00 % ( 0 / 20723 ) ; -; -- Achieved ; 0.00 % ( 0 / 20723 ) ; 0.00 % ( 0 / 20723 ) ; 0.00 % ( 0 / 20723 ) ; -; ; ; ; ; -; Number of Tiles locked to High-Speed ; 0 ; ; ; -+--------------------------------------+----------------------+----------------------------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+------------------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+------------------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ; -+------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; -+------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 20452 ) ; N/A ; Source File ; N/A ; ; -; sld_hub:auto_hub ; 0.00 % ( 0 / 271 ) ; N/A ; Post-Synthesis ; N/A ; ; -+------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.pin. - - -+----------------------------------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+-------------------------------------------------------------+------------------------+-------+ -; Resource ; Usage ; % ; -+-------------------------------------------------------------+------------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 5,726 / 251,680 ; 2 % ; -; ALMs needed [=A-B+C] ; 5,726 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 7,226 / 251,680 ; 3 % ; -; [a] ALMs used for LUT logic and registers ; 1,851 ; ; -; [b] ALMs used for LUT logic ; 2,512 ; ; -; [c] ALMs used for registers ; 2,863 ; ; -; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; -; [B] Estimate of ALMs recoverable by dense packing ; 1,599 / 251,680 ; < 1 % ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 99 / 251,680 ; < 1 % ; -; [a] Due to location constrained logic ; 0 ; ; -; [b] Due to LAB-wide signal conflicts ; 81 ; ; -; [c] Due to LAB input limits ; 18 ; ; -; [d] Due to virtual I/Os ; 0 ; ; -; ; ; ; -; Difficulty packing design ; Low ; ; -; ; ; ; -; Total LABs: partially or completely used ; 1,019 / 25,168 ; 4 % ; -; -- Logic LABs ; 1,019 ; ; -; -- Memory LABs (up to half of total LABs) ; 0 ; ; -; ; ; ; -; Combinational ALUT usage for logic ; 7,134 ; ; -; -- 7 input functions ; 86 ; ; -; -- 6 input functions ; 1,613 ; ; -; -- 5 input functions ; 1,021 ; ; -; -- 4 input functions ; 1,096 ; ; -; -- <=3 input functions ; 3,318 ; ; -; ; ; ; -; Dedicated logic registers ; 10,270 ; ; -; -- By type: ; ; ; -; -- Primary logic registers ; 9,426 / 503,360 ; 2 % ; -; -- Secondary logic registers ; 844 / 503,360 ; < 1 % ; -; -- By function: ; ; ; -; -- Design implementation registers ; 10,063 ; ; -; -- Routing optimization registers ; 207 ; ; -; ; ; ; -; Virtual pins ; 0 ; ; -; I/O pins ; 439 / 864 ; 51 % ; -; -- Clock pins ; 22 / 42 ; 52 % ; -; -- Dedicated input pins ; 24 / 83 ; 29 % ; -; ; ; ; -; Hard processor system peripheral utilization ; ; ; -; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ; -; -- Clock resets ; 1 / 1 ( 100 % ) ; ; -; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; -; -- S2F AXI ; 1 / 1 ( 100 % ) ; ; -; -- F2S AXI ; 1 / 1 ( 100 % ) ; ; -; -- AXI Lightweight ; 1 / 1 ( 100 % ) ; ; -; -- SDRAM ; 1 / 1 ( 100 % ) ; ; -; -- Interrupts ; 1 / 1 ( 100 % ) ; ; -; -- JTAG ; 0 / 1 ( 0 % ) ; ; -; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; -; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; -; -- STM event ; 1 / 1 ( 100 % ) ; ; -; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; -; -- DMA ; 0 / 1 ( 0 % ) ; ; -; -- EMAC ; 1 / 3 ( 33 % ) ; ; -; -- I2C ; 1 / 5 ( 20 % ) ; ; -; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; -; -- QSPI ; 0 / 1 ( 0 % ) ; ; -; -- SDMMC ; 1 / 1 ( 100 % ) ; ; -; -- SPI Master ; 0 / 2 ( 0 % ) ; ; -; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; -; -- UART ; 1 / 2 ( 50 % ) ; ; -; -- USB ; 1 / 2 ( 50 % ) ; ; -; ; ; ; -; M20K blocks ; 134 / 2,131 ; 6 % ; -; Total MLAB memory bits ; 0 ; ; -; Total block memory bits ; 2,099,384 / 43,642,880 ; 5 % ; -; Total block memory implementation bits ; 2,744,320 / 43,642,880 ; 6 % ; -; ; ; ; -; Total DSP Blocks ; 0 / 1,687 ; 0 % ; -; -- Total Fixed Point DSP Blocks ; 0 ; ; -; -- Total Floating Point DSP Blocks ; 0 ; ; -; ; ; ; -; IOPLLs ; 2 / 16 ; 13 % ; -; FPLLs ; 0 / 16 ; 0 % ; -; Global signals ; 3 ; ; -; -- Global clocks ; 3 / 32 ; 9 % ; -; -- Regional clocks ; 0 / 16 ; 0 % ; -; -- Periphery clocks ; 0 / 288 ; 0 % ; -; JTAGs ; 1 / 1 ; 100 % ; -; ASMI blocks ; 0 / 1 ; 0 % ; -; CRC blocks ; 0 / 1 ; 0 % ; -; Remote update blocks ; 0 / 1 ; 0 % ; -; Oscillator blocks ; 0 / 1 ; 0 % ; -; PCIe Hard IPs ; 0 / 2 ; 0 % ; -; HSSI RX PCSs ; 0 / 36 ; 0 % ; -; HSSI PMA RX DESERs ; 0 / 36 ; 0 % ; -; HSSI TX PCSs ; 0 / 36 ; 0 % ; -; HSSI PMA TX SERs ; 0 / 36 ; 0 % ; -; HSSI CDR PLL ; 10 / 36 ; 28 % ; -; -- CDR PLLs for Unused RX Clock Workaround ; 10 / 36 ; 28 % ; -; HSSI ATX PLL ; 0 / 12 ; 0 % ; -; Impedance control blocks ; 1 / 14 ; 7 % ; -; Average interconnect usage (total/H/V) ; 1.1% / 1.0% / 1.3% ; ; -; Peak interconnect usage (total/H/V) ; 20.8% / 18.7% / 24.0% ; ; -; ; ; ; -; Programmable power technology high-speed tiles ; 436 / 13,367 ; 3 % ; -; Programmable power technology low-power tiles ; 12,931 / 13,367 ; 97 % ; -; -- low-power tiles that are used by the design ; 1,509 / 12,931 ; 12 % ; -; -- unused tiles (low-power) ; 11,422 / 12,931 ; 88 % ; -; ; ; ; -; Programmable power technology high-speed LAB tiles ; 301 / 9,417 ; 3 % ; -; Programmable power technology low-power LAB tiles ; 9,116 / 9,417 ; 97 % ; -; -- low-power LAB tiles that are used by the design ; 1,445 / 9,116 ; 16 % ; -; -- unused LAB tiles (low-power) ; 7,671 / 9,116 ; 84 % ; -; ; ; ; -; Maximum fan-out ; 8654 ; ; -; Highest non-global fan-out ; 2860 ; ; -; Total fan-out ; 76472 ; ; -; Average fan-out ; 3.65 ; ; -+-------------------------------------------------------------+------------------------+-------+ - - -+----------------------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+-------------------------------------------------------------+-------------------------+------------------------+ -; Statistic ; Top ; sld_hub:auto_hub ; -+-------------------------------------------------------------+-------------------------+------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 5628 / 251680 ( 2 % ) ; 98 / 251680 ( < 1 % ) ; -; ALMs needed [=A-B+C] ; 5628 ; 98 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 7116 / 251680 ( 3 % ) ; 110 / 251680 ( < 1 % ) ; -; [a] ALMs used for LUT logic and registers ; 1807 ; 44 ; -; [b] ALMs used for LUT logic ; 2457 ; 55 ; -; [c] ALMs used for registers ; 2852 ; 11 ; -; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 1587 / 251680 ( < 1 % ) ; 13 / 251680 ( < 1 % ) ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 99 / 251680 ( < 1 % ) ; 1 / 251680 ( < 1 % ) ; -; [a] Due to location constrained logic ; 0 ; 0 ; -; [b] Due to LAB-wide signal conflicts ; 81 ; 1 ; -; [c] Due to LAB input limits ; 18 ; 0 ; -; [d] Due to virtual I/Os ; 0 ; 0 ; -; ; ; ; -; Difficulty packing design ; Low ; Low ; -; ; ; ; -; Total LABs: partially or completely used ; 1005 / 25168 ( 4 % ) ; 15 / 25168 ( < 1 % ) ; -; -- Logic LABs ; 1005 ; 15 ; -; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; -; ; ; ; -; Combinational ALUT usage for logic ; 6974 ; 160 ; -; -- 7 input functions ; 82 ; 4 ; -; -- 6 input functions ; 1580 ; 33 ; -; -- 5 input functions ; 996 ; 25 ; -; -- 4 input functions ; 1074 ; 22 ; -; -- <=3 input functions ; 3242 ; 76 ; -; Combinational ALUT usage for route-throughs ; 2016 ; 0 ; -; Memory ALUT usage ; 0 ; 0 ; -; -- 64-address deep ; 0 ; 0 ; -; -- 32-address deep ; 0 ; 0 ; -; ; ; ; -; Dedicated logic registers ; 0 ; 0 ; -; -- By type: ; ; ; -; -- Primary logic registers ; 9318 / 503360 ( 2 % ) ; 108 / 503360 ( < 1 % ) ; -; -- Secondary logic registers ; 837 / 503360 ( < 1 % ) ; 7 / 503360 ( < 1 % ) ; -; -- By function: ; ; ; -; -- Design implementation registers ; 9952 ; 111 ; -; -- Routing optimization registers ; 203 ; 4 ; -; ; ; ; -; ; ; ; -; Virtual pins ; 0 ; 0 ; -; I/O pins ; 439 ; 0 ; -; I/O registers ; 0 ; 0 ; -; Total block memory bits ; 2099384 ; 0 ; -; Total block memory implementation bits ; 2744320 ; 0 ; -; EC ; 230 / 85240 ( < 1 % ) ; 0 / 85240 ( 0 % ) ; -; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; M20K block ; 134 / 2131 ( 6 % ) ; 0 / 2131 ( 0 % ) ; -; Clock enable block ; 3 / 792 ( < 1 % ) ; 0 / 792 ( 0 % ) ; -; Impedance control block ; 1 / 14 ( 7 % ) ; 0 / 14 ( 0 % ) ; -; Impedance logic block ; 40 / 336 ( 11 % ) ; 0 / 336 ( 0 % ) ; -; PSEUDO DIFF OUT ; 5 / 768 ( < 1 % ) ; 0 / 768 ( 0 % ) ; -; HPS EMAC peripheral ; 1 / 3 ( 33 % ) ; 0 / 3 ( 0 % ) ; -; HPS GPIO peripheral ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS I2C peripheral ; 1 / 5 ( 20 % ) ; 0 / 5 ( 0 % ) ; -; HPS SDMMC peripheral ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS UART peripheral ; 1 / 2 ( 50 % ) ; 0 / 2 ( 0 % ) ; -; HPS USB peripheral ; 1 / 2 ( 50 % ) ; 0 / 2 ( 0 % ) ; -; HPS DBG APB interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; I/O lane circuitry ; 8 / 64 ( 12 % ) ; 0 / 64 ( 0 % ) ; -; IOPLL ; 2 / 16 ( 12 % ) ; 0 / 16 ( 0 % ) ; -; I/O tile control logic ; 2 / 16 ( 12 % ) ; 0 / 16 ( 0 % ) ; -; I/O reference clock tree ; 2 / 16 ( 12 % ) ; 0 / 16 ( 0 % ) ; -; I/O AUX ; 1 / 2 ( 50 % ) ; 0 / 2 ( 0 % ) ; -; HPS Interface DDR ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS boot from FPGA interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS clock resets interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; FPGA-to-HPS interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS FPGA-to-SDRAM interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS-to-FPGA interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS-to-FPGA lightweight interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS interrupts interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HPS STM event interface ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; HSSI PMA AUX ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; -; HSSI PMA CDR REFCLK SELECT MUX ; 10 / 36 ( 27 % ) ; 0 / 36 ( 0 % ) ; -; HSSI PMA RX BUF ; 10 / 36 ( 27 % ) ; 0 / 36 ( 0 % ) ; -; HSSI PMA TX BUF ; 10 / 36 ( 27 % ) ; 0 / 36 ( 0 % ) ; -; HSSI REFCLK DIVIDER ; 3 / 12 ( 25 % ) ; 0 / 12 ( 0 % ) ; -; CMU/CDR PLL ; 10 / 36 ( 27 % ) ; 0 / 36 ( 0 % ) ; -; HSSI PMA UC ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; -; ; ; ; -; Connections ; ; ; -; -- Input Connections ; 1736 ; 182 ; -; -- Registered Input Connections ; 728 ; 124 ; -; -- Output Connections ; 1208 ; 710 ; -; -- Registered Output Connections ; 0 ; 705 ; -; ; ; ; -; Internal Connections ; ; ; -; -- Total Connections ; 82662 ; 1735 ; -; -- Registered Connections ; 35806 ; 1399 ; -; ; ; ; -; External Connections ; ; ; -; -- Top ; 2052 ; 892 ; -; -- sld_hub:auto_hub ; 892 ; 0 ; -; ; ; ; -; Partition Interface ; ; ; -; -- Input Ports ; 140 ; 120 ; -; -- Output Ports ; 87 ; 137 ; -; -- Bidir Ports ; 297 ; 0 ; -; ; ; ; -; Registered Ports ; ; ; -; -- Registered Input Ports ; 0 ; 3 ; -; -- Registered Output Ports ; 0 ; 86 ; -; ; ; ; -; Port Connectivity ; ; ; -; -- Input Ports driven by GND ; 0 ; 17 ; -; -- Output Ports driven by GND ; 0 ; 31 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 91 ; -; -- Output Ports with no Source ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 96 ; -; -- Output Ports with no Fanout ; 0 ; 93 ; -+-------------------------------------------------------------+-------------------------+------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+----------+--------------+-----------------------------+--------------+---------------------------+----------------------+-----------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; -+------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+----------+--------------+-----------------------------+--------------+---------------------------+----------------------+-----------+ -; CLKUSR_100 ; AJ18 ; 2A ; 78 ; 7 ; 31 ; 8654 ; 0 ; yes ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; CLK_50_B2H ; AR23 ; 2H ; 78 ; 88 ; 46 ; 815 ; 0 ; yes ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; CLK_50_B3H ; D11 ; 3H ; 148 ; 196 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; CPU_RESET_n ; AN18 ; 2A ; 78 ; 6 ; 16 ; 7 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; DDR4H_ALERT_n ; A23 ; 2J ; 78 ; 142 ; 46 ; 1 ; 0 ; no ; no ; no ; Off ; SSTL-12 ; Off ; -- ; User ; no ; -; DDR4H_REFCLK_p ; M27 ; 2K ; 78 ; 169 ; 46 ; 2 ; 0 ; no ; no ; no ; Off ; LVDS ; Differential ; -- ; User ; no ; -; DDR4H_REFCLK_p(n) ; M26 ; 2K ; 78 ; 170 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; Differential ; -- ; Fitter ; no ; -; DDR4H_RZQ ; J26 ; 2K ; 78 ; 171 ; 46 ; 1 ; 0 ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; -; ETH_INT_n ; AU19 ; 2G ; 78 ; 65 ; 31 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; ETH_RX_p ; AM20 ; 2G ; 78 ; 69 ; 31 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; -; ETH_RX_p(n) ; AL20 ; 2G ; 78 ; 70 ; 31 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; Off ; -- ; Fitter ; no ; -; FAN_ALERT_n ; E25 ; 2L ; 78 ; 201 ; 61 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; FMC_CLK_M2C_n[0] ; L5 ; 3F ; 148 ; 143 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; FMC_CLK_M2C_n[1] ; AW15 ; 2A ; 78 ; 7 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; FMC_CLK_M2C_p[0] ; K5 ; 3F ; 148 ; 142 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; FMC_CLK_M2C_p[1] ; AW14 ; 2A ; 78 ; 6 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; FMC_DP_M2C_p[0] ; P35 ; 1G ; 0 ; 115 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[0](n) ; P34 ; 1G ; 0 ; 115 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[1] ; R33 ; 1G ; 0 ; 116 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[1](n) ; R32 ; 1G ; 0 ; 116 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[2] ; M35 ; 1G ; 0 ; 117 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[2](n) ; M34 ; 1G ; 0 ; 117 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[3] ; N33 ; 1G ; 0 ; 119 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[3](n) ; N32 ; 1G ; 0 ; 119 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[4] ; K35 ; 1G ; 0 ; 120 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[4](n) ; K34 ; 1G ; 0 ; 120 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[5] ; L33 ; 1G ; 0 ; 121 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[5](n) ; L32 ; 1G ; 0 ; 121 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[6] ; H35 ; 1H ; 0 ; 142 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[6](n) ; H34 ; 1H ; 0 ; 142 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[7] ; J33 ; 1H ; 0 ; 143 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[7](n) ; J32 ; 1H ; 0 ; 143 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[8] ; F35 ; 1H ; 0 ; 144 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[8](n) ; F34 ; 1H ; 0 ; 144 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_DP_M2C_p[9] ; G33 ; 1H ; 0 ; 146 ; 111 ; 1 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; User ; no ; -; FMC_DP_M2C_p[9](n) ; G32 ; 1H ; 0 ; 146 ; 109 ; 0 ; 0 ; no ; no ; no ; Off ; High Speed Differential I/O ; r_r1 ; -- ; Fitter ; no ; -; FMC_GBTCLK_M2C_p[0] ; P31 ; 1G ; 0 ; 122 ; 107 ; 1 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; User ; no ; -; FMC_GBTCLK_M2C_p[0](n) ; P30 ; 1G ; 0 ; 122 ; 105 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; Fitter ; no ; -; FMC_GBTCLK_M2C_p[1] ; K31 ; 1H ; 0 ; 149 ; 107 ; 1 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; User ; no ; -; FMC_GBTCLK_M2C_p[1](n) ; K30 ; 1H ; 0 ; 149 ; 105 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; Fitter ; no ; -; FMC_REFCLK_p ; T31 ; 1G ; 0 ; 118 ; 107 ; 1 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; User ; no ; -; FMC_REFCLK_p(n) ; T30 ; 1G ; 0 ; 118 ; 105 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; tristate_off ; -- ; Fitter ; no ; -; FMC_RZQ ; H9 ; 3G ; 148 ; 171 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_CLK ; K22 ; 2L ; 78 ; 198 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_DATA[0] ; H23 ; 2L ; 78 ; 202 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_DATA[1] ; J23 ; 2L ; 78 ; 203 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_DATA[2] ; F24 ; 2L ; 78 ; 206 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_DATA[3] ; G24 ; 2L ; 78 ; 207 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_ENET_RX_DV ; L22 ; 2L ; 78 ; 199 ; 31 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_RXD ; L20 ; HPS ; 79 ; 188 ; 96 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_USB_CLKOUT ; L25 ; 2L ; 78 ; 196 ; 16 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_USB_DIR ; J25 ; 2L ; 78 ; 198 ; 16 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; HPS_USB_NXT ; H26 ; 2L ; 78 ; 201 ; 16 ; 1 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; KEY[0] ; AU15 ; 2A ; 78 ; 8 ; 46 ; 33 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; KEY[1] ; AT15 ; 2A ; 78 ; 9 ; 46 ; 33 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; PM_ALERT_n ; D25 ; 2L ; 78 ; 200 ; 61 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; SMA_CLKIN_p ; AJ21 ; 2G ; 78 ; 61 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; -; SMA_CLKIN_p(n) ; AH21 ; 2G ; 78 ; 62 ; 46 ; 0 ; 0 ; no ; no ; no ; Off ; LVDS ; Off ; -- ; Fitter ; no ; -; SW[0] ; AJ19 ; 2A ; 78 ; 10 ; 16 ; 3 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; SW[1] ; AV16 ; 2A ; 78 ; 17 ; 31 ; 3 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -; USBFX3_CTL11_A1 ; AU22 ; 2H ; 78 ; 90 ; 16 ; 0 ; 0 ; no ; no ; no ; Off ; 1.8 V ; Off ; -- ; User ; no ; -+------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+----------+--------------+-----------------------------+--------------+---------------------------+----------------------+-----------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+---------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-----------------------------+------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+---------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-----------------------------+------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; DDR4H_ACT_n ; Y25 ; 2K ; 78 ; 172 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[0] ; U27 ; 2K ; 78 ; 169 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[10] ; T25 ; 2K ; 78 ; 179 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[11] ; U25 ; 2K ; 78 ; 180 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[12] ; K26 ; 2K ; 78 ; 172 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[13] ; G29 ; 2K ; 78 ; 173 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[14] ; H28 ; 2K ; 78 ; 174 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[15] ; K28 ; 2K ; 78 ; 175 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[16] ; L28 ; 2K ; 78 ; 176 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[1] ; V27 ; 2K ; 78 ; 170 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[2] ; P28 ; 2K ; 78 ; 171 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[3] ; N27 ; 2K ; 78 ; 172 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[4] ; N26 ; 2K ; 78 ; 173 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[5] ; P26 ; 2K ; 78 ; 174 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[6] ; R26 ; 2K ; 78 ; 175 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[7] ; R25 ; 2K ; 78 ; 176 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[8] ; R28 ; 2K ; 78 ; 177 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_A[9] ; R27 ; 2K ; 78 ; 178 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_BA[0] ; H27 ; 2K ; 78 ; 178 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_BA[1] ; E32 ; 2K ; 78 ; 179 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_BG[0] ; E31 ; 2K ; 78 ; 180 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_CK ; U26 ; 2K ; 78 ; 177 ; 16 ; no ; no ; 1 ; no ; yes ; no ; Off ; Differential 1.2-V SSTL ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_CKE ; V28 ; 2K ; 78 ; 175 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_CK_n ; V26 ; 2K ; 78 ; 178 ; 16 ; no ; no ; 1 ; no ; yes ; no ; Off ; Differential 1.2-V SSTL ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_CS_n ; W25 ; 2K ; 78 ; 171 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_ODT ; Y28 ; 2K ; 78 ; 173 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_PAR ; T27 ; 2K ; 78 ; 180 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; SSTL-12 ; Default ; Series 40 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; no ; no ; User ; - ; - ; -; DDR4H_RESET_n ; Y26 ; 2K ; 78 ; 170 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.2 V ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; ETH_MDC ; AT19 ; 2G ; 78 ; 66 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; ETH_RST_n ; AK20 ; 2G ; 78 ; 63 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; ETH_TX_p ; AP19 ; 2G ; 78 ; 61 ; 31 ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 2 ; User ; - ; - ; -; ETH_TX_p(n) ; AN19 ; 2G ; 78 ; 62 ; 31 ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 2 ; Fitter ; - ; - ; -; FMC_DP_C2M_p[0] ; M39 ; 1G ; 0 ; 115 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[0](n) ; M38 ; 1G ; 0 ; 115 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[1] ; L37 ; 1G ; 0 ; 116 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[1](n) ; L36 ; 1G ; 0 ; 116 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[2] ; K39 ; 1G ; 0 ; 117 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[2](n) ; K38 ; 1G ; 0 ; 117 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[3] ; J37 ; 1G ; 0 ; 119 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[3](n) ; J36 ; 1G ; 0 ; 119 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[4] ; H39 ; 1G ; 0 ; 120 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[4](n) ; H38 ; 1G ; 0 ; 120 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[5] ; G37 ; 1G ; 0 ; 121 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[5](n) ; G36 ; 1G ; 0 ; 121 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[6] ; F39 ; 1H ; 0 ; 142 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[6](n) ; F38 ; 1H ; 0 ; 142 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[7] ; E37 ; 1H ; 0 ; 143 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[7](n) ; E36 ; 1H ; 0 ; 143 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[8] ; D39 ; 1H ; 0 ; 144 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[8](n) ; D38 ; 1H ; 0 ; 144 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; FMC_DP_C2M_p[9] ; C37 ; 1H ; 0 ; 146 ; 107 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; User ; - ; - ; -; FMC_DP_C2M_p[9](n) ; C36 ; 1H ; 0 ; 146 ; 105 ; no ; no ; no ; no ; no ; no ; Off ; High Speed Differential I/O ; Default ; OCT 100 Ohms ; -- ; no ; no ; Fitter ; - ; - ; -; HEX0_DP ; AU31 ; 2I ; 78 ; 122 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[0] ; AT32 ; 2I ; 78 ; 117 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[1] ; AR32 ; 2I ; 78 ; 118 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[2] ; AU32 ; 2I ; 78 ; 121 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[3] ; AU30 ; 2I ; 78 ; 115 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[4] ; AT30 ; 2I ; 78 ; 116 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[5] ; AU29 ; 2I ; 78 ; 120 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[6] ; AV29 ; 2I ; 78 ; 119 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_DP ; AR31 ; 2I ; 78 ; 123 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[0] ; AT28 ; 2I ; 78 ; 116 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[1] ; AT29 ; 2I ; 78 ; 115 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[2] ; AR30 ; 2I ; 78 ; 124 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[3] ; AM27 ; 2I ; 78 ; 125 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[4] ; AL27 ; 2I ; 78 ; 117 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[5] ; AK27 ; 2I ; 78 ; 118 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1_D[6] ; AM26 ; 2I ; 78 ; 126 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_GTX_CLK ; F25 ; 2L ; 78 ; 196 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_MDC ; D24 ; 2L ; 78 ; 207 ; 46 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_TX_DATA[0] ; H24 ; 2L ; 78 ; 200 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_TX_DATA[1] ; J24 ; 2L ; 78 ; 201 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_TX_DATA[2] ; M22 ; 2L ; 78 ; 204 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_TX_DATA[3] ; M21 ; 2L ; 78 ; 205 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_ENET_TX_EN ; G25 ; 2L ; 78 ; 197 ; 31 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_TXD ; J19 ; HPS ; 79 ; 175 ; 96 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HPS_USB_STP ; M25 ; 2L ; 78 ; 197 ; 16 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LED[0] ; C26 ; 2L ; 78 ; 207 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LED[1] ; B24 ; 2L ; 78 ; 205 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; SMA_CLKOUT_p ; AN21 ; 2G ; 78 ; 65 ; 46 ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 2 ; User ; - ; - ; -; SMA_CLKOUT_p(n) ; AM21 ; 2G ; 78 ; 66 ; 46 ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 2 ; Fitter ; - ; - ; -+---------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-----------------------------+------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+----------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+------------+----------+--------------+------------------------+------------------+----------------------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+----------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Slew Rate ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Input Termination ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+----------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+------------+----------+--------------+------------------------+------------------+----------------------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+----------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; CDCM6208_SCL ; AK21 ; 2G ; 78 ; 68 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; CDCM6208_SDA ; AK22 ; 2G ; 78 ; 67 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; DDR4H_DBI_n[0] ; H18 ; 2J ; 78 ; 153 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[59] (inverted) ; -; DDR4H_DBI_n[1] ; E18 ; 2J ; 78 ; 153 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[71] (inverted) ; -; DDR4H_DBI_n[2] ; D16 ; 2J ; 78 ; 153 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[83] (inverted) ; -; DDR4H_DBI_n[3] ; E20 ; 2J ; 78 ; 153 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[95] (inverted) ; -; DDR4H_DQS[0] ; A20 ; 2J ; 78 ; 146 ; 46 ; 2 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b|pdiff_out_oe (inverted) ; -; DDR4H_DQS[1] ; B17 ; 2J ; 78 ; 146 ; 31 ; 2 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b|pdiff_out_oe (inverted) ; -; DDR4H_DQS[2] ; L15 ; 2J ; 78 ; 146 ; 16 ; 2 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b|pdiff_out_oe (inverted) ; -; DDR4H_DQS[3] ; F18 ; 2J ; 78 ; 146 ; 61 ; 2 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b|pdiff_out_oe (inverted) ; -; DDR4H_DQS_n[0] ; B20 ; 2J ; 78 ; 147 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b|pdiff_out_oebar (inverted) ; -; DDR4H_DQS_n[1] ; C17 ; 2J ; 78 ; 147 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b|pdiff_out_oebar (inverted) ; -; DDR4H_DQS_n[2] ; M15 ; 2J ; 78 ; 147 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b|pdiff_out_oebar (inverted) ; -; DDR4H_DQS_n[3] ; F19 ; 2J ; 78 ; 147 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; Differential 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b|pdiff_out_oebar (inverted) ; -; DDR4H_DQ[0] ; C19 ; 2J ; 78 ; 150 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[56] (inverted) ; -; DDR4H_DQ[10] ; D18 ; 2J ; 78 ; 149 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[67] (inverted) ; -; DDR4H_DQ[11] ; E17 ; 2J ; 78 ; 152 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[70] (inverted) ; -; DDR4H_DQ[12] ; A17 ; 2J ; 78 ; 150 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[68] (inverted) ; -; DDR4H_DQ[13] ; A15 ; 2J ; 78 ; 144 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[62] (inverted) ; -; DDR4H_DQ[14] ; A18 ; 2J ; 78 ; 151 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[69] (inverted) ; -; DDR4H_DQ[15] ; K17 ; 2J ; 78 ; 143 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[61] (inverted) ; -; DDR4H_DQ[16] ; J16 ; 2J ; 78 ; 151 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[81] (inverted) ; -; DDR4H_DQ[17] ; G16 ; 2J ; 78 ; 144 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[74] (inverted) ; -; DDR4H_DQ[18] ; H17 ; 2J ; 78 ; 150 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[80] (inverted) ; -; DDR4H_DQ[19] ; H16 ; 2J ; 78 ; 145 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[75] (inverted) ; -; DDR4H_DQ[1] ; B21 ; 2J ; 78 ; 148 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[54] (inverted) ; -; DDR4H_DQ[20] ; J15 ; 2J ; 78 ; 148 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[78] (inverted) ; -; DDR4H_DQ[21] ; G15 ; 2J ; 78 ; 143 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[73] (inverted) ; -; DDR4H_DQ[22] ; K15 ; 2J ; 78 ; 149 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[79] (inverted) ; -; DDR4H_DQ[23] ; C16 ; 2J ; 78 ; 152 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[82] (inverted) ; -; DDR4H_DQ[24] ; F20 ; 2J ; 78 ; 150 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[92] (inverted) ; -; DDR4H_DQ[25] ; D21 ; 2J ; 78 ; 148 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[90] (inverted) ; -; DDR4H_DQ[26] ; F17 ; 2J ; 78 ; 144 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[86] (inverted) ; -; DDR4H_DQ[27] ; G20 ; 2J ; 78 ; 151 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[93] (inverted) ; -; DDR4H_DQ[28] ; E21 ; 2J ; 78 ; 149 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[91] (inverted) ; -; DDR4H_DQ[29] ; C22 ; 2J ; 78 ; 143 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[85] (inverted) ; -; DDR4H_DQ[2] ; C21 ; 2J ; 78 ; 149 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[55] (inverted) ; -; DDR4H_DQ[30] ; G17 ; 2J ; 78 ; 145 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[87] (inverted) ; -; DDR4H_DQ[31] ; D20 ; 2J ; 78 ; 152 ; 61 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[94] (inverted) ; -; DDR4H_DQ[3] ; A22 ; 2J ; 78 ; 143 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[49] (inverted) ; -; DDR4H_DQ[4] ; D19 ; 2J ; 78 ; 151 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[57] (inverted) ; -; DDR4H_DQ[5] ; B19 ; 2J ; 78 ; 145 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[51] (inverted) ; -; DDR4H_DQ[6] ; G19 ; 2J ; 78 ; 152 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[58] (inverted) ; -; DDR4H_DQ[7] ; A19 ; 2J ; 78 ; 144 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[50] (inverted) ; -; DDR4H_DQ[8] ; C18 ; 2J ; 78 ; 148 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[66] (inverted) ; -; DDR4H_DQ[9] ; B16 ; 2J ; 78 ; 145 ; 31 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2-V POD ; Default ; Parallel 60 Ohm with Calibration ; Series 48 Ohm with Calibration ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[63] (inverted) ; -; ETH_MDIO ; AJ20 ; 2G ; 78 ; 64 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_CLK2_BIDIR_n ; AV17 ; 2A ; 78 ; 15 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_CLK2_BIDIR_p ; AW18 ; 2A ; 78 ; 14 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_CLK3_BIDIR_n ; D1 ; 3F ; 148 ; 147 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_CLK3_BIDIR_p ; C1 ; 3F ; 148 ; 146 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_GA[0] ; E11 ; 3H ; 148 ; 197 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_GA[1] ; AL18 ; 2A ; 78 ; 12 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[0] ; L12 ; 3H ; 148 ; 203 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[10] ; E13 ; 3H ; 148 ; 205 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[11] ; H14 ; 3H ; 148 ; 207 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[12] ; B10 ; 3H ; 148 ; 205 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[13] ; H12 ; 3H ; 148 ; 205 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[14] ; B12 ; 3H ; 148 ; 207 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[15] ; A8 ; 3H ; 148 ; 197 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[16] ; B9 ; 3H ; 148 ; 199 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[17] ; C13 ; 3H ; 148 ; 201 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[18] ; C11 ; 3H ; 148 ; 203 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[19] ; N7 ; 3F ; 148 ; 145 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[1] ; N12 ; 3H ; 148 ; 207 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[20] ; G10 ; 3H ; 148 ; 207 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[21] ; D9 ; 3H ; 148 ; 203 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[22] ; D8 ; 3H ; 148 ; 201 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[23] ; H11 ; 3H ; 148 ; 199 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[2] ; E10 ; 3H ; 148 ; 197 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[3] ; F12 ; 3H ; 148 ; 199 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[4] ; J13 ; 3H ; 148 ; 201 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[5] ; K11 ; 3H ; 148 ; 201 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[6] ; P13 ; 3H ; 148 ; 197 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[7] ; L14 ; 3H ; 148 ; 205 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[8] ; K13 ; 3H ; 148 ; 203 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_n[9] ; F14 ; 3H ; 148 ; 199 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[0] ; K12 ; 3H ; 148 ; 202 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[10] ; D13 ; 3H ; 148 ; 204 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[11] ; G14 ; 3H ; 148 ; 206 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[12] ; A10 ; 3H ; 148 ; 204 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[13] ; G12 ; 3H ; 148 ; 204 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[14] ; A12 ; 3H ; 148 ; 206 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[15] ; A7 ; 3H ; 148 ; 196 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[16] ; A9 ; 3H ; 148 ; 198 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[17] ; C12 ; 3H ; 148 ; 200 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[18] ; B11 ; 3H ; 148 ; 202 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[19] ; M7 ; 3F ; 148 ; 144 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[1] ; M12 ; 3H ; 148 ; 206 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[20] ; F10 ; 3H ; 148 ; 206 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[21] ; C9 ; 3H ; 148 ; 202 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[22] ; C8 ; 3H ; 148 ; 200 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[23] ; G11 ; 3H ; 148 ; 198 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[2] ; D10 ; 3H ; 148 ; 196 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[3] ; E12 ; 3H ; 148 ; 198 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[4] ; H13 ; 3H ; 148 ; 200 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[5] ; J11 ; 3H ; 148 ; 200 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[6] ; N13 ; 3H ; 148 ; 196 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[7] ; L13 ; 3H ; 148 ; 204 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[8] ; J14 ; 3H ; 148 ; 202 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HA_p[9] ; F13 ; 3H ; 148 ; 198 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[0] ; E2 ; 3F ; 148 ; 151 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[10] ; AL17 ; 2A ; 78 ; 9 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[11] ; AH16 ; 2A ; 78 ; 15 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[12] ; AV13 ; 2A ; 78 ; 13 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[13] ; AU14 ; 2A ; 78 ; 7 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[14] ; AP15 ; 2A ; 78 ; 17 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[15] ; AK17 ; 2A ; 78 ; 13 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[16] ; AU17 ; 2A ; 78 ; 13 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[17] ; AT18 ; 2A ; 78 ; 11 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[18] ; AM16 ; 2A ; 78 ; 17 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[19] ; AR16 ; 2A ; 78 ; 11 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[1] ; H4 ; 3F ; 148 ; 145 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[20] ; AN16 ; 2A ; 78 ; 11 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[21] ; AV19 ; 2A ; 78 ; 9 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[2] ; P8 ; 3F ; 148 ; 147 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[3] ; J5 ; 3F ; 148 ; 153 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[4] ; H3 ; 3F ; 148 ; 147 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[5] ; H6 ; 3F ; 148 ; 151 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[6] ; E3 ; 3F ; 148 ; 149 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[7] ; B2 ; 3F ; 148 ; 143 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[8] ; C2 ; 3F ; 148 ; 149 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_n[9] ; AT14 ; 2A ; 78 ; 15 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[0] ; E1 ; 3F ; 148 ; 150 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[10] ; AM17 ; 2A ; 78 ; 8 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[11] ; AJ16 ; 2A ; 78 ; 14 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[12] ; AW13 ; 2A ; 78 ; 12 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[13] ; AV14 ; 2A ; 78 ; 6 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[14] ; AP14 ; 2A ; 78 ; 16 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[15] ; AK16 ; 2A ; 78 ; 12 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[16] ; AU16 ; 2A ; 78 ; 12 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[17] ; AT17 ; 2A ; 78 ; 10 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[18] ; AM15 ; 2A ; 78 ; 16 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[19] ; AR15 ; 2A ; 78 ; 10 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[1] ; G4 ; 3F ; 148 ; 144 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[20] ; AP16 ; 2A ; 78 ; 10 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[21] ; AV18 ; 2A ; 78 ; 8 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[2] ; N8 ; 3F ; 148 ; 146 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[3] ; J4 ; 3F ; 148 ; 152 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[4] ; H2 ; 3F ; 148 ; 146 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[5] ; G5 ; 3F ; 148 ; 150 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[6] ; D3 ; 3F ; 148 ; 148 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[7] ; A2 ; 3F ; 148 ; 142 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[8] ; B1 ; 3F ; 148 ; 148 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_HB_p[9] ; AT13 ; 2A ; 78 ; 14 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[0] ; A4 ; 3G ; 148 ; 180 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[10] ; F8 ; 3G ; 148 ; 178 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[11] ; C6 ; 3G ; 148 ; 172 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[12] ; B5 ; 3G ; 148 ; 180 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[13] ; D6 ; 3G ; 148 ; 176 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[14] ; C7 ; 3G ; 148 ; 178 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[15] ; E7 ; 3G ; 148 ; 170 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[16] ; F5 ; 3G ; 148 ; 174 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[17] ; G9 ; 3G ; 148 ; 174 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[18] ; L8 ; 3G ; 148 ; 170 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[19] ; P9 ; 3F ; 148 ; 153 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[1] ; C3 ; 3G ; 148 ; 176 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[20] ; G7 ; 3G ; 148 ; 172 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[21] ; D4 ; 3G ; 148 ; 174 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[22] ; U12 ; 3F ; 148 ; 145 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[23] ; V12 ; 3F ; 148 ; 143 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[24] ; R12 ; 3G ; 148 ; 174 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[25] ; G2 ; 3F ; 148 ; 145 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[26] ; T8 ; 3F ; 148 ; 151 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[27] ; T13 ; 3G ; 148 ; 172 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[28] ; K6 ; 3F ; 148 ; 153 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[29] ; H1 ; 3F ; 148 ; 143 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[2] ; T10 ; 3F ; 148 ; 147 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[30] ; L7 ; 3F ; 148 ; 151 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[31] ; R10 ; 3G ; 148 ; 170 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[32] ; N6 ; 3F ; 148 ; 149 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[33] ; P11 ; 3G ; 148 ; 180 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[3] ; M11 ; 3G ; 148 ; 178 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[4] ; U10 ; 3F ; 148 ; 149 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[5] ; K10 ; 3G ; 148 ; 178 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[6] ; J8 ; 3G ; 148 ; 176 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[7] ; L10 ; 3G ; 148 ; 180 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[8] ; N9 ; 3G ; 148 ; 176 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_n[9] ; H7 ; 3G ; 148 ; 170 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[0] ; A3 ; 3G ; 148 ; 179 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[10] ; E8 ; 3G ; 148 ; 177 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[11] ; B6 ; 3G ; 148 ; 171 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[12] ; A5 ; 3G ; 148 ; 179 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[13] ; D5 ; 3G ; 148 ; 175 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[14] ; B7 ; 3G ; 148 ; 177 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[15] ; E6 ; 3G ; 148 ; 169 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[16] ; E5 ; 3G ; 148 ; 173 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[17] ; F9 ; 3G ; 148 ; 173 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[18] ; K8 ; 3G ; 148 ; 169 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[19] ; R8 ; 3F ; 148 ; 152 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[1] ; B4 ; 3G ; 148 ; 175 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[20] ; F7 ; 3G ; 148 ; 171 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[21] ; C4 ; 3G ; 148 ; 173 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[22] ; U11 ; 3F ; 148 ; 144 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[23] ; V11 ; 3F ; 148 ; 142 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[24] ; R11 ; 3G ; 148 ; 173 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[25] ; F2 ; 3F ; 148 ; 144 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[26] ; R7 ; 3F ; 148 ; 150 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[27] ; T12 ; 3G ; 148 ; 171 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[28] ; J6 ; 3F ; 148 ; 152 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[29] ; G1 ; 3F ; 148 ; 142 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[2] ; T9 ; 3F ; 148 ; 146 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[30] ; K7 ; 3F ; 148 ; 150 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[31] ; P10 ; 3G ; 148 ; 169 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[32] ; M6 ; 3F ; 148 ; 148 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[33] ; N11 ; 3G ; 148 ; 179 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[3] ; M10 ; 3G ; 148 ; 177 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[4] ; U9 ; 3F ; 148 ; 148 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[5] ; J10 ; 3G ; 148 ; 177 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[6] ; H8 ; 3G ; 148 ; 175 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[7] ; L9 ; 3G ; 148 ; 179 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[8] ; M9 ; 3G ; 148 ; 175 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_LA_p[9] ; G6 ; 3G ; 148 ; 169 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_SCL ; J9 ; 3G ; 148 ; 172 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FMC_SDA ; F4 ; 3F ; 148 ; 153 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FPGA_I2C_SCL ; M1 ; 3E ; 148 ; 115 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; FPGA_I2C_SDA ; M4 ; 3E ; 148 ; 125 ; 31 ; 5 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.2 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|SDAO (inverted) ; -; HPS_DIO[0] ; J18 ; HPS ; 79 ; 190 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[5] (inverted) ; -; HPS_DIO[1] ; F22 ; HPS ; 79 ; 186 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[3] (inverted) ; -; HPS_DIO[2] ; K18 ; HPS ; 79 ; 185 ; 96 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; HPS_DIO[3] ; E23 ; HPS ; 79 ; 187 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[7] (inverted) ; -; HPS_DIO[4] ; G21 ; HPS ; 79 ; 181 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[9] (inverted) ; -; HPS_DIO[5] ; H21 ; HPS ; 79 ; 180 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[11] (inverted) ; -; HPS_ENET_MDIO ; C24 ; 2L ; 78 ; 206 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[1] (inverted) ; -; HPS_GPIO[0] ; D23 ; HPS ; 79 ; 178 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[31] (inverted) ; -; HPS_GPIO[1] ; C23 ; HPS ; 79 ; 184 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[33] (inverted) ; -; HPS_GPIO[2] ; F23 ; HPS ; 79 ; 177 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[35] (inverted) ; -; HPS_GPIO[3] ; G22 ; HPS ; 79 ; 182 ; 96 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[37] (inverted) ; -; HPS_I2C0_SCLK ; B30 ; 2L ; 78 ; 199 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[29] ; -; HPS_I2C0_SDAT ; A30 ; 2L ; 78 ; 198 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[28] ; -; HPS_KEY ; A29 ; 2L ; 78 ; 200 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[41] (inverted) ; -; HPS_LED ; D29 ; 2L ; 78 ; 197 ; 46 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[39] (inverted) ; -; HPS_USB_DATA[0] ; K25 ; 2L ; 78 ; 199 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[13] (inverted) ; -; HPS_USB_DATA[1] ; G26 ; 2L ; 78 ; 200 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[15] (inverted) ; -; HPS_USB_DATA[2] ; E27 ; 2L ; 78 ; 202 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[17] (inverted) ; -; HPS_USB_DATA[3] ; F27 ; 2L ; 78 ; 203 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[19] (inverted) ; -; HPS_USB_DATA[4] ; L24 ; 2L ; 78 ; 204 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[21] (inverted) ; -; HPS_USB_DATA[5] ; M24 ; 2L ; 78 ; 205 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[23] (inverted) ; -; HPS_USB_DATA[6] ; K23 ; 2L ; 78 ; 206 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[25] (inverted) ; -; HPS_USB_DATA[7] ; L23 ; 2L ; 78 ; 207 ; 16 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[27] (inverted) ; -; I2C_INT ; AH27 ; 2I ; 78 ; 118 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; MPU_INT ; E26 ; 2L ; 78 ; 199 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; REFCLK0_SCL ; AU20 ; 2G ; 78 ; 67 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; REFCLK0_SDA ; AT20 ; 2G ; 78 ; 68 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; REFCLK1_SCL ; AR22 ; 2G ; 78 ; 63 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; REFCLK1_SDA ; AR21 ; 2G ; 78 ; 64 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; SRC_DP_HPD ; AD25 ; 2I ; 78 ; 116 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL0_SLCS_n ; AV26 ; 2H ; 78 ; 95 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL10 ; AU24 ; 2H ; 78 ; 99 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL12_A0 ; AT23 ; 2H ; 78 ; 91 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL15_INT_n ; AW21 ; 2H ; 78 ; 96 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL1_SLWR_n ; AT22 ; 2H ; 78 ; 91 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL2_SLOE_n ; AT25 ; 2H ; 78 ; 90 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL3_SLRD_n ; AR27 ; 2H ; 78 ; 93 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL4_FLAGA ; AN22 ; 2G ; 78 ; 70 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL5_FLAGB ; AN23 ; 2H ; 78 ; 95 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL6 ; AL24 ; 2H ; 78 ; 99 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL7_PKTEND_n ; AL25 ; 2H ; 78 ; 96 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL8 ; AV21 ; 2H ; 78 ; 88 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_CTL9 ; AV22 ; 2H ; 78 ; 97 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[0] ; AU21 ; 2H ; 78 ; 89 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[10] ; AV28 ; 2H ; 78 ; 93 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[11] ; AU26 ; 2H ; 78 ; 97 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[12] ; AV23 ; 2H ; 78 ; 93 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[13] ; AU25 ; 2H ; 78 ; 98 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[14] ; AR25 ; 2H ; 78 ; 91 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[15] ; AP24 ; 2H ; 78 ; 89 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[16] ; AL23 ; 2H ; 78 ; 90 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[17] ; AM24 ; 2H ; 78 ; 98 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[18] ; AK25 ; 2H ; 78 ; 97 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[19] ; AM25 ; 2H ; 78 ; 95 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[1] ; AW23 ; 2H ; 78 ; 92 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[20] ; AT24 ; 2H ; 78 ; 90 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[21] ; AR26 ; 2H ; 78 ; 96 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[22] ; AP26 ; 2H ; 78 ; 97 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[23] ; AP25 ; 2H ; 78 ; 88 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[24] ; AN24 ; 2H ; 78 ; 94 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[25] ; AN26 ; 2H ; 78 ; 94 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[26] ; AK23 ; 2H ; 78 ; 91 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[27] ; AJ25 ; 2H ; 78 ; 98 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[28] ; AJ23 ; 2H ; 78 ; 92 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[29] ; AH23 ; 2H ; 78 ; 93 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[2] ; AW24 ; 2H ; 78 ; 94 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[30] ; AR20 ; 2G ; 78 ; 71 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[31] ; AP20 ; 2G ; 78 ; 72 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[3] ; AW25 ; 2H ; 78 ; 89 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[4] ; AW26 ; 2H ; 78 ; 88 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[5] ; AV24 ; 2H ; 78 ; 95 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[6] ; AW28 ; 2H ; 78 ; 92 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[7] ; AW30 ; 2H ; 78 ; 98 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[8] ; AW29 ; 2H ; 78 ; 99 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_DQ[9] ; AV27 ; 2H ; 78 ; 94 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_OTG_ID ; AG26 ; 2I ; 78 ; 120 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_PCLK ; AT27 ; 2H ; 78 ; 92 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_RESET_n ; AJ24 ; 2H ; 78 ; 99 ; 61 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_UART_RX ; AU27 ; 2H ; 78 ; 96 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -; USBFX3_UART_TX ; AP23 ; 2H ; 78 ; 89 ; 46 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; yes ; no ; Off ; 1.8 V ; Default ; Off ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ; -+----------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+------------+----------+--------------+------------------------+------------------+----------------------------------+-----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+----------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+-------------------+---------------+--------------+ -; 1J ; 0 / 0 ( -- ) ; -- ; -- ; -; 1I ; 0 / 0 ( -- ) ; -- ; -- ; -; 1H ; 18 / 28 ( 64 % ) ; -- ; -- ; -; 1G ; 28 / 28 ( 100 % ) ; -- ; -- ; -; 1F ; 0 / 28 ( 0 % ) ; -- ; -- ; -; 1E ; 0 / 28 ( 0 % ) ; -- ; -- ; -; 1D ; 0 / 28 ( 0 % ) ; -- ; -- ; -; 1C ; 0 / 28 ( 0 % ) ; -- ; -- ; -; 2L ; 35 / 48 ( 73 % ) ; 1.8V ; -- ; -; 2K ; 31 / 48 ( 65 % ) ; 1.2V ; -- ; -; 2J ; 45 / 48 ( 94 % ) ; 1.2V ; -- ; -; 2I ; 19 / 48 ( 40 % ) ; 1.8V ; -- ; -; 2H ; 48 / 48 ( 100 % ) ; 1.8V ; -- ; -; 2G ; 21 / 24 ( 88 % ) ; 1.8V ; -- ; -; 2A ; 37 / 48 ( 77 % ) ; 1.8V ; -- ; -; 3H ; 48 / 48 ( 100 % ) ; 1.8V ; -- ; -; 3G ; 48 / 48 ( 100 % ) ; 1.8V ; -- ; -; 3F ; 47 / 48 ( 98 % ) ; 1.8V ; -- ; -; 3E ; 2 / 48 ( 4 % ) ; 1.2V ; -- ; -; 3D ; 0 / 48 ( 0 % ) ; 1.8V ; -- ; -; 3C ; 0 / 48 ( 0 % ) ; 1.8V ; -- ; -; 3B ; 0 / 48 ( 0 % ) ; 1.8V ; -- ; -; 3A ; 0 / 48 ( 0 % ) ; 1.8V ; -- ; -+----------+-------------------+---------------+--------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------------------------------+--------+-----------------------------+---------+--------------+-----------------+----------+--------------+---------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; Package Delay ; -+----------+------------+----------+------------------------------------------------------------------+--------+-----------------------------+---------+--------------+-----------------+----------+--------------+---------------+ -; A2 ; 739 ; 3F ; FMC_HB_p[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A3 ; 681 ; 3G ; FMC_LA_p[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A4 ; 680 ; 3G ; FMC_LA_n[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A5 ; 693 ; 3G ; FMC_LA_p[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A7 ; 655 ; 3H ; FMC_HA_p[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A8 ; 654 ; 3H ; FMC_HA_n[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A9 ; 653 ; 3H ; FMC_HA_p[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A10 ; 647 ; 3H ; FMC_HA_p[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A12 ; 621 ; 3H ; FMC_HA_p[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A13 ; ; ; VREFP_ADC ; ; ; ; -- ; ; -- ; -- ; -- ; -; A14 ; ; ; VREFN_ADC ; ; ; ; -- ; ; -- ; -- ; -- ; -; A15 ; 353 ; 2J ; DDR4H_DQ[13] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 175ps ; -; A16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A17 ; 347 ; 2J ; DDR4H_DQ[12] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 177ps ; -; A18 ; 346 ; 2J ; DDR4H_DQ[14] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 171ps ; -; A19 ; 341 ; 2J ; DDR4H_DQ[7] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 178ps ; -; A20 ; 339 ; 2J ; DDR4H_DQS[0] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 180ps ; -; A21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A22 ; 342 ; 2J ; DDR4H_DQ[3] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 189ps ; -; A23 ; 343 ; 2J ; DDR4H_ALERT_n ; input ; SSTL-12 ; ; -- ; Y ; no ; Off ; 190ps ; -; A24 ; 227 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; A25 ; 229 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; A26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A27 ; 238 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; A28 ; 239 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; A29 ; 243 ; 2L ; HPS_KEY ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A30 ; 245 ; 2L ; HPS_I2C0_SDAT ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; A31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A32 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; -- ; -; A33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; A36 ; 58 ; 1H ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; A37 ; 59 ; 1H ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; A38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA2 ; 828 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA3 ; 831 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA4 ; 830 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA5 ; 832 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA6 ; ; 3D ; VCCIO3D ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AA7 ; 818 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA8 ; 821 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA9 ; 820 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA10 ; 812 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA11 ; ; 3D ; VCCIO3D ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AA12 ; 822 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA13 ; ; 3D ; VREFB3DN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AA14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AA25 ; ; 2I ; VREFB2IN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AA26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA27 ; 370 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AA28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AA30 ; ; -- ; VCCT_GXBL1E ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AA31 ; ; -- ; VCCT_GXBL1E ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AA32 ; 144 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AA33 ; 145 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AA34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA36 ; 148 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AA37 ; 149 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AA38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AA39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB1 ; 834 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB2 ; 840 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB4 ; 833 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB5 ; 827 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB6 ; 826 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB7 ; 819 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB8 ; ; 3D ; VCCIO3D ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AB9 ; 813 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB10 ; 817 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB11 ; 816 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB12 ; 823 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AB25 ; 376 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB26 ; 377 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB27 ; 371 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AB28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB30 ; 141 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AB31 ; 140 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AB32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB34 ; 152 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AB35 ; 153 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AB36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AB38 ; 146 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AB39 ; 147 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AC1 ; 835 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC2 ; 841 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC3 ; 843 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC4 ; 842 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC6 ; 836 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC7 ; 882 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC8 ; 889 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC9 ; 888 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC10 ; ; 3C ; VCCIO3C ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC11 ; 892 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC12 ; 895 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC13 ; ; 3C ; VREFB3CN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AC14 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC16 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AC18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AC19 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC21 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AC23 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC24 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC25 ; ; 2I ; VCCIO2I ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AC26 ; 380 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC27 ; 381 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC28 ; 372 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AC29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC30 ; ; -- ; VCCR_GXBL1E ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AC31 ; ; -- ; VCCR_GXBL1E ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AC32 ; 156 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AC33 ; 157 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AC34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC36 ; 160 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AC37 ; 161 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AC38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AC39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD1 ; 844 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD3 ; 839 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD4 ; 838 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD5 ; 837 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD6 ; 883 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD7 ; ; 3C ; VCCIO3C ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AD8 ; 890 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD9 ; 887 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD10 ; 886 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD11 ; 893 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD13 ; 894 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD16 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AD25 ; 378 ; 2I ; SRC_DP_HPD ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AD26 ; 368 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD27 ; ; 2I ; VCCIO2I ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AD28 ; 373 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AD29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD30 ; 167 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD31 ; 166 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD34 ; 164 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD35 ; 165 ; 1E ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AD38 ; 150 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AD39 ; 151 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE1 ; 845 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE2 ; 847 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE3 ; 846 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE5 ; 858 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE6 ; 872 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE7 ; 878 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE8 ; 891 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE10 ; 931 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE11 ; 930 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE12 ; 939 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE13 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AE14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE16 ; ; ; GNDSENSE ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE17 ; ; ; VCCLSENSE ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AE19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AE21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AE22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AE23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AE24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE25 ; 379 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE26 ; 369 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE27 ; 382 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AE28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AE30 ; ; -- ; VCCT_GXBL1D ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AE31 ; ; -- ; VCCT_GXBL1D ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AE32 ; 176 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE33 ; 177 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE36 ; 154 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE37 ; 155 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AE38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AE39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF2 ; 851 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF3 ; 850 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF4 ; 859 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF5 ; 873 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF6 ; ; 3C ; VCCIO3C ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AF7 ; 879 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF8 ; 884 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF9 ; 937 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF10 ; 936 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF11 ; ; 3B ; VCCIO3B ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AF12 ; 940 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF13 ; 938 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF15 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AF25 ; 384 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF26 ; ; 2I ; VCCIO2I ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AF27 ; 383 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF28 ; 386 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AF29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF30 ; 169 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AF31 ; 168 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AF32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF34 ; 172 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AF35 ; 173 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AF36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AF38 ; 158 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AF39 ; 159 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AG1 ; 853 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG2 ; 852 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG4 ; 856 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG5 ; 877 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG6 ; 876 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG7 ; 885 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG9 ; 935 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG10 ; 934 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG11 ; 941 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG12 ; 942 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG14 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AG15 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG16 ; ; -- ; VCCBAT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AG17 ; ; -- ; VCCPGM ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AG18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG19 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG20 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG22 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG24 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; AG25 ; 385 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG26 ; 374 ; 2I ; USBFX3_OTG_ID ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AG27 ; 387 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AG28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG30 ; ; -- ; VCCR_GXBL1D ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AG31 ; ; -- ; VCCR_GXBL1D ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AG32 ; 184 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AG33 ; 185 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AG34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG36 ; 162 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AG37 ; 163 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AG38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AG39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH1 ; 848 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH2 ; 855 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH3 ; 854 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH4 ; 857 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH6 ; 874 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH7 ; 921 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH8 ; 920 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH9 ; 922 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH10 ; ; 3B ; VCCIO3B ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AH11 ; 943 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH12 ; 978 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH13 ; 988 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH14 ; 990 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH16 ; 562 ; 2A ; FMC_HB_n[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AH17 ; ; -- ; VCCPGM ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AH18 ; 602 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH19 ; ; 2A ; VREFB2AN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AH20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH21 ; 486 ; 2G ; SMA_CLKIN_p(n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; AH22 ; ; 2G ; VREFB2GN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AH23 ; 422 ; 2H ; USBFX3_DQ[29] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AH24 ; ; 2H ; VREFB2HN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; AH25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH26 ; 375 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH27 ; 388 ; 2I ; I2C_INT ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AH28 ; 389 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AH29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH30 ; 195 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AH31 ; 194 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AH32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH34 ; 180 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AH35 ; 181 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AH36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AH38 ; 170 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AH39 ; 171 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ1 ; 849 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ3 ; 861 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ4 ; 860 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ5 ; 875 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ6 ; 880 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ8 ; 923 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ9 ; 933 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ10 ; 932 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ11 ; 979 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ12 ; ; 3A ; VCCIO3A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AJ13 ; 989 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ14 ; 991 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ15 ; 992 ; CSS ; ^GND ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ16 ; 563 ; 2A ; FMC_HB_p[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ18 ; 594 ; 2A ; CLKUSR_100 ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ19 ; 603 ; 2A ; SW[0] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ20 ; 496 ; 2G ; ETH_MDIO ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ21 ; 487 ; 2G ; SMA_CLKIN_p ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; AJ22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ23 ; 423 ; 2H ; USBFX3_DQ[28] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ24 ; 416 ; 2H ; USBFX3_RESET_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ25 ; 417 ; 2H ; USBFX3_DQ[27] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AJ26 ; 390 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AJ27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AJ30 ; ; -- ; VCCT_GXBL1C ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AJ31 ; ; -- ; VCCT_GXBL1C ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AJ32 ; 192 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ33 ; 193 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ36 ; 174 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ37 ; 175 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AJ38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AJ39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK1 ; 865 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK2 ; 864 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK3 ; 870 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK5 ; 881 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK6 ; 925 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK7 ; 924 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK8 ; 926 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK9 ; ; 3B ; VCCIO3B ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AK10 ; 985 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK11 ; 984 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK12 ; 986 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK13 ; 982 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK15 ; 1001 ; CSS ; ^nIO_PULLUP ; input ; ; ; -- ; ; -- ; -- ; -- ; -; AK16 ; 565 ; 2A ; FMC_HB_p[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK17 ; 564 ; 2A ; FMC_HB_n[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK18 ; 595 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK19 ; ; 2A ; VCCIO2A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AK20 ; 497 ; 2G ; ETH_RST_n ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK21 ; 480 ; 2G ; CDCM6208_SCL ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK22 ; 481 ; 2G ; CDCM6208_SDA ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK23 ; 424 ; 2H ; USBFX3_DQ[26] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK24 ; ; 2H ; VCCIO2H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AK25 ; 418 ; 2H ; USBFX3_DQ[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK26 ; 391 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK27 ; 400 ; 2I ; HEX1_D[5] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AK28 ; 394 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AK29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK30 ; 197 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AK31 ; 196 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AK32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK34 ; 188 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AK35 ; 189 ; 1D ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AK36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AK38 ; 178 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AK39 ; 179 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL2 ; 871 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL3 ; 869 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL4 ; 868 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL5 ; 908 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL7 ; 927 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL8 ; 929 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL9 ; 928 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL10 ; 968 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL11 ; ; 3A ; VCCIO3A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AL12 ; 987 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL13 ; 983 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL14 ; 996 ; CSS ; altera_reserved_tck ; input ; 1.8 V ; ; -- ; N ; no ; Off ; -- ; -; AL15 ; 1004 ; CSS ; ^GND ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL16 ; ; 2A ; VCCIO2A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AL17 ; 568 ; 2A ; FMC_HB_n[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL18 ; 601 ; 2A ; FMC_GA[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL19 ; 600 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL20 ; 490 ; 2G ; ETH_RX_p(n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; AL21 ; ; 2G ; VCCIO2G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AL22 ; 476 ; 2G ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL23 ; 425 ; 2H ; USBFX3_DQ[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL24 ; 428 ; 2H ; USBFX3_CTL6 ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL25 ; 419 ; 2H ; USBFX3_CTL7_PKTEND_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL27 ; 401 ; 2I ; HEX1_D[4] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AL28 ; 395 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AL29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL30 ; ; -- ; VCCR_GXBL1C ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AL31 ; ; -- ; VCCR_GXBL1C ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; AL32 ; 204 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL33 ; 205 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL36 ; 182 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL37 ; 183 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AL38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AL39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM1 ; 863 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM2 ; 862 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM4 ; 909 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM5 ; 913 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM6 ; 912 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM7 ; 916 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM9 ; 969 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM10 ; 975 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM11 ; 974 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM12 ; 980 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM13 ; ; 3A ; VCCIO3A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AM14 ; 998 ; CSS ; ^MSEL0 ; input ; ; ; -- ; ; -- ; -- ; -- ; -; AM15 ; 573 ; 2A ; FMC_HB_p[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM16 ; 572 ; 2A ; FMC_HB_n[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM17 ; 569 ; 2A ; FMC_HB_p[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM18 ; ; 2A ; VCCIO2A ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AM19 ; 606 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM20 ; 491 ; 2G ; ETH_RX_p ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; AM21 ; 482 ; 2G ; SMA_CLKOUT_p(n) ; output ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; AM22 ; 477 ; 2G ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AM23 ; ; 2H ; VCCIO2H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AM24 ; 429 ; 2H ; USBFX3_DQ[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM25 ; 420 ; 2H ; USBFX3_DQ[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM26 ; 404 ; 2I ; HEX1_D[6] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM27 ; 405 ; 2I ; HEX1_D[3] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AM28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM30 ; 223 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AM31 ; 222 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AM32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM34 ; 200 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AM35 ; 201 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AM36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AM38 ; 186 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AM39 ; 187 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN1 ; 867 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN2 ; 866 ; 3C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN3 ; 901 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN4 ; 900 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN6 ; 918 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN7 ; 917 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN8 ; 956 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN9 ; 972 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN11 ; 976 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN12 ; 981 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN13 ; 1006 ; CSS ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN14 ; 1000 ; CSS ; ^MSEL2 ; input ; ; ; -- ; ; -- ; -- ; -- ; -; AN15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN16 ; 566 ; 2A ; FMC_HB_n[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN17 ; 598 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN18 ; 607 ; 2A ; CPU_RESET_n ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN19 ; 498 ; 2G ; ETH_TX_p(n) ; output ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; AN20 ; ; 2G ; VCCIO2G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AN21 ; 483 ; 2G ; SMA_CLKOUT_p ; output ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; AN22 ; 478 ; 2G ; USBFX3_CTL4_FLAGA ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN23 ; 432 ; 2H ; USBFX3_CTL5_FLAGB ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN24 ; 433 ; 2H ; USBFX3_DQ[24] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN25 ; ; 2H ; VCCIO2H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AN26 ; 421 ; 2H ; USBFX3_DQ[25] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AN27 ; 392 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN28 ; 393 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AN29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN32 ; 212 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN33 ; 213 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN36 ; 190 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN37 ; 191 ; 1D ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AN38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AN39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP1 ; 898 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP3 ; 907 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP4 ; 906 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP5 ; 919 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP6 ; 914 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP8 ; 957 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP9 ; 973 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP10 ; 970 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP11 ; 977 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP13 ; 999 ; CSS ; ^MSEL1 ; input ; ; ; -- ; ; -- ; -- ; -- ; -; AP14 ; 561 ; 2A ; FMC_HB_p[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP15 ; 560 ; 2A ; FMC_HB_n[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP16 ; 567 ; 2A ; FMC_HB_p[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP18 ; 599 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP19 ; 499 ; 2G ; ETH_TX_p ; output ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; AP20 ; 488 ; 2G ; USBFX3_DQ[31] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP21 ; 479 ; 2G ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP22 ; ; 2G ; VCCIO2G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; AP23 ; 438 ; 2H ; USBFX3_UART_TX ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP24 ; 426 ; 2H ; USBFX3_DQ[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP25 ; 427 ; 2H ; USBFX3_DQ[23] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP26 ; 430 ; 2H ; USBFX3_DQ[22] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AP27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP28 ; 398 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP29 ; 396 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP30 ; 397 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AP31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP34 ; 208 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AP35 ; 209 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AP36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AP38 ; 198 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AP39 ; 199 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AR1 ; 899 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR2 ; 897 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR3 ; 896 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR5 ; 910 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR6 ; 915 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR7 ; 961 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR8 ; 960 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR10 ; 971 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR11 ; 993 ; CSS ; altera_reserved_tdo ; output ; 1.8 V ; ; -- ; N ; no ; Off ; -- ; -; AR12 ; 997 ; CSS ; altera_reserved_tdi ; input ; 1.8 V ; ; -- ; N ; no ; Off ; -- ; -; AR13 ; 1011 ; CSS ; ^AS_DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AR14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR15 ; 579 ; 2A ; FMC_HB_p[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR16 ; 578 ; 2A ; FMC_HB_n[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR17 ; 605 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR18 ; 604 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR20 ; 489 ; 2G ; USBFX3_DQ[30] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR21 ; 484 ; 2G ; REFCLK1_SDA ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR22 ; 485 ; 2G ; REFCLK1_SCL ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR23 ; 439 ; 2H ; CLK_50_B2H ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR25 ; 436 ; 2H ; USBFX3_DQ[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR26 ; 431 ; 2H ; USBFX3_DQ[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR27 ; 434 ; 2H ; USBFX3_CTL3_SLRD_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR28 ; 399 ; 2I ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AR29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR30 ; 406 ; 2I ; HEX1_D[2] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR31 ; 407 ; 2I ; HEX1_DP ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR32 ; 412 ; 2I ; HEX0_D[1] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AR33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR36 ; 202 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AR37 ; 203 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AR38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AR39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT2 ; 903 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT3 ; 902 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT4 ; 911 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT5 ; 944 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT7 ; 966 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT8 ; 963 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT9 ; 962 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AT10 ; 1005 ; CSS ; ^nCONFIG ; input ; ; ; -- ; ; -- ; -- ; -- ; -; AT11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT12 ; 1010 ; CSS ; ^AS_DATA0, ASDO ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AT13 ; 575 ; 2A ; FMC_HB_p[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT14 ; 574 ; 2A ; FMC_HB_n[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT15 ; 580 ; 2A ; KEY[1] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT17 ; 591 ; 2A ; FMC_HB_p[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT18 ; 590 ; 2A ; FMC_HB_n[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT19 ; 494 ; 2G ; ETH_MDC ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT20 ; 492 ; 2G ; REFCLK0_SDA ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT22 ; 460 ; 2H ; USBFX3_CTL1_SLWR_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT23 ; 448 ; 2H ; USBFX3_CTL12_A0 ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT24 ; 449 ; 2H ; USBFX3_DQ[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT25 ; 437 ; 2H ; USBFX3_CTL2_SLOE_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT27 ; 435 ; 2H ; USBFX3_PCLK ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT28 ; 414 ; 2I ; HEX1_D[0] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT29 ; 415 ; 2I ; HEX1_D[1] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT30 ; 402 ; 2I ; HEX0_D[4] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT32 ; 413 ; 2I ; HEX0_D[0] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AT33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT34 ; 216 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AT35 ; 217 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AT36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AT38 ; 206 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AT39 ; 207 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AU1 ; 905 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU2 ; 904 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU4 ; 946 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU5 ; 945 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU6 ; 958 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU7 ; 967 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AU8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU9 ; 995 ; CSS ; altera_reserved_ntrst ; input ; 1.8 V ; ; -- ; N ; no ; Off ; -- ; -; AU10 ; 1003 ; CSS ; ^CONF_DONE ; bidir ; ; ; -- ; ; -- ; -- ; -- ; -; AU11 ; 1008 ; CSS ; ^nCSO1 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AU12 ; 994 ; CSS ; altera_reserved_tms ; input ; 1.8 V ; ; -- ; N ; no ; Off ; -- ; -; AU13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU14 ; 570 ; 2A ; FMC_HB_n[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU15 ; 581 ; 2A ; KEY[0] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU16 ; 589 ; 2A ; FMC_HB_p[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU17 ; 588 ; 2A ; FMC_HB_n[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU19 ; 495 ; 2G ; ETH_INT_n ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU20 ; 493 ; 2G ; REFCLK0_SCL ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU21 ; 462 ; 2H ; USBFX3_DQ[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU22 ; 461 ; 2H ; USBFX3_CTL11_A1 ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU24 ; 452 ; 2H ; USBFX3_CTL10 ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU25 ; 453 ; 2H ; USBFX3_DQ[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU26 ; 442 ; 2H ; USBFX3_DQ[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU27 ; 443 ; 2H ; USBFX3_UART_RX ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU29 ; 410 ; 2I ; HEX0_D[5] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU30 ; 403 ; 2I ; HEX0_D[3] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU31 ; 408 ; 2I ; HEX0_DP ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU32 ; 409 ; 2I ; HEX0_D[2] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AU33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU36 ; 210 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AU37 ; 211 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AU38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AU39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV1 ; 949 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV2 ; 948 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV3 ; 954 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV4 ; 947 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV6 ; 952 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV7 ; 959 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV8 ; 964 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AV9 ; 1002 ; CSS ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV11 ; 1012 ; CSS ; ^AS_DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AV12 ; 1013 ; CSS ; ^AS_DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AV13 ; 576 ; 2A ; FMC_HB_n[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV14 ; 571 ; 2A ; FMC_HB_p[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV16 ; 584 ; 2A ; SW[1] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV17 ; 586 ; 2A ; FMC_CLK2_BIDIR_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV18 ; 593 ; 2A ; FMC_HB_p[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV19 ; 592 ; 2A ; FMC_HB_n[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV21 ; 463 ; 2H ; USBFX3_CTL8 ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV22 ; 454 ; 2H ; USBFX3_CTL9 ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV23 ; 458 ; 2H ; USBFX3_DQ[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV24 ; 456 ; 2H ; USBFX3_DQ[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV26 ; 444 ; 2H ; USBFX3_CTL0_SLCS_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV27 ; 445 ; 2H ; USBFX3_DQ[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV28 ; 446 ; 2H ; USBFX3_DQ[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV29 ; 411 ; 2I ; HEX0_D[6] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AV30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV31 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV32 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV34 ; 220 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV35 ; 221 ; 1C ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AV38 ; 214 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AV39 ; 215 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AW2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW3 ; 955 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW4 ; 951 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW5 ; 950 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW6 ; 953 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW8 ; 965 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW9 ; 1007 ; CSS ; ^nCSO0 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AW10 ; 1009 ; CSS ; ^nCSO2 ; ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AW11 ; 1014 ; CSS ; ^DCLK ; bidir ; ; ; Weak Pull Up ; ; -- ; On ; -- ; -; AW12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW13 ; 577 ; 2A ; FMC_HB_p[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW14 ; 583 ; 2A ; FMC_CLK_M2C_p[1] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW15 ; 582 ; 2A ; FMC_CLK_M2C_n[1] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW16 ; 585 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW18 ; 587 ; 2A ; FMC_CLK2_BIDIR_p ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW19 ; 596 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW20 ; 597 ; 2A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; AW21 ; 455 ; 2H ; USBFX3_CTL15_INT_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW23 ; 459 ; 2H ; USBFX3_DQ[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW24 ; 457 ; 2H ; USBFX3_DQ[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW25 ; 450 ; 2H ; USBFX3_DQ[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW26 ; 451 ; 2H ; USBFX3_DQ[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW28 ; 447 ; 2H ; USBFX3_DQ[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW29 ; 440 ; 2H ; USBFX3_DQ[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW30 ; 441 ; 2H ; USBFX3_DQ[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; AW31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW32 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; -- ; -; AW33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; AW36 ; 218 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AW37 ; 219 ; 1C ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; AW38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B1 ; 745 ; 3F ; FMC_HB_p[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B2 ; 738 ; 3F ; FMC_HB_n[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B4 ; 685 ; 3G ; FMC_LA_p[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B5 ; 692 ; 3G ; FMC_LA_n[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B6 ; 689 ; 3G ; FMC_LA_p[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B7 ; 683 ; 3G ; FMC_LA_p[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B9 ; 652 ; 3H ; FMC_HA_n[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B10 ; 646 ; 3H ; FMC_HA_n[12] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B11 ; 625 ; 3H ; FMC_HA_p[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B12 ; 620 ; 3H ; FMC_HA_n[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B14 ; ; ; TEMPDIODEn ; ; ; ; -- ; ; -- ; -- ; -- ; -; B15 ; ; ; TEMPDIODEp ; ; ; ; -- ; ; -- ; -- ; -- ; -; B16 ; 352 ; 2J ; DDR4H_DQ[9] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 184ps ; -; B17 ; 351 ; 2J ; DDR4H_DQS[1] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 173ps ; -; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B19 ; 340 ; 2J ; DDR4H_DQ[5] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 178ps ; -; B20 ; 338 ; 2J ; DDR4H_DQS_n[0] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 182ps ; -; B21 ; 337 ; 2J ; DDR4H_DQ[1] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 179ps ; -; B22 ; 331 ; 2J ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; B23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B24 ; 226 ; 2L ; LED[1] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B25 ; 228 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; B26 ; 225 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; B27 ; 235 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; B28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B29 ; 242 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; B30 ; 244 ; 2L ; HPS_I2C0_SCLK ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; B31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B34 ; 60 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; B35 ; 61 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; B36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; B38 ; 62 ; 1H ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; B39 ; 63 ; 1H ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; C1 ; 747 ; 3F ; FMC_CLK3_BIDIR_p ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C2 ; 744 ; 3F ; FMC_HB_n[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C3 ; 684 ; 3G ; FMC_LA_n[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C4 ; 687 ; 3G ; FMC_LA_p[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C6 ; 688 ; 3G ; FMC_LA_n[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C7 ; 682 ; 3G ; FMC_LA_n[14] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C8 ; 651 ; 3H ; FMC_HA_p[22] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C9 ; 649 ; 3H ; FMC_HA_p[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C11 ; 624 ; 3H ; FMC_HA_n[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C12 ; 627 ; 3H ; FMC_HA_p[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C13 ; 626 ; 3H ; FMC_HA_n[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C14 ; ; ; ADCGND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C16 ; 357 ; 2J ; DDR4H_DQ[23] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 162ps ; -; C17 ; 350 ; 2J ; DDR4H_DQS_n[1] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 174ps ; -; C18 ; 349 ; 2J ; DDR4H_DQ[8] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 168ps ; -; C19 ; 335 ; 2J ; DDR4H_DQ[0] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 158ps ; -; C20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C21 ; 336 ; 2J ; DDR4H_DQ[2] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 174ps ; -; C22 ; 330 ; 2J ; DDR4H_DQ[29] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 174ps ; -; C23 ; 1027 ; HPS ; HPS_GPIO[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C24 ; 237 ; 2L ; HPS_ENET_MDIO ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C26 ; 224 ; 2L ; LED[0] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; C27 ; 234 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; C28 ; 241 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; C29 ; 247 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; C30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C31 ; 274 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; C32 ; 275 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; C33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C36 ; 66 ; 1H ; FMC_DP_C2M_p[9](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; C37 ; 67 ; 1H ; FMC_DP_C2M_p[9] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; C38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; C39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D1 ; 746 ; 3F ; FMC_CLK3_BIDIR_n ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D3 ; 733 ; 3F ; FMC_HB_p[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D4 ; 686 ; 3G ; FMC_LA_n[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D5 ; 697 ; 3G ; FMC_LA_p[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D6 ; 696 ; 3G ; FMC_LA_n[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D8 ; 650 ; 3H ; FMC_HA_n[22] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D9 ; 648 ; 3H ; FMC_HA_n[21] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D10 ; 643 ; 3H ; FMC_HA_p[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D11 ; 631 ; 3H ; CLK_50_B3H ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D13 ; 623 ; 3H ; FMC_HA_p[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D14 ; ; ; VSIGP_0 ; ; ; ; -- ; ; -- ; -- ; -- ; -; D15 ; ; ; VSIGN_0 ; ; ; ; -- ; ; -- ; -- ; -- ; -; D16 ; 356 ; 2J ; DDR4H_DBI_n[2] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 160ps ; -; D17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D18 ; 348 ; 2J ; DDR4H_DQ[10] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 173ps ; -; D19 ; 334 ; 2J ; DDR4H_DQ[4] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 160ps ; -; D20 ; 321 ; 2J ; DDR4H_DQ[31] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 137ps ; -; D21 ; 325 ; 2J ; DDR4H_DQ[25] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 153ps ; -; D22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D23 ; 1026 ; HPS ; HPS_GPIO[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D24 ; 236 ; 2L ; HPS_ENET_MDC ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D25 ; 231 ; 2L ; PM_ALERT_n ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D26 ; 233 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; D27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D28 ; 240 ; 2L ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; D29 ; 246 ; 2L ; HPS_LED ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; D30 ; 276 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; D31 ; 277 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; D32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D34 ; 64 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; D35 ; 65 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; D36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; D38 ; 70 ; 1H ; FMC_DP_C2M_p[8](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; D39 ; 71 ; 1H ; FMC_DP_C2M_p[8] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; E1 ; 743 ; 3F ; FMC_HB_p[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E2 ; 742 ; 3F ; FMC_HB_n[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E3 ; 732 ; 3F ; FMC_HB_n[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E5 ; 699 ; 3G ; FMC_LA_p[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E6 ; 691 ; 3G ; FMC_LA_p[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E7 ; 690 ; 3G ; FMC_LA_n[15] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E8 ; 695 ; 3G ; FMC_LA_p[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E10 ; 642 ; 3H ; FMC_HA_n[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E11 ; 630 ; 3H ; FMC_GA[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E12 ; 629 ; 3H ; FMC_HA_p[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E13 ; 622 ; 3H ; FMC_HA_n[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E15 ; ; ; VSIGP_1 ; ; ; ; -- ; ; -- ; -- ; -- ; -; E16 ; ; ; VSIGN_1 ; ; ; ; -- ; ; -- ; -- ; -- ; -; E17 ; 345 ; 2J ; DDR4H_DQ[11] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 153ps ; -; E18 ; 344 ; 2J ; DDR4H_DBI_n[1] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 150ps ; -; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E20 ; 320 ; 2J ; DDR4H_DBI_n[3] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 145ps ; -; E21 ; 324 ; 2J ; DDR4H_DQ[28] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 158ps ; -; E22 ; 1015 ; HPS ; HPS_CLK1 ; ; ; ; -- ; ; no ; On ; -- ; -; E23 ; 1021 ; HPS ; HPS_DIO[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E25 ; 230 ; 2L ; FAN_ALERT_n ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E26 ; 232 ; 2L ; MPU_INT ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E27 ; 265 ; 2L ; HPS_USB_DATA[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; E28 ; 273 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; E29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E30 ; 279 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; E31 ; 284 ; 2K ; DDR4H_BG[0] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 175ps ; -; E32 ; 285 ; 2K ; DDR4H_BA[1] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 176ps ; -; E33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E36 ; 74 ; 1H ; FMC_DP_C2M_p[7](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; E37 ; 75 ; 1H ; FMC_DP_C2M_p[7] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; E38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; E39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F2 ; 749 ; 3F ; FMC_LA_p[25] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F3 ; 729 ; 3F ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; F4 ; 728 ; 3F ; FMC_SDA ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F5 ; 698 ; 3G ; FMC_LA_n[16] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F7 ; 701 ; 3G ; FMC_LA_p[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F8 ; 694 ; 3G ; FMC_LA_n[10] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F9 ; 675 ; 3G ; FMC_LA_p[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F10 ; 645 ; 3H ; FMC_HA_p[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F12 ; 628 ; 3H ; FMC_HA_n[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F13 ; 617 ; 3H ; FMC_HA_p[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F14 ; 616 ; 3H ; FMC_HA_n[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F15 ; 367 ; 2J ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; F16 ; ; 2J ; VCCIO2J ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; F17 ; 329 ; 2J ; DDR4H_DQ[26] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 125ps ; -; F18 ; 327 ; 2J ; DDR4H_DQS[3] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 127ps ; -; F19 ; 326 ; 2J ; DDR4H_DQS_n[3] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 133ps ; -; F20 ; 323 ; 2J ; DDR4H_DQ[24] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 133ps ; -; F21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F22 ; 1019 ; HPS ; HPS_DIO[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F23 ; 1028 ; HPS ; HPS_GPIO[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F24 ; 249 ; 2L ; HPS_ENET_RX_DATA[2] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F25 ; 259 ; 2L ; HPS_ENET_GTX_CLK ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F27 ; 264 ; 2L ; HPS_USB_DATA[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; F28 ; 272 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; F29 ; 278 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; F30 ; 281 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; F31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F34 ; 72 ; 1H ; FMC_DP_M2C_p[8](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; F35 ; 73 ; 1H ; FMC_DP_M2C_p[8] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; F36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; F38 ; 78 ; 1H ; FMC_DP_C2M_p[6](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; F39 ; 79 ; 1H ; FMC_DP_C2M_p[6] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; G1 ; 751 ; 3F ; FMC_LA_p[29] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G2 ; 748 ; 3F ; FMC_LA_n[25] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G4 ; 737 ; 3F ; FMC_HB_p[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G5 ; 731 ; 3F ; FMC_HB_p[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G6 ; 703 ; 3G ; FMC_LA_p[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G7 ; 700 ; 3G ; FMC_LA_n[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G8 ; ; 3G ; VCCIO3G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; G9 ; 674 ; 3G ; FMC_LA_n[17] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G10 ; 644 ; 3H ; FMC_HA_n[20] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G11 ; 641 ; 3H ; FMC_HA_p[23] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G12 ; 635 ; 3H ; FMC_HA_p[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G13 ; ; 3H ; VCCIO3H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; G14 ; 609 ; 3H ; FMC_HA_p[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G15 ; 366 ; 2J ; DDR4H_DQ[21] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 149ps ; -; G16 ; 365 ; 2J ; DDR4H_DQ[17] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 136ps ; -; G17 ; 328 ; 2J ; DDR4H_DQ[30] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 127ps ; -; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G19 ; 333 ; 2J ; DDR4H_DQ[6] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 137ps ; -; G20 ; 322 ; 2J ; DDR4H_DQ[27] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 136ps ; -; G21 ; 1022 ; HPS ; HPS_DIO[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G22 ; 1029 ; HPS ; HPS_GPIO[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G24 ; 248 ; 2L ; HPS_ENET_RX_DATA[3] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G25 ; 258 ; 2L ; HPS_ENET_TX_EN ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G26 ; 267 ; 2L ; HPS_USB_DATA[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; G27 ; 287 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; G28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G29 ; 291 ; 2K ; DDR4H_A[13] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 179ps ; -; G30 ; 280 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; G31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G32 ; 68 ; 1H ; FMC_DP_M2C_p[9](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; G33 ; 69 ; 1H ; FMC_DP_M2C_p[9] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; G34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G36 ; 86 ; 1G ; FMC_DP_C2M_p[5](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; G37 ; 87 ; 1G ; FMC_DP_C2M_p[5] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; G38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; G39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H1 ; 750 ; 3F ; FMC_LA_n[29] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H2 ; 735 ; 3F ; FMC_HB_p[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H3 ; 734 ; 3F ; FMC_HB_n[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H4 ; 736 ; 3F ; FMC_HB_n[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H6 ; 730 ; 3F ; FMC_HB_n[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H7 ; 702 ; 3G ; FMC_LA_n[9] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H8 ; 673 ; 3G ; FMC_LA_p[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H9 ; 677 ; 3G ; FMC_RZQ ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H11 ; 640 ; 3H ; FMC_HA_n[23] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H12 ; 634 ; 3H ; FMC_HA_n[13] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H13 ; 615 ; 3H ; FMC_HA_p[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H14 ; 608 ; 3H ; FMC_HA_n[11] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H15 ; ; 2J ; VCCIO2J ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; H16 ; 364 ; 2J ; DDR4H_DQ[19] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 137ps ; -; H17 ; 359 ; 2J ; DDR4H_DQ[18] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 134ps ; -; H18 ; 332 ; 2J ; DDR4H_DBI_n[0] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 129ps ; -; H19 ; 1025 ; HPS ; GPIO2_IO7,NAND_ALE,QSPI_SS1,SPIM0_CLK,BOOTSEL0 ; ; ; ; -- ; ; no ; On ; -- ; -; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H21 ; 1023 ; HPS ; HPS_DIO[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H22 ; 1024 ; HPS ; GPIO2_IO6,NAND_CLE,SDMMC_PWR_ENA,SPIM0_SS1_N,SPIS0_MISO,BOOTSEL1 ; ; ; ; -- ; ; no ; On ; -- ; -; H23 ; 253 ; 2L ; HPS_ENET_RX_DATA[0] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H24 ; 255 ; 2L ; HPS_ENET_TX_DATA[0] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H25 ; ; 2L ; VCCIO2L ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; H26 ; 266 ; 2L ; HPS_USB_NXT ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; H27 ; 286 ; 2K ; DDR4H_BA[0] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 181ps ; -; H28 ; 290 ; 2K ; DDR4H_A[14] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 179ps ; -; H29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H31 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H34 ; 80 ; 1H ; FMC_DP_M2C_p[6](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; H35 ; 81 ; 1H ; FMC_DP_M2C_p[6] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; H36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; H38 ; 90 ; 1G ; FMC_DP_C2M_p[4](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; H39 ; 91 ; 1G ; FMC_DP_C2M_p[4] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; J1 ; 797 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J3 ; 783 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; J4 ; 741 ; 3F ; FMC_HB_p[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J5 ; 740 ; 3F ; FMC_HB_n[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J6 ; 717 ; 3F ; FMC_LA_p[28] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J8 ; 672 ; 3G ; FMC_LA_n[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J9 ; 676 ; 3G ; FMC_SCL ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J10 ; 671 ; 3G ; FMC_LA_p[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J11 ; 639 ; 3H ; FMC_HA_p[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J12 ; ; 3H ; VCCIO3H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; J13 ; 614 ; 3H ; FMC_HA_n[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J14 ; 613 ; 3H ; FMC_HA_p[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J15 ; 361 ; 2J ; DDR4H_DQ[20] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 126ps ; -; J16 ; 358 ; 2J ; DDR4H_DQ[16] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 134ps ; -; J17 ; ; 2J ; VCCIO2J ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; J18 ; 1018 ; HPS ; HPS_DIO[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J19 ; 1030 ; HPS ; HPS_TXD ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J20 ; ; -- ; VCCIOREF_HPS ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; J21 ; 1017 ; HPS ; HPS_nRST ; ; ; ; -- ; ; no ; On ; -- ; -; J22 ; ; 2L ; VCCIO2L ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; J23 ; 252 ; 2L ; HPS_ENET_RX_DATA[1] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J24 ; 254 ; 2L ; HPS_ENET_TX_DATA[1] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J25 ; 269 ; 2L ; HPS_USB_DIR ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; J26 ; 293 ; 2K ; DDR4H_RZQ ; input ; 1.2 V ; ; -- ; Y ; no ; Off ; -- ; -; J27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; J30 ; ; -- ; VCCT_GXBL1H ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; J31 ; ; -- ; VCCT_GXBL1H ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; J32 ; 76 ; 1H ; FMC_DP_M2C_p[7](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; J33 ; 77 ; 1H ; FMC_DP_M2C_p[7] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; J34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J36 ; 94 ; 1G ; FMC_DP_C2M_p[3](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; J37 ; 95 ; 1G ; FMC_DP_C2M_p[3] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; J38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; J39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K1 ; 796 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; K2 ; 791 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; K3 ; 782 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K5 ; 727 ; 3F ; FMC_CLK_M2C_p[0] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K6 ; 716 ; 3F ; FMC_LA_n[28] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K7 ; 719 ; 3F ; FMC_LA_p[30] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K8 ; 679 ; 3G ; FMC_LA_p[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K9 ; ; 3G ; VCCIO3G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; K10 ; 670 ; 3G ; FMC_LA_n[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K11 ; 638 ; 3H ; FMC_HA_n[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K12 ; 637 ; 3H ; FMC_HA_p[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K13 ; 612 ; 3H ; FMC_HA_n[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K14 ; ; 3H ; VCCIO3H ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; K15 ; 360 ; 2J ; DDR4H_DQ[22] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 125ps ; -; K16 ; 355 ; 2J ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; K17 ; 354 ; 2J ; DDR4H_DQ[15] ; bidir ; 1.2-V POD ; ; -- ; Y ; no ; Off ; 121ps ; -; K18 ; 1020 ; HPS ; HPS_DIO[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K20 ; ; -- ; VCCIO_HPS ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; K21 ; 1016 ; HPS ; HPS_nPOR ; ; ; ; -- ; ; no ; On ; -- ; -; K22 ; 257 ; 2L ; HPS_ENET_RX_CLK ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K23 ; 261 ; 2L ; HPS_USB_DATA[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K24 ; ; 2L ; VCCIO2L ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; K25 ; 268 ; 2L ; HPS_USB_DATA[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; K26 ; 292 ; 2K ; DDR4H_A[12] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 173ps ; -; K27 ; 283 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; K28 ; 289 ; 2K ; DDR4H_A[15] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 176ps ; -; K29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K30 ; 57 ; 1H ; FMC_GBTCLK_M2C_p[1](n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; K31 ; 56 ; 1H ; FMC_GBTCLK_M2C_p[1] ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; K32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K34 ; 92 ; 1G ; FMC_DP_M2C_p[4](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; K35 ; 93 ; 1G ; FMC_DP_M2C_p[4] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; K36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; K38 ; 98 ; 1G ; FMC_DP_C2M_p[2](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; K39 ; 99 ; 1G ; FMC_DP_C2M_p[2] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L2 ; 790 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; L3 ; 781 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; L4 ; 780 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; L5 ; 726 ; 3F ; FMC_CLK_M2C_n[0] ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L7 ; 718 ; 3F ; FMC_LA_n[30] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L8 ; 678 ; 3G ; FMC_LA_n[18] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L9 ; 669 ; 3G ; FMC_LA_p[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L10 ; 668 ; 3G ; FMC_LA_n[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L12 ; 636 ; 3H ; FMC_HA_n[0] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L13 ; 611 ; 3H ; FMC_HA_p[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L14 ; 610 ; 3H ; FMC_HA_n[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L15 ; 363 ; 2J ; DDR4H_DQS[2] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 124ps ; -; L16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L17 ; ; -- ; VCCL_HPS ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; L18 ; ; -- ; VCCL_HPS ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; L19 ; ; -- ; VCCL_HPS ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; L20 ; 1031 ; HPS ; HPS_RXD ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L22 ; 256 ; 2L ; HPS_ENET_RX_DV ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L23 ; 260 ; 2L ; HPS_USB_DATA[7] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L24 ; 263 ; 2L ; HPS_USB_DATA[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L25 ; 271 ; 2L ; HPS_USB_CLKOUT ; input ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; L26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L27 ; 282 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; L28 ; 288 ; 2K ; DDR4H_A[16] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 177ps ; -; L29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L30 ; ; -- ; VCCR_GXBL1H ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; L31 ; ; -- ; VCCR_GXBL1H ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; L32 ; 88 ; 1G ; FMC_DP_M2C_p[5](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; L33 ; 89 ; 1G ; FMC_DP_M2C_p[5] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; L34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L36 ; 102 ; 1G ; FMC_DP_C2M_p[1](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; L37 ; 103 ; 1G ; FMC_DP_C2M_p[1] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; L38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; L39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M1 ; 799 ; 3E ; FPGA_I2C_SCL ; bidir ; 1.2 V ; ; -- ; Y ; no ; Off ; -- ; -; M2 ; 798 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M4 ; 777 ; 3E ; FPGA_I2C_SDA ; bidir ; 1.2 V ; ; -- ; Y ; no ; Off ; -- ; -; M5 ; 776 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; M6 ; 721 ; 3F ; FMC_LA_p[32] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M7 ; 725 ; 3F ; FMC_HA_p[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M9 ; 661 ; 3G ; FMC_LA_p[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M10 ; 659 ; 3G ; FMC_LA_p[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M11 ; 658 ; 3G ; FMC_LA_n[3] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M12 ; 633 ; 3H ; FMC_HA_p[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M14 ; ; 3H ; VREFB3HN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; M15 ; 362 ; 2J ; DDR4H_DQS_n[2] ; bidir ; Differential 1.2-V POD ; ; -- ; Y ; no ; Off ; 126ps ; -; M16 ; ; 2J ; VREFB2JN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; M17 ; ; -- ; VCCL_HPS ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M19 ; ; -- ; VCCPLL_HPS ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; M20 ; ; 2L ; VREFB2LN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; M21 ; 250 ; 2L ; HPS_ENET_TX_DATA[3] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M22 ; 251 ; 2L ; HPS_ENET_TX_DATA[2] ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M24 ; 262 ; 2L ; HPS_USB_DATA[5] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M25 ; 270 ; 2L ; HPS_USB_STP ; output ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; M26 ; 294 ; 2K ; DDR4H_REFCLK_p(n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; M27 ; 295 ; 2K ; DDR4H_REFCLK_p ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; M28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M30 ; 83 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; M31 ; 82 ; 1H ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; M32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M34 ; 100 ; 1G ; FMC_DP_M2C_p[2](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; M35 ; 101 ; 1G ; FMC_DP_M2C_p[2] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; M36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; M38 ; 106 ; 1G ; FMC_DP_C2M_p[0](n) ; output ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; M39 ; 107 ; 1G ; FMC_DP_C2M_p[0] ; output ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; N1 ; 793 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; N2 ; 792 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; N3 ; 785 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; N4 ; 784 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; N5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N6 ; 720 ; 3F ; FMC_LA_n[32] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N7 ; 724 ; 3F ; FMC_HA_n[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N8 ; 723 ; 3F ; FMC_HB_p[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N9 ; 660 ; 3G ; FMC_LA_n[8] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N10 ; ; 3G ; VCCIO3G ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; N11 ; 657 ; 3G ; FMC_LA_p[33] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N12 ; 632 ; 3H ; FMC_HA_n[1] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N13 ; 619 ; 3H ; FMC_HA_p[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; N14 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N16 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N17 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N19 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N21 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N23 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N24 ; ; -- ; VCCP ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; N25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N26 ; 303 ; 2K ; DDR4H_A[4] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 245ps ; -; N27 ; 304 ; 2K ; DDR4H_A[3] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 232ps ; -; N28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; N30 ; ; -- ; VCCT_GXBL1G ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; N31 ; ; -- ; VCCT_GXBL1G ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; N32 ; 96 ; 1G ; FMC_DP_M2C_p[3](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; N33 ; 97 ; 1G ; FMC_DP_M2C_p[3] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; N34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N36 ; 114 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; N37 ; 115 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; N38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; N39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P1 ; 795 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P3 ; 789 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; P4 ; 788 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; P5 ; 779 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; P6 ; 778 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; P7 ; ; 3F ; VCCIO3F ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; P8 ; 722 ; 3F ; FMC_HB_n[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; P9 ; 704 ; 3F ; FMC_LA_n[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; P10 ; 667 ; 3G ; FMC_LA_p[31] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; P11 ; 656 ; 3G ; FMC_LA_n[33] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P13 ; 618 ; 3H ; FMC_HA_n[6] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; P14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; P25 ; ; 2K ; VREFB2KN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; P26 ; 302 ; 2K ; DDR4H_A[5] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 248ps ; -; P27 ; ; 2K ; VCCIO2K ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; P28 ; 305 ; 2K ; DDR4H_A[2] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 231ps ; -; P29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P30 ; 85 ; 1G ; FMC_GBTCLK_M2C_p[0](n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; P31 ; 84 ; 1G ; FMC_GBTCLK_M2C_p[0] ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; P32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P34 ; 108 ; 1G ; FMC_DP_M2C_p[0](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; P35 ; 109 ; 1G ; FMC_DP_M2C_p[0] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; P36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; P38 ; 118 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; P39 ; 119 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; R1 ; 794 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; R2 ; 787 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; R3 ; 786 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R5 ; 771 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; R6 ; 770 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; R7 ; 707 ; 3F ; FMC_LA_p[26] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; R8 ; 705 ; 3F ; FMC_LA_p[19] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; R9 ; ; 3F ; VCCIO3F ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; R10 ; 666 ; 3G ; FMC_LA_n[31] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; R11 ; 663 ; 3G ; FMC_LA_p[24] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; R12 ; 662 ; 3G ; FMC_LA_n[24] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; R13 ; ; 3G ; VREFB3GN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; R24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R25 ; 300 ; 2K ; DDR4H_A[7] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 248ps ; -; R26 ; 301 ; 2K ; DDR4H_A[6] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 254ps ; -; R27 ; 298 ; 2K ; DDR4H_A[9] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 231ps ; -; R28 ; 299 ; 2K ; DDR4H_A[8] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 231ps ; -; R29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R30 ; ; -- ; VCCR_GXBL1G ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; R31 ; ; -- ; VCCR_GXBL1G ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; R32 ; 104 ; 1G ; FMC_DP_M2C_p[1](n) ; input ; High Speed Differential I/O ; ; -- ; N ; no ; Off ; -- ; -; R33 ; 105 ; 1G ; FMC_DP_M2C_p[1] ; input ; High Speed Differential I/O ; ; -- ; Y ; no ; Off ; -- ; -; R34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R36 ; 122 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; R37 ; 123 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; R38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; R39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T2 ; 801 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T3 ; 765 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T4 ; 764 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T5 ; 773 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T7 ; 767 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T8 ; 706 ; 3F ; FMC_LA_n[26] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; T9 ; 711 ; 3F ; FMC_LA_p[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; T10 ; 710 ; 3F ; FMC_LA_n[2] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; T11 ; ; 3F ; VCCIO3F ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; T12 ; 665 ; 3G ; FMC_LA_p[27] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; T13 ; 664 ; 3G ; FMC_LA_n[27] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; T14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; T25 ; 297 ; 2K ; DDR4H_A[10] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 247ps ; -; T26 ; ; 2K ; VCCIO2K ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; T27 ; 308 ; 2K ; DDR4H_PAR ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 261ps ; -; T28 ; 309 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; T29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T30 ; 111 ; 1G ; FMC_REFCLK_p(n) ; input ; LVDS ; ; -- ; N ; no ; Off ; -- ; -; T31 ; 110 ; 1G ; FMC_REFCLK_p ; input ; LVDS ; ; -- ; Y ; no ; Off ; -- ; -; T32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T34 ; 116 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; T35 ; 117 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; T36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; T38 ; 126 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; T39 ; 127 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; U1 ; 809 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U2 ; 800 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U4 ; 769 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U5 ; 768 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U6 ; 772 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U7 ; 766 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; U8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U9 ; 709 ; 3F ; FMC_LA_p[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; U10 ; 708 ; 3F ; FMC_LA_n[4] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; U11 ; 713 ; 3F ; FMC_LA_p[22] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; U12 ; 712 ; 3F ; FMC_LA_n[22] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U14 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U15 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; U17 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U19 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; U21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; U22 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U24 ; ; -- ; VCCPT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U25 ; 296 ; 2K ; DDR4H_A[11] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 246ps ; -; U26 ; 311 ; 2K ; DDR4H_CK ; output ; Differential 1.2-V SSTL ; ; -- ; Y ; no ; Off ; 230ps ; -; U27 ; 307 ; 2K ; DDR4H_A[0] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 224ps ; -; U28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U29 ; ; -- ; VCCH_GXBL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; U30 ; ; -- ; VCCT_GXBL1F ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; U31 ; ; -- ; VCCT_GXBL1F ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; U32 ; 120 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; U33 ; 121 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; U34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U36 ; 130 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; U37 ; 131 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; U38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; U39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V1 ; 808 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V2 ; 807 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V3 ; 806 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V4 ; 803 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V6 ; 775 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V7 ; 753 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V8 ; 752 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V9 ; 759 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; V10 ; ; 3E ; VCCIO3E ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; V11 ; 715 ; 3F ; FMC_LA_p[23] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; V12 ; 714 ; 3F ; FMC_LA_n[23] ; bidir ; 1.8 V ; ; -- ; Y ; no ; Off ; -- ; -; V13 ; ; 3F ; VREFB3FN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; V14 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V19 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V22 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; V25 ; ; 2K ; VCCIO2K ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; V26 ; 310 ; 2K ; DDR4H_CK_n ; output ; Differential 1.2-V SSTL ; ; -- ; Y ; no ; Off ; 229ps ; -; V27 ; 306 ; 2K ; DDR4H_A[1] ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 220ps ; -; V28 ; 313 ; 2K ; DDR4H_CKE ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 230ps ; -; V29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V30 ; 113 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; V31 ; 112 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; V32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V34 ; 124 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; V35 ; 125 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; V36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; V38 ; 134 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; V39 ; 135 ; 1F ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; W1 ; 805 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W3 ; 811 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W4 ; 802 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W5 ; 825 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W6 ; 774 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W7 ; ; 3E ; VCCIO3E ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; W8 ; 755 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W9 ; 758 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W10 ; 761 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W11 ; 760 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W13 ; ; 3E ; VREFB3EN0 ; power ; ; ; -- ; ; -- ; -- ; -- ; -; W14 ; ; ; VCCA_PLL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; W15 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W16 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W18 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W19 ; ; ; VCCA_PLL ; power ; ; 1.8V ; -- ; ; -- ; -- ; -- ; -; W20 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W23 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W24 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; W25 ; 317 ; 2K ; DDR4H_CS_n ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 189ps ; -; W26 ; 319 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W28 ; 312 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; W29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W30 ; ; -- ; VCCR_GXBL1F ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; W31 ; ; -- ; VCCR_GXBL1F ; power ; ; 0.95V ; -- ; ; -- ; -- ; -- ; -; W32 ; 128 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; W33 ; 129 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; W34 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W35 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W36 ; 132 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; W37 ; 133 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; W38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; W39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y1 ; 804 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y2 ; 829 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y3 ; 810 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y5 ; 824 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y6 ; 815 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y7 ; 814 ; 3D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y8 ; 754 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y9 ; ; 3E ; VCCIO3E ; power ; ; 1.2V ; -- ; ; -- ; -- ; -- ; -; Y10 ; 757 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y11 ; 756 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y12 ; 763 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y13 ; 762 ; 3E ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y15 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y16 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y17 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y18 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y20 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y21 ; ; -- ; VCC ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y22 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y23 ; ; -- ; VCCERAM ; power ; ; 0.9V ; -- ; ; -- ; -- ; -- ; -; Y24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y25 ; 316 ; 2K ; DDR4H_ACT_n ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 192ps ; -; Y26 ; 318 ; 2K ; DDR4H_RESET_n ; output ; 1.2 V ; ; -- ; Y ; no ; Off ; 234ps ; -; Y27 ; 314 ; 2K ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; -- ; ; no ; On ; -- ; -; Y28 ; 315 ; 2K ; DDR4H_ODT ; output ; SSTL-12 ; ; -- ; Y ; no ; Off ; 251ps ; -; Y29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y30 ; 139 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; Y31 ; 138 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; Y32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y34 ; 136 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; Y35 ; 137 ; 1F ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -- ; -; Y36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y37 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -- ; -; Y38 ; 142 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -; Y39 ; 143 ; 1E ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -- ; -+----------+------------+----------+------------------------------------------------------------------+--------+-----------------------------+---------+--------------+-----------------+----------+--------------+---------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+---------------------------------------------------------------+ -; I/O Assignment Warnings ; -+------------------------+--------------------------------------+ -; Pin Name ; Reason ; -+------------------------+--------------------------------------+ -; LED[0] ; Missing drive strength and slew rate ; -; LED[1] ; Missing drive strength and slew rate ; -; HPS_ENET_GTX_CLK ; Missing drive strength and slew rate ; -; HPS_ENET_MDC ; Missing drive strength and slew rate ; -; HPS_ENET_TX_DATA[0] ; Missing drive strength and slew rate ; -; HPS_ENET_TX_DATA[1] ; Missing drive strength and slew rate ; -; HPS_ENET_TX_DATA[2] ; Missing drive strength and slew rate ; -; HPS_ENET_TX_DATA[3] ; Missing drive strength and slew rate ; -; HPS_ENET_TX_EN ; Missing drive strength and slew rate ; -; HPS_TXD ; Missing drive strength and slew rate ; -; HPS_USB_STP ; Missing drive strength and slew rate ; -; ETH_RST_n ; Missing drive strength and slew rate ; -; ETH_MDC ; Missing drive strength and slew rate ; -; HEX0_D[0] ; Missing drive strength and slew rate ; -; HEX0_D[1] ; Missing drive strength and slew rate ; -; HEX0_D[2] ; Missing drive strength and slew rate ; -; HEX0_D[3] ; Missing drive strength and slew rate ; -; HEX0_D[4] ; Missing drive strength and slew rate ; -; HEX0_D[5] ; Missing drive strength and slew rate ; -; HEX0_D[6] ; Missing drive strength and slew rate ; -; HEX0_DP ; Missing drive strength and slew rate ; -; HEX1_D[0] ; Missing drive strength and slew rate ; -; HEX1_D[1] ; Missing drive strength and slew rate ; -; HEX1_D[2] ; Missing drive strength and slew rate ; -; HEX1_D[3] ; Missing drive strength and slew rate ; -; HEX1_D[4] ; Missing drive strength and slew rate ; -; HEX1_D[5] ; Missing drive strength and slew rate ; -; HEX1_D[6] ; Missing drive strength and slew rate ; -; HEX1_DP ; Missing drive strength and slew rate ; -; FPGA_I2C_SCL ; Missing drive strength and slew rate ; -; FPGA_I2C_SDA ; Missing drive strength and slew rate ; -; HPS_GPIO[0] ; Missing drive strength and slew rate ; -; HPS_GPIO[1] ; Missing drive strength and slew rate ; -; HPS_GPIO[2] ; Missing drive strength and slew rate ; -; HPS_GPIO[3] ; Missing drive strength and slew rate ; -; HPS_KEY ; Missing drive strength and slew rate ; -; HPS_LED ; Missing drive strength and slew rate ; -; HPS_ENET_MDIO ; Missing drive strength and slew rate ; -; HPS_USB_DATA[0] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[1] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[2] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[3] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[4] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[5] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[6] ; Missing drive strength and slew rate ; -; HPS_USB_DATA[7] ; Missing drive strength and slew rate ; -; HPS_I2C0_SCLK ; Missing drive strength and slew rate ; -; HPS_I2C0_SDAT ; Missing drive strength and slew rate ; -; HPS_DIO[0] ; Missing drive strength and slew rate ; -; HPS_DIO[1] ; Missing drive strength and slew rate ; -; HPS_DIO[2] ; Missing drive strength and slew rate ; -; HPS_DIO[3] ; Missing drive strength and slew rate ; -; HPS_DIO[4] ; Missing drive strength and slew rate ; -; HPS_DIO[5] ; Missing drive strength and slew rate ; -; I2C_INT ; Missing drive strength and slew rate ; -; REFCLK0_SCL ; Missing drive strength and slew rate ; -; REFCLK0_SDA ; Missing drive strength and slew rate ; -; REFCLK1_SCL ; Missing drive strength and slew rate ; -; REFCLK1_SDA ; Missing drive strength and slew rate ; -; CDCM6208_SCL ; Missing drive strength and slew rate ; -; CDCM6208_SDA ; Missing drive strength and slew rate ; -; FMC_CLK2_BIDIR_p ; Missing drive strength and slew rate ; -; FMC_CLK2_BIDIR_n ; Missing drive strength and slew rate ; -; FMC_CLK3_BIDIR_p ; Missing drive strength and slew rate ; -; FMC_CLK3_BIDIR_n ; Missing drive strength and slew rate ; -; FMC_HA_p[0] ; Missing drive strength and slew rate ; -; FMC_HA_p[1] ; Missing drive strength and slew rate ; -; FMC_HA_p[2] ; Missing drive strength and slew rate ; -; FMC_HA_p[3] ; Missing drive strength and slew rate ; -; FMC_HA_p[4] ; Missing drive strength and slew rate ; -; FMC_HA_p[5] ; Missing drive strength and slew rate ; -; FMC_HA_p[6] ; Missing drive strength and slew rate ; -; FMC_HA_p[7] ; Missing drive strength and slew rate ; -; FMC_HA_p[8] ; Missing drive strength and slew rate ; -; FMC_HA_p[9] ; Missing drive strength and slew rate ; -; FMC_HA_p[10] ; Missing drive strength and slew rate ; -; FMC_HA_p[11] ; Missing drive strength and slew rate ; -; FMC_HA_p[12] ; Missing drive strength and slew rate ; -; FMC_HA_p[13] ; Missing drive strength and slew rate ; -; FMC_HA_p[14] ; Missing drive strength and slew rate ; -; FMC_HA_p[15] ; Missing drive strength and slew rate ; -; FMC_HA_p[16] ; Missing drive strength and slew rate ; -; FMC_HA_p[17] ; Missing drive strength and slew rate ; -; FMC_HA_p[18] ; Missing drive strength and slew rate ; -; FMC_HA_p[19] ; Missing drive strength and slew rate ; -; FMC_HA_p[20] ; Missing drive strength and slew rate ; -; FMC_HA_p[21] ; Missing drive strength and slew rate ; -; FMC_HA_p[22] ; Missing drive strength and slew rate ; -; FMC_HA_p[23] ; Missing drive strength and slew rate ; -; FMC_HA_n[0] ; Missing drive strength and slew rate ; -; FMC_HA_n[1] ; Missing drive strength and slew rate ; -; FMC_HA_n[2] ; Missing drive strength and slew rate ; -; FMC_HA_n[3] ; Missing drive strength and slew rate ; -; FMC_HA_n[4] ; Missing drive strength and slew rate ; -; FMC_HA_n[5] ; Missing drive strength and slew rate ; -; FMC_HA_n[6] ; Missing drive strength and slew rate ; -; FMC_HA_n[7] ; Missing drive strength and slew rate ; -; FMC_HA_n[8] ; Missing drive strength and slew rate ; -; FMC_HA_n[9] ; Missing drive strength and slew rate ; -; FMC_HA_n[10] ; Missing drive strength and slew rate ; -; FMC_HA_n[11] ; Missing drive strength and slew rate ; -; FMC_HA_n[12] ; Missing drive strength and slew rate ; -; FMC_HA_n[13] ; Missing drive strength and slew rate ; -; FMC_HA_n[14] ; Missing drive strength and slew rate ; -; FMC_HA_n[15] ; Missing drive strength and slew rate ; -; FMC_HA_n[16] ; Missing drive strength and slew rate ; -; FMC_HA_n[17] ; Missing drive strength and slew rate ; -; FMC_HA_n[18] ; Missing drive strength and slew rate ; -; FMC_HA_n[19] ; Missing drive strength and slew rate ; -; FMC_HA_n[20] ; Missing drive strength and slew rate ; -; FMC_HA_n[21] ; Missing drive strength and slew rate ; -; FMC_HA_n[22] ; Missing drive strength and slew rate ; -; FMC_HA_n[23] ; Missing drive strength and slew rate ; -; FMC_HB_p[0] ; Missing drive strength and slew rate ; -; FMC_HB_p[1] ; Missing drive strength and slew rate ; -; FMC_HB_p[2] ; Missing drive strength and slew rate ; -; FMC_HB_p[3] ; Missing drive strength and slew rate ; -; FMC_HB_p[4] ; Missing drive strength and slew rate ; -; FMC_HB_p[5] ; Missing drive strength and slew rate ; -; FMC_HB_p[6] ; Missing drive strength and slew rate ; -; FMC_HB_p[7] ; Missing drive strength and slew rate ; -; FMC_HB_p[8] ; Missing drive strength and slew rate ; -; FMC_HB_p[9] ; Missing drive strength and slew rate ; -; FMC_HB_p[10] ; Missing drive strength and slew rate ; -; FMC_HB_p[11] ; Missing drive strength and slew rate ; -; FMC_HB_p[12] ; Missing drive strength and slew rate ; -; FMC_HB_p[13] ; Missing drive strength and slew rate ; -; FMC_HB_p[14] ; Missing drive strength and slew rate ; -; FMC_HB_p[15] ; Missing drive strength and slew rate ; -; FMC_HB_p[16] ; Missing drive strength and slew rate ; -; FMC_HB_p[17] ; Missing drive strength and slew rate ; -; FMC_HB_p[18] ; Missing drive strength and slew rate ; -; FMC_HB_p[19] ; Missing drive strength and slew rate ; -; FMC_HB_p[20] ; Missing drive strength and slew rate ; -; FMC_HB_p[21] ; Missing drive strength and slew rate ; -; FMC_HB_n[0] ; Missing drive strength and slew rate ; -; FMC_HB_n[1] ; Missing drive strength and slew rate ; -; FMC_HB_n[2] ; Missing drive strength and slew rate ; -; FMC_HB_n[3] ; Missing drive strength and slew rate ; -; FMC_HB_n[4] ; Missing drive strength and slew rate ; -; FMC_HB_n[5] ; Missing drive strength and slew rate ; -; FMC_HB_n[6] ; Missing drive strength and slew rate ; -; FMC_HB_n[7] ; Missing drive strength and slew rate ; -; FMC_HB_n[8] ; Missing drive strength and slew rate ; -; FMC_HB_n[9] ; Missing drive strength and slew rate ; -; FMC_HB_n[10] ; Missing drive strength and slew rate ; -; FMC_HB_n[11] ; Missing drive strength and slew rate ; -; FMC_HB_n[12] ; Missing drive strength and slew rate ; -; FMC_HB_n[13] ; Missing drive strength and slew rate ; -; FMC_HB_n[14] ; Missing drive strength and slew rate ; -; FMC_HB_n[15] ; Missing drive strength and slew rate ; -; FMC_HB_n[16] ; Missing drive strength and slew rate ; -; FMC_HB_n[17] ; Missing drive strength and slew rate ; -; FMC_HB_n[18] ; Missing drive strength and slew rate ; -; FMC_HB_n[19] ; Missing drive strength and slew rate ; -; FMC_HB_n[20] ; Missing drive strength and slew rate ; -; FMC_HB_n[21] ; Missing drive strength and slew rate ; -; FMC_LA_p[0] ; Missing drive strength and slew rate ; -; FMC_LA_p[1] ; Missing drive strength and slew rate ; -; FMC_LA_p[2] ; Missing drive strength and slew rate ; -; FMC_LA_p[3] ; Missing drive strength and slew rate ; -; FMC_LA_p[4] ; Missing drive strength and slew rate ; -; FMC_LA_p[5] ; Missing drive strength and slew rate ; -; FMC_LA_p[6] ; Missing drive strength and slew rate ; -; FMC_LA_p[7] ; Missing drive strength and slew rate ; -; FMC_LA_p[8] ; Missing drive strength and slew rate ; -; FMC_LA_p[9] ; Missing drive strength and slew rate ; -; FMC_LA_p[10] ; Missing drive strength and slew rate ; -; FMC_LA_p[11] ; Missing drive strength and slew rate ; -; FMC_LA_p[12] ; Missing drive strength and slew rate ; -; FMC_LA_p[13] ; Missing drive strength and slew rate ; -; FMC_LA_p[14] ; Missing drive strength and slew rate ; -; FMC_LA_p[15] ; Missing drive strength and slew rate ; -; FMC_LA_p[16] ; Missing drive strength and slew rate ; -; FMC_LA_p[17] ; Missing drive strength and slew rate ; -; FMC_LA_p[18] ; Missing drive strength and slew rate ; -; FMC_LA_p[19] ; Missing drive strength and slew rate ; -; FMC_LA_p[20] ; Missing drive strength and slew rate ; -; FMC_LA_p[21] ; Missing drive strength and slew rate ; -; FMC_LA_p[22] ; Missing drive strength and slew rate ; -; FMC_LA_p[23] ; Missing drive strength and slew rate ; -; FMC_LA_p[24] ; Missing drive strength and slew rate ; -; FMC_LA_p[25] ; Missing drive strength and slew rate ; -; FMC_LA_p[26] ; Missing drive strength and slew rate ; -; FMC_LA_p[27] ; Missing drive strength and slew rate ; -; FMC_LA_p[28] ; Missing drive strength and slew rate ; -; FMC_LA_p[29] ; Missing drive strength and slew rate ; -; FMC_LA_p[30] ; Missing drive strength and slew rate ; -; FMC_LA_p[31] ; Missing drive strength and slew rate ; -; FMC_LA_p[32] ; Missing drive strength and slew rate ; -; FMC_LA_p[33] ; Missing drive strength and slew rate ; -; FMC_LA_n[0] ; Missing drive strength and slew rate ; -; FMC_LA_n[1] ; Missing drive strength and slew rate ; -; FMC_LA_n[2] ; Missing drive strength and slew rate ; -; FMC_LA_n[3] ; Missing drive strength and slew rate ; -; FMC_LA_n[4] ; Missing drive strength and slew rate ; -; FMC_LA_n[5] ; Missing drive strength and slew rate ; -; FMC_LA_n[6] ; Missing drive strength and slew rate ; -; FMC_LA_n[7] ; Missing drive strength and slew rate ; -; FMC_LA_n[8] ; Missing drive strength and slew rate ; -; FMC_LA_n[9] ; Missing drive strength and slew rate ; -; FMC_LA_n[10] ; Missing drive strength and slew rate ; -; FMC_LA_n[11] ; Missing drive strength and slew rate ; -; FMC_LA_n[12] ; Missing drive strength and slew rate ; -; FMC_LA_n[13] ; Missing drive strength and slew rate ; -; FMC_LA_n[14] ; Missing drive strength and slew rate ; -; FMC_LA_n[15] ; Missing drive strength and slew rate ; -; FMC_LA_n[16] ; Missing drive strength and slew rate ; -; FMC_LA_n[17] ; Missing drive strength and slew rate ; -; FMC_LA_n[18] ; Missing drive strength and slew rate ; -; FMC_LA_n[19] ; Missing drive strength and slew rate ; -; FMC_LA_n[20] ; Missing drive strength and slew rate ; -; FMC_LA_n[21] ; Missing drive strength and slew rate ; -; FMC_LA_n[22] ; Missing drive strength and slew rate ; -; FMC_LA_n[23] ; Missing drive strength and slew rate ; -; FMC_LA_n[24] ; Missing drive strength and slew rate ; -; FMC_LA_n[25] ; Missing drive strength and slew rate ; -; FMC_LA_n[26] ; Missing drive strength and slew rate ; -; FMC_LA_n[27] ; Missing drive strength and slew rate ; -; FMC_LA_n[28] ; Missing drive strength and slew rate ; -; FMC_LA_n[29] ; Missing drive strength and slew rate ; -; FMC_LA_n[30] ; Missing drive strength and slew rate ; -; FMC_LA_n[31] ; Missing drive strength and slew rate ; -; FMC_LA_n[32] ; Missing drive strength and slew rate ; -; FMC_LA_n[33] ; Missing drive strength and slew rate ; -; FMC_GA[0] ; Missing drive strength and slew rate ; -; FMC_GA[1] ; Missing drive strength and slew rate ; -; FMC_SCL ; Missing drive strength and slew rate ; -; FMC_SDA ; Missing drive strength and slew rate ; -; ETH_MDIO ; Missing drive strength and slew rate ; -; MPU_INT ; Missing drive strength and slew rate ; -; SRC_DP_HPD ; Missing drive strength and slew rate ; -; USBFX3_RESET_n ; Missing drive strength and slew rate ; -; USBFX3_PCLK ; Missing drive strength and slew rate ; -; USBFX3_CTL0_SLCS_n ; Missing drive strength and slew rate ; -; USBFX3_UART_TX ; Missing drive strength and slew rate ; -; USBFX3_UART_RX ; Missing drive strength and slew rate ; -; USBFX3_CTL10 ; Missing drive strength and slew rate ; -; USBFX3_CTL12_A0 ; Missing drive strength and slew rate ; -; USBFX3_CTL15_INT_n ; Missing drive strength and slew rate ; -; USBFX3_CTL1_SLWR_n ; Missing drive strength and slew rate ; -; USBFX3_CTL2_SLOE_n ; Missing drive strength and slew rate ; -; USBFX3_CTL3_SLRD_n ; Missing drive strength and slew rate ; -; USBFX3_CTL4_FLAGA ; Missing drive strength and slew rate ; -; USBFX3_CTL5_FLAGB ; Missing drive strength and slew rate ; -; USBFX3_CTL6 ; Missing drive strength and slew rate ; -; USBFX3_CTL7_PKTEND_n ; Missing drive strength and slew rate ; -; USBFX3_CTL8 ; Missing drive strength and slew rate ; -; USBFX3_CTL9 ; Missing drive strength and slew rate ; -; USBFX3_DQ[0] ; Missing drive strength and slew rate ; -; USBFX3_DQ[1] ; Missing drive strength and slew rate ; -; USBFX3_DQ[2] ; Missing drive strength and slew rate ; -; USBFX3_DQ[3] ; Missing drive strength and slew rate ; -; USBFX3_DQ[4] ; Missing drive strength and slew rate ; -; USBFX3_DQ[5] ; Missing drive strength and slew rate ; -; USBFX3_DQ[6] ; Missing drive strength and slew rate ; -; USBFX3_DQ[7] ; Missing drive strength and slew rate ; -; USBFX3_DQ[8] ; Missing drive strength and slew rate ; -; USBFX3_DQ[9] ; Missing drive strength and slew rate ; -; USBFX3_DQ[10] ; Missing drive strength and slew rate ; -; USBFX3_DQ[11] ; Missing drive strength and slew rate ; -; USBFX3_DQ[12] ; Missing drive strength and slew rate ; -; USBFX3_DQ[13] ; Missing drive strength and slew rate ; -; USBFX3_DQ[14] ; Missing drive strength and slew rate ; -; USBFX3_DQ[15] ; Missing drive strength and slew rate ; -; USBFX3_DQ[16] ; Missing drive strength and slew rate ; -; USBFX3_DQ[17] ; Missing drive strength and slew rate ; -; USBFX3_DQ[18] ; Missing drive strength and slew rate ; -; USBFX3_DQ[19] ; Missing drive strength and slew rate ; -; USBFX3_DQ[20] ; Missing drive strength and slew rate ; -; USBFX3_DQ[21] ; Missing drive strength and slew rate ; -; USBFX3_DQ[22] ; Missing drive strength and slew rate ; -; USBFX3_DQ[23] ; Missing drive strength and slew rate ; -; USBFX3_DQ[24] ; Missing drive strength and slew rate ; -; USBFX3_DQ[25] ; Missing drive strength and slew rate ; -; USBFX3_DQ[26] ; Missing drive strength and slew rate ; -; USBFX3_DQ[27] ; Missing drive strength and slew rate ; -; USBFX3_DQ[28] ; Missing drive strength and slew rate ; -; USBFX3_DQ[29] ; Missing drive strength and slew rate ; -; USBFX3_DQ[30] ; Missing drive strength and slew rate ; -; USBFX3_DQ[31] ; Missing drive strength and slew rate ; -; USBFX3_OTG_ID ; Missing drive strength and slew rate ; -; SMA_CLKOUT_p(n) ; Incomplete set of assignments ; -; FMC_GBTCLK_M2C_p[0](n) ; Incomplete set of assignments ; -; FMC_GBTCLK_M2C_p[1](n) ; Incomplete set of assignments ; -; FMC_REFCLK_p(n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[0](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[1](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[2](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[3](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[4](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[5](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[6](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[7](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[8](n) ; Incomplete set of assignments ; -; FMC_DP_C2M_p[9](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[0](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[1](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[2](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[3](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[4](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[5](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[6](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[7](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[8](n) ; Incomplete set of assignments ; -; FMC_DP_M2C_p[9](n) ; Incomplete set of assignments ; -; ETH_TX_p(n) ; Incomplete set of assignments ; -; ETH_RX_p(n) ; Incomplete set of assignments ; -; SMA_CLKIN_p(n) ; Incomplete set of assignments ; -; DDR4H_REFCLK_p(n) ; Incomplete set of assignments ; -+------------------------+--------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PLL Usage Summary ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ; ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst ; ; -; -- PLL Location ; IOPLL_2K ; -; -- PLL Bandwidth ; Auto ; -; -- PLL Bandwidth Range ; 7780000 to 4210000 Hz ; -; -- Reference Clock Frequency ; 3752 ps ; -; -- PLL VCO Frequency ; 938 ps ; -; -- PLL Operation Mode ; emif ; -; -- PLL Freq Min Lock ; 150.000000 MHz ; -; -- PLL Freq Max Lock ; 325.000000 MHz ; -; -- PLL Enable ; On ; -; -- M Counter ; 4 ; -; -- N Counter ; 1 ; -; -- Delay Chain Setting ; 0 ; -; -- PLL Refclk Select ; ; -; -- PLL Reference Clock Input 0 source ; pll_clkin_0_src_refclkin ; -; -- PLL Reference Clock Input 1 source ; pll_clkin_1_src_refclkin ; -; -- CLKIN(0) source ; N/A ; -; -- CLKIN(1) source ; N/A ; -; -- CLKIN(2) source ; N/A ; -; -- CLKIN(3) source ; N/A ; -; -- CORE_REFCLK source ; N/A ; -; -- PLL_CASCADE_IN source ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~refclk ; -; -- PLL Output Counter 0 ; ; -; -- Output Clock Frequency ; 1876 ps ; -; -- Duty Cycle ; 50 ; -; -- Phase Shift ; 117 ps ; -; -- C Counter Odd Divider Even Duty Enable ; Off ; -; -- C Counter ; 2 ; -; -- C Counter PH Mux PRST ; 1 ; -; -- C Counter PRST ; 1 ; -; -- C Counter Delay Chain Setting ; 0 ; -; -- LVDS Delay Chain Setting ; 0 ; -; -- PLL Output Counter 1 ; ; -; -- Output Clock Frequency ; 1876 ps ; -; -- Duty Cycle ; 50 ; -; -- Phase Shift ; 117 ps ; -; -- C Counter Odd Divider Even Duty Enable ; Off ; -; -- C Counter ; 2 ; -; -- C Counter PH Mux PRST ; 1 ; -; -- C Counter PRST ; 1 ; -; -- C Counter Delay Chain Setting ; 0 ; -; -- LVDS Delay Chain Setting ; 0 ; -; -- PLL Output Counter 2 ; ; -; -- Output Clock Frequency ; 1876 ps ; -; -- Duty Cycle ; 50 ; -; -- Phase Shift ; 117 ps ; -; -- C Counter Odd Divider Even Duty Enable ; Off ; -; -- C Counter ; 2 ; -; -- C Counter PH Mux PRST ; 1 ; -; -- C Counter PRST ; 1 ; -; -- C Counter Delay Chain Setting ; 0 ; -; -- LVDS Delay Chain Setting ; 0 ; -; -- PLL Output Counter 3 ; ; -; -- Output Clock Frequency ; 6566 ps ; -; -- Duty Cycle ; 50 ; -; -- Phase Shift ; 0 ps ; -; -- C Counter Odd Divider Even Duty Enable ; On ; -; -- C Counter ; 7 ; -; -- C Counter PH Mux PRST ; 0 ; -; -- C Counter PRST ; 1 ; -; -- C Counter Delay Chain Setting ; 0 ; -; -- LVDS Delay Chain Setting ; 0 ; -; -- PLL Output Counter 4 ; ; -; -- Output Clock Frequency ; 6566 ps ; -; -- Duty Cycle ; 50 ; -; -- Phase Shift ; 0 ps ; -; -- C Counter Odd Divider Even Duty Enable ; On ; -; -- C Counter ; 7 ; -; -- C Counter PH Mux PRST ; 0 ; -; -- C Counter PRST ; 1 ; -; -- C Counter Delay Chain Setting ; 0 ; -; ; ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~_Duplicate ; ; -; -- PLL Location ; IOPLL_2J ; -; -- PLL Bandwidth ; Auto ; -; -- PLL Bandwidth Range ; 7780000 to 4210000 Hz ; -; -- Reference Clock Frequency ; 3752 ps ; -; -- PLL VCO Frequency ; 938 ps ; -; -- PLL Operation Mode ; emif ; -; -- PLL Freq Min Lock ; 150.000000 MHz ; -; -- PLL Freq Max Lock ; 325.000000 MHz ; -; -- PLL Enable ; On ; -; -- M Counter ; 4 ; -; -- N Counter ; 1 ; -; -- Delay Chain Setting ; 0 ; -; -- PLL Refclk Select ; ; -; -- PLL Reference Clock Input 0 source ; pll_clkin_0_src_refclkin ; -; -- PLL Reference Clock Input 1 source ; pll_clkin_1_src_refclkin ; -; -- CLKIN(0) source ; N/A ; -; -- CLKIN(1) source ; N/A ; -; -- CLKIN(2) source ; N/A ; -; -- CLKIN(3) source ; N/A ; -; -- CORE_REFCLK source ; N/A ; -; -- PLL_CASCADE_IN source ; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~refclk_Duplicate ; -; ; ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------+ -; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M20Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; -+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------+ -; |a10s ; 5725.0 (0.5) ; 7225.0 (0.5) ; 1598.5 (0.0) ; 98.5 (0.0) ; 0.0 (0.0) ; 7134 (2) ; 10270 (0) ; 0 (0) ; 2099384 ; 134 ; 0 ; 439 ; 0 ; |a10s ; a10s ; work ; -; |a10s_ghrd:u0| ; 5556.6 (0.0) ; 7039.5 (0.0) ; 1579.3 (0.0) ; 96.5 (0.0) ; 0.0 (0.0) ; 6860 (0) ; 10045 (0) ; 0 (0) ; 2099384 ; 134 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0 ; a10s_ghrd ; a10s_ghrd ; -; |HAN_FanTempControll:fancmd| ; 490.3 (0.0) ; 506.0 (0.0) ; 16.2 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 836 (0) ; 321 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd ; HAN_FanTempControll ; a10s_ghrd_HAN_FanControll_10 ; -; |TEMP_FAN_LOOP:lp| ; 490.3 (0.0) ; 506.0 (0.0) ; 16.2 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 836 (0) ; 321 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp ; TEMP_FAN_LOOP ; work ; -; |FAN_ONOFF:OL| ; 52.5 (29.2) ; 60.0 (36.5) ; 7.5 (7.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 91 (50) ; 64 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL ; FAN_ONOFF ; work ; -; |CLOCKMEM:mm| ; 23.3 (23.3) ; 23.5 (23.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 41 (41) ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm ; CLOCKMEM ; work ; -; |FAN_TEMP_I2C:i2c1| ; 437.8 (115.5) ; 446.0 (116.0) ; 8.7 (0.5) ; 0.5 (0.0) ; 0.0 (0.0) ; 745 (180) ; 257 (107) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1 ; FAN_TEMP_I2C ; work ; -; |CLOCKMEM:k400| ; 23.0 (23.0) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400 ; CLOCKMEM ; work ; -; |I2C_READ_DATA:rd| ; 44.5 (44.5) ; 46.5 (46.5) ; 2.5 (2.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 66 (66) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd ; I2C_READ_DATA ; work ; -; |I2C_WRITE_BYTE:wrd| ; 31.0 (31.0) ; 33.0 (33.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd ; I2C_WRITE_BYTE ; work ; -; |I2C_WRITE_POINTER:wpt| ; 58.0 (58.0) ; 58.5 (58.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 93 (93) ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt ; I2C_WRITE_POINTER ; work ; -; |lpm_divide:Div0| ; 60.5 (0.0) ; 61.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div0 ; lpm_divide ; work ; -; |lpm_divide_04m:auto_generated| ; 60.5 (0.0) ; 61.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div0|lpm_divide_04m:auto_generated ; lpm_divide_04m ; work ; -; |sign_div_unsign_plh:divider| ; 60.5 (0.0) ; 61.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div0|lpm_divide_04m:auto_generated|sign_div_unsign_plh:divider ; sign_div_unsign_plh ; work ; -; |alt_u_div_5oe:divider| ; 60.5 (60.5) ; 61.0 (61.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (116) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div0|lpm_divide_04m:auto_generated|sign_div_unsign_plh:divider|alt_u_div_5oe:divider ; alt_u_div_5oe ; work ; -; |lpm_divide:Div1| ; 105.3 (0.0) ; 108.0 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 206 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div1 ; lpm_divide ; work ; -; |lpm_divide_d5m:auto_generated| ; 105.3 (0.0) ; 108.0 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 206 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div1|lpm_divide_d5m:auto_generated ; lpm_divide_d5m ; work ; -; |sign_div_unsign_7nh:divider| ; 105.3 (0.0) ; 108.0 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 206 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div1|lpm_divide_d5m:auto_generated|sign_div_unsign_7nh:divider ; sign_div_unsign_7nh ; work ; -; |alt_u_div_1re:divider| ; 105.3 (105.3) ; 108.0 (108.0) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 206 (206) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|lpm_divide:Div1|lpm_divide_d5m:auto_generated|sign_div_unsign_7nh:divider|alt_u_div_1re:divider ; alt_u_div_1re ; work ; -; |a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps| ; 1012.1 (0.0) ; 1918.8 (0.0) ; 928.4 (0.0) ; 21.7 (0.0) ; 0.0 (0.0) ; 1056 (0) ; 3606 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps ; a10s_ghrd_altera_arria10_hps_181_paoasmy ; a10s_ghrd_altera_arria10_hps_181 ; -; |a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io ; a10s_ghrd_altera_arria10_hps_io_181_vma6nca ; a10s_ghrd_altera_arria10_hps_io_181 ; -; |a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border ; a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces| ; 1012.1 (0.0) ; 1918.8 (0.0) ; 928.4 (0.0) ; 21.7 (0.0) ; 0.0 (0.0) ; 1056 (0) ; 3606 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces ; a10s_ghrd_altera_arria10_interface_generator_140_q66yweq ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |a10_hps_emif_interface:emif_interface| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface ; a10_hps_emif_interface ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |hps_emif_interface_to_ddr:inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface|hps_emif_interface_to_ddr:inst ; hps_emif_interface_to_ddr ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |twentynm_hps_rl_interface_fpga2hps:fpga2hps| ; 323.3 (0.0) ; 659.6 (0.0) ; 344.5 (0.0) ; 8.1 (0.0) ; 0.0 (0.0) ; 222 (0) ; 1301 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps ; twentynm_hps_rl_interface_fpga2hps ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_ar_user| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_ar_user ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_cache_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_cache_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_len_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_len_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:araddr_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:araddr_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_ar_user| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_ar_user ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_cache_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_cache_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_len_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_len_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:awaddr_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:awaddr_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:w_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:w_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:wdata_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:wdata_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |f2s_rl_adp:f2s_rl_adp_inst| ; 302.3 (106.1) ; 638.6 (166.5) ; 344.5 (62.6) ; 8.1 (2.2) ; 0.0 (0.0) ; 180 (0) ; 1301 (347) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst ; f2s_rl_adp ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_ar| ; 3.7 (3.7) ; 29.7 (29.7) ; 26.0 (26.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_aw| ; 4.7 (4.7) ; 28.0 (28.0) ; 23.7 (23.7) ; 0.4 (0.4) ; 0.0 (0.0) ; 9 (9) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_b| ; 6.0 (6.0) ; 8.3 (8.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_r| ; 139.6 (139.6) ; 271.5 (271.5) ; 135.7 (135.7) ; 3.8 (3.8) ; 0.0 (0.0) ; 143 (143) ; 522 (522) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_w| ; 42.2 (42.2) ; 134.8 (134.8) ; 94.3 (94.3) ; 1.7 (1.7) ; 0.0 (0.0) ; 9 (9) ; 293 (293) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |twentynm_hps_rl_interface_hps2fpga:hps2fpga| ; 228.3 (0.0) ; 418.7 (0.0) ; 198.2 (0.0) ; 7.8 (0.0) ; 0.0 (0.0) ; 257 (0) ; 776 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga ; twentynm_hps_rl_interface_hps2fpga ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:b_id_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:b_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:r_id_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:r_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:rdata_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:rdata_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |s2f_rl_adp:s2f_rl_adp_ins| ; 228.3 (0.0) ; 418.7 (0.0) ; 198.2 (0.0) ; 7.8 (0.0) ; 0.0 (0.0) ; 257 (0) ; 776 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins ; s2f_rl_adp ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_ar| ; 41.1 (41.1) ; 94.0 (94.0) ; 53.0 (53.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 49 (49) ; 159 (159) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_aw| ; 33.8 (33.8) ; 77.2 (77.2) ; 46.0 (46.0) ; 2.6 (2.6) ; 0.0 (0.0) ; 30 (30) ; 161 (161) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_b| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_r| ; 65.8 (65.8) ; 65.7 (65.7) ; 0.0 (0.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 79 (79) ; 143 (143) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_w| ; 77.5 (77.5) ; 172.2 (172.2) ; 99.7 (99.7) ; 5.0 (5.0) ; 0.0 (0.0) ; 86 (86) ; 299 (299) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight| ; 138.9 (0.0) ; 307.0 (0.0) ; 171.1 (0.0) ; 3.0 (0.0) ; 0.0 (0.0) ; 143 (0) ; 580 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight ; twentynm_hps_rl_interface_hps2fpga_light_weight ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:b_id_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:b_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:r_id_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:r_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:rdata_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:rdata_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |s2f_rl_adp:s2f_rl_adp_inst| ; 138.9 (24.4) ; 307.0 (58.8) ; 171.1 (35.9) ; 3.0 (1.5) ; 0.0 (0.0) ; 143 (0) ; 580 (136) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst ; s2f_rl_adp ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_ar| ; 30.4 (30.4) ; 58.9 (58.9) ; 29.0 (29.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 37 (37) ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_aw| ; 27.1 (27.1) ; 51.2 (51.2) ; 25.2 (25.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 31 (31) ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_b| ; 5.9 (5.9) ; 8.7 (8.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_r| ; 6.7 (6.7) ; 38.4 (38.4) ; 31.8 (31.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_s2f_w| ; 44.4 (44.4) ; 90.9 (90.9) ; 46.5 (46.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (52) ; 158 (158) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |twentynm_hps_rl_mode2_fpga2sdram:f2sdram| ; 321.6 (0.0) ; 533.4 (0.0) ; 214.6 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 434 (0) ; 949 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram ; twentynm_hps_rl_mode2_fpga2sdram ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |f2s_rl_delay_adp:f2s_rl_adp_inst_0| ; 321.6 (0.0) ; 533.4 (0.0) ; 214.6 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 434 (0) ; 949 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0 ; f2s_rl_delay_adp ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:_w_valid_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:_w_valid_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_ar_user| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_ar_user ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_burst_alen| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_burst_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_cache_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_cache_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_len_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_len_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_lock_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_lock_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_prot_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_prot_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_size_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_size_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:ar_valid_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_valid_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:araddr_alen| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:araddr_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_ar_user| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_ar_user ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_burst_alen| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_burst_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_cache_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_cache_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_len_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_len_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_lock_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_lock_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_prot_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_prot_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_size_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_size_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:aw_valid_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_valid_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:awaddr_alen| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:awaddr_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:b_ready_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:b_ready_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:r_ready_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:r_ready_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:w_id_alen| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_id_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:w_last_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_last_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:w_strb_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_strb_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |alentar:wdata_alen| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:wdata_alen ; alentar ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |f2s_rl_adp:f2s_rl_adp_inst| ; 293.1 (0.0) ; 504.9 (0.0) ; 214.6 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 377 (0) ; 949 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst ; f2s_rl_adp ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_ar| ; 19.0 (19.0) ; 34.0 (34.0) ; 15.0 (15.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (38) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_aw| ; 19.5 (19.5) ; 34.5 (34.5) ; 15.0 (15.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 39 (39) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_b| ; 5.0 (5.0) ; 5.0 (5.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_r| ; 135.8 (135.8) ; 282.8 (282.8) ; 148.5 (148.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 139 (139) ; 519 (519) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |full_reg_slice:i_f2s_w| ; 113.8 (113.8) ; 148.7 (148.7) ; 36.2 (36.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 153 (153) ; 293 (293) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; full_reg_slice ; a10s_ghrd_altera_arria10_interface_generator_140 ; -; |a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2| ; 48.0 (0.0) ; 50.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (0) ; 4 (0) ; 0 (0) ; 2097152 ; 128 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2 ; a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa ; a10s_ghrd_altera_avalon_onchip_memory2_181 ; -; |altsyncram:the_altsyncram| ; 48.0 (0.0) ; 50.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (0) ; 4 (0) ; 0 (0) ; 2097152 ; 128 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram ; altsyncram ; work ; -; |altsyncram_0jk1:auto_generated| ; 48.0 (1.3) ; 50.0 (2.0) ; 2.0 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (0) ; 4 (4) ; 0 (0) ; 2097152 ; 128 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated ; altsyncram_0jk1 ; work ; -; |decode_afa:decode3| ; 8.0 (8.0) ; 8.0 (8.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3 ; decode_afa ; work ; -; |mux_q9b:mux2| ; 38.7 (38.7) ; 40.0 (40.0) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|mux_q9b:mux2 ; mux_q9b ; work ; -; |a10s_ghrd_altera_avalon_pio_181_b3m6h3q:led_pio| ; 2.0 (2.0) ; 3.2 (3.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_b3m6h3q:led_pio ; a10s_ghrd_altera_avalon_pio_181_b3m6h3q ; a10s_ghrd_altera_avalon_pio_181 ; -; |a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio| ; 4.3 (4.3) ; 5.8 (5.8) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio ; a10s_ghrd_altera_avalon_pio_181_na6njny ; a10s_ghrd_altera_avalon_pio_181 ; -; |a10s_ghrd_altera_avalon_pio_181_u6z2bzq:button_pio| ; 5.5 (5.5) ; 6.3 (6.3) ; 1.3 (1.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 8 (8) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_u6z2bzq:button_pio ; a10s_ghrd_altera_avalon_pio_181_u6z2bzq ; a10s_ghrd_altera_avalon_pio_181 ; -; |a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps ; a10s_ghrd_altera_emif_a10_hps_181_oeawlci ; a10s_ghrd_altera_emif_a10_hps_181 ; -; |a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux:io_aux_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux:io_aux_inst ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_bufs:bufs_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst ; altera_emif_arch_nf_bufs ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b ; altera_emif_arch_nf_buf_bdir_df ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b ; altera_emif_arch_nf_buf_bdir_df ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b ; altera_emif_arch_nf_buf_bdir_df ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b ; altera_emif_arch_nf_buf_bdir_df ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[0].b ; altera_emif_arch_nf_buf_bdir_se ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[1].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[1].b ; altera_emif_arch_nf_buf_bdir_se ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[2].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[2].b ; altera_emif_arch_nf_buf_bdir_se ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[3].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[3].b ; altera_emif_arch_nf_buf_bdir_se ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 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0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[3].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[4].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[4].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[5].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[5].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[6].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[6].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[7].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[7].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[8].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[8].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[9].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[9].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_act_n.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_act_n.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[1].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[1].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_bg.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_bg.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_cke.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cke.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_cs_n.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cs_n.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_odt.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_odt.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_par.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_par.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b ; altera_emif_arch_nf_buf_udir_se_o ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst ; altera_emif_arch_nf_io_tiles_wrap ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_io_tiles:io_tiles_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst ; altera_emif_arch_nf_io_tiles ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_oct:oct_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst ; altera_emif_arch_nf_oct ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |altera_emif_arch_nf_pll:pll_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst ; altera_emif_arch_nf_pll ; a10s_ghrd_altera_emif_arch_nf_181 ; -; |a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m| ; 367.8 (0.0) ; 432.2 (0.0) ; 73.8 (0.0) ; 9.5 (0.0) ; 0.0 (0.0) ; 560 (0) ; 490 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m ; a10s_ghrd_altera_jtag_avalon_master_181_winiqja ; a10s_ghrd_altera_jtag_avalon_master_181 ; -; |altera_avalon_packets_to_master:transacto| ; 143.3 (0.0) ; 160.2 (0.0) ; 16.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 214 (0) ; 167 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto ; altera_avalon_packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |packets_to_master:p2m| ; 143.3 (143.3) ; 160.2 (160.2) ; 16.8 (16.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 214 (214) ; 167 (167) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |altera_avalon_sc_fifo:fifo| ; 14.7 (14.7) ; 15.0 (15.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (27) ; 18 (18) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_tom1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated ; altsyncram_tom1 ; work ; -; |altera_avalon_st_bytes_to_packets:b2p| ; 7.8 (7.8) ; 10.3 (10.3) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p ; altera_avalon_st_bytes_to_packets ; a10s_ghrd_altera_avalon_st_bytes_to_packets_181 ; -; |altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master| ; 189.2 (0.0) ; 231.5 (0.0) ; 51.7 (0.0) ; 9.5 (0.0) ; 0.0 (0.0) ; 281 (0) ; 275 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; altera_avalon_st_jtag_interface ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_dc_streaming:normal.jtag_dc_streaming| ; 188.2 (0.0) ; 230.2 (0.0) ; 51.6 (0.0) ; 9.5 (0.0) ; 0.0 (0.0) ; 278 (0) ; 275 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; altera_jtag_dc_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_clock_crosser:sink_crosser| ; 15.5 (4.2) ; 23.9 (8.9) ; 13.3 (6.0) ; 4.8 (1.3) ; 0.0 (0.0) ; 9 (4) ; 47 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_pipeline_base:output_stage| ; 7.3 (7.3) ; 11.1 (11.1) ; 3.8 (3.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; altera_avalon_st_pipeline_base ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 1.3 (1.3) ; 1.3 (1.3) ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 2.8 (2.8) ; 2.7 (2.7) ; 2.4 (2.4) ; 2.5 (2.5) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_src_crosser:source_crosser| ; 2.8 (1.8) ; 11.7 (8.2) ; 10.7 (7.4) ; 1.8 (1.1) ; 0.0 (0.0) ; 1 (0) ; 27 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; altera_jtag_src_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_control_signal_crosser:crosser| ; 1.0 (0.6) ; 3.5 (0.8) ; 3.2 (0.3) ; 0.8 (0.1) ; 0.0 (0.0) ; 1 (1) ; 9 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; altera_jtag_control_signal_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:synchronizer| ; 0.4 (0.4) ; 2.8 (2.8) ; 3.0 (3.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_streaming:jtag_streaming| ; 169.3 (164.9) ; 193.3 (182.0) ; 26.3 (18.1) ; 2.3 (1.1) ; 0.0 (0.0) ; 268 (262) ; 198 (179) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; altera_jtag_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_inserter:idle_inserter| ; 1.0 (1.0) ; 1.8 (1.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter ; altera_avalon_st_idle_inserter ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_remover:idle_remover| ; 2.5 (2.5) ; 2.3 (2.3) ; 0.2 (0.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover ; altera_avalon_st_idle_remover ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:clock_sense_reset_n_synchronizer| ; 0.7 (0.7) ; 3.0 (3.0) ; 3.0 (3.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_sensor_synchronizer| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_to_sample_div2_synchronizer| ; 0.3 (0.3) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:reset_to_sample_synchronizer| ; 0.0 (0.0) ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:synchronizer| ; 0.5 (0.5) ; 1.3 (1.3) ; 1.3 (1.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_sld_node:node| ; 1.1 (0.0) ; 1.3 (0.0) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; altera_jtag_sld_node ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |sld_virtual_jtag_basic:sld_virtual_jtag_component| ; 1.1 (1.1) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; sld_virtual_jtag_basic ; work ; -; |altera_avalon_st_packets_to_bytes:p2b| ; 12.7 (12.7) ; 14.2 (14.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b ; altera_avalon_st_packets_to_bytes ; a10s_ghrd_altera_avalon_st_packets_to_bytes_181 ; -; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.0 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m| ; 343.4 (0.0) ; 411.1 (0.0) ; 76.7 (0.0) ; 9.0 (0.0) ; 0.0 (0.0) ; 527 (0) ; 464 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m ; a10s_ghrd_altera_jtag_avalon_master_181_winiqja ; a10s_ghrd_altera_jtag_avalon_master_181 ; -; |altera_avalon_packets_to_master:transacto| ; 120.2 (0.0) ; 135.8 (0.0) ; 18.2 (0.0) ; 2.5 (0.0) ; 0.0 (0.0) ; 181 (0) ; 137 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto ; altera_avalon_packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |packets_to_master:p2m| ; 120.2 (120.2) ; 135.8 (135.8) ; 18.2 (18.2) ; 2.5 (2.5) ; 0.0 (0.0) ; 181 (181) ; 137 (137) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |altera_avalon_sc_fifo:fifo| ; 14.2 (14.2) ; 16.2 (16.2) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (27) ; 17 (17) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_tom1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated ; altsyncram_tom1 ; work ; -; |altera_avalon_st_bytes_to_packets:b2p| ; 8.5 (8.5) ; 10.3 (10.3) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p ; altera_avalon_st_bytes_to_packets ; a10s_ghrd_altera_avalon_st_bytes_to_packets_181 ; -; |altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master| ; 187.5 (0.0) ; 233.8 (0.0) ; 52.8 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 281 (0) ; 280 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; altera_avalon_st_jtag_interface ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_dc_streaming:normal.jtag_dc_streaming| ; 186.2 (0.0) ; 232.7 (0.0) ; 52.9 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 278 (0) ; 280 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; altera_jtag_dc_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_clock_crosser:sink_crosser| ; 12.7 (2.0) ; 26.6 (9.6) ; 16.4 (7.6) ; 2.5 (0.0) ; 0.0 (0.0) ; 9 (4) ; 48 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_pipeline_base:output_stage| ; 7.7 (7.7) ; 12.0 (12.0) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; altera_avalon_st_pipeline_base ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.3 (0.3) ; 1.5 (1.5) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 2.8 (2.8) ; 3.5 (3.5) ; 3.2 (3.2) ; 2.5 (2.5) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_src_crosser:source_crosser| ; 2.0 (1.8) ; 12.1 (8.6) ; 11.1 (7.8) ; 1.0 (1.0) ; 0.0 (0.0) ; 1 (0) ; 27 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; altera_jtag_src_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_control_signal_crosser:crosser| ; 0.3 (0.5) ; 3.5 (0.7) ; 3.3 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 9 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; altera_jtag_control_signal_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:synchronizer| ; -0.3 (-0.3) ; 2.8 (2.8) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_streaming:jtag_streaming| ; 171.5 (166.9) ; 192.5 (181.0) ; 24.0 (16.3) ; 3.0 (2.2) ; 0.0 (0.0) ; 268 (262) ; 202 (183) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; altera_jtag_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_inserter:idle_inserter| ; 1.1 (1.1) ; 1.5 (1.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter ; altera_avalon_st_idle_inserter ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_remover:idle_remover| ; 2.7 (2.7) ; 2.8 (2.8) ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover ; altera_avalon_st_idle_remover ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:clock_sense_reset_n_synchronizer| ; 0.0 (0.0) ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_sensor_synchronizer| ; 0.0 (0.0) ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_to_sample_div2_synchronizer| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:reset_to_sample_synchronizer| ; 0.8 (0.8) ; 1.5 (1.5) ; 1.2 (1.2) ; 0.5 (0.5) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:synchronizer| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_sld_node:node| ; 1.2 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; altera_jtag_sld_node ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |sld_virtual_jtag_basic:sld_virtual_jtag_component| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; sld_virtual_jtag_basic ; work ; -; |altera_avalon_st_packets_to_bytes:p2b| ; 13.3 (13.3) ; 13.9 (13.9) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b ; altera_avalon_st_packets_to_bytes ; a10s_ghrd_altera_avalon_st_packets_to_bytes_181 ; -; |altera_reset_controller:rst_controller| ; -0.3 (0.0) ; 1.0 (0.0) ; 1.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; -0.3 (-0.3) ; 1.0 (1.0) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m| ; 367.9 (0.0) ; 434.1 (0.0) ; 72.2 (0.0) ; 6.0 (0.0) ; 0.0 (0.0) ; 566 (0) ; 488 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m ; a10s_ghrd_altera_jtag_avalon_master_181_winiqja ; a10s_ghrd_altera_jtag_avalon_master_181 ; -; |altera_avalon_packets_to_master:transacto| ; 148.2 (0.0) ; 164.8 (0.0) ; 18.2 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 220 (0) ; 170 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto ; altera_avalon_packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |packets_to_master:p2m| ; 148.2 (148.2) ; 164.8 (164.8) ; 18.2 (18.2) ; 1.6 (1.6) ; 0.0 (0.0) ; 220 (220) ; 170 (170) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; packets_to_master ; a10s_ghrd_altera_avalon_packets_to_master_181 ; -; |altera_avalon_sc_fifo:fifo| ; 14.3 (14.3) ; 15.7 (15.7) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (27) ; 17 (17) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_tom1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated ; altsyncram_tom1 ; work ; -; |altera_avalon_st_bytes_to_packets:b2p| ; 9.5 (9.5) ; 10.8 (10.8) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 13 (13) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p ; altera_avalon_st_bytes_to_packets ; a10s_ghrd_altera_avalon_st_bytes_to_packets_181 ; -; |altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master| ; 181.5 (0.0) ; 227.7 (0.0) ; 49.2 (0.0) ; 3.0 (0.0) ; 0.0 (0.0) ; 281 (0) ; 270 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; altera_avalon_st_jtag_interface ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_dc_streaming:normal.jtag_dc_streaming| ; 180.1 (0.0) ; 226.4 (0.0) ; 49.2 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 278 (0) ; 270 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; altera_jtag_dc_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_clock_crosser:sink_crosser| ; 11.3 (2.3) ; 23.3 (8.3) ; 13.3 (6.2) ; 1.3 (0.3) ; 0.0 (0.0) ; 9 (4) ; 47 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_pipeline_base:output_stage| ; 8.3 (8.3) ; 10.8 (10.8) ; 3.4 (3.4) ; 1.0 (1.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; altera_avalon_st_pipeline_base ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.3 (0.3) ; 0.8 (0.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.3 (0.3) ; 3.5 (3.5) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_src_crosser:source_crosser| ; 1.1 (1.1) ; 11.1 (7.6) ; 10.2 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 1 (0) ; 27 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; altera_jtag_src_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_jtag_control_signal_crosser:crosser| ; 0.0 (0.0) ; 3.5 (0.5) ; 3.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 9 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; altera_jtag_control_signal_crosser ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:synchronizer| ; 0.0 (0.0) ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_streaming:jtag_streaming| ; 167.8 (163.5) ; 190.5 (180.1) ; 24.2 (17.8) ; 1.5 (1.3) ; 0.0 (0.0) ; 268 (262) ; 193 (174) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; altera_jtag_streaming ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_inserter:idle_inserter| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter ; altera_avalon_st_idle_inserter ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_avalon_st_idle_remover:idle_remover| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover ; altera_avalon_st_idle_remover ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |altera_std_synchronizer:clock_sense_reset_n_synchronizer| ; 0.0 (0.0) ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_sensor_synchronizer| ; 0.0 (0.0) ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:clock_to_sample_div2_synchronizer| ; 0.5 (0.5) ; 1.3 (1.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:reset_to_sample_synchronizer| ; 0.3 (0.3) ; 1.3 (1.3) ; 1.3 (1.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; altera_std_synchronizer ; work ; -; |altera_std_synchronizer:synchronizer| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; altera_std_synchronizer ; work ; -; |altera_jtag_sld_node:node| ; 1.3 (0.0) ; 1.3 (0.0) ; 0.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; altera_jtag_sld_node ; a10s_ghrd_altera_jtag_dc_streaming_181 ; -; |sld_virtual_jtag_basic:sld_virtual_jtag_component| ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; sld_virtual_jtag_basic ; work ; -; |altera_avalon_st_packets_to_bytes:p2b| ; 14.3 (14.3) ; 14.0 (14.0) ; 0.7 (0.7) ; 1.0 (1.0) ; 0.0 (0.0) ; 25 (25) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b ; altera_avalon_st_packets_to_bytes ; a10s_ghrd_altera_avalon_st_packets_to_bytes_181 ; -; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.0 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1| ; 223.6 (0.0) ; 244.2 (0.0) ; 20.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 398 (0) ; 240 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1 ; a10s_ghrd_altera_mm_interconnect_181_2w3xhoq ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux| ; 0.8 (0.8) ; 1.5 (1.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux| ; 40.7 (36.3) ; 41.7 (37.3) ; 1.0 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 93 (88) ; 8 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux ; a10s_ghrd_altera_merlin_multiplexer_181_zoswswa ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_merlin_arbitrator:arb| ; 4.3 (4.3) ; 4.4 (4.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo| ; 27.3 (27.3) ; 39.0 (39.0) ; 11.7 (11.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (69) ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo| ; 13.5 (13.5) ; 16.7 (16.7) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 21 (21) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent| ; 49.3 (26.2) ; 49.5 (26.8) ; 0.2 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 86 (47) ; 15 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent ; altera_merlin_axi_master_ni ; a10s_ghrd_altera_merlin_axi_master_ni_181 ; -; |altera_merlin_address_alignment:align_address_to_size| ; 22.7 (22.7) ; 22.7 (22.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 39 (39) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; a10s_ghrd_altera_merlin_axi_master_ni_181 ; -; |altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter| ; 77.2 (0.0) ; 79.5 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 101 (0) ; 108 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter ; altera_merlin_burst_adapter ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 77.2 (76.2) ; 79.5 (78.5) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 101 (100) ; 108 (108) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_address_alignment:align_address_to_size| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_master_agent:fpga_m_master_agent| ; 1.3 (1.3) ; 2.0 (2.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent ; altera_merlin_master_agent ; a10s_ghrd_altera_merlin_master_agent_181 ; -; |altera_merlin_slave_agent:pb_lwh2f_s0_agent| ; 13.4 (3.2) ; 14.3 (3.8) ; 0.8 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_burst_uncompressor:uncompressor| ; 10.3 (10.3) ; 10.4 (10.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2| ; 67.2 (0.0) ; 73.0 (0.0) ; 5.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 123 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2 ; a10s_ghrd_altera_mm_interconnect_181_6tzbopq ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux| ; 7.3 (7.3) ; 7.3 (7.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux| ; 9.4 (9.4) ; 9.7 (9.7) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (36) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux ; a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |a10s_ghrd_altera_merlin_router_181_45pxmci:router| ; 3.2 (3.2) ; 3.7 (3.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router ; a10s_ghrd_altera_merlin_router_181_45pxmci ; a10s_ghrd_altera_merlin_router_181 ; -; |altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo| ; 5.0 (5.0) ; 5.7 (5.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo| ; 5.8 (5.8) ; 5.8 (5.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo| ; 3.7 (3.7) ; 3.9 (3.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo| ; 5.2 (5.2) ; 5.2 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo| ; 2.1 (2.1) ; 2.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_merlin_master_agent:pb_lwh2f_m0_agent| ; 0.0 (0.0) ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent ; altera_merlin_master_agent ; a10s_ghrd_altera_merlin_master_agent_181 ; -; |altera_merlin_slave_agent:ilc_avalon_slave_agent| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_agent:sysid_qsys_control_slave_agent| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_translator:button_pio_s1_translator| ; 1.7 (1.7) ; 3.2 (3.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_slave_translator:dipsw_pio_s1_translator| ; 2.6 (2.6) ; 3.1 (3.1) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_slave_translator:ilc_avalon_slave_translator| ; 0.3 (0.3) ; 1.1 (1.1) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_slave_translator:led_pio_s1_translator| ; 3.2 (3.2) ; 4.0 (4.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_slave_translator:sysid_qsys_control_slave_translator| ; 5.8 (5.8) ; 6.4 (6.4) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter| ; 8.5 (8.5) ; 8.8 (8.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5| ; 743.9 (0.0) ; 815.0 (0.0) ; 88.2 (0.0) ; 17.1 (0.0) ; 0.0 (0.0) ; 538 (0) ; 1346 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5 ; a10s_ghrd_altera_mm_interconnect_181_72qrvsa ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux| ; 0.5 (0.5) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_edscloq ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux| ; 83.4 (83.4) ; 88.1 (88.1) ; 4.7 (4.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 153 (153) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux ; a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent| ; 608.4 (2.7) ; 643.6 (2.7) ; 52.1 (0.0) ; 16.9 (0.0) ; 0.0 (0.0) ; 217 (5) ; 1337 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent ; altera_merlin_axi_slave_ni ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_avalon_sc_fifo:read_rsp_fifo| ; 73.0 (73.0) ; 80.5 (80.5) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 43 (43) ; 154 (154) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_avalon_sc_fifo:write_rsp_fifo| ; 532.5 (532.5) ; 560.4 (560.4) ; 44.7 (44.7) ; 16.9 (16.9) ; 0.0 (0.0) ; 169 (169) ; 1181 (1181) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_merlin_master_agent:f2sdram_m_master_agent| ; 8.2 (8.2) ; 9.0 (9.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent ; altera_merlin_master_agent ; a10s_ghrd_altera_merlin_master_agent_181 ; -; |altera_merlin_traffic_limiter:f2sdram_m_master_limiter| ; 7.2 (7.2) ; 7.7 (7.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter| ; 36.2 (36.2) ; 65.7 (65.7) ; 29.6 (29.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 144 (144) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4| ; 746.5 (0.0) ; 815.2 (0.0) ; 88.7 (0.0) ; 20.0 (0.0) ; 0.0 (0.0) ; 533 (0) ; 1351 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4 ; a10s_ghrd_altera_mm_interconnect_181_gwzlhmy ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_edscloq ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux| ; 83.0 (83.0) ; 89.4 (89.4) ; 6.9 (6.9) ; 0.5 (0.5) ; 0.0 (0.0) ; 148 (148) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux ; a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent| ; 610.0 (2.8) ; 643.3 (2.8) ; 52.7 (0.0) ; 19.3 (0.0) ; 0.0 (0.0) ; 217 (5) ; 1341 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent ; altera_merlin_axi_slave_ni ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_avalon_sc_fifo:read_rsp_fifo| ; 72.3 (72.3) ; 79.7 (79.7) ; 7.3 (7.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 43 (43) ; 157 (157) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_avalon_sc_fifo:write_rsp_fifo| ; 534.8 (534.8) ; 560.8 (560.8) ; 45.3 (45.3) ; 19.3 (19.3) ; 0.0 (0.0) ; 169 (169) ; 1182 (1182) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_merlin_axi_slave_ni_181 ; -; |altera_merlin_master_agent:hps_m_master_agent| ; 9.2 (9.2) ; 9.7 (9.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent ; altera_merlin_master_agent ; a10s_ghrd_altera_merlin_master_agent_181 ; -; |altera_merlin_traffic_limiter:hps_m_master_limiter| ; 7.0 (7.0) ; 7.3 (7.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter| ; 36.3 (36.3) ; 64.5 (64.5) ; 28.3 (28.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 144 (144) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3| ; 30.4 (0.0) ; 52.3 (0.0) ; 22.3 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 53 (0) ; 95 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3 ; a10s_ghrd_altera_mm_interconnect_181_opfju6i ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux| ; 1.0 (1.0) ; 1.3 (1.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux| ; 0.6 (0.6) ; 0.7 (0.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux ; a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo| ; 1.3 (1.3) ; 1.5 (1.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo| ; 2.0 (2.0) ; 2.6 (2.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo| ; 2.0 (2.0) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser| ; 4.1 (0.0) ; 16.9 (0.0) ; 12.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (0) ; 34 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 4.1 (3.7) ; 16.9 (15.8) ; 12.8 (12.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 34 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.3 (0.3) ; 0.4 (0.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.1 (0.1) ; 0.7 (0.7) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_001| ; 3.8 (0.0) ; 5.4 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 3.8 (2.8) ; 5.4 (4.2) ; 1.6 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 12 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.5 (0.5) ; 0.8 (0.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.4 (0.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_002| ; 2.4 (0.0) ; 4.4 (0.0) ; 2.2 (0.0) ; 0.2 (0.0) ; 0.0 (0.0) ; 2 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 2.4 (1.4) ; 4.4 (2.8) ; 2.2 (1.6) ; 0.2 (0.1) ; 0.0 (0.0) ; 2 (2) ; 10 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.1 (0.1) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.5 (0.5) ; 0.6 (0.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_003| ; 1.6 (0.0) ; 3.6 (0.0) ; 2.2 (0.0) ; 0.2 (0.0) ; 0.0 (0.0) ; 2 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 1.6 (1.2) ; 3.6 (2.0) ; 2.2 (0.9) ; 0.2 (0.1) ; 0.0 (0.0) ; 2 (2) ; 8 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.2 (0.2) ; 0.8 (0.8) ; 0.7 (0.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.3 (0.3) ; 0.8 (0.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_merlin_master_agent:h2fw_clockbridge_m0_agent| ; -0.2 (-0.2) ; 0.3 (0.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent ; altera_merlin_master_agent ; a10s_ghrd_altera_merlin_master_agent_181 ; -; |altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_agent:sevensig_avalon_slave_0_agent| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator| ; 2.0 (2.0) ; 3.0 (3.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_slave_translator:sevensig_avalon_slave_0_translator| ; 2.0 (2.0) ; 2.4 (2.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter| ; 4.8 (4.8) ; 4.8 (4.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0| ; 908.4 (0.0) ; 1003.0 (0.0) ; 99.8 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 1329 (0) ; 1049 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0 ; a10s_ghrd_altera_mm_interconnect_181_ss6apia ; a10s_ghrd_altera_mm_interconnect_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001 ; a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux| ; 1.7 (1.7) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux ; a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux_001| ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux_001 ; a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i ; a10s_ghrd_altera_merlin_demultiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux ; a10s_ghrd_altera_merlin_multiplexer_181_owhafhq ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001| ; 87.1 (87.1) ; 88.8 (88.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 184 (184) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001 ; a10s_ghrd_altera_merlin_multiplexer_181_owhafhq ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux| ; 10.6 (8.3) ; 13.4 (10.2) ; 2.8 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (25) ; 7 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux ; a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_merlin_arbitrator:arb| ; 2.3 (2.3) ; 3.2 (3.2) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001| ; 40.7 (37.2) ; 40.5 (37.3) ; 0.0 (0.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 75 (70) ; 6 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001 ; a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |altera_merlin_arbitrator:arb| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; a10s_ghrd_altera_merlin_multiplexer_181 ; -; |a10s_ghrd_altera_merlin_router_181_6b3wcra:router| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router ; a10s_ghrd_altera_merlin_router_181_6b3wcra ; a10s_ghrd_altera_merlin_router_181 ; -; |a10s_ghrd_altera_merlin_router_181_6b3wcra:router_001| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router_001 ; a10s_ghrd_altera_merlin_router_181_6b3wcra ; a10s_ghrd_altera_merlin_router_181 ; -; |altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo| ; 13.7 (13.7) ; 15.1 (15.1) ; 1.4 (1.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 20 (20) ; 13 (13) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_drm1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated ; altsyncram_drm1 ; work ; -; |altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo| ; 114.5 (114.5) ; 122.3 (122.3) ; 9.7 (9.7) ; 1.9 (1.9) ; 0.0 (0.0) ; 45 (45) ; 243 (243) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo| ; 10.2 (10.2) ; 10.5 (10.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo| ; 21.1 (21.1) ; 25.0 (25.0) ; 3.9 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (30) ; 52 (52) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; a10s_ghrd_altera_avalon_sc_fifo_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser| ; 23.5 (0.0) ; 38.6 (0.0) ; 16.4 (0.0) ; 1.3 (0.0) ; 0.0 (0.0) ; 5 (0) ; 106 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 23.5 (22.9) ; 38.6 (37.2) ; 16.4 (15.6) ; 1.3 (1.3) ; 0.0 (0.0) ; 5 (5) ; 106 (102) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.0 (0.0) ; 0.8 (0.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_001| ; 11.9 (0.0) ; 18.8 (0.0) ; 6.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (0) ; 48 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 11.9 (11.7) ; 18.8 (17.6) ; 6.9 (5.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 48 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.0 (0.0) ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.2 (0.2) ; 0.7 (0.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_002| ; 2.2 (0.0) ; 7.5 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 2.2 (2.3) ; 7.5 (6.2) ; 5.3 (3.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 16 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.0 (0.0) ; 0.8 (0.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; -0.2 (-0.2) ; 0.6 (0.6) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_handshake_clock_crosser:crosser_003| ; 23.8 (0.0) ; 47.0 (0.0) ; 23.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (0) ; 144 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003 ; altera_avalon_st_handshake_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_avalon_st_clock_crosser:clock_xer| ; 23.8 (23.4) ; 47.0 (45.8) ; 23.2 (22.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 144 (140) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer ; altera_avalon_st_clock_crosser ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:in_to_out_synchronizer| ; 0.1 (0.1) ; 0.5 (0.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_std_synchronizer_nocut:out_to_in_synchronizer| ; 0.3 (0.3) ; 0.8 (0.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_st_handshake_clock_crosser_181 ; -; |altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent| ; 83.8 (31.0) ; 86.5 (33.6) ; 3.3 (2.8) ; 0.7 (0.3) ; 0.0 (0.0) ; 162 (65) ; 38 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; a10s_ghrd_altera_merlin_axi_master_ni_181 ; -; |altera_merlin_address_alignment:align_address_to_size| ; 52.8 (52.8) ; 52.9 (52.9) ; 0.5 (0.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 97 (97) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; a10s_ghrd_altera_merlin_axi_master_ni_181 ; -; |altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter| ; 64.3 (0.0) ; 67.6 (0.0) ; 3.4 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 90 (0) ; 72 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter ; altera_merlin_burst_adapter ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 64.3 (63.2) ; 67.6 (66.4) ; 3.4 (3.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 90 (87) ; 72 (72) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_address_alignment:align_address_to_size| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter| ; 97.7 (0.0) ; 101.8 (0.0) ; 4.2 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 129 (0) ; 98 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter ; altera_merlin_burst_adapter ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 97.7 (97.7) ; 101.8 (101.8) ; 4.2 (4.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 129 (129) ; 98 (98) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; a10s_ghrd_altera_merlin_burst_adapter_181 ; -; |altera_merlin_slave_agent:h2fw_clockbridge_s0_agent| ; 31.9 (5.2) ; 33.8 (5.5) ; 2.0 (0.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 52 (8) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_burst_uncompressor:uncompressor| ; 26.7 (26.7) ; 28.3 (28.3) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_agent:onchip_memory2_s1_agent| ; 26.9 (1.1) ; 28.2 (1.3) ; 1.2 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (3) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent ; altera_merlin_slave_agent ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_burst_uncompressor:uncompressor| ; 25.8 (25.8) ; 26.8 (26.8) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 54 (54) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; a10s_ghrd_altera_merlin_slave_agent_181 ; -; |altera_merlin_slave_translator:onchip_memory2_s1_translator| ; 0.4 (0.4) ; 1.3 (1.3) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator ; altera_merlin_slave_translator ; a10s_ghrd_altera_merlin_slave_translator_181 ; -; |altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter| ; 8.4 (8.4) ; 8.4 (8.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; a10s_ghrd_altera_merlin_traffic_limiter_181 ; -; |altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter| ; 31.7 (31.7) ; 36.3 (36.3) ; 4.6 (4.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (60) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter| ; 32.7 (32.7) ; 38.7 (38.7) ; 6.0 (6.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 75 (75) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter| ; 72.0 (71.0) ; 72.2 (71.6) ; 0.6 (0.9) ; 0.4 (0.4) ; 0.0 (0.0) ; 114 (113) ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |altera_merlin_address_alignment:check_and_align_address_to_size| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size ; altera_merlin_address_alignment ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter| ; 73.9 (73.9) ; 77.8 (77.8) ; 4.3 (4.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 120 (120) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter ; altera_merlin_width_adapter ; a10s_ghrd_altera_merlin_width_adapter_181 ; -; |altera_avalon_mm_bridge:pb_lwh2f| ; 32.0 (32.0) ; 48.0 (48.0) ; 16.0 (16.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 119 (119) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f ; altera_avalon_mm_bridge ; a10s_ghrd_altera_avalon_mm_bridge_181 ; -; |altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge| ; 23.2 (4.1) ; 36.3 (4.9) ; 13.2 (0.8) ; 0.1 (0.0) ; 0.0 (0.0) ; 41 (10) ; 63 (5) ; 0 (0) ; 184 ; 2 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge ; altera_avalon_mm_clock_crossing_bridge ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_avalon_dc_fifo:cmd_fifo| ; 9.5 (8.8) ; 15.8 (11.5) ; 6.3 (2.7) ; 0.1 (0.0) ; 0.0 (0.0) ; 15 (15) ; 28 (16) ; 0 (0) ; 56 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo ; altera_avalon_dc_fifo ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_dcfifo_synchronizer_bundle:read_crosser| ; 0.4 (0.0) ; 2.1 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser ; altera_dcfifo_synchronizer_bundle ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[0].u| ; 0.1 (0.1) ; 0.6 (0.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[1].u| ; 0.2 (0.2) ; 0.8 (0.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[2].u| ; 0.2 (0.2) ; 0.8 (0.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_dcfifo_synchronizer_bundle:write_crosser| ; 0.2 (0.0) ; 2.2 (0.0) ; 2.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 0 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser ; altera_dcfifo_synchronizer_bundle ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[0].u| ; 0.5 (0.5) ; 0.8 (0.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[1].u| ; -0.4 (-0.4) ; 0.5 (0.5) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[2].u| ; 0.2 (0.2) ; 0.8 (0.8) ; 0.8 (0.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 56 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_bri1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 56 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated ; altsyncram_bri1 ; work ; -; |altera_avalon_dc_fifo:rsp_fifo| ; 9.6 (9.5) ; 15.6 (11.3) ; 6.0 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 30 (18) ; 0 (0) ; 128 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo ; altera_avalon_dc_fifo ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_dcfifo_synchronizer_bundle:read_crosser| ; 0.3 (0.0) ; 2.3 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser ; altera_dcfifo_synchronizer_bundle ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[0].u| ; 0.6 (0.6) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[1].u| ; 0.0 (0.0) ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[2].u| ; -0.3 (-0.3) ; 1.0 (1.0) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_dcfifo_synchronizer_bundle:write_crosser| ; -0.2 (0.0) ; 2.0 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser ; altera_dcfifo_synchronizer_bundle ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[0].u| ; -0.4 (-0.4) ; 0.5 (0.5) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[1].u| ; 0.1 (0.1) ; 0.8 (0.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altera_std_synchronizer_nocut:sync[2].u| ; 0.2 (0.2) ; 0.8 (0.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; altera_std_synchronizer_nocut ; a10s_ghrd_altera_avalon_mm_clock_crossing_bridge_181 ; -; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 128 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0 ; altsyncram ; work ; -; |altsyncram_9ri1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 128 ; 1 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated ; altsyncram_9ri1 ; work ; -; |altera_reset_controller:rst_controller| ; 8.8 (3.0) ; 7.5 (4.5) ; 3.8 (1.5) ; 5.0 (0.0) ; 0.0 (0.0) ; 7 (6) ; 17 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_req_sync_uq1| ; 5.5 (5.5) ; 2.0 (2.0) ; 1.5 (1.5) ; 5.0 (5.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.3 (0.3) ; 1.0 (1.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_controller:rst_controller_001| ; 0.0 (0.0) ; 1.0 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_controller:rst_controller_003| ; 0.2 (0.0) ; 1.0 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_003 ; altera_reset_controller ; a10s_ghrd_altera_reset_controller_181 ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.2 (0.2) ; 1.0 (1.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; a10s_ghrd_altera_reset_controller_181 ; -; |altsource_probe_top:issp| ; 15.2 (0.0) ; 20.0 (0.0) ; 4.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (0) ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp ; altsource_probe_top ; a10s_ghrd_altera_in_system_sources_probes_181 ; -; |altsource_probe:issp_impl| ; 15.2 (0.0) ; 20.0 (0.0) ; 4.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (0) ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl ; altsource_probe ; work ; -; |altsource_probe_body:altsource_probe_body_inst| ; 15.2 (1.0) ; 20.0 (1.0) ; 4.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (2) ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst ; altsource_probe_body ; work ; -; |altsource_probe_impl:\wider_source_gen:wider_source_inst| ; 14.2 (7.2) ; 19.0 (10.5) ; 4.8 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (11) ; 25 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst ; altsource_probe_impl ; work ; -; |sld_rom_sr:\instance_id_gen:rom_info_inst| ; 7.0 (7.0) ; 8.5 (8.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst ; sld_rom_sr ; work ; -; |interrupt_latency_counter:ilc| ; 83.8 (77.3) ; 119.9 (112.2) ; 37.6 (36.4) ; 1.5 (1.5) ; 0.0 (0.0) ; 122 (114) ; 214 (204) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc ; interrupt_latency_counter ; a10s_ghrd_interrupt_latency_counter_181 ; -; |irq_detector:irq_detector_cicuit[0].irq_detector| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[0].irq_detector ; irq_detector ; a10s_ghrd_interrupt_latency_counter_181 ; -; |irq_detector:irq_detector_cicuit[1].irq_detector| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[1].irq_detector ; irq_detector ; a10s_ghrd_interrupt_latency_counter_181 ; -; |state_machine_counter:state_machine[0].state_machine_counter| ; 3.0 (3.0) ; 3.2 (3.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter ; state_machine_counter ; a10s_ghrd_interrupt_latency_counter_181 ; -; |state_machine_counter:state_machine[1].state_machine_counter| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter ; state_machine_counter ; a10s_ghrd_interrupt_latency_counter_181 ; -; |sevenSigDisplay:sevensig| ; 32.2 (32.2) ; 35.7 (35.7) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (61) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|a10s_ghrd:u0|sevenSigDisplay:sevensig ; sevenSigDisplay ; a10s_ghrd_SevenSigmentDisplay_10 ; -; |altera_edge_detector:pulse_cold_reset| ; 4.0 (4.0) ; 3.4 (3.4) ; 0.9 (0.9) ; 1.5 (1.5) ; 0.0 (0.0) ; 4 (4) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|altera_edge_detector:pulse_cold_reset ; altera_edge_detector ; work ; -; |altera_edge_detector:pulse_debug_reset| ; 8.0 (8.0) ; 13.8 (13.8) ; 5.8 (5.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|altera_edge_detector:pulse_debug_reset ; altera_edge_detector ; work ; -; |altera_edge_detector:pulse_warm_reset| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|altera_edge_detector:pulse_warm_reset ; altera_edge_detector ; work ; -; |debounce:debounce_inst| ; 55.8 (55.8) ; 57.0 (57.0) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 94 (94) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|debounce:debounce_inst ; debounce ; work ; -; |sld_hub:auto_hub| ; 98.0 (0.5) ; 109.0 (0.5) ; 11.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 160 (1) ; 115 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub ; sld_hub ; altera_sld ; -; |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 97.5 (0.0) ; 108.5 (0.0) ; 11.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 159 (0) ; 115 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric ; alt_sld_fab_with_jtag_input ; altera_sld ; -; |alt_sld_fab:instrumentation_fabric| ; 97.5 (0.0) ; 108.5 (0.0) ; 11.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 159 (0) ; 115 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; alt_sld_fab ; alt_sld_fab ; -; |alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab| ; 97.5 (1.8) ; 108.5 (3.5) ; 11.5 (1.7) ; 0.5 (0.0) ; 0.0 (0.0) ; 159 (1) ; 115 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab ; alt_sld_fab_alt_sld_fab_181_vximuei ; alt_sld_fab_alt_sld_fab_181 ; -; |alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric| ; 95.7 (0.0) ; 105.0 (0.0) ; 9.8 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 158 (0) ; 107 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric ; alt_sld_fab_altera_sld_jtag_hub_181_usvbikq ; alt_sld_fab_altera_sld_jtag_hub_181 ; -; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub| ; 95.7 (72.2) ; 105.0 (79.8) ; 9.8 (8.2) ; 0.5 (0.5) ; 0.0 (0.0) ; 158 (118) ; 107 (76) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; sld_jtag_hub ; work ; -; |sld_rom_sr:hub_info_reg| ; 13.5 (13.5) ; 14.5 (14.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 21 (21) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ; sld_rom_sr ; work ; -; |sld_shadow_jsm:shadow_jsm| ; 10.0 (10.0) ; 10.7 (10.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm ; altera_sld ; -+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------------------------+----------+---------------------+--------------------+----------------+-----------------------------------+-------------------------------------+ -; Name ; Pin Type ; Input Delay Chain 0 ; Output Delay Chain ; OE Delay Chain ; IO_12_LANE Input Data Delay Chain ; IO_12_LANE Input Strobe Delay Chain ; -+------------------------+----------+---------------------+--------------------+----------------+-----------------------------------+-------------------------------------+ -; LED[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; LED[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_GTX_CLK ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_MDC ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_TX_DATA[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_TX_DATA[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_TX_DATA[2] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_TX_DATA[3] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_TX_EN ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_TXD ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_USB_STP ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; SMA_CLKOUT_p ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[2] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[3] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[4] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[5] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[6] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[7] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[8] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[9] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[10] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[11] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[12] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[13] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[14] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[15] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_A[16] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_BA[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_BA[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_BG[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_CK ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_CK_n ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_CKE ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_CS_n ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_RESET_n ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_ODT ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_PAR ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; DDR4H_ACT_n ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; ETH_RST_n ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; CLK_50_B3H ; Input ; -- ; -- ; -- ; -- ; -- ; -; FAN_ALERT_n ; Input ; -- ; -- ; -- ; -- ; -- ; -; PM_ALERT_n ; Input ; -- ; -- ; -- ; -- ; -- ; -; FMC_CLK_M2C_p[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -; FMC_CLK_M2C_p[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -; FMC_CLK_M2C_n[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -; FMC_CLK_M2C_n[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -; FMC_GBTCLK_M2C_p[0] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_GBTCLK_M2C_p[1] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_REFCLK_p ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_C2M_p[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[2] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[3] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[4] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[5] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[6] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[7] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[8] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[9] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_M2C_p[0] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[1] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[2] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[3] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[4] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[5] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[6] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[7] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[8] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[9] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_RZQ ; Input ; -- ; -- ; -- ; -- ; -- ; -; ETH_TX_p ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; ETH_RX_p ; Input ; -- ; -- ; -- ; -- ; -- ; -; ETH_INT_n ; Input ; -- ; -- ; -- ; -- ; -- ; -; ETH_MDC ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL11_A1 ; Input ; -- ; -- ; -- ; -- ; -- ; -; SMA_CLKIN_p ; Input ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[2] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[3] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[4] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[5] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_D[6] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX0_DP ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[0] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[1] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[2] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[3] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[4] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[5] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_D[6] ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; HEX1_DP ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FPGA_I2C_SCL ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FPGA_I2C_SDA ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_GPIO[0] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_GPIO[1] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_GPIO[2] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_GPIO[3] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_KEY ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_LED ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_ENET_MDIO ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[0] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[1] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[2] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[3] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[4] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[5] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[6] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_USB_DATA[7] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_I2C0_SCLK ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_I2C0_SDAT ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; DDR4H_DQS[0] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS[1] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS[2] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS[3] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS_n[0] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS_n[1] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS_n[2] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQS_n[3] ; Bidir ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DDR4H_DQ[0] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[1] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[2] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[3] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[4] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[5] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[6] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[7] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[8] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[9] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[10] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[11] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[12] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[13] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[14] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[15] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[16] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[17] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[18] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[19] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[20] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[21] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[22] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[23] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[24] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[25] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[26] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[27] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[28] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[29] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[30] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DQ[31] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DBI_n[0] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DBI_n[1] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DBI_n[2] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; DDR4H_DBI_n[3] ; Bidir ; 0 ; 0 ; 0 ; 0 ; -- ; -; HPS_DIO[0] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_DIO[1] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_DIO[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; HPS_DIO[3] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_DIO[4] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; HPS_DIO[5] ; Bidir ; 0 ; 0 ; 0 ; -- ; -- ; -; I2C_INT ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; REFCLK0_SCL ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; REFCLK0_SDA ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; REFCLK1_SCL ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; REFCLK1_SDA ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; CDCM6208_SCL ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; CDCM6208_SDA ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_CLK2_BIDIR_p ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_CLK2_BIDIR_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_CLK3_BIDIR_p ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_CLK3_BIDIR_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[22] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_p[23] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[22] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HA_n[23] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_p[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_HB_n[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[22] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[23] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[24] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[25] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[26] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[27] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[28] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[29] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[30] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[31] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[32] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_p[33] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[22] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[23] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[24] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[25] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[26] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[27] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[28] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[29] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[30] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[31] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[32] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_LA_n[33] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_GA[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_GA[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_SCL ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_SDA ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; ETH_MDIO ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; MPU_INT ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; SRC_DP_HPD ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_RESET_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_PCLK ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL0_SLCS_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_UART_TX ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_UART_RX ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL10 ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL12_A0 ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL15_INT_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL1_SLWR_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL2_SLOE_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL3_SLRD_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL4_FLAGA ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL5_FLAGB ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL6 ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL7_PKTEND_n ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL8 ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_CTL9 ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[0] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[1] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[2] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[3] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[4] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[5] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[6] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[7] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[8] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[9] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[10] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[11] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[12] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[13] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[14] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[15] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[16] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[17] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[18] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[19] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[20] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[21] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[22] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[23] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[24] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[25] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[26] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[27] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[28] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[29] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[30] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_DQ[31] ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; USBFX3_OTG_ID ; Bidir ; -- ; 0 ; 0 ; -- ; -- ; -; CLKUSR_100 ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_CLK ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_DV ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_DATA[0] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_DATA[1] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_DATA[2] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_ENET_RX_DATA[3] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_RXD ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_USB_CLKOUT ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_USB_DIR ; Input ; 0 ; -- ; -- ; -- ; -- ; -; HPS_USB_NXT ; Input ; 0 ; -- ; -- ; -- ; -- ; -; DDR4H_ALERT_n ; Input ; 0 ; -- ; -- ; 0 ; -- ; -; DDR4H_RZQ ; Input ; 0 ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; SW[1] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; CLK_50_B2H ; Input ; 0 ; -- ; -- ; -- ; -- ; -; KEY[0] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; KEY[1] ; Input ; 0 ; -- ; -- ; -- ; -- ; -; CPU_RESET_n ; Input ; 0 ; -- ; -- ; -- ; -- ; -; DDR4H_REFCLK_p ; Input ; 0 ; -- ; -- ; -- ; -- ; -; SMA_CLKOUT_p(n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_GBTCLK_M2C_p[0](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_GBTCLK_M2C_p[1](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_REFCLK_p(n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_C2M_p[0](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[1](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[2](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[3](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[4](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[5](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[6](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[7](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[8](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_C2M_p[9](n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; FMC_DP_M2C_p[0](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[1](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[2](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[3](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[4](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[5](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[6](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[7](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[8](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; FMC_DP_M2C_p[9](n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -; ETH_TX_p(n) ; Output ; -- ; 0 ; 0 ; -- ; -- ; -; ETH_RX_p(n) ; Input ; -- ; -- ; -- ; -- ; -- ; -; SMA_CLKIN_p(n) ; Input ; -- ; -- ; -- ; -- ; -- ; -; DDR4H_REFCLK_p(n) ; Input ; 0 ; -- ; -- ; -- ; -- ; -+------------------------+----------+---------------------+--------------------+----------------+-----------------------------------+-------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------+-----------------------------------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------+-----------------------------------------+--------+----------------------+------------------+---------------------------+ -; CLKUSR_100 ; PIN_AJ18 ; 8634 ; Clock ; yes ; Global Clock ; -- ; -- ; -; CLK_50_B2H ; PIN_AR23 ; 815 ; Clock ; yes ; Global Clock ; -- ; -- ; -; CPU_RESET_n ; PIN_AN18 ; 7 ; Async. clear ; no ; -- ; -- ; -- ; -; KEY[0] ; PIN_AU15 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; KEY[1] ; PIN_AT15 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|BUSY_GO_HI ; LABCELL_X117_Y164_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm|LessThan0~7 ; LABCELL_X117_Y166_N0 ; 36 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|FPGA_CURR_C[7]~0 ; LABCELL_X117_Y164_N15 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|FPGA_TEMP_C[7]~0 ; LABCELL_X117_Y164_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ ; FF_X116_Y162_N56 ; 289 ; Clock ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|LessThan0~6 ; MLABCELL_X116_Y162_N42 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CNT[0]~0 ; MLABCELL_X115_Y161_N45 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CNT[0]~3 ; MLABCELL_X115_Y161_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[20]~0 ; MLABCELL_X115_Y164_N21 ; 36 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|DELY[20]~6 ; LABCELL_X114_Y161_N12 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|A[8]~0 ; LABCELL_X117_Y162_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|BYTE[5]~0 ; LABCELL_X120_Y162_N54 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|BYTE[5]~2 ; MLABCELL_X119_Y162_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|CNT[5]~0 ; LABCELL_X117_Y161_N0 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|CNT[5]~1 ; MLABCELL_X119_Y162_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|DATA[3]~0 ; LABCELL_X117_Y162_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|DELY[3]~0 ; LABCELL_X117_Y161_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|ST[2] ; FF_X117_Y162_N50 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|ST[3] ; FF_X117_Y162_N44 ; 29 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd|ST[4] ; FF_X117_Y162_N10 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|A[8]~3 ; LABCELL_X120_Y161_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|CNT[1]~0 ; MLABCELL_X119_Y161_N57 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd|CNT[1]~2 ; LABCELL_X120_Y161_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|A[8]~6 ; LABCELL_X120_Y160_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|CNT[2]~0 ; LABCELL_X117_Y159_N3 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|CNT[2]~3 ; MLABCELL_X116_Y159_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|DELY[2]~0 ; MLABCELL_X116_Y159_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|ST[2] ; FF_X117_Y159_N14 ; 42 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|REMT1_H[7]~1 ; MLABCELL_X116_Y161_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|SDAO ; MLABCELL_X119_Y161_N18 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|SLAVE_ADDR[7]~2 ; LABCELL_X114_Y163_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|STATUS[7]~0 ; MLABCELL_X116_Y161_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|ST[4] ; FF_X116_Y164_N31 ; 34 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|WCNT[2]~0 ; LABCELL_X114_Y162_N39 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|WCNT[2]~2 ; LABCELL_X114_Y162_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|W_WORD_DATA[7]~2 ; LABCELL_X114_Y163_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[11] ; HPSPERIPHERALSDMMC_X78_Y219_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[13] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[15] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[17] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[19] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[1] ; HPSPERIPHERALEMAC_X78_Y207_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[21] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[23] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[25] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[27] ; HPSPERIPHERALUSB_X79_Y170_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[31] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[33] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[35] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[37] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[39] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[3] ; HPSPERIPHERALSDMMC_X78_Y219_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[41] ; HPSPERIPHERALGPIO_X78_Y210_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[5] ; HPSPERIPHERALSDMMC_X78_Y219_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[7] ; HPSPERIPHERALSDMMC_X78_Y219_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border|intermediate[9] ; HPSPERIPHERALSDMMC_X78_Y219_N96 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar|getptr[0] ; FF_X116_Y191_N38 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar|mem[0][2]~1 ; MLABCELL_X116_Y191_N21 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar|mem[1][2]~0 ; MLABCELL_X116_Y191_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw|getptr[0] ; FF_X120_Y192_N2 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw|mem[0][2]~1 ; LABCELL_X120_Y192_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw|mem[1][2]~0 ; LABCELL_X120_Y192_N33 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~0 ; MLABCELL_X115_Y199_N45 ; 129 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~1 ; MLABCELL_X115_Y199_N18 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~2 ; MLABCELL_X115_Y199_N27 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~3 ; MLABCELL_X115_Y199_N57 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w|getptr[0] ; FF_X125_Y195_N28 ; 148 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w|mem[0][0]~1 ; MLABCELL_X125_Y195_N3 ; 144 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w|mem[1][1]~0 ; MLABCELL_X125_Y195_N18 ; 144 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar|Decoder0~0 ; LABCELL_X113_Y179_N12 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar|Decoder0~1 ; LABCELL_X113_Y179_N33 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar|Decoder0~2 ; LABCELL_X113_Y179_N51 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar|Decoder0~3 ; LABCELL_X113_Y179_N18 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|Decoder0~0 ; MLABCELL_X115_Y186_N9 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|Decoder0~1 ; MLABCELL_X115_Y186_N54 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|Decoder0~2 ; MLABCELL_X115_Y186_N39 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|Decoder0~3 ; MLABCELL_X115_Y186_N6 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw|Mux26~0 ; LABCELL_X113_Y186_N54 ; 43 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b|mem[0][0]~0 ; LABCELL_X120_Y178_N27 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b|mem[1][1]~1 ; LABCELL_X120_Y178_N48 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r|mem[0][0]~0 ; LABCELL_X114_Y175_N15 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r|mem[1][1]~1 ; LABCELL_X114_Y175_N6 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w|Decoder0~0 ; LABCELL_X112_Y184_N54 ; 73 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w|Decoder0~1 ; LABCELL_X112_Y184_N27 ; 73 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w|Decoder0~2 ; LABCELL_X112_Y184_N57 ; 73 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w|Decoder0~3 ; LABCELL_X112_Y184_N24 ; 73 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar|Decoder0~0 ; LABCELL_X113_Y205_N36 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar|Decoder0~1 ; LABCELL_X113_Y205_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar|Decoder0~2 ; LABCELL_X113_Y205_N39 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar|Decoder0~3 ; LABCELL_X113_Y205_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|Decoder0~0 ; MLABCELL_X116_Y209_N12 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|Decoder0~1 ; MLABCELL_X116_Y209_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|Decoder0~2 ; MLABCELL_X116_Y209_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|Decoder0~3 ; MLABCELL_X116_Y209_N45 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|Mux26~0 ; LABCELL_X117_Y208_N45 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw|get~0 ; LABCELL_X117_Y202_N3 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b|mem[0][0]~1 ; LABCELL_X112_Y206_N45 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b|mem[1][1]~0 ; LABCELL_X112_Y206_N9 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r|getptr[0] ; FF_X115_Y202_N31 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r|mem[0][0]~1 ; MLABCELL_X115_Y202_N57 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r|mem[1][1]~0 ; MLABCELL_X115_Y202_N51 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|Decoder0~0 ; MLABCELL_X116_Y203_N30 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|Decoder0~1 ; MLABCELL_X116_Y203_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|Decoder0~2 ; MLABCELL_X116_Y203_N33 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w|Decoder0~3 ; MLABCELL_X116_Y203_N27 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar|mem[0][2]~1 ; LABCELL_X74_Y173_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar|mem[1][2]~0 ; LABCELL_X74_Y173_N18 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw|mem[0][2]~1 ; LABCELL_X74_Y168_N27 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw|mem[1][2]~0 ; LABCELL_X74_Y168_N57 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~0 ; LABCELL_X74_Y185_N42 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~1 ; LABCELL_X74_Y185_N18 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~2 ; LABCELL_X74_Y185_N33 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r|Decoder0~3 ; LABCELL_X74_Y185_N12 ; 128 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w|mem[0][0]~0 ; LABCELL_X71_Y171_N9 ; 144 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w|mem[1][1]~1 ; LABCELL_X71_Y171_N42 ; 144 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode826w[3] ; MLABCELL_X109_Y157_N33 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode843w[3] ; MLABCELL_X109_Y157_N54 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode853w[3] ; MLABCELL_X109_Y157_N21 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode863w[3] ; MLABCELL_X109_Y157_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode873w[3] ; MLABCELL_X109_Y157_N12 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode883w[3] ; MLABCELL_X109_Y157_N39 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode893w[3] ; MLABCELL_X109_Y157_N36 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode903w[3] ; MLABCELL_X109_Y157_N24 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode922w[3] ; MLABCELL_X109_Y157_N18 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode933w[3] ; MLABCELL_X109_Y157_N6 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode943w[3] ; MLABCELL_X109_Y157_N9 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode953w[3] ; MLABCELL_X109_Y157_N57 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode963w[3] ; MLABCELL_X109_Y157_N3 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode973w[3] ; MLABCELL_X109_Y157_N30 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode983w[3] ; MLABCELL_X109_Y157_N0 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3|w_anode993w[3] ; MLABCELL_X109_Y157_N15 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_b3m6h3q:led_pio|always0~1 ; MLABCELL_X125_Y204_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio|always1~0 ; MLABCELL_X125_Y204_N3 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_u6z2bzq:button_pio|always1~0 ; MLABCELL_X125_Y204_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b|pdiff_out_oe ; PSEUDODIFFOUT_X78_Y146_N60 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b|pdiff_out_oebar ; PSEUDODIFFOUT_X78_Y146_N60 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b|pdiff_out_oe ; PSEUDODIFFOUT_X78_Y146_N45 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b|pdiff_out_oebar ; PSEUDODIFFOUT_X78_Y146_N45 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b|pdiff_out_oe ; PSEUDODIFFOUT_X78_Y146_N30 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b|pdiff_out_oebar ; PSEUDODIFFOUT_X78_Y146_N30 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b|pdiff_out_oe ; PSEUDODIFFOUT_X78_Y146_N75 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b|pdiff_out_oebar ; PSEUDODIFFOUT_X78_Y146_N75 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_df_o:gen_mem_ck.inst[0].b|pdiff_out_oe ; PSEUDODIFFOUT_X78_Y177_N30 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_df_o:gen_mem_ck.inst[0].b|pdiff_out_oebar ; PSEUDODIFFOUT_X78_Y177_N30 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[49] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[50] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[51] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[54] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[55] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[56] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[57] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[58] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[59] ; IO12LANE_X78_Y144_N2 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[61] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[62] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[63] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[66] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[67] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[68] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[69] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[70] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[71] ; IO12LANE_X78_Y143_N1 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[73] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[74] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[75] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[78] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[79] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[80] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[81] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[82] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[83] ; IO12LANE_X78_Y142_N0 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[85] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[86] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[87] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[90] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[91] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[92] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[93] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[94] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|l2b_oe_nonabphy[95] ; IO12LANE_X78_Y145_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector3~0 ; LABCELL_X74_Y164_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[16]~2 ; LABCELL_X76_Y163_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[30]~3 ; LABCELL_X75_Y164_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[6]~0 ; LABCELL_X76_Y163_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[8]~1 ; LABCELL_X76_Y163_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~1 ; LABCELL_X74_Y161_N45 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[12]~1 ; LABCELL_X75_Y161_N12 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[7]~0 ; LABCELL_X75_Y161_N45 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~2 ; LABCELL_X73_Y164_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[0]~4 ; LABCELL_X73_Y164_N54 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data~0 ; LABCELL_X74_Y162_N30 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR1 ; FF_X75_Y161_N29 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR2 ; FF_X75_Y161_N31 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR3 ; FF_X75_Y161_N44 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT ; FF_X75_Y162_N50 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|unshifted_byteenable[3]~0 ; LABCELL_X74_Y163_N21 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15]~1 ; LABCELL_X69_Y165_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[31]~2 ; LABCELL_X69_Y165_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[7]~0 ; LABCELL_X74_Y164_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|internal_out_ready ; LABCELL_X73_Y161_N33 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|write ; LABCELL_X71_Y157_N39 ; 16 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p|always2~0 ; LABCELL_X73_Y161_N36 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p|out_channel[0]~0 ; LABCELL_X73_Y161_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0 ; FF_X113_Y15_N20 ; 19 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0~0 ; LABCELL_X113_Y13_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_taken ; LABCELL_X113_Y15_N39 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data ; LABCELL_X106_Y147_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0 ; LABCELL_X77_Y153_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0 ; LABCELL_X113_Y10_N3 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~1 ; LABCELL_X113_Y10_N36 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid ; LABCELL_X113_Y14_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6] ; FF_X114_Y10_N13 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]~1 ; LABCELL_X110_Y7_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter~0 ; MLABCELL_X109_Y10_N6 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n ; FF_X113_Y10_N49 ; 8 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~1 ; LABCELL_X113_Y10_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0 ; MLABCELL_X109_Y7_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~10 ; LABCELL_X113_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1 ; LABCELL_X113_Y10_N45 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~1 ; LABCELL_X113_Y12_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[4]~0 ; MLABCELL_X109_Y10_N24 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~3 ; MLABCELL_X109_Y7_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~1 ; LABCELL_X111_Y10_N9 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0 ; MLABCELL_X109_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_valid ; FF_X114_Y10_N23 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0 ; LABCELL_X113_Y10_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~1 ; LABCELL_X112_Y11_N51 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~2 ; LABCELL_X112_Y10_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1 ; LABCELL_X112_Y10_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[0]~1 ; LABCELL_X111_Y7_N18 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~0 ; LABCELL_X112_Y4_N42 ; 22 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~10 ; LABCELL_X112_Y4_N9 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~1 ; MLABCELL_X109_Y5_N33 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~2 ; MLABCELL_X109_Y7_N12 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1 ; LABCELL_X110_Y7_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~1 ; LABCELL_X111_Y7_N36 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1] ; FF_X114_Y11_N26 ; 41 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b|in_ready~3 ; LABCELL_X106_Y147_N33 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b|sent_channel ; FF_X73_Y162_N8 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b|sent_eop~1 ; LABCELL_X72_Y162_N15 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b|sent_sop~1 ; LABCELL_X73_Y162_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X105_Y153_N52 ; 259 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector3~0 ; LABCELL_X120_Y199_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5]~2 ; MLABCELL_X125_Y198_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[9]~1 ; MLABCELL_X125_Y198_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~0 ; LABCELL_X127_Y199_N39 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[4]~0 ; LABCELL_X124_Y198_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9]~1 ; MLABCELL_X125_Y198_N21 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[1]~2 ; MLABCELL_X125_Y198_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[5]~3 ; MLABCELL_X125_Y199_N48 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data~0 ; LABCELL_X124_Y200_N27 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR3 ; FF_X124_Y198_N40 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR4 ; FF_X124_Y198_N38 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT ; FF_X124_Y200_N37 ; 27 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|unshifted_byteenable[3]~0 ; LABCELL_X127_Y199_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15]~1 ; MLABCELL_X126_Y199_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[31]~2 ; MLABCELL_X126_Y199_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[7]~0 ; LABCELL_X120_Y199_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|internal_out_ready ; LABCELL_X132_Y199_N15 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|write ; MLABCELL_X135_Y193_N27 ; 16 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p|always2~0 ; LABCELL_X132_Y199_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p|out_channel[0]~0 ; LABCELL_X132_Y199_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0 ; FF_X114_Y16_N55 ; 19 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0~0 ; LABCELL_X114_Y17_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_taken ; LABCELL_X114_Y16_N3 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data ; LABCELL_X117_Y174_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0 ; LABCELL_X136_Y187_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0 ; MLABCELL_X115_Y8_N27 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~1 ; MLABCELL_X115_Y8_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid ; MLABCELL_X125_Y2_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6] ; FF_X124_Y6_N58 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]~1 ; MLABCELL_X115_Y5_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter~0 ; LABCELL_X114_Y5_N6 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n ; FF_X115_Y8_N52 ; 8 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~1 ; MLABCELL_X115_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0 ; MLABCELL_X126_Y1_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~10 ; MLABCELL_X115_Y8_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1 ; MLABCELL_X115_Y8_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~1 ; MLABCELL_X115_Y8_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[4]~0 ; LABCELL_X114_Y5_N39 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~3 ; LABCELL_X114_Y5_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~1 ; LABCELL_X110_Y1_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0 ; LABCELL_X124_Y3_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_valid ; FF_X113_Y1_N47 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0 ; MLABCELL_X115_Y8_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~1 ; LABCELL_X124_Y1_N30 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~2 ; LABCELL_X124_Y1_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1 ; LABCELL_X111_Y3_N15 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[0]~1 ; LABCELL_X113_Y5_N42 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~0 ; LABCELL_X111_Y5_N0 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~10 ; MLABCELL_X115_Y11_N36 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~1 ; LABCELL_X114_Y5_N18 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~2 ; LABCELL_X114_Y5_N24 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1 ; LABCELL_X124_Y3_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~1 ; LABCELL_X114_Y5_N36 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1] ; FF_X114_Y15_N19 ; 41 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b|in_ready~0 ; LABCELL_X117_Y174_N27 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b|sent_channel ; FF_X124_Y197_N7 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b|sent_eop~1 ; MLABCELL_X125_Y197_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b|sent_sop~1 ; LABCELL_X124_Y197_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X116_Y153_N25 ; 229 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector3~0 ; LABCELL_X124_Y182_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[14]~2 ; LABCELL_X127_Y183_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[16]~3 ; LABCELL_X127_Y183_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[31]~4 ; LABCELL_X127_Y183_N51 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5]~1 ; LABCELL_X127_Y183_N48 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~0 ; LABCELL_X127_Y182_N12 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[12]~1 ; LABCELL_X127_Y182_N33 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[1]~0 ; LABCELL_X127_Y182_N30 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[1]~2 ; MLABCELL_X125_Y182_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[0]~4 ; MLABCELL_X125_Y182_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data~1 ; MLABCELL_X125_Y183_N39 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR1 ; FF_X127_Y182_N5 ; 18 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR2 ; FF_X127_Y182_N8 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR3 ; FF_X127_Y182_N47 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT ; FF_X127_Y183_N37 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|unshifted_byteenable[1]~0 ; LABCELL_X124_Y180_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15]~1 ; LABCELL_X124_Y184_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[31]~2 ; LABCELL_X124_Y184_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[7]~0 ; LABCELL_X124_Y184_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|internal_out_ready ; MLABCELL_X129_Y181_N24 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|write ; MLABCELL_X131_Y177_N3 ; 16 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p|always2~0 ; MLABCELL_X129_Y181_N39 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p|out_channel[0]~0 ; LABCELL_X127_Y181_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0 ; FF_X115_Y13_N37 ; 19 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0~0 ; MLABCELL_X115_Y13_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_taken ; MLABCELL_X115_Y13_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data ; LABCELL_X122_Y138_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0 ; LABCELL_X130_Y177_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0 ; LABCELL_X112_Y3_N9 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~1 ; LABCELL_X112_Y3_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid ; LABCELL_X114_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6] ; FF_X107_Y5_N19 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]~1 ; MLABCELL_X109_Y3_N15 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter~0 ; MLABCELL_X115_Y7_N6 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n ; FF_X112_Y3_N50 ; 8 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~1 ; LABCELL_X112_Y3_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0 ; LABCELL_X112_Y7_N3 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~10 ; MLABCELL_X109_Y3_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1 ; LABCELL_X112_Y3_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~1 ; LABCELL_X111_Y2_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[4]~0 ; LABCELL_X110_Y3_N45 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~3 ; LABCELL_X110_Y3_N27 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~1 ; MLABCELL_X109_Y3_N45 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0 ; LABCELL_X112_Y7_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_valid ; FF_X113_Y3_N11 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0 ; LABCELL_X112_Y3_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~1 ; LABCELL_X112_Y7_N48 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~2 ; LABCELL_X113_Y7_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1 ; LABCELL_X113_Y7_N36 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[0]~1 ; LABCELL_X110_Y3_N54 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~0 ; LABCELL_X112_Y6_N51 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~10 ; LABCELL_X111_Y6_N3 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~1 ; LABCELL_X113_Y4_N48 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~2 ; LABCELL_X113_Y4_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1 ; LABCELL_X112_Y7_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~1 ; LABCELL_X110_Y3_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1] ; FF_X115_Y13_N50 ; 41 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|in_ready~0 ; LABCELL_X122_Y138_N30 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|sent_channel ; FF_X124_Y179_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|sent_eop~1 ; LABCELL_X124_Y179_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b|sent_sop~1 ; LABCELL_X124_Y179_N15 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X116_Y153_N55 ; 262 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[1]~0 ; LABCELL_X117_Y202_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|update_grant~0 ; LABCELL_X117_Y202_N48 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo|always0~0 ; MLABCELL_X121_Y202_N12 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo|always0~0 ; MLABCELL_X121_Y202_N39 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X119_Y202_N6 ; 60 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X119_Y202_N3 ; 46 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X121_Y202_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent|m0_read~0 ; MLABCELL_X126_Y204_N24 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter|save_dest_id~2 ; MLABCELL_X126_Y205_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always0~0 ; LABCELL_X74_Y179_N12 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always1~0 ; LABCELL_X74_Y178_N27 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always2~0 ; LABCELL_X73_Y178_N51 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always3~0 ; LABCELL_X74_Y178_N51 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always4~0 ; LABCELL_X74_Y178_N24 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always5~0 ; LABCELL_X74_Y178_N33 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|always6~0 ; LABCELL_X75_Y178_N42 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[1] ; FF_X74_Y178_N20 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[1]~3 ; LABCELL_X74_Y178_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[2] ; FF_X74_Y178_N23 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[3] ; FF_X74_Y178_N41 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[4] ; FF_X74_Y178_N38 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[5] ; FF_X74_Y178_N17 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[6] ; FF_X74_Y178_N14 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always0~0 ; LABCELL_X71_Y177_N6 ; 150 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always1~0 ; LABCELL_X67_Y175_N15 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always2~0 ; LABCELL_X69_Y176_N30 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always3~0 ; LABCELL_X69_Y176_N48 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always4~0 ; LABCELL_X67_Y175_N12 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always5~0 ; MLABCELL_X68_Y175_N12 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|always6~0 ; LABCELL_X72_Y177_N45 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[1] ; FF_X67_Y175_N1 ; 153 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[1]~3 ; LABCELL_X67_Y175_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[2] ; FF_X67_Y175_N4 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[3] ; FF_X67_Y175_N34 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[4] ; FF_X67_Y175_N32 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[5] ; FF_X67_Y175_N58 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[6] ; FF_X67_Y175_N55 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter|pending_response_count[3]~0 ; LABCELL_X75_Y174_N3 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter|save_dest_id~0 ; LABCELL_X75_Y174_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always0~0 ; LABCELL_X120_Y189_N3 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always1~0 ; MLABCELL_X119_Y193_N9 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always2~0 ; MLABCELL_X119_Y193_N6 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always3~0 ; MLABCELL_X119_Y189_N15 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always4~0 ; MLABCELL_X119_Y189_N30 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always5~0 ; MLABCELL_X119_Y189_N33 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|always6~0 ; LABCELL_X120_Y189_N33 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[1] ; FF_X119_Y189_N44 ; 25 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[1]~3 ; MLABCELL_X119_Y189_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[2] ; FF_X119_Y189_N5 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[3] ; FF_X119_Y189_N1 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[4] ; FF_X119_Y189_N47 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[5] ; FF_X119_Y189_N28 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo|mem_used[6] ; FF_X119_Y189_N25 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always0~0 ; MLABCELL_X125_Y189_N30 ; 152 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always1~0 ; MLABCELL_X125_Y191_N54 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always2~0 ; MLABCELL_X126_Y194_N12 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always3~0 ; MLABCELL_X126_Y193_N27 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always4~0 ; MLABCELL_X125_Y189_N21 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always5~0 ; MLABCELL_X125_Y194_N24 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|always6~0 ; MLABCELL_X125_Y190_N3 ; 146 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[1] ; FF_X124_Y195_N14 ; 155 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[1]~3 ; LABCELL_X124_Y195_N33 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[2] ; FF_X124_Y195_N46 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[3] ; FF_X124_Y195_N43 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[4] ; FF_X124_Y195_N16 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[5] ; FF_X124_Y195_N55 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo|mem_used[6] ; FF_X124_Y195_N58 ; 149 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter|pending_response_count[3]~0 ; LABCELL_X122_Y184_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter|save_dest_id~0 ; LABCELL_X122_Y184_N57 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|take_in_data~1 ; MLABCELL_X131_Y165_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|take_in_data~0 ; LABCELL_X130_Y164_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|take_in_data~0 ; MLABCELL_X131_Y165_N33 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter|pending_response_count[2]~0 ; MLABCELL_X131_Y165_N27 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~1 ; MLABCELL_X115_Y184_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|update_grant~0 ; MLABCELL_X115_Y184_N27 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~1 ; LABCELL_X114_Y171_N51 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|saved_grant[0] ; FF_X114_Y171_N1 ; 44 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|update_grant~0 ; LABCELL_X114_Y171_N39 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|internal_out_ready~1 ; MLABCELL_X135_Y173_N12 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|write ; MLABCELL_X131_Y173_N6 ; 38 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always0~0 ; LABCELL_X122_Y173_N24 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always1~0 ; LABCELL_X122_Y173_N39 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always2~0 ; LABCELL_X122_Y173_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always3~0 ; LABCELL_X124_Y172_N51 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always4~0 ; LABCELL_X122_Y173_N9 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always5~0 ; LABCELL_X122_Y173_N18 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always6~0 ; LABCELL_X120_Y173_N15 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|always7~0 ; LABCELL_X120_Y173_N6 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[1] ; FF_X122_Y173_N55 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[1]~3 ; LABCELL_X122_Y173_N57 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[2] ; FF_X122_Y173_N46 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[3] ; FF_X122_Y173_N43 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[4] ; FF_X122_Y173_N16 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[5] ; FF_X122_Y173_N14 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[6] ; FF_X122_Y173_N53 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo|mem_used[7] ; FF_X122_Y173_N50 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo|always0~0 ; LABCELL_X117_Y176_N45 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X119_Y177_N48 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_taken ; MLABCELL_X115_Y171_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|take_in_data~1 ; LABCELL_X114_Y179_N27 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_taken ; MLABCELL_X121_Y178_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|take_in_data~0 ; MLABCELL_X126_Y173_N33 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_taken ; MLABCELL_X116_Y175_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|take_in_data~1 ; MLABCELL_X125_Y173_N24 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_taken ; MLABCELL_X115_Y171_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|take_in_data~0 ; MLABCELL_X116_Y184_N30 ; 51 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X116_Y171_N3 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|always10~0 ; MLABCELL_X119_Y172_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X116_Y169_N21 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; FF_X116_Y171_N26 ; 38 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; FF_X120_Y171_N4 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X117_Y182_N42 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|always10~0 ; MLABCELL_X119_Y179_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X119_Y179_N0 ; 68 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; FF_X120_Y179_N38 ; 75 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; FF_X119_Y175_N37 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|always1~0 ; LABCELL_X127_Y173_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|sink_ready~0 ; MLABCELL_X126_Y173_N18 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor|source_addr[2]~1 ; LABCELL_X127_Y173_N48 ; 64 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always1~0 ; MLABCELL_X119_Y176_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|last_packet_beat~6 ; MLABCELL_X119_Y177_N12 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor|sink_ready~0 ; MLABCELL_X119_Y176_N12 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|m0_write~0 ; MLABCELL_X119_Y179_N48 ; 144 ; Read enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X114_Y179_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter|pending_response_count[3]~0 ; LABCELL_X114_Y178_N3 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X114_Y186_N45 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 ; MLABCELL_X115_Y184_N57 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter|pending_response_count[3]~0 ; MLABCELL_X119_Y178_N27 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|address_reg~0 ; MLABCELL_X115_Y168_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|use_reg ; FF_X114_Y171_N16 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|always10~3 ; MLABCELL_X126_Y174_N27 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|always9~0 ; LABCELL_X127_Y173_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|address_reg~0 ; LABCELL_X117_Y180_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|count~0 ; LABCELL_X117_Y182_N21 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|use_reg ; FF_X117_Y182_N49 ; 67 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|always10~2 ; MLABCELL_X119_Y176_N24 ; 130 ; Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|always9~0 ; MLABCELL_X119_Y176_N57 ; 56 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|cmd_waitrequest~0 ; MLABCELL_X125_Y205_N15 ; 44 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|use_reg ; FF_X126_Y205_N31 ; 43 ; Sync. load ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f|wait_rise ; MLABCELL_X126_Y205_N9 ; 41 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|internal_out_ready~1 ; LABCELL_X133_Y165_N48 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|next_in_wr_ptr~0 ; LABCELL_X117_Y169_N39 ; 16 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|next_in_wr_ptr~0 ; LABCELL_X133_Y166_N6 ; 35 ; Write enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|pending_read_count[2]~0 ; MLABCELL_X131_Y166_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X119_Y166_N29 ; 1696 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X116_Y158_N50 ; 899 ; Async. clear, Latch enable, Sync. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller|merged_reset~0 ; MLABCELL_X105_Y153_N42 ; 12 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller|r_early_rst ; FF_X109_Y153_N31 ; 132 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller|r_sync_rst ; FF_X110_Y153_N43 ; 2860 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|shift_reg[1]~4 ; MLABCELL_X109_Y21_N39 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|WORD_SR[0]~2 ; MLABCELL_X115_Y12_N21 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[0]~1 ; MLABCELL_X115_Y12_N36 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|global_enable_comb~1 ; MLABCELL_X126_Y204_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|pulse_irq_counter_stop_comb~0 ; MLABCELL_X126_Y204_N6 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter|state.IDLE ; FF_X129_Y204_N13 ; 39 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter|state.START ; FF_X130_Y201_N13 ; 40 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter|state.STORE ; FF_X130_Y201_N17 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter|state.IDLE ; FF_X129_Y204_N23 ; 38 ; Async. clear ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter|state.START ; FF_X129_Y204_N32 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter|state.STORE ; FF_X129_Y204_N20 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|HEX1_D[1]~0 ; LABCELL_X127_Y166_N42 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|inputReg[9]~0 ; LABCELL_X132_Y164_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; a10s_ghrd:u0|sevenSigDisplay:sevensig|time_base_counter[31]~0 ; LABCELL_X127_Y166_N36 ; 36 ; Sync. clear ; no ; -- ; -- ; -- ; -; altera_edge_detector:pulse_cold_reset|reset_qual_n ; LABCELL_X114_Y54_N24 ; 6 ; Async. clear ; no ; -- ; -- ; -- ; -; altera_edge_detector:pulse_debug_reset|reset_qual_n ; MLABCELL_X105_Y146_N0 ; 32 ; Async. clear ; no ; -- ; -- ; -- ; -; altera_edge_detector:pulse_warm_reset|reset_qual_n ; LABCELL_X114_Y53_N39 ; 2 ; Async. clear ; no ; -- ; -- ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X118_Y0_N2 ; 823 ; Clock ; no ; -- ; -- ; -- ; -; altera_internal_jtag~TMSUTAP ; JTAG_X118_Y0_N2 ; 31 ; Sync. clear ; no ; -- ; -- ; -- ; -; debounce:debounce_inst|counter[0][4]~4 ; LABCELL_X120_Y186_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; debounce:debounce_inst|counter[1][31]~9 ; LABCELL_X122_Y181_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg ; FF_X112_Y8_N37 ; 46 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[1]~3 ; LABCELL_X110_Y8_N48 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_info_reg_ena~0 ; LABCELL_X111_Y8_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|identity_contrib_shift_reg[0]~0 ; LABCELL_X111_Y8_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][0]~4 ; LABCELL_X112_Y9_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[2][0]~9 ; LABCELL_X112_Y9_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[3][0]~14 ; LABCELL_X112_Y9_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[4][0]~21 ; LABCELL_X113_Y9_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[2]~3 ; LABCELL_X113_Y9_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[2]~8 ; LABCELL_X113_Y8_N54 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]~1 ; MLABCELL_X109_Y8_N33 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|node_ena~2 ; MLABCELL_X109_Y8_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|reset_ena_reg_proc~0 ; LABCELL_X113_Y2_N51 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[1][0]~2 ; LABCELL_X114_Y9_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[2][0]~6 ; LABCELL_X113_Y9_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[3][0]~10 ; LABCELL_X114_Y9_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[4][0]~14 ; LABCELL_X113_Y9_N21 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]~1 ; MLABCELL_X109_Y8_N48 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[5]~1 ; MLABCELL_X109_Y8_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X113_Y2_N28 ; 15 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell ; LABCELL_X114_Y12_N36 ; 5 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X109_Y1_N53 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X113_Y2_N44 ; 67 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_dr_scan_proc~0 ; MLABCELL_X109_Y1_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_scan_reg ; FF_X109_Y1_N25 ; 216 ; Async. clear, Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|sldfabric_ident_writedata[0]~0 ; LABCELL_X111_Y8_N9 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------+-----------------------------------------+--------+----------------------+------------------+---------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals Summary ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+-------------+----------------+----------------------+ -; Name ; Location ; Fan-Out ; Signal Type ; Promotion Type ; Global Resource Used ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+-------------+----------------+----------------------+ -; CLKUSR_100 ; PIN_AJ18 ; 8634 ; Global ; Automatic ; Global Clock Region ; -; CLK_50_B2H ; PIN_AR23 ; 815 ; Global ; Automatic ; Global Clock Region ; -; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X78_Y168_N96 ; 1 ; Global ; Required ; Global Clock Region ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+-------------+----------------+----------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals Details ; -+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; CLKUSR_100 ; -; -- Source Type ; I/O pad ; -; -- Source Location ; PIN_AJ18 ; -; -- Fan-Out ; 8634 ; -; -- Promotion Type ; Automatic Promotion ; -; -- Global Buffer ; CLKUSR_100~inputCLKENA0 ; -; -- Global Buffer Location ; CLKCTRL_1C_G_I11 ; -; -- Global Signal Type ; Global ; -; -- Region Drivable by Buffer ; Global Clock Region ; -; -- Bounding Box Drivable by Buffer ; (0, 0) to (148, 224) ; -; -- Clock Region Line ; 11 ; -; ; ; -; Name ; CLK_50_B2H ; -; -- Source Type ; I/O pad ; -; -- Source Location ; PIN_AR23 ; -; -- Fan-Out ; 815 ; -; -- Promotion Type ; Automatic Promotion ; -; -- Global Buffer ; CLK_50_B2H~inputCLKENA0 ; -; -- Global Buffer Location ; CLKCTRL_2H_G_I23 ; -; -- Global Signal Type ; Global ; -; -- Region Drivable by Buffer ; Global Clock Region ; -; -- Bounding Box Drivable by Buffer ; (0, 0) to (148, 224) ; -; -- Clock Region Line ; 23 ; -; ; ; -; Name ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|h2f_rst_n[0] ; -; -- Source Type ; HPS clock resets interface ; -; -- Source Location ; HPSINTERFACECLOCKSRESETS_X78_Y168_N96 ; -; -- Fan-Out ; 1 ; -; -- Promotion Type ; Required Promotion ; -; -- Global Buffer ; a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; -; -- Global Buffer Location ; CLKCTRL_2L_G_I21 ; -; -- Global Signal Type ; Global ; -; -- Region Drivable by Buffer ; Global Clock Region ; -; -- Bounding Box Drivable by Buffer ; (0, 0) to (148, 224) ; -; -- Clock Region Line ; 21 ; -+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+--------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+ -; Name ; Fan-Out ; Physical Fan-Out ; -+--------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+ -; a10s_ghrd:u0|altera_reset_controller:rst_controller|r_sync_rst ; 2860 ; 299 ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 1696 ; 171 ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 899 ; 112 ; -; altera_internal_jtag~TCKUTAP ; 823 ; 87 ; -+--------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter RAM Summary ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+ -; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M20K blocks ; MLABs ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+ -; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 262144 ; 8 ; -- ; -- ; yes ; no ; -- ; -- ; 2097152 ; 262144 ; 8 ; -- ; -- ; 2097152 ; 128 ; 0 ; a10s_ghrd_onchip_memory2.hex ; M20K_X84_Y160_N0, M20K_X102_Y163_N0, M20K_X84_Y159_N0, M20K_X90_Y158_N0, M20K_X102_Y164_N0, M20K_X108_Y162_N0, M20K_X102_Y144_N0, M20K_X84_Y156_N0, M20K_X102_Y142_N0, M20K_X102_Y155_N0, M20K_X102_Y146_N0, M20K_X90_Y148_N0, M20K_X102_Y166_N0, M20K_X108_Y156_N0, M20K_X90_Y159_N0, M20K_X90_Y146_N0, M20K_X84_Y154_N0, M20K_X90_Y153_N0, M20K_X90_Y166_N0, M20K_X108_Y153_N0, M20K_X108_Y159_N0, M20K_X102_Y148_N0, M20K_X108_Y145_N0, M20K_X108_Y147_N0, M20K_X84_Y155_N0, M20K_X102_Y145_N0, M20K_X108_Y151_N0, M20K_X108_Y158_N0, M20K_X108_Y150_N0, M20K_X108_Y149_N0, M20K_X90_Y151_N0, M20K_X90_Y147_N0, M20K_X90_Y152_N0, M20K_X108_Y152_N0, M20K_X108_Y143_N0, M20K_X84_Y158_N0, M20K_X108_Y155_N0, M20K_X90_Y155_N0, M20K_X102_Y143_N0, M20K_X108_Y146_N0, M20K_X90_Y156_N0, M20K_X102_Y154_N0, M20K_X102_Y150_N0, M20K_X90_Y154_N0, M20K_X102_Y151_N0, M20K_X102_Y147_N0, M20K_X108_Y148_N0, M20K_X108_Y144_N0, M20K_X140_Y173_N0, M20K_X134_Y164_N0, M20K_X140_Y168_N0, M20K_X134_Y178_N0, M20K_X134_Y176_N0, M20K_X134_Y167_N0, M20K_X140_Y176_N0, M20K_X134_Y172_N0, M20K_X102_Y161_N0, M20K_X102_Y160_N0, M20K_X108_Y160_N0, M20K_X102_Y162_N0, M20K_X134_Y169_N0, M20K_X140_Y172_N0, M20K_X134_Y171_N0, M20K_X140_Y169_N0, M20K_X134_Y151_N0, M20K_X84_Y157_N0, M20K_X108_Y142_N0, M20K_X134_Y153_N0, M20K_X108_Y157_N0, M20K_X108_Y154_N0, M20K_X140_Y161_N0, M20K_X108_Y163_N0, M20K_X140_Y159_N0, M20K_X90_Y167_N0, M20K_X134_Y160_N0, M20K_X84_Y162_N0, M20K_X90_Y150_N0, M20K_X84_Y161_N0, M20K_X90_Y161_N0, M20K_X90_Y149_N0, M20K_X90_Y164_N0, M20K_X102_Y158_N0, M20K_X90_Y160_N0, M20K_X102_Y159_N0, M20K_X108_Y166_N0, M20K_X134_Y152_N0, M20K_X140_Y157_N0, M20K_X134_Y156_N0, M20K_X102_Y157_N0, M20K_X108_Y164_N0, M20K_X102_Y152_N0, M20K_X102_Y156_N0, M20K_X134_Y155_N0, M20K_X140_Y158_N0, M20K_X134_Y154_N0, M20K_X108_Y167_N0, M20K_X134_Y157_N0, M20K_X134_Y159_N0, M20K_X90_Y165_N0, M20K_X134_Y161_N0, M20K_X108_Y161_N0, M20K_X108_Y165_N0, M20K_X134_Y158_N0, M20K_X134_Y150_N0, M20K_X90_Y157_N0, M20K_X102_Y153_N0, M20K_X90_Y163_N0, M20K_X102_Y167_N0, M20K_X102_Y165_N0, M20K_X84_Y163_N0, M20K_X90_Y162_N0, M20K_X102_Y149_N0, M20K_X140_Y174_N0, M20K_X134_Y163_N0, M20K_X140_Y167_N0, M20K_X134_Y179_N0, M20K_X134_Y177_N0, M20K_X134_Y168_N0, M20K_X140_Y175_N0, M20K_X134_Y174_N0, M20K_X140_Y166_N0, M20K_X140_Y164_N0, M20K_X140_Y165_N0, M20K_X134_Y162_N0, M20K_X134_Y170_N0, M20K_X140_Y171_N0, M20K_X134_Y175_N0, M20K_X140_Y170_N0 ; Don't care ; Don't care ; New data ; Off ; No ; No - Address Too Wide ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; 0 ; None ; M20K_X70_Y157_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; 0 ; None ; M20K_X134_Y193_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ; -; a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_tom1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; 0 ; None ; M20K_X134_Y180_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ; -; a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo|altsyncram:mem_rtl_0|altsyncram_drm1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; yes ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; 0 ; None ; M20K_X134_Y173_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_bri1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 4 ; 15 ; 4 ; 15 ; yes ; no ; yes ; yes ; 60 ; 4 ; 14 ; 4 ; 14 ; 56 ; 1 ; 0 ; None ; M20K_X134_Y165_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Read Address Using Clock 1 on Port B ; -; a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_9ri1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 4 ; 32 ; 4 ; 32 ; yes ; no ; yes ; yes ; 128 ; 4 ; 32 ; 4 ; 32 ; 128 ; 1 ; 0 ; None ; M20K_X134_Y166_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Read Address Using Clock 1 on Port B ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+ -Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. - - -+-------------------------------------------------------------+ -; Routing Usage Summary ; -+------------------------------+------------------------------+ -; Routing Resource Type ; Usage ; -+------------------------------+------------------------------+ -; Block interconnects ; 29,579 / 2,248,138 ( 1 % ) ; -; C27 interconnects ; 560 / 35,203 ( 2 % ) ; -; C4 interconnects ; 18,238 / 1,597,544 ( 1 % ) ; -; Direct links ; 7,448 / 2,248,138 ( < 1 % ) ; -; Global clocks ; 3 / 32 ( 9 % ) ; -; Periphery clocks ; 0 / 739 ( 0 % ) ; -; R3 interconnects ; 8,089 / 758,112 ( 1 % ) ; -; R32 interconnects ; 344 / 66,605 ( < 1 % ) ; -; R32/C27 interconnect drivers ; 478 / 239,816 ( < 1 % ) ; -; R6 interconnects ; 13,827 / 1,488,576 ( < 1 % ) ; -; Regional clock lefts ; 0 / 16 ( 0 % ) ; -; Regional clock out bottoms ; 0 / 16 ( 0 % ) ; -; Regional clock out tops ; 0 / 16 ( 0 % ) ; -; Regional clock rights ; 0 / 16 ( 0 % ) ; -; Regional clocks ; 0 / 16 ( 0 % ) ; -; Spine buffers ; 12 / 660 ( 2 % ) ; -; Spine clocks ; 16 / 990 ( 2 % ) ; -; Spine feedthroughs ; 0 / 736 ( 0 % ) ; -+------------------------------+------------------------------+ - - -+---------------------------------------------------------------------------------+ -; Fitter HSLP Summary ; -+--------------------------------------------------------+-----------------+------+ -; Resource ; Usage ; % ; -+--------------------------------------------------------+-----------------+------+ -; ; ; ; -; Programmable power technology high-speed tiles ; 436 / 13,367 ; 3 % ; -; Programmable power technology low-power tiles ; 12,931 / 13,367 ; 97 % ; -; -- low-power tiles that are used by the design ; 1,509 / 12,931 ; 12 % ; -; -- unused tiles (low-power) ; 11,422 / 12,931 ; 88 % ; -; ; ; ; -; Programmable power technology high-speed LAB tiles ; 301 / 9,417 ; 3 % ; -; Programmable power technology low-power LAB tiles ; 9,116 / 9,417 ; 97 % ; -; -- low-power LAB tiles that are used by the design ; 1,445 / 9,116 ; 16 % ; -; -- unused LAB tiles (low-power) ; 7,671 / 9,116 ; 84 % ; -; ; ; ; -+--------------------------------------------------------+-----------------+------+ - - -+------------------------------------------------------------------------------------------------+ -; Fitter Device Options ; -+------------------------------------------------------------------+-----------------------------+ -; Option ; Setting ; -+------------------------------------------------------------------+-----------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial x4 ; -; Enable Error Detection CRC_ERROR pin ; Off ; -; Enable CvP_CONFDONE pin ; Off ; -; Enable open drain on CRC_ERROR pin ; On ; -; Enable open drain on CvP_CONFDONE pin ; On ; -; Enable open drain on INIT_DONE pin ; On ; -; Enable open drain on Partial Reconfiguration pins ; Off ; -; Enable open drain on nCEO pin ; On ; -; Enable Partial Reconfiguration pins ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; -; Enable internal scrubbing ; Off ; -; Active Serial clock source ; 100 MHz Internal Oscillator ; -; Device initialization clock source ; Internal Oscillator ; -; Configuration via Protocol ; Off ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; Off ; -; Enable nCEO output ; Off ; -; Data[7..1] ; Unreserved ; -; Data[0] ; Unreserved ; -; Data[31..16] ; Unreserved ; -; Data[15..8] ; Unreserved ; -; Base pin-out file on sameframe device ; Off ; -+------------------------------------------------------------------+-----------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 0.90 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 100 °C ; -+---------------------------+--------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected -Info (119006): Selected device 10AS066K3F40E2SG for design "a10s" -Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 100 degrees C -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. -Info (12290): Loading the periphery placement data. -Info (12291): Periphery placement data loaded: elapsed time is 00:00:36 -Critical Warning (18326): The design pin 'CLKUSR_100' has been assigned to CLKUSR pin location 'AJ18'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transceivers and certain IOs. If the pin 'CLKUSR_100' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'. -Info (12623): DATA[0] dual-purpose pin not reserved -Info (11685): 28 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins - Info (11684): Differential I/O pin "SMA_CLKOUT_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "SMA_CLKOUT_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 385 - Info (11684): Differential I/O pin "FMC_GBTCLK_M2C_p[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_GBTCLK_M2C_p[0](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 199 - Info (11684): Differential I/O pin "FMC_GBTCLK_M2C_p[1]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_GBTCLK_M2C_p[1](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 199 - Info (11684): Differential I/O pin "FMC_REFCLK_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_REFCLK_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 200 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[0](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[1]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[1](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[2]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[2](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[3]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[3](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[4]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[4](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[5]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[5](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[6]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[6](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[7]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[7](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[8]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[8](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_C2M_p[9]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_C2M_p[9](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 201 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[0](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[1]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[1](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[2]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[2](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[3]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[3](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[4]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[4](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[5]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[5](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[6]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[6](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[7]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[7](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[8]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[8](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "FMC_DP_M2C_p[9]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "FMC_DP_M2C_p[9](n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 202 - Info (11684): Differential I/O pin "ETH_TX_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "ETH_TX_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 283 - Info (11684): Differential I/O pin "ETH_RX_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "ETH_RX_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 284 - Info (11684): Differential I/O pin "SMA_CLKIN_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "SMA_CLKIN_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 382 - Info (11684): Differential I/O pin "DDR4H_REFCLK_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "DDR4H_REFCLK_p(n)" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 124 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Warning (11696): 2 I/O Standard assignments found for DDR4H_RESET_n. Only the assignment assigned to DDR4H_RESET_n will take effect - Info (11697): DDR4H_RESET_n has I/O Standard set to 1.2 V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 - Info (11697): a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b|o has I/O Standard set to 1.2-V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 -Warning (11696): 2 I/O Standard assignments found for DDR4H_RESET_n. Only the assignment assigned to DDR4H_RESET_n will take effect - Info (11697): DDR4H_RESET_n has I/O Standard set to 1.2 V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 - Info (11697): a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b|o has I/O Standard set to 1.2-V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 -Info (12785): Fitter finished merging On-chip termination (OCT) logic blocks - Info (12786): Removing unused on-chip termination logic block "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst" from the netlist -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (11696): 2 I/O Standard assignments found for DDR4H_RESET_n. Only the assignment assigned to DDR4H_RESET_n will take effect - Info (11697): DDR4H_RESET_n has I/O Standard set to 1.2 V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 - Info (11697): a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b|o has I/O Standard set to 1.2-V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 -Warning (11696): 2 I/O Standard assignments found for DDR4H_RESET_n. Only the assignment assigned to DDR4H_RESET_n will take effect - Info (11697): DDR4H_RESET_n has I/O Standard set to 1.2 V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 - Info (11697): a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b|o has I/O Standard set to 1.2-V. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 136 -Info (16210): Plan updated with currently enabled project assignments. -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:03 -Critical Warning (17951): There are 26 unused RX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. -Critical Warning (18655): There are 26 unused TX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (11178): Promoted 1 clock (1 global) - Info (13173): a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|h2f_rst_n[0]~CLKENA0 (1 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2L_G_I21 -Info (11191): Automatically promoted 2 clocks (2 global) - Info (13173): CLKUSR_100~inputCLKENA0 (8563 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I11 - Info (13173): CLK_50_B2H~inputCLKENA0 (863 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2H_G_I23 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (176233): Starting register packing -Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 30MHz - Info (332166): if { [string equal quartus_fit $::TimeQuestInfo(nameofexecutable)] } { set_max_delay -to [get_ports { altera_reserved_tdo } ] 0 } - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Info (332104): Reading SDC File: 'a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sdc' -Info (332151): Clock uncertainty is not calculated until you update the timing netlist. -Info (332104): Reading SDC File: 'a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.sdc' -Info (332104): Reading SDC File: 'a10s.sdc' -Warning (332174): Ignored filter at a10s.sdc(12): CLK_50_B3H could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 -Warning (332049): Ignored create_clock at a10s.sdc(12): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 - Info (332050): create_clock -period 20 [get_ports CLK_50_B3H] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 -Warning (332049): Ignored create_clock at a10s.sdc(15): Incorrect assignment for clock. Source node: DDR4H_REFCLK_p already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 15 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4H_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 15 -Warning (332174): Ignored filter at a10s.sdc(16): PCIE_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 -Warning (332049): Ignored create_clock at a10s.sdc(16): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 - Info (332050): create_clock -period "100.000000 MHz" [get_ports PCIE_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 -Warning (332174): Ignored filter at a10s.sdc(17): DDR4A_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 -Warning (332049): Ignored create_clock at a10s.sdc(17): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4A_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 -Warning (332174): Ignored filter at a10s.sdc(18): DDR4B_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 -Warning (332049): Ignored create_clock at a10s.sdc(18): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4B_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332151): Clock uncertainty is not calculated until you update the timing netlist. -Warning (332060): Node: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|CNT[5] is being clocked by a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ -Warning (332060): Node: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out was determined to be a clock but was found without an associated clock assignment. - Info (13166): Latch a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|rTEMP_BUSY~1 is being clocked by a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out -Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o -Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 21 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 33.333 altera_reserved_tck - Info (332111): 20.000 CLK_50_B2H - Info (332111): 10.000 CLKUSR_100 - Info (332111): 0.938 DDR4H_DQS[0]_IN - Info (332111): 0.938 DDR4H_DQS[1]_IN - Info (332111): 0.938 DDR4H_DQS[2]_IN - Info (332111): 0.938 DDR4H_DQS[3]_IN - Info (332111): 1.876 u0|emif_a10_hps_phy_clk_0 - Info (332111): 1.876 u0|emif_a10_hps_phy_clk_1 - Info (332111): 1.876 u0|emif_a10_hps_phy_clk_l_0 - Info (332111): 1.876 u0|emif_a10_hps_phy_clk_l_1 - Info (332111): 3.752 u0|emif_a10_hps_ref_clock - Info (332111): 0.938 u0|emif_a10_hps_vco_clk_0 - Info (332111): 0.938 u0|emif_a10_hps_vco_clk_1 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_0 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_1 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_2 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_3 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_4 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_5 - Info (332111): 0.938 u0|emif_a10_hps_wf_clk_6 -Info (176235): Finished register packing - Extra Info (176218): Packed 102 registers into blocks of type Block RAM -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Info (12263): Fitter periphery placement operations ending: elapsed time is 00:01:36 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (15705): Ignored locations or region assignments to the following nodes - Warning (15706): Node "CLK_50_B2A" is assigned to location or region, but does not exist in design - Warning (15706): Node "CLK_50_B3F" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDCSCL_RX" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDCSDA_RX" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_ACT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_AC_R[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_AC_R[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_ALERT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_A[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_BG[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_BG[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_CK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_CK_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_CS_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_C[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_C[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DBI_n[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQS_n[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[32]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[33]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[34]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[35]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[36]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[37]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[38]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[39]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[40]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[41]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[42]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[43]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[44]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[45]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[46]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[47]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[48]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[49]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[50]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[51]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[52]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[53]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[54]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[55]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[56]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[57]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[58]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[59]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[60]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[61]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[62]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[63]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[64]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[65]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[66]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[67]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[68]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[69]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[70]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[71]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_EVENT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_ODT" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_PAR" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_RESET_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_RZQ" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4A_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_ACT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_ALERT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_A[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_BG[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_BG[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_CK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_CK_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_CS_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DBI_n[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DBI_n[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DBI_n[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DBI_n[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS_n[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS_n[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS_n[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQS_n[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_ODT" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_PAR" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_RESET_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4B_RZQ" is assigned to location or region, but does not exist in design - Warning (15706): Node "DDR4H_BG[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_AUX_SEL" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_AUX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_DX_SEL" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_RX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_RX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_RX_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_RX_p[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_TX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_TX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_TX_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DP_TX_p[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_5V_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_CEC" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_CLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_D_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_D_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_D_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_HPD" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_RX_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_CEC" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_CLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_D_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_D_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_D_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_HPD" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "HDMI_TX_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "HPS_CLK_25" is assigned to location or region, but does not exist in design - Warning (15706): Node "HPS_DIO[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HPS_DIO[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HPS_RESET_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "HPS_WARM_RST_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "OB_PCIE_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_PERST_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_RX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_RX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_RX_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_RX_p[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_TX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_TX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_TX_p[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_TX_p[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "PCIE_WAKE_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "RX_SENSE_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "RX_SENSE_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_DEVICE_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_DEVICE_RX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_DEVICE_RX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_DEVICE_TX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_DEVICE_TX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_HOST_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_HOST_RX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_HOST_RX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_HOST_TX_p[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SATA_HOST_TX_p[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_LOS" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_MOD0_PRSNT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_MOD1_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_MOD2_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_RATESEL[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_RATESEL[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_RX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_TXDISABLE" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_TXFAULT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPA_TX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_LOS" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_MOD0_PRSNT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_MOD1_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_MOD2_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_RATESEL[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_RATESEL[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_RX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_TXDISABLE" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_TXFAULT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPB_TX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_LOS" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_MOD0_PRSNT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_MOD1_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_MOD2_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_RATESEL[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_RATESEL[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_RX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_TXDISABLE" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_TXFAULT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPC_TX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_LOS" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_MOD0_PRSNT_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_MOD1_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_MOD2_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_RATESEL[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_RATESEL[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_RX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_TXDISABLE" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_TXFAULT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFPD_TX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SFP_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "SINK_DP_HPD" is assigned to location or region, but does not exist in design - Warning (15706): Node "TYPEC_5V_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "TYPEC_PD_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "TYPEC_PD_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "TYPEC_PD_SLAVE_SCL" is assigned to location or region, but does not exist in design - Warning (15706): Node "TYPEC_PD_SLAVE_SDA" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB20_OE_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB20_SW" is assigned to location or region, but does not exist in design - Warning (15706): Node "USBDP_SW_CNF[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "USBDP_SW_CNF[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "USBDP_SW_CNF[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_HOST_DEV_OE_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_HOST_DEV_SEL_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_REFCLK_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_RX_p" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_SSFX3_PATH_OE_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_SSFX3_PATH_SEL_n" is assigned to location or region, but does not exist in design - Warning (15706): Node "USB_TX_p" is assigned to location or region, but does not exist in design -Info (11165): Fitter preparation operations ending: elapsed time is 00:01:27 -Info (170189): Fitter placement preparation operations beginning -Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. -Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:49 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:19 -Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. -Info (11888): Total time spent on timing analysis during Placement is 16.16 seconds. -Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 1% of the available device resources - Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X111_Y189 to location X123_Y200 -Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during Routing is 11.28 seconds. -Info (16607): Fitter routing operations ending: elapsed time is 00:00:41 -Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. -Info (11888): Total time spent on timing analysis during Post-Routing is 0.67 seconds. -Info (16557): Fitter post-fit operations ending: elapsed time is 00:01:24 -Warning (12620): Input port OE of I/O output buffer "FPGA_I2C_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 175 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 306 -Warning (12620): Input port OE of I/O output buffer "HPS_I2C0_SDAT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 307 -Warning (12620): Input port OE of I/O output buffer "HPS_DIO[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 294 -Warning (12620): Input port OE of I/O output buffer "I2C_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 172 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 177 -Warning (12620): Input port OE of I/O output buffer "REFCLK0_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 178 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 179 -Warning (12620): Input port OE of I/O output buffer "REFCLK1_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 180 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 181 -Warning (12620): Input port OE of I/O output buffer "CDCM6208_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 182 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 187 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK2_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 188 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_p~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 189 -Warning (12620): Input port OE of I/O output buffer "FMC_CLK3_BIDIR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 190 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 193 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 194 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 195 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_HB_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 196 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_p[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 197 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[32]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_LA_n[33]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 198 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_GA[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 203 -Warning (12620): Input port OE of I/O output buffer "FMC_SCL~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 205 -Warning (12620): Input port OE of I/O output buffer "FMC_SDA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 206 -Warning (12620): Input port OE of I/O output buffer "ETH_MDIO~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 287 -Warning (12620): Input port OE of I/O output buffer "MPU_INT~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 325 -Warning (12620): Input port OE of I/O output buffer "SRC_DP_HPD~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 328 -Warning (12620): Input port OE of I/O output buffer "USBFX3_RESET_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 359 -Warning (12620): Input port OE of I/O output buffer "USBFX3_PCLK~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 360 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL0_SLCS_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 361 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_TX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 362 -Warning (12620): Input port OE of I/O output buffer "USBFX3_UART_RX~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 363 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL10~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 364 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL12_A0~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 366 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL15_INT_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 367 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL1_SLWR_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 368 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL2_SLOE_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL3_SLRD_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 370 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL4_FLAGA~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 371 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL5_FLAGB~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 372 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL6~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 373 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL7_PKTEND_n~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 374 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL8~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 375 -Warning (12620): Input port OE of I/O output buffer "USBFX3_CTL9~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 376 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[0]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[1]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[2]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[3]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[4]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[5]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[6]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[7]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[8]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[9]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[10]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[11]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[12]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[13]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[14]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[15]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[16]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[17]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[18]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[19]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[20]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[21]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[22]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[23]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[24]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[25]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[26]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[27]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[28]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[29]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[30]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_DQ[31]~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 377 -Warning (12620): Input port OE of I/O output buffer "USBFX3_OTG_ID~output" is not connected, but the atom is driving a bi-directional pin File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 378 -Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Info (144001): Generated suppressed messages file D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.fit.smsg -Info (11793): Fitter databases successfully split. -Info: Quartus Prime Fitter was successful. 0 errors, 3147 warnings - Info: Peak virtual memory: 17109 megabytes - Info: Processing ended: Mon Dec 16 14:05:45 2019 - Info: Elapsed time: 00:06:07 - Info: Total CPU time (on all processors): 00:19:44 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.fit.smsg. - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.fit.smsg b/fpga/HAN_A10rsyocto/output_files/a10s.fit.smsg deleted file mode 100644 index 9302919..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info (176236): Started Fast Input/Output/OE register processing -Extra Info (176237): Finished Fast Input/Output/OE register processing -Extra Info (176238): Start inferring scan chains for DSP blocks -Extra Info (176239): Inferring scan chains for DSP blocks is complete -Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density -Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.fit.summary b/fpga/HAN_A10rsyocto/output_files/a10s.fit.summary deleted file mode 100644 index 579cb97..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.fit.summary +++ /dev/null @@ -1,17 +0,0 @@ -Fitter Status : Successful - Mon Dec 16 14:05:42 2019 -Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition -Revision Name : a10s -Top-level Entity Name : a10s -Family : Arria 10 -Device : 10AS066K3F40E2SG -Timing Models : Final -Logic utilization (in ALMs) : 5,726 / 251,680 ( 2 % ) -Total registers : 10270 -Total pins : 439 / 864 ( 51 % ) -Total virtual pins : 0 -Total block memory bits : 2,099,384 / 43,642,880 ( 5 % ) -Total RAM Blocks : 134 / 2,131 ( 6 % ) -Total DSP Blocks : 0 / 1,687 ( 0 % ) -Total HSSI RX channels : 0 / 36 ( 0 % ) -Total HSSI TX channels : 0 / 36 ( 0 % ) -Total PLLs : 12 / 80 ( 15 % ) diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.flow.rpt b/fpga/HAN_A10rsyocto/output_files/a10s.flow.rpt deleted file mode 100644 index 5e3f910..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.flow.rpt +++ /dev/null @@ -1,131 +0,0 @@ -Flow report for a10s -Mon Dec 16 18:02:56 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+-------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Mon Dec 16 18:02:56 2019 ; -; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; -; Revision Name ; a10s ; -; Top-level Entity Name ; a10s ; -; Family ; Arria 10 ; -; Device ; 10AS066K3F40E2SG ; -; Timing Models ; Final ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -+-----------------------------+-------------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 12/16/2019 18:01:54 ; -; Main task ; Compilation ; -; Revision Name ; a10s ; -+-------------------+---------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-------------------------------------+--------------------------------------------------------------------+---------------+----------------------------------------------------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-------------------------------------+--------------------------------------------------------------------+---------------+----------------------------------------------------------+------------+ -; COMPILER_SIGNATURE_ID ; 255543657905904.157651571409348 ; -- ; -- ; -- ; -; HPS_ISW_FILE ; a10s_ghrd/altera_arria10_interface_generator_140/synth/hps.pre.xml ; -- ; a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi ; -- ; -; HPS_ISW_FILE ; a10s_ghrd/altera_emif_arch_nf_181/synth/emif.pre.xml ; -- ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ; -; MESSAGE_DISABLE ; 10230 ; -- ; a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi ; -- ; -; MESSAGE_DISABLE ; 10230 ; -- ; a10s_ghrd_altera_arria10_interface_generator_140_q66yweq ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/a10s_ghrd.cmp ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/../D ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/a10s_ghrd_arria10_hps_hps.svd ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/../a10s_ghrd.qsys ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/altera_emif_arch_nf_181/synth/emif.pre.xml ; -- ; -- ; -- ; -; MISC_FILE ; a10s_ghrd/altera_arria10_interface_generator_140/synth/hps.pre.xml ; -- ; -- ; -- ; -; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ; -; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ; -; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ; -; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ; -; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; -; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; -; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SLD_FILE ; a10s_ghrd/a10s_ghrd.regmap ; -- ; -- ; -- ; -; SLD_FILE ; a10s_ghrd/a10s_ghrd.debuginfo ; -- ; -- ; -- ; -; SLD_INFO ; QSYS_NAME a10s_ghrd HAS_SOPCINFO 1 GENERATION_ID 1576500538 ; -- ; a10s_ghrd ; -- ; -; SOPCINFO_FILE ; a10s_ghrd/../a10s_ghrd.sopcinfo ; -- ; -- ; -- ; -; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ; -+-------------------------------------+--------------------------------------------------------------------+---------------+----------------------------------------------------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Elaboration ; 00:01:02 ; 1.0 ; 5308 MB ; 00:01:24 ; -; Total ; 00:01:02 ; -- ; -- ; 00:01:24 ; -+------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+------------------------+-------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+------------------------+-------------------+------------+------------+----------------+ -; Analysis & Elaboration ; robsebThinkPadP52 ; Windows 10 ; 10.0 ; x86_64 ; -+------------------------+-------------------+------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off a10s -c a10s --disable_all_banners --analysis_and_elaboration - - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.jdi b/fpga/HAN_A10rsyocto/output_files/a10s.jdi deleted file mode 100644 index 23c99c7..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.jdi +++ /dev/null @@ -1,306 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.map.rpt b/fpga/HAN_A10rsyocto/output_files/a10s.map.rpt deleted file mode 100644 index f88f399..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.map.rpt +++ /dev/null @@ -1,20195 +0,0 @@ -Analysis & Elaboration report for a10s -Mon Dec 16 18:02:56 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Elaboration Summary - 3. Parallel Compilation - 4. Analysis & Elaboration IP Cores Summary - 5. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst - 6. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar - 7. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw - 8. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w - 9. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r - 10. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b - 11. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar - 12. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw - 13. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w - 14. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r - 15. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b - 16. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar - 17. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw - 18. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w - 19. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r - 20. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b - 21. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst - 22. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar - 23. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw - 24. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w - 25. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r - 26. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b - 27. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst - 28. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar - 29. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw - 30. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w - 31. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r - 32. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b - 33. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst - 34. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_req_regs - 35. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_refresh_done_regs - 36. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_long_idle_regs - 37. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_rlat_regs - 38. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_wlat_regs - 39. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_seq_busy_regs - 40. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_success_regs - 41. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_fail_regs - 42. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer - 43. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming - 44. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer - 45. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer - 46. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer - 47. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer - 48. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer - 49. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer - 50. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser - 51. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer - 52. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 - 53. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 - 54. Source assignments for a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1 - 55. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer - 56. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming - 57. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer - 58. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer - 59. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer - 60. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer - 61. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer - 62. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer - 63. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser - 64. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer - 65. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 - 66. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 - 67. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge - 68. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u - 69. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u - 70. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u - 71. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u - 72. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u - 73. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u - 74. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u - 75. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u - 76. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u - 77. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u - 78. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u - 79. Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u - 80. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer - 81. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming - 82. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer - 83. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer - 84. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer - 85. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer - 86. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer - 87. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer - 88. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser - 89. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer - 90. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 - 91. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 - 92. Source assignments for a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst - 93. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated - 94. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux - 95. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux_001 - 96. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux - 97. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001 - 98. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer - 99. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -100. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -101. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -102. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -103. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -104. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -105. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -106. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux -107. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_001 -108. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_002 -109. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux -110. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux -111. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux -112. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_001 -113. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_002 -114. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_003 -115. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_004 -116. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux -117. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux -118. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux_001 -119. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -120. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -121. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -122. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -123. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -124. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -125. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -126. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -127. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux -128. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux -129. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 -130. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux -131. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux -132. Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 -133. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller -134. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -135. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 -136. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 -137. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 -138. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1 -139. Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_req_sync_uq1 -140. Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc -141. Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[0].irq_detector -142. Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[1].irq_detector -143. Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter -144. Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter -145. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps -146. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps -147. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst -148. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar -149. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw -150. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w -151. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r -152. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b -153. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:wdata_alen -154. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:awaddr_alen -155. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:araddr_alen -156. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_cache_alen -157. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_id_alen -158. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_len_alen -159. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_ar_user -160. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_cache_alen -161. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_id_alen -162. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_len_alen -163. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_ar_user -164. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:w_id_alen -165. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight -166. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst -167. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar -168. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw -169. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w -170. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r -171. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b -172. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:rdata_alen -173. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:b_id_alen -174. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:r_id_alen -175. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga -176. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins -177. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar -178. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw -179. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w -180. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r -181. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b -182. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:rdata_alen -183. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:b_id_alen -184. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:r_id_alen -185. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram -186. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0 -187. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:wdata_alen -188. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:awaddr_alen -189. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:araddr_alen -190. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_cache_alen -191. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_id_alen -192. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_len_alen -193. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_ar_user -194. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_cache_alen -195. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_id_alen -196. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_len_alen -197. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_ar_user -198. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_id_alen -199. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_burst_alen -200. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_lock_alen -201. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_burst_alen -202. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_lock_alen -203. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_prot_alen -204. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_size_alen -205. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_prot_alen -206. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_size_alen -207. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_valid_alen -208. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_last_alen -209. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:r_ready_alen -210. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_valid_alen -211. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:b_ready_alen -212. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_strb_alen -213. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:_w_valid_alen -214. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst -215. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar -216. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw -217. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w -218. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r -219. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b -220. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2 -221. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst -222. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar -223. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw -224. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w -225. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r -226. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b -227. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch -228. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst -229. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst -230. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll_extra_clks:pll_extra_clks_inst -231. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst -232. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hps_clks_rsts:hps.hps_clks_rsts_inst -233. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst -234. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_df_o:gen_mem_ck.inst[0].b -235. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[0].b -236. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[1].b -237. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[2].b -238. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[3].b -239. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[4].b -240. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[5].b -241. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[6].b -242. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[7].b -243. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[8].b -244. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[9].b -245. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[10].b -246. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[11].b -247. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[12].b -248. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[13].b -249. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[14].b -250. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[15].b -251. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[16].b -252. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[0].b -253. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[1].b -254. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_bg.inst[0].b -255. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cke.inst[0].b -256. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cs_n.inst[0].b -257. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_odt.inst[0].b -258. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b -259. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_act_n.inst[0].b -260. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_par.inst[0].b -261. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[0].b -262. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[1].b -263. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[2].b -264. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[3].b -265. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[4].b -266. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[5].b -267. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[6].b -268. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[7].b -269. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[8].b -270. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[9].b -271. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[10].b -272. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[11].b -273. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[12].b -274. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[13].b -275. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[14].b -276. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[15].b -277. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[16].b -278. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[17].b -279. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[18].b -280. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[19].b -281. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[20].b -282. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[21].b -283. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[22].b -284. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[23].b -285. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[24].b -286. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[25].b -287. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[26].b -288. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[27].b -289. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[28].b -290. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[29].b -291. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[30].b -292. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[31].b -293. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[0].b -294. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[1].b -295. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[2].b -296. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[3].b -297. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_i:gen_mem_alert_n.inst[0].b -298. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b -299. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b -300. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b -301. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b -302. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux:io_aux_inst -303. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst -304. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst -305. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_abphy_mux:altera_emif_arch_nf_abphy_mux_inst -306. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst -307. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_req_regs -308. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_refresh_done_regs -309. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_long_idle_regs -310. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_rlat_regs -311. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_wlat_regs -312. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_seq_busy_regs -313. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_success_regs -314. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_fail_regs -315. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_avl_if:hmc_avl_if_inst -316. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_sideband_if:hmc_sideband_if_inst -317. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_mmr_if:hmc_mmr_if_inst -318. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_ast_data_if:hmc.hmc_ast.data_if_inst -319. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m -320. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master -321. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node -322. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component -323. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming -324. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer -325. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming -326. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer -327. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer -328. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer -329. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer -330. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser -331. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer -332. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer -333. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage -334. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser -335. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser -336. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer -337. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo -338. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p -339. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b -340. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto -341. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m -342. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller -343. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -344. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 -345. Parameter Settings for User Entity Instance: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1 -346. Parameter Settings for User Entity Instance: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL -347. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m -348. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master -349. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node -350. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component -351. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming -352. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer -353. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming -354. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer -355. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer -356. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer -357. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer -358. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser -359. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer -360. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer -361. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage -362. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser -363. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser -364. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer -365. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo -366. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p -367. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b -368. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto -369. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m -370. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller -371. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -372. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 -373. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge -374. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo -375. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser -376. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u -377. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u -378. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u -379. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser -380. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u -381. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u -382. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u -383. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo -384. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser -385. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u -386. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u -387. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u -388. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser -389. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u -390. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u -391. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u -392. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m -393. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master -394. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node -395. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component -396. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming -397. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer -398. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming -399. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer -400. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer -401. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer -402. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer -403. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser -404. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer -405. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer -406. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage -407. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser -408. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser -409. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer -410. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo -411. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p -412. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b -413. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto -414. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m -415. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller -416. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -417. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 -418. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altsource_probe_top:issp -419. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl -420. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2 -421. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram -422. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f -423. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator -424. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator -425. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent -426. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size -427. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent -428. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor -429. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo -430. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo -431. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent -432. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor -433. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo -434. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo -435. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode -436. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router_001|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode -437. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002|a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode:the_default_decode -438. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003|a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode:the_default_decode -439. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter -440. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter -441. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter -442. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter -443. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size -444. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment -445. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min -446. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub -447. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract -448. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub -449. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract -450. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub -451. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract -452. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub -453. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract -454. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub -455. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract -456. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub -457. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract -458. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter -459. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter -460. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size -461. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment -462. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min -463. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub -464. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract -465. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub -466. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract -467. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub -468. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract -469. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub -470. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract -471. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub -472. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract -473. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub -474. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract -475. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb -476. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -477. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb -478. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -479. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb -480. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -481. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001|altera_merlin_arbitrator:arb -482. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -483. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter -484. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor -485. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter -486. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor -487. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter -488. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size -489. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter -490. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size -491. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser -492. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer -493. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -494. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -495. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001 -496. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer -497. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -498. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -499. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002 -500. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer -501. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -502. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -503. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003 -504. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer -505. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -506. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -507. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter -508. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001 -509. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator -510. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator -511. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent -512. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size -513. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent -514. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent -515. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor -516. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo -517. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo -518. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode -519. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_001|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode -520. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_002|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode -521. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003|a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode:the_default_decode -522. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter -523. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter -524. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size -525. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment -526. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min -527. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub -528. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract -529. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub -530. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract -531. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub -532. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract -533. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub -534. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract -535. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub -536. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract -537. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub -538. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract -539. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb -540. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -541. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter -542. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator -543. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator -544. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator -545. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator -546. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator -547. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator -548. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent -549. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent -550. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent|altera_merlin_burst_uncompressor:uncompressor -551. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo -552. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent -553. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent|altera_merlin_burst_uncompressor:uncompressor -554. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo -555. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent -556. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor -557. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo -558. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent -559. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor -560. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo -561. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent -562. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor -563. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo -564. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router|a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode:the_default_decode -565. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode -566. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_002|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode -567. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_003|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode -568. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_004|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode -569. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_005|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode -570. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter -571. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb -572. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -573. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter -574. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 -575. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_002 -576. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_003 -577. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_004 -578. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator -579. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator -580. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator -581. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent -582. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent -583. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -584. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo -585. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo -586. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent -587. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent|altera_merlin_burst_uncompressor:uncompressor -588. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo -589. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo -590. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router|a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode:the_default_decode -591. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode -592. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_002|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode -593. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter -594. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux|altera_merlin_arbitrator:arb -595. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -596. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser -597. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer -598. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -599. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -600. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001 -601. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer -602. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -603. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -604. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002 -605. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer -606. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -607. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -608. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003 -609. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer -610. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer -611. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer -612. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter -613. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 -614. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_translator:hps_m_master_translator -615. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent -616. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent -617. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_address_alignment:check_and_align_address_to_size -618. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_burst_uncompressor:read_burst_uncompressor -619. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo -620. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo -621. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode -622. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode -623. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode -624. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter -625. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb -626. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -627. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter -628. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor -629. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter -630. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor -631. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter -632. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_rsp_width_adapter -633. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_translator:f2sdram_m_master_translator -634. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent -635. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent -636. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_merlin_address_alignment:check_and_align_address_to_size -637. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_merlin_burst_uncompressor:read_burst_uncompressor -638. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo -639. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo -640. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode -641. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode -642. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode -643. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter -644. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb -645. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -646. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter -647. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor -648. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter -649. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor -650. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_rsp_width_adapter -651. Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_rsp_width_adapter -652. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller -653. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -654. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 -655. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001 -656. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 -657. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 -658. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_002 -659. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003 -660. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1 -661. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_req_sync_uq1 -662. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_004 -663. Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_005 -664. Parameter Settings for User Entity Instance: debounce:debounce_inst -665. Parameter Settings for User Entity Instance: altera_edge_detector:pulse_cold_reset -666. Parameter Settings for User Entity Instance: altera_edge_detector:pulse_warm_reset -667. Parameter Settings for User Entity Instance: altera_edge_detector:pulse_debug_reset -668. altsyncram Parameter Settings by Entity Instance -669. Analysis & Elaboration Settings -670. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_005" -671. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_004" -672. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_003" -673. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_002" -674. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_001" -675. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" -676. Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller" -677. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_acw3b6a:irq_mapper_002" -678. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_4ipexzi:irq_mapper_001" -679. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_rsp_width_adapter" -680. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_rsp_width_adapter" -681. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter" -682. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter" -683. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent" -684. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent" -685. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_translator:f2sdram_m_master_translator" -686. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_rsp_width_adapter" -687. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter" -688. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter" -689. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" -690. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter" -691. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode" -692. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode" -693. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo" -694. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo" -695. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_address_alignment:check_and_align_address_to_size" -696. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent" -697. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent" -698. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_translator:hps_m_master_translator" -699. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003" -700. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002" -701. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001" -702. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser" -703. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode" -704. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router|a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode:the_default_decode" -705. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo" -706. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo" -707. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent" -708. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo" -709. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo" -710. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent" -711. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent" -712. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator" -713. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator" -714. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator" -715. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -716. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode" -717. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router|a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode:the_default_decode" -718. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo" -719. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent" -720. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo" -721. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent" -722. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo" -723. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent" -724. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo" -725. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent" -726. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo" -727. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent" -728. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent" -729. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator" -730. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator" -731. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator" -732. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator" -733. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator" -734. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator" -735. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -736. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" -737. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" -738. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" -739. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" -740. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" -741. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" -742. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" -743. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" -744. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" -745. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003|a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode:the_default_decode" -746. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode" -747. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo" -748. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo" -749. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent" -750. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent" -751. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" -752. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent" -753. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator" -754. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator" -755. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003" -756. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002" -757. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001" -758. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser" -759. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size" -760. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter" -761. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size" -762. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter" -763. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" -764. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter" -765. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" -766. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter" -767. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -768. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -769. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" -770. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" -771. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" -772. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" -773. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" -774. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" -775. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" -776. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" -777. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" -778. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" -779. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" -780. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003|a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode:the_default_decode" -781. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002|a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode:the_default_decode" -782. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode" -783. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo" -784. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo" -785. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent" -786. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo" -787. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo" -788. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent" -789. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" -790. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent" -791. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator" -792. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator" -793. Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f" -794. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2" -795. Port Connectivity Checks: "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl" -796. Port Connectivity Checks: "a10s_ghrd:u0|altsource_probe_top:issp" -797. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m" -798. Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo" -799. Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo" -800. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m" -801. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm" -802. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL" -803. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd" -804. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt" -805. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd" -806. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400" -807. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1" -808. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp" -809. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|CLOCKMEM:k10" -810. Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd" -811. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" -812. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller" -813. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo" -814. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser" -815. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter" -816. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover" -817. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" -818. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer" -819. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer" -820. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer" -821. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" -822. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" -823. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node" -824. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master" -825. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m" -826. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst" -827. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_abphy_mux:altera_emif_arch_nf_abphy_mux_inst" -828. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst" -829. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch" -830. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b" -831. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" -832. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" -833. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw" -834. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar" -835. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2" -836. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram" -837. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b" -838. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r" -839. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w" -840. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw" -841. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar" -842. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins" -843. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga" -844. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b" -845. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r" -846. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w" -847. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw" -848. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar" -849. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight" -850. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b" -851. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" -852. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" -853. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw" -854. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar" -855. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps" -856. Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface|hps_emif_interface_to_ddr:inst" -857. Port Connectivity Checks: "a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter" -858. Port Connectivity Checks: "a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter" -859. Port Connectivity Checks: "a10s_ghrd:u0" -860. Analysis & Elaboration Messages -861. Analysis & Elaboration Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+---------------------------------------------------------------------------------+ -; Analysis & Elaboration Summary ; -+-------------------------------+-------------------------------------------------+ -; Analysis & Elaboration Status ; Successful - Mon Dec 16 18:02:56 2019 ; -; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; -; Revision Name ; a10s ; -; Top-level Entity Name ; a10s ; -; Family ; Arria 10 ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -+-------------------------------+-------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 6 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -+----------------------------+-------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Elaboration IP Cores Summary ; -+--------+------------------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+------------------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+ -; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; ; -; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab ; ; -; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_super_splitter_181_hav7emy:presplit ; ; -; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_jtag_hub_181_usvbikq:sldfabric ; ; -; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |a10s|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab_181_vximuei:alt_sld_fab|alt_sld_fab_altera_sld_splitter_181_zactcby:splitter ; ; -; N/A ; Qsys ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0 ; a10s_ghrd.qsys ; -; Altera ; altera_arria10_hps ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps ; a10s_ghrd.qsys ; -; Altera ; altera_arria10_hps_io ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_pio ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_u6z2bzq:button_pio ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_pio ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio ; a10s_ghrd.qsys ; -; Altera ; altera_emif_a10_hps ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps ; a10s_ghrd.qsys ; -; Altera ; altera_emif_arch_nf ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_jtag_avalon_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_bytes_to_packets ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_channel_adapter_181_arrjpdi:b2p_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo ; a10s_ghrd.qsys ; -; Altera ; altera_jtag_dc_streaming ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_packets_to_bytes ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_channel_adapter_181_xiycpqq:p2b_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller ; a10s_ghrd.qsys ; -; Altera ; timing_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_timing_adapter_181_v2af63i:timing_adt ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_packets_to_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto ; a10s_ghrd.qsys ; -; Altera ; altera_jtag_avalon_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_bytes_to_packets ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|a10s_ghrd_channel_adapter_181_arrjpdi:b2p_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo ; a10s_ghrd.qsys ; -; Altera ; altera_jtag_dc_streaming ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_packets_to_bytes ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|a10s_ghrd_channel_adapter_181_xiycpqq:p2b_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller ; a10s_ghrd.qsys ; -; Altera ; timing_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|a10s_ghrd_timing_adapter_181_v2af63i:timing_adt ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_packets_to_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_mm_clock_crossing_bridge ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge ; a10s_ghrd.qsys ; -; Altera ; altera_jtag_avalon_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_bytes_to_packets ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|a10s_ghrd_channel_adapter_181_arrjpdi:b2p_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo ; a10s_ghrd.qsys ; -; Altera ; altera_jtag_dc_streaming ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_packets_to_bytes ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b ; a10s_ghrd.qsys ; -; Altera ; channel_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|a10s_ghrd_channel_adapter_181_xiycpqq:p2b_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller ; a10s_ghrd.qsys ; -; Altera ; timing_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|a10s_ghrd_timing_adapter_181_v2af63i:timing_adt ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_packets_to_master ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto ; a10s_ghrd.qsys ; -; Altera ; interrupt_latency_counter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|interrupt_latency_counter:ilc ; a10s_ghrd.qsys ; -; Altera ; altera_irq_mapper ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_s3yuekq:irq_mapper ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_irq_mapper ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_4ipexzi:irq_mapper_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_irq_mapper ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_acw3b6a:irq_mapper_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_in_system_sources_probes ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altsource_probe_top:issp ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_pio ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_b3m6h3q:led_pio ; a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0 ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_axi_master_ni ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001|a10s_ghrd_error_adapter_181_rr5nq7i:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_burst_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_burst_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1 ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_axi_master_ni ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_burst_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka:rsp_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka:rsp_mux_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2 ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_002 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_002|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_003 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_003|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_004 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_004|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux_004 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_004 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_005 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_004 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3 ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 ; a10s_ghrd.qsys ; -; Altera ; error_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy:cmd_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_st_handshake_clock_crosser ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_slave_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4 ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_axi_slave_ni ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq:cmd_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_translator:hps_m_master_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_mm_interconnect ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5 ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_axi_slave_ni ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sc_fifo ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo ; a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_width_adapter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_rsp_width_adapter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq:cmd_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq:cmd_mux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_agent ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_traffic_limiter ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_master_translator ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_translator:f2sdram_m_master_translator ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_raxibmi:router ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_router ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_demultiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_merlin_multiplexer ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux ; D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys ; -; Altera ; altera_avalon_onchip_memory2 ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2 ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_mm_bridge ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_001 ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_002 ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_003 ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_004 ; a10s_ghrd.qsys ; -; Altera ; altera_reset_controller ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|altera_reset_controller:rst_controller_005 ; a10s_ghrd.qsys ; -; Altera ; altera_avalon_sysid_qsys ; 18.1 ; N/A ; N/A ; |a10s|a10s_ghrd:u0|a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy:sysid_qsys ; a10s_ghrd.qsys ; -+--------+------------------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_RAM_RECOGNITION ; OFF ; - ; - ; -+----------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_req_regs ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_refresh_done_regs ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_long_idle_regs ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_rlat_regs ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_wlat_regs ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_seq_busy_regs ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_success_regs ; -+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_fail_regs ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DONT_MERGE_REGISTER ; on ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+---------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; GLOBAL_SIGNAL ; OFF ; - ; clock_sense_reset_n ; -+---------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; ON ; - ; src_data[7] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[7]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1]~reg0 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1 ; -+------------------------------+-------+------+-----------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+------------------------------+-------+------+-----------------------------------------------------+ -; IGNORE_LCELL_BUFFERS ; off ; - ; const_zero_sig ; -; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; const_zero_sig ; -+------------------------------+-------+------+-----------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; GLOBAL_SIGNAL ; OFF ; - ; clock_sense_reset_n ; -+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; ON ; - ; src_data[7] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[7]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1]~reg0 ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge ; -+------------------------------------+-------+------+-----------------------------------------+ -; Assignment ; Value ; From ; To ; -+------------------------------------+-------+------+-----------------------------------------+ -; ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ; ON ; - ; altera_avalon_dc_fifo:cmd_fifo ; -; ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ; ON ; - ; altera_avalon_dc_fifo:rsp_fifo ; -+------------------------------------+-------+------+-----------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+---------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; GLOBAL_SIGNAL ; OFF ; - ; clock_sense_reset_n ; -+---------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; ON ; - ; src_data[7] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0] ; -; PRESERVE_REGISTER ; ON ; - ; src_data[0]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[7]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[6]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[5]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[4]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[3]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[2]~reg0 ; -; PRESERVE_REGISTER ; ON ; - ; src_data[1]~reg0 ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[6] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[6] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[6] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[6] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[5] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[5] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[5] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[5] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[4] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[4] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[4] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[4] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[3] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[3] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[3] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[3] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[2] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[2] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[2] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[1] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[1] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[1] ; -+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst ; -+---------------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------+ -; NOT_GATE_PUSH_BACK ; OFF ; - ; - ; -; POWER_UP_LEVEL ; LOW ; - ; - ; -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l2_reg[0] ; -; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; hold_reg[2] ; -; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; hold_reg[1] ; -; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; hold_reg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l2_reg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l2_reg[2] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l1_reg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l1_reg[1] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; metastable_l1_reg[2] ; -+---------------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux_002 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_002 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_003 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux_004 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux_001 ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller ; -+-------------------+-------+------+-----------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-----------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[4] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[3] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[2] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+-----------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+----------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -+-------------------+-------+------+--------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc ; -+----------------+-----------+------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-----------+------------------------------------------------------------+ -; INTR_TYPE ; 0 ; Signed Integer ; -; CLOCK_RATE ; 100000000 ; Signed Integer ; -; IRQ_PORT_CNT ; 2 ; Signed Integer ; -+----------------+-----------+------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[0].irq_detector ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -; INTR_TYPE ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[1].irq_detector ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -; INTR_TYPE ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; INTR_TYPE ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; INTR_TYPE ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps ; -+----------------+-------+---------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------+ -; F2S_Width ; 6 ; Signed Integer ; -; S2F_Width ; 2 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 128 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 128 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 149 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 135 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:wdata_alen ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 128 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:awaddr_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:araddr_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_cache_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_id_alen ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_len_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_ar_user ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 5 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_cache_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_id_alen ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_len_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:aw_ar_user ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 5 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:w_id_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 32 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 32 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 41 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 39 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:rdata_alen ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:b_id_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|alentar:r_id_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 64 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 64 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 77 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 71 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:rdata_alen ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 64 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:b_id_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:r_id_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEPTH ; 4 ; Signed Integer ; -; DWIDTH0 ; 128 ; Signed Integer ; -; DWIDTH1 ; 16 ; Signed Integer ; -; DWIDTH2 ; 16 ; Signed Integer ; -; mode ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 128 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:wdata_alen ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 128 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:awaddr_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:araddr_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_cache_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_id_alen ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_len_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_ar_user ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 5 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_cache_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_id_alen ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_len_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_ar_user ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 5 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_id_alen ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 4 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_burst_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 2 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_lock_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 2 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_burst_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 2 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_lock_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 2 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_prot_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_size_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_prot_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_size_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_valid_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_last_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:r_ready_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_valid_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:b_ready_alen ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_strb_alen ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 16 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:_w_valid_alen ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 1 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 128 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 149 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 135 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 16 ; Signed Integer ; -; DEPTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DWIDTH ; 16 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 59 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 23 ; Signed Integer ; -; PTR_WIDTH ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 23 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -; PTR_WIDTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch ; -+--------------------------------------------+----------------------------+---------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------------------+----------------------------+---------------------------------------------------------------------------------------+ -; PROTOCOL_ENUM ; PROTOCOL_DDR4 ; String ; -; PHY_TARGET_IS_ES ; 0 ; Signed Integer ; -; PHY_TARGET_IS_ES2 ; 0 ; Signed Integer ; -; PHY_TARGET_IS_PRODUCTION ; 1 ; Signed Integer ; -; PHY_CONFIG_ENUM ; CONFIG_PHY_AND_HARD_CTRL ; String ; -; PHY_PING_PONG_EN ; 0 ; Signed Integer ; -; PHY_CORE_CLKS_SHARING_ENUM ; CORE_CLKS_SHARING_DISABLED ; String ; -; PHY_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_AC_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_CK_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_DATA_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_HPS_ENABLE_EARLY_RELEASE ; 1 ; Signed Integer ; -; PLL_NUM_OF_EXTRA_CLKS ; 0 ; Signed Integer ; -; MEM_FORMAT_ENUM ; MEM_FORMAT_DISCRETE ; String ; -; MEM_BURST_LENGTH ; 8 ; Signed Integer ; -; MEM_DATA_MASK_EN ; 1 ; Signed Integer ; -; MEM_TTL_DATA_WIDTH ; 32 ; Signed Integer ; -; MEM_TTL_NUM_OF_READ_GROUPS ; 4 ; Signed Integer ; -; MEM_TTL_NUM_OF_WRITE_GROUPS ; 4 ; Signed Integer ; -; DIAG_SIM_REGTEST_MODE ; 0 ; Signed Integer ; -; DIAG_SYNTH_FOR_SIM ; 0 ; Signed Integer ; -; DIAG_VERBOSE_IOAUX ; 0 ; Signed Integer ; -; DIAG_ECLIPSE_DEBUG ; 0 ; Signed Integer ; -; DIAG_EXPORT_VJI ; 0 ; Signed Integer ; -; DIAG_INTERFACE_ID ; 0 ; Signed Integer ; -; DIAG_FAST_SIM ; 1 ; Signed Integer ; -; DIAG_USE_ABSTRACT_PHY ; 0 ; Signed Integer ; -; SILICON_REV ; 20nm4 ; String ; -; IS_HPS ; 1 ; Signed Integer ; -; IS_VID ; 0 ; Signed Integer ; -; USER_CLK_RATIO ; 2 ; Signed Integer ; -; C2P_P2C_CLK_RATIO ; 2 ; Signed Integer ; -; PHY_HMC_CLK_RATIO ; 2 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_WLAT ; 8 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_RLAT ; 19 ; Signed Integer ; -; DIAG_CPA_OUT_1_EN ; 0 ; Signed Integer ; -; DIAG_USE_CPA_LOCK ; 1 ; Signed Integer ; -; DQS_BUS_MODE_ENUM ; DQS_BUS_MODE_X8_X9 ; String ; -; AC_PIN_MAP_SCHEME ; use_0_1_2_lane ; String ; -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; HMC_AVL_PROTOCOL_ENUM ; CTRL_AVL_PROTOCOL_ST ; String ; -; HMC_CTRL_DIMM_TYPE ; component ; String ; -; REGISTER_AFI ; 0 ; Signed Integer ; -; SEQ_SYNTH_CPU_CLK_DIVIDE ; 2 ; Signed Integer ; -; SEQ_SYNTH_CAL_CLK_DIVIDE ; 8 ; Signed Integer ; -; SEQ_SIM_CPU_CLK_DIVIDE ; 1 ; Signed Integer ; -; SEQ_SIM_CAL_CLK_DIVIDE ; 32 ; Signed Integer ; -; SEQ_SYNTH_OSC_FREQ_MHZ ; 450 ; Signed Integer ; -; SEQ_SIM_OSC_FREQ_MHZ ; 2123 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; PRI_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; LANES_USAGE_0 ; 11980873 ; Signed Integer ; -; LANES_USAGE_1 ; 0 ; Signed Integer ; -; LANES_USAGE_2 ; 0 ; Signed Integer ; -; LANES_USAGE_3 ; 0 ; Signed Integer ; -; LANES_USAGE_AUTOGEN_WCNT ; 4 ; Signed Integer ; -; PINS_USAGE_0 ; 956300126 ; Signed Integer ; -; PINS_USAGE_1 ; 1073479739 ; Signed Integer ; -; PINS_USAGE_2 ; 1056960510 ; Signed Integer ; -; PINS_USAGE_3 ; 63 ; Signed Integer ; -; PINS_USAGE_4 ; 0 ; Signed Integer ; -; PINS_USAGE_5 ; 0 ; Signed Integer ; -; PINS_USAGE_6 ; 0 ; Signed Integer ; -; PINS_USAGE_7 ; 0 ; Signed Integer ; -; PINS_USAGE_8 ; 0 ; Signed Integer ; -; PINS_USAGE_9 ; 0 ; Signed Integer ; -; PINS_USAGE_10 ; 0 ; Signed Integer ; -; PINS_USAGE_11 ; 0 ; Signed Integer ; -; PINS_USAGE_12 ; 0 ; Signed Integer ; -; PINS_USAGE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_RATE_0 ; 956299358 ; Signed Integer ; -; PINS_RATE_1 ; 262203 ; Signed Integer ; -; PINS_RATE_2 ; 0 ; Signed Integer ; -; PINS_RATE_3 ; 0 ; Signed Integer ; -; PINS_RATE_4 ; 0 ; Signed Integer ; -; PINS_RATE_5 ; 0 ; Signed Integer ; -; PINS_RATE_6 ; 0 ; Signed Integer ; -; PINS_RATE_7 ; 0 ; Signed Integer ; -; PINS_RATE_8 ; 0 ; Signed Integer ; -; PINS_RATE_9 ; 0 ; Signed Integer ; -; PINS_RATE_10 ; 0 ; Signed Integer ; -; PINS_RATE_11 ; 0 ; Signed Integer ; -; PINS_RATE_12 ; 0 ; Signed Integer ; -; PINS_RATE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_WDB_0 ; 151261768 ; Signed Integer ; -; PINS_WDB_1 ; 153391688 ; Signed Integer ; -; PINS_WDB_2 ; 153092681 ; Signed Integer ; -; PINS_WDB_3 ; 37385 ; Signed Integer ; -; PINS_WDB_4 ; 905969664 ; Signed Integer ; -; PINS_WDB_5 ; 920347830 ; Signed Integer ; -; PINS_WDB_6 ; 920202672 ; Signed Integer ; -; PINS_WDB_7 ; 910912566 ; Signed Integer ; -; PINS_WDB_8 ; 316345782 ; Signed Integer ; -; PINS_WDB_9 ; 224694 ; Signed Integer ; -; PINS_WDB_10 ; 0 ; Signed Integer ; -; PINS_WDB_11 ; 0 ; Signed Integer ; -; PINS_WDB_12 ; 0 ; Signed Integer ; -; PINS_WDB_13 ; 0 ; Signed Integer ; -; PINS_WDB_14 ; 0 ; Signed Integer ; -; PINS_WDB_15 ; 0 ; Signed Integer ; -; PINS_WDB_16 ; 0 ; Signed Integer ; -; PINS_WDB_17 ; 0 ; Signed Integer ; -; PINS_WDB_18 ; 0 ; Signed Integer ; -; PINS_WDB_19 ; 0 ; Signed Integer ; -; PINS_WDB_20 ; 0 ; Signed Integer ; -; PINS_WDB_21 ; 0 ; Signed Integer ; -; PINS_WDB_22 ; 0 ; Signed Integer ; -; PINS_WDB_23 ; 0 ; Signed Integer ; -; PINS_WDB_24 ; 0 ; Signed Integer ; -; PINS_WDB_25 ; 0 ; Signed Integer ; -; PINS_WDB_26 ; 0 ; Signed Integer ; -; PINS_WDB_27 ; 0 ; Signed Integer ; -; PINS_WDB_28 ; 0 ; Signed Integer ; -; PINS_WDB_29 ; 0 ; Signed Integer ; -; PINS_WDB_30 ; 0 ; Signed Integer ; -; PINS_WDB_31 ; 0 ; Signed Integer ; -; PINS_WDB_32 ; 0 ; Signed Integer ; -; PINS_WDB_33 ; 0 ; Signed Integer ; -; PINS_WDB_34 ; 0 ; Signed Integer ; -; PINS_WDB_35 ; 0 ; Signed Integer ; -; PINS_WDB_36 ; 0 ; Signed Integer ; -; PINS_WDB_37 ; 0 ; Signed Integer ; -; PINS_WDB_38 ; 0 ; Signed Integer ; -; PINS_WDB_AUTOGEN_WCNT ; 39 ; Signed Integer ; -; PINS_DATA_IN_MODE_0 ; 1057231432 ; Signed Integer ; -; PINS_DATA_IN_MODE_1 ; 153391688 ; Signed Integer ; -; PINS_DATA_IN_MODE_2 ; 153092681 ; Signed Integer ; -; PINS_DATA_IN_MODE_3 ; 37385 ; Signed Integer ; -; PINS_DATA_IN_MODE_4 ; 150994944 ; Signed Integer ; -; PINS_DATA_IN_MODE_5 ; 153395145 ; Signed Integer ; -; PINS_DATA_IN_MODE_6 ; 153612872 ; Signed Integer ; -; PINS_DATA_IN_MODE_7 ; 167547401 ; Signed Integer ; -; PINS_DATA_IN_MODE_8 ; 1059357257 ; Signed Integer ; -; PINS_DATA_IN_MODE_9 ; 37449 ; Signed Integer ; -; PINS_DATA_IN_MODE_10 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_11 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_12 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_13 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_14 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_15 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_16 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_17 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_18 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_19 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_20 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_21 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_22 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_23 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_24 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_25 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_26 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_27 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_28 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_29 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_30 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_31 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_32 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_33 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_34 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_35 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_36 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_37 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_38 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_AUTOGEN_WCNT ; 39 ; Signed Integer ; -; PINS_C2L_DRIVEN_0 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_1 ; 1060634624 ; Signed Integer ; -; PINS_C2L_DRIVEN_2 ; 251457486 ; Signed Integer ; -; PINS_C2L_DRIVEN_3 ; 63 ; Signed Integer ; -; PINS_C2L_DRIVEN_4 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_5 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_6 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_7 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_8 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_9 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_10 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_11 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_12 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_IN_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_DB_IN_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_IN_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_OE_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_DB_OE_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_OE_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_INVERT_WR_0 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_1 ; 8388608 ; Signed Integer ; -; PINS_INVERT_WR_2 ; 537002016 ; Signed Integer ; -; PINS_INVERT_WR_3 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_4 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_5 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_6 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_7 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_8 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_9 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_10 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_11 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_12 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_INVERT_OE_0 ; 956300126 ; Signed Integer ; -; PINS_INVERT_OE_1 ; 1073217595 ; Signed Integer ; -; PINS_INVERT_OE_2 ; 1056960510 ; Signed Integer ; -; PINS_INVERT_OE_3 ; 63 ; Signed Integer ; -; PINS_INVERT_OE_4 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_5 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_6 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_7 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_8 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_9 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_10 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_11 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_12 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_0 ; 768 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_1 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_2 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_3 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_4 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_5 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_6 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_7 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_8 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_9 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_10 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_11 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_12 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_OCT_MODE_0 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_1 ; 1073217536 ; Signed Integer ; -; PINS_OCT_MODE_2 ; 1056960510 ; Signed Integer ; -; PINS_OCT_MODE_3 ; 63 ; Signed Integer ; -; PINS_OCT_MODE_4 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_5 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_6 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_7 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_8 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_9 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_10 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_11 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_12 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_GPIO_MODE_0 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_1 ; 262144 ; Signed Integer ; -; PINS_GPIO_MODE_2 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_3 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_4 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_5 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_6 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_7 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_8 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_9 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_10 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_11 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_12 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_0 ; 75583511 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_1 ; 48282684 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_2 ; 45133869 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_3 ; 41985066 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_4 ; 38836263 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_5 ; 27295780 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_6 ; 10510361 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_7 ; 5127 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_8 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_9 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_10 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_11 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_12 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_13 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_14 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_15 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_16 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_17 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_18 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_19 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_20 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_21 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_22 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_23 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_24 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_25 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_26 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_27 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_28 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_29 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_30 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_31 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_32 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_33 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_34 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_35 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_36 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_37 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_38 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_39 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_40 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_41 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_42 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_43 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_44 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_45 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_46 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_47 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_48 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_49 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_50 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_51 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_52 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_53 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_54 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_55 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_56 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_57 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_58 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_59 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_60 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_61 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_62 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_63 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_64 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_65 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_66 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_67 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_68 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_69 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_70 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_71 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_72 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_73 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_74 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_75 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_76 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_77 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_78 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_79 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_80 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_81 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_82 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_83 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_84 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_85 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_86 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_87 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_88 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_89 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_90 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_91 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_92 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_93 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_94 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_95 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_96 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_97 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_98 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_99 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_100 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_101 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_102 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_103 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_104 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_105 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_106 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_107 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_108 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_109 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_110 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_111 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_112 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_113 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_114 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_115 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_116 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_117 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_118 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_119 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_120 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_121 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_122 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_123 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_124 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_125 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_126 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_127 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_128 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT ; 129 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_0 ; 2100228 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_1 ; 1 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_2 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_3 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_4 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_5 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_6 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_7 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_8 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_9 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_10 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT ; 11 ; Signed Integer ; -; CENTER_TIDS_0 ; 6148 ; Signed Integer ; -; CENTER_TIDS_1 ; 0 ; Signed Integer ; -; CENTER_TIDS_2 ; 0 ; Signed Integer ; -; CENTER_TIDS_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; HMC_TIDS_0 ; 6661 ; Signed Integer ; -; HMC_TIDS_1 ; 0 ; Signed Integer ; -; HMC_TIDS_2 ; 0 ; Signed Integer ; -; HMC_TIDS_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; LANE_TIDS_0 ; 403177984 ; Signed Integer ; -; LANE_TIDS_1 ; 168067584 ; Signed Integer ; -; LANE_TIDS_2 ; 88 ; Signed Integer ; -; LANE_TIDS_3 ; 0 ; Signed Integer ; -; LANE_TIDS_4 ; 0 ; Signed Integer ; -; LANE_TIDS_5 ; 0 ; Signed Integer ; -; LANE_TIDS_6 ; 0 ; Signed Integer ; -; LANE_TIDS_7 ; 0 ; Signed Integer ; -; LANE_TIDS_8 ; 0 ; Signed Integer ; -; LANE_TIDS_9 ; 0 ; Signed Integer ; -; LANE_TIDS_AUTOGEN_WCNT ; 10 ; Signed Integer ; -; PREAMBLE_MODE ; preamble_one_cycle ; String ; -; DBI_WR_ENABLE ; false ; String ; -; DBI_RD_ENABLE ; true ; String ; -; CRC_EN ; crc_disable ; String ; -; SWAP_DQS_A_B ; false ; String ; -; DQS_PACK_MODE ; packed ; String ; -; OCT_SIZE ; 2 ; Signed Integer ; -; DBC_WB_RESERVED_ENTRY ; 40 ; Signed Integer ; -; DLL_MODE ; ctl_dynamic ; String ; -; DLL_CODEWORD ; 0 ; Signed Integer ; -; ABPHY_WRITE_PROTOCOL ; 0 ; Signed Integer ; -; PHY_USERMODE_OCT ; 0 ; Signed Integer ; -; PHY_PERIODIC_OCT_RECAL ; 0 ; Signed Integer ; -; PHY_HAS_DCC ; 1 ; Signed Integer ; -; PRI_HMC_CFG_ENABLE_ECC ; disable ; String ; -; PRI_HMC_CFG_REORDER_DATA ; enable ; String ; -; PRI_HMC_CFG_REORDER_READ ; enable ; String ; -; PRI_HMC_CFG_REORDER_RDATA ; enable ; String ; -; PRI_HMC_CFG_STARVE_LIMIT ; 10 ; Signed Integer ; -; PRI_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; PRI_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; PRI_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; PRI_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; PRI_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; PRI_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; PRI_HMC_CFG_SLOT_ROTATE_EN ; 0 ; Signed Integer ; -; PRI_HMC_CFG_SLOT_OFFSET ; 2 ; Signed Integer ; -; PRI_HMC_CFG_COL_CMD_SLOT ; 2 ; Signed Integer ; -; PRI_HMC_CFG_ROW_CMD_SLOT ; 1 ; Signed Integer ; -; PRI_HMC_CFG_ENABLE_RC ; disable ; String ; -; PRI_HMC_CFG_CS_TO_CHIP_MAPPING ; 33825 ; Signed Integer ; -; PRI_HMC_CFG_RB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; PRI_HMC_CFG_WB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; PRI_HMC_CFG_TCL ; 20 ; Signed Integer ; -; PRI_HMC_CFG_POWER_SAVING_EXIT_CYC ; 3 ; Signed Integer ; -; PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 14 ; Signed Integer ; -; PRI_HMC_CFG_WRITE_ODT_CHIP ; 1 ; Signed Integer ; -; PRI_HMC_CFG_READ_ODT_CHIP ; 0 ; Signed Integer ; -; PRI_HMC_CFG_WR_ODT_ON ; 0 ; Signed Integer ; -; PRI_HMC_CFG_RD_ODT_ON ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_ODT_PERIOD ; 6 ; Signed Integer ; -; PRI_HMC_CFG_RD_ODT_PERIOD ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ0 ; 15 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ1 ; 240 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ2 ; 3840 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ3 ; 61440 ; Signed Integer ; -; PRI_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 512 ; Signed Integer ; -; PRI_HMC_CFG_DQSTRK_TO_VALID_LAST ; 24 ; Signed Integer ; -; PRI_HMC_CFG_DQSTRK_TO_VALID ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RFSH_WARN_THRESHOLD ; 4 ; Signed Integer ; -; PRI_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; PRI_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; PRI_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; PRI_HMC_CFG_SB_DDR4_MR3 ; 197120 ; Signed Integer ; -; PRI_HMC_CFG_SB_DDR4_MR4 ; 264192 ; Signed Integer ; -; PRI_HMC_CFG_SB_DDR4_MR5 ; 5152 ; Signed Integer ; -; PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; PRI_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; PRI_HMC_CFG_ACT_TO_RDWR ; 8 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_PCH ; 18 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT ; 26 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 4 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD ; 3 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_BG ; 2 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_BG ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_PCH ; 5 ; Signed Integer ; -; PRI_HMC_CFG_RD_AP_TO_VALID ; 13 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_BG ; 2 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD ; 17 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 5 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_BG ; 15 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_PCH ; 19 ; Signed Integer ; -; PRI_HMC_CFG_WR_AP_TO_VALID ; 27 ; Signed Integer ; -; PRI_HMC_CFG_PCH_TO_VALID ; 8 ; Signed Integer ; -; PRI_HMC_CFG_PCH_ALL_TO_VALID ; 8 ; Signed Integer ; -; PRI_HMC_CFG_ARF_TO_VALID ; 140 ; Signed Integer ; -; PRI_HMC_CFG_PDN_TO_VALID ; 4 ; Signed Integer ; -; PRI_HMC_CFG_SRF_TO_VALID ; 513 ; Signed Integer ; -; PRI_HMC_CFG_SRF_TO_ZQ_CAL ; 449 ; Signed Integer ; -; PRI_HMC_CFG_ARF_PERIOD ; 4161 ; Signed Integer ; -; PRI_HMC_CFG_PDN_PERIOD ; 0 ; Signed Integer ; -; PRI_HMC_CFG_ZQCL_TO_VALID ; 257 ; Signed Integer ; -; PRI_HMC_CFG_ZQCS_TO_VALID ; 65 ; Signed Integer ; -; PRI_HMC_CFG_MRS_TO_VALID ; 7 ; Signed Integer ; -; PRI_HMC_CFG_MPS_TO_VALID ; 768 ; Signed Integer ; -; PRI_HMC_CFG_MRR_TO_VALID ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MPR_TO_VALID ; 16 ; Signed Integer ; -; PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 5 ; Signed Integer ; -; PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 6 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MMR_CMD_TO_VALID ; 16 ; Signed Integer ; -; PRI_HMC_CFG_4_ACT_TO_ACT ; 15 ; Signed Integer ; -; PRI_HMC_CFG_16_ACT_TO_ACT ; 0 ; Signed Integer ; -; SEC_HMC_CFG_ENABLE_ECC ; disable ; String ; -; SEC_HMC_CFG_REORDER_DATA ; enable ; String ; -; SEC_HMC_CFG_REORDER_READ ; enable ; String ; -; SEC_HMC_CFG_REORDER_RDATA ; enable ; String ; -; SEC_HMC_CFG_STARVE_LIMIT ; 10 ; Signed Integer ; -; SEC_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; SEC_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; SEC_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; SEC_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; SEC_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; SEC_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; SEC_HMC_CFG_SLOT_ROTATE_EN ; 0 ; Signed Integer ; -; SEC_HMC_CFG_SLOT_OFFSET ; 2 ; Signed Integer ; -; SEC_HMC_CFG_COL_CMD_SLOT ; 2 ; Signed Integer ; -; SEC_HMC_CFG_ROW_CMD_SLOT ; 1 ; Signed Integer ; -; SEC_HMC_CFG_ENABLE_RC ; disable ; String ; -; SEC_HMC_CFG_CS_TO_CHIP_MAPPING ; 33825 ; Signed Integer ; -; SEC_HMC_CFG_RB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; SEC_HMC_CFG_WB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; SEC_HMC_CFG_TCL ; 20 ; Signed Integer ; -; SEC_HMC_CFG_POWER_SAVING_EXIT_CYC ; 3 ; Signed Integer ; -; SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 14 ; Signed Integer ; -; SEC_HMC_CFG_WRITE_ODT_CHIP ; 1 ; Signed Integer ; -; SEC_HMC_CFG_READ_ODT_CHIP ; 0 ; Signed Integer ; -; SEC_HMC_CFG_WR_ODT_ON ; 0 ; Signed Integer ; -; SEC_HMC_CFG_RD_ODT_ON ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_ODT_PERIOD ; 6 ; Signed Integer ; -; SEC_HMC_CFG_RD_ODT_PERIOD ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ0 ; 15 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ1 ; 240 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ2 ; 3840 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ3 ; 61440 ; Signed Integer ; -; SEC_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 512 ; Signed Integer ; -; SEC_HMC_CFG_DQSTRK_TO_VALID_LAST ; 24 ; Signed Integer ; -; SEC_HMC_CFG_DQSTRK_TO_VALID ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RFSH_WARN_THRESHOLD ; 4 ; Signed Integer ; -; SEC_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; SEC_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; SEC_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; SEC_HMC_CFG_SB_DDR4_MR3 ; 197120 ; Signed Integer ; -; SEC_HMC_CFG_SB_DDR4_MR4 ; 264192 ; Signed Integer ; -; SEC_HMC_CFG_SB_DDR4_MR5 ; 5152 ; Signed Integer ; -; SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; SEC_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; SEC_HMC_CFG_ACT_TO_RDWR ; 8 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_PCH ; 18 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT ; 26 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 4 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD ; 3 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_BG ; 2 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_BG ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_PCH ; 5 ; Signed Integer ; -; SEC_HMC_CFG_RD_AP_TO_VALID ; 13 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_BG ; 2 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD ; 17 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 5 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_BG ; 15 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_PCH ; 19 ; Signed Integer ; -; SEC_HMC_CFG_WR_AP_TO_VALID ; 27 ; Signed Integer ; -; SEC_HMC_CFG_PCH_TO_VALID ; 8 ; Signed Integer ; -; SEC_HMC_CFG_PCH_ALL_TO_VALID ; 8 ; Signed Integer ; -; SEC_HMC_CFG_ARF_TO_VALID ; 140 ; Signed Integer ; -; SEC_HMC_CFG_PDN_TO_VALID ; 4 ; Signed Integer ; -; SEC_HMC_CFG_SRF_TO_VALID ; 513 ; Signed Integer ; -; SEC_HMC_CFG_SRF_TO_ZQ_CAL ; 449 ; Signed Integer ; -; SEC_HMC_CFG_ARF_PERIOD ; 4161 ; Signed Integer ; -; SEC_HMC_CFG_PDN_PERIOD ; 0 ; Signed Integer ; -; SEC_HMC_CFG_ZQCL_TO_VALID ; 257 ; Signed Integer ; -; SEC_HMC_CFG_ZQCS_TO_VALID ; 65 ; Signed Integer ; -; SEC_HMC_CFG_MRS_TO_VALID ; 7 ; Signed Integer ; -; SEC_HMC_CFG_MPS_TO_VALID ; 768 ; Signed Integer ; -; SEC_HMC_CFG_MRR_TO_VALID ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MPR_TO_VALID ; 16 ; Signed Integer ; -; SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 5 ; Signed Integer ; -; SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 6 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MMR_CMD_TO_VALID ; 16 ; Signed Integer ; -; SEC_HMC_CFG_4_ACT_TO_ACT ; 15 ; Signed Integer ; -; SEC_HMC_CFG_16_ACT_TO_ACT ; 0 ; Signed Integer ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; PORT_MEM_CK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_0 ; 8193 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_0 ; 9217 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_K_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_K_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_A_WIDTH ; 17 ; Signed Integer ; -; PORT_MEM_A_PINLOC_0 ; 13643793 ; Signed Integer ; -; PORT_MEM_A_PINLOC_1 ; 16792590 ; Signed Integer ; -; PORT_MEM_A_PINLOC_2 ; 19941393 ; Signed Integer ; -; PORT_MEM_A_PINLOC_3 ; 23090196 ; Signed Integer ; -; PORT_MEM_A_PINLOC_4 ; 29387799 ; Signed Integer ; -; PORT_MEM_A_PINLOC_5 ; 32536605 ; Signed Integer ; -; PORT_MEM_A_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_AUTOGEN_WCNT ; 17 ; Signed Integer ; -; PORT_MEM_BA_WIDTH ; 2 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_0 ; 35685378 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_0 ; 35841 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_C_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_C_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CKE_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_0 ; 6145 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_0 ; 2049 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_RM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_ODT_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_0 ; 4097 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_RESET_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_0 ; 1025 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_0 ; 3073 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_PAR_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_0 ; 11265 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_AUTOGEN_WCNT ; 17 ; Signed Integer ; -; PORT_MEM_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_REF_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_DOFF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DOFF_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LBK0_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK0_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LBK1_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK1_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_CFG_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CFG_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_AP_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AP_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_AP_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_AINV_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AINV_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_D_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_D_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQ_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_0 ; 52479008 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_1 ; 57727027 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_2 ; 60875832 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_3 ; 66123837 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_4 ; 71371842 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_5 ; 76617797 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_6 ; 81865802 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_7 ; 85016655 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_8 ; 90264658 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_9 ; 95512663 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_10 ; 98661468 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DBI_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_0 ; 74509316 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_1 ; 97363 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT ; 7 ; Signed Integer ; -; PORT_MEM_DQA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DINVA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_DINVB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_Q_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQS_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_0 ; 67162116 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_1 ; 90188 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_DQS_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_0 ; 68211716 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_1 ; 91213 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_QK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CQ_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CQ_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_ALERT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_0 ; 49153 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_PE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_CLKS_SHARING_MASTER_OUT_WIDTH ; 32 ; Signed Integer ; -; PORT_CLKS_SHARING_SLAVE_IN_WIDTH ; 32 ; Signed Integer ; -; PORT_AFI_RLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_WLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_SEQ_BUSY_WIDTH ; 4 ; Signed Integer ; -; PORT_AFI_ADDR_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_C_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CKE_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RM_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ODT_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RST_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_PAR_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DOFF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LD_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RW_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LBK0_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LBK1_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CFG_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_AP_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_AINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DM_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_DBI_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_DBI_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_DINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_DINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DQS_BURST_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_VALID_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_EN_FULL_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_VALID_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RRANK_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WRANK_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ALERT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_PE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AST_CMD_DATA_WIDTH ; 58 ; Signed Integer ; -; PORT_CTRL_AST_WR_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_CTRL_AST_RD_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_CTRL_AMM_ADDRESS_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_RDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_WDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_BCOUNT_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_BYTEEN_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_BANK_WIDTH ; 16 ; Signed Integer ; -; PORT_CTRL_SELF_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PORT_CTRL_ECC_WRITE_INFO_WIDTH ; 15 ; Signed Integer ; -; PORT_CTRL_ECC_RDATA_ID_WIDTH ; 13 ; Signed Integer ; -; PORT_CTRL_ECC_READ_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_CMD_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_WB_POINTER_WIDTH ; 12 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH ; 10 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_WIDTH ; 4096 ; Signed Integer ; -; PORT_HPS_EMIF_E2H_WIDTH ; 4096 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_GP_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_E2H_GP_WIDTH ; 1 ; Signed Integer ; -; PORT_CAL_DEBUG_ADDRESS_WIDTH ; 24 ; Signed Integer ; -; PORT_CAL_DEBUG_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH ; 24 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_MASTER_ADDRESS_WIDTH ; 16 ; Signed Integer ; -; PORT_CAL_MASTER_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_IN_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH ; 9 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PLL_CNTSEL_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH ; 3 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH ; 2 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH ; 2 ; Signed Integer ; -; PLL_VCO_FREQ_MHZ_INT ; 1067 ; Signed Integer ; -; PLL_VCO_TO_MEM_CLK_FREQ_RATIO ; 1 ; Signed Integer ; -; PLL_PHY_CLK_VCO_PHASE ; 1 ; Signed Integer ; -; PLL_VCO_FREQ_PS_STR ; 938 ps ; String ; -; PLL_REF_CLK_FREQ_PS_STR ; 3752 ps ; String ; -; PLL_REF_CLK_FREQ_PS ; 3752 ; Signed Integer ; -; PLL_SIM_VCO_FREQ_PS ; 944 ; Signed Integer ; -; PLL_SIM_PHYCLK_0_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHYCLK_1_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHYCLK_FB_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHY_CLK_VCO_PHASE_PS ; 118 ; Signed Integer ; -; PLL_SIM_CAL_SLAVE_CLK_FREQ_PS ; 6608 ; Signed Integer ; -; PLL_SIM_CAL_MASTER_CLK_FREQ_PS ; 6608 ; Signed Integer ; -; PLL_REF_CLK_FREQ_PS_STR_FROM_API ; 3752 ps ; String ; -; PLL_VCO_FREQ_PS_STR_FROM_API ; 938 ps ; String ; -; PLL_M_CNT_HIGH ; 2 ; Signed Integer ; -; PLL_M_CNT_LOW ; 2 ; Signed Integer ; -; PLL_N_CNT_HIGH ; 256 ; Signed Integer ; -; PLL_N_CNT_LOW ; 256 ; Signed Integer ; -; PLL_M_CNT_BYPASS_EN ; false ; String ; -; PLL_N_CNT_BYPASS_EN ; true ; String ; -; PLL_M_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_N_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_CP_SETTING ; pll_cp_setting15 ; String ; -; PLL_BW_CTRL ; pll_bw_res_setting2 ; String ; -; PLL_C_CNT_HIGH_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_0 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_0 ; false ; String ; -; PLL_C_CNT_HIGH_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_1 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_1 ; false ; String ; -; PLL_C_CNT_HIGH_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_2 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_2 ; false ; String ; -; PLL_C_CNT_HIGH_3 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_3 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_3 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_3 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_3 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_3 ; true ; String ; -; PLL_C_CNT_HIGH_4 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_4 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_4 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_4 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_4 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_4 ; true ; String ; -; PLL_C_CNT_HIGH_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_5 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_5 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_5 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_5 ; false ; String ; -; PLL_C_CNT_HIGH_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_6 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_6 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_6 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_6 ; false ; String ; -; PLL_C_CNT_HIGH_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_7 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_7 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_7 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_7 ; false ; String ; -; PLL_C_CNT_HIGH_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_8 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_8 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_8 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_8 ; false ; String ; -; PLL_C_CNT_FREQ_PS_STR_0 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_0 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_0 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_1 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_1 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_1 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_2 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_2 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_2 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_3 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_3 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_3 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_4 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_4 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_4 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_5 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_5 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_5 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_6 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_6 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_6 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_7 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_7 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_7 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_8 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_8 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_8 ; 50 ; Signed Integer ; -; PLL_C_CNT_OUT_EN_0 ; true ; String ; -; PLL_C_CNT_OUT_EN_1 ; true ; String ; -; PLL_C_CNT_OUT_EN_2 ; true ; String ; -; PLL_C_CNT_OUT_EN_3 ; true ; String ; -; PLL_C_CNT_OUT_EN_4 ; true ; String ; -; PLL_C_CNT_OUT_EN_5 ; false ; String ; -; PLL_C_CNT_OUT_EN_6 ; false ; String ; -; PLL_C_CNT_OUT_EN_7 ; false ; String ; -; PLL_C_CNT_OUT_EN_8 ; false ; String ; -; PLL_FBCLK_MUX_1 ; pll_fbclk_mux_1_glb ; String ; -; PLL_FBCLK_MUX_2 ; pll_fbclk_mux_2_m_cnt ; String ; -; PLL_M_CNT_IN_SRC ; c_m_cnt_in_src_ph_mux_clk ; String ; -; PLL_BW_SEL ; high ; String ; -+--------------------------------------------+----------------------------+---------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst ; -+--------------------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ -; PROTOCOL_ENUM ; PROTOCOL_DDR4 ; String ; -; MEM_FORMAT_ENUM ; MEM_FORMAT_DISCRETE ; String ; -; PHY_CONFIG_ENUM ; CONFIG_PHY_AND_HARD_CTRL ; String ; -; PHY_PING_PONG_EN ; 0 ; Signed Integer ; -; PHY_CORE_CLKS_SHARING_ENUM ; CORE_CLKS_SHARING_DISABLED ; String ; -; PHY_HPS_ENABLE_EARLY_RELEASE ; 1 ; Signed Integer ; -; IS_HPS ; 1 ; Signed Integer ; -; IS_VID ; 0 ; Signed Integer ; -; PHY_TARGET_IS_ES ; 0 ; Signed Integer ; -; PHY_TARGET_IS_ES2 ; 0 ; Signed Integer ; -; PHY_TARGET_IS_PRODUCTION ; 1 ; Signed Integer ; -; SILICON_REV ; 20nm4 ; String ; -; PHY_HAS_DCC ; 1 ; Signed Integer ; -; PLL_NUM_OF_EXTRA_CLKS ; 0 ; Signed Integer ; -; USER_CLK_RATIO ; 2 ; Signed Integer ; -; PHY_HMC_CLK_RATIO ; 2 ; Signed Integer ; -; C2P_P2C_CLK_RATIO ; 2 ; Signed Integer ; -; DQS_BUS_MODE_ENUM ; DQS_BUS_MODE_X8_X9 ; String ; -; MEM_BURST_LENGTH ; 8 ; Signed Integer ; -; MEM_DATA_MASK_EN ; 1 ; Signed Integer ; -; MEM_TTL_DATA_WIDTH ; 32 ; Signed Integer ; -; MEM_TTL_NUM_OF_READ_GROUPS ; 4 ; Signed Integer ; -; MEM_TTL_NUM_OF_WRITE_GROUPS ; 4 ; Signed Integer ; -; REGISTER_AFI ; 0 ; Signed Integer ; -; PHY_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_AC_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_CK_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_DATA_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_USERMODE_OCT ; 0 ; Signed Integer ; -; PHY_PERIODIC_OCT_RECAL ; 0 ; Signed Integer ; -; DIAG_SIM_REGTEST_MODE ; 0 ; Signed Integer ; -; DIAG_SYNTH_FOR_SIM ; 0 ; Signed Integer ; -; DIAG_FAST_SIM ; 1 ; Signed Integer ; -; DIAG_VERBOSE_IOAUX ; 0 ; Signed Integer ; -; DIAG_INTERFACE_ID ; 0 ; Signed Integer ; -; DIAG_CPA_OUT_1_EN ; 0 ; Signed Integer ; -; DIAG_USE_CPA_LOCK ; 1 ; Signed Integer ; -; DIAG_ECLIPSE_DEBUG ; 0 ; Signed Integer ; -; DIAG_EXPORT_VJI ; 0 ; Signed Integer ; -; DIAG_USE_ABSTRACT_PHY ; 0 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_WLAT ; 8 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_RLAT ; 19 ; Signed Integer ; -; ABPHY_WRITE_PROTOCOL ; 0 ; Signed Integer ; -; SEQ_CODE_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_cal.hex ; String ; -; SEQ_SYNTH_OSC_FREQ_MHZ ; 450 ; Signed Integer ; -; SEQ_SYNTH_PARAMS_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_synth.hex ; String ; -; SEQ_SYNTH_CPU_CLK_DIVIDE ; 2 ; Signed Integer ; -; SEQ_SYNTH_CAL_CLK_DIVIDE ; 8 ; Signed Integer ; -; SEQ_SIM_OSC_FREQ_MHZ ; 2123 ; Signed Integer ; -; SEQ_SIM_PARAMS_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_sim.hex ; String ; -; SEQ_SIM_CPU_CLK_DIVIDE ; 1 ; Signed Integer ; -; SEQ_SIM_CAL_CLK_DIVIDE ; 32 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; PLL_VCO_FREQ_MHZ_INT ; 1067 ; Signed Integer ; -; PLL_REF_CLK_FREQ_PS ; 3752 ; Signed Integer ; -; PLL_VCO_TO_MEM_CLK_FREQ_RATIO ; 1 ; Signed Integer ; -; PLL_PHY_CLK_VCO_PHASE ; 1 ; Signed Integer ; -; PLL_SIM_VCO_FREQ_PS ; 944 ; Signed Integer ; -; PLL_SIM_PHYCLK_0_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHYCLK_1_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHYCLK_FB_FREQ_PS ; 1888 ; Signed Integer ; -; PLL_SIM_PHY_CLK_VCO_PHASE_PS ; 118 ; Signed Integer ; -; PLL_SIM_CAL_SLAVE_CLK_FREQ_PS ; 6608 ; Signed Integer ; -; PLL_SIM_CAL_MASTER_CLK_FREQ_PS ; 6608 ; Signed Integer ; -; PLL_REF_CLK_FREQ_PS_STR_FROM_API ; 3752 ps ; String ; -; PLL_VCO_FREQ_PS_STR_FROM_API ; 938 ps ; String ; -; PLL_REF_CLK_FREQ_PS_STR ; 3752 ps ; String ; -; PLL_VCO_FREQ_PS_STR ; 938 ps ; String ; -; PLL_M_CNT_HIGH ; 2 ; Signed Integer ; -; PLL_M_CNT_LOW ; 2 ; Signed Integer ; -; PLL_N_CNT_HIGH ; 256 ; Signed Integer ; -; PLL_N_CNT_LOW ; 256 ; Signed Integer ; -; PLL_M_CNT_BYPASS_EN ; false ; String ; -; PLL_N_CNT_BYPASS_EN ; true ; String ; -; PLL_M_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_N_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_FBCLK_MUX_1 ; pll_fbclk_mux_1_glb ; String ; -; PLL_FBCLK_MUX_2 ; pll_fbclk_mux_2_m_cnt ; String ; -; PLL_M_CNT_IN_SRC ; c_m_cnt_in_src_ph_mux_clk ; String ; -; PLL_CP_SETTING ; pll_cp_setting15 ; String ; -; PLL_BW_CTRL ; pll_bw_res_setting2 ; String ; -; PLL_BW_SEL ; high ; String ; -; PLL_C_CNT_HIGH_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_0 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_0 ; false ; String ; -; PLL_C_CNT_HIGH_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_1 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_1 ; false ; String ; -; PLL_C_CNT_HIGH_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_2 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_2 ; false ; String ; -; PLL_C_CNT_HIGH_3 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_3 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_3 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_3 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_3 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_3 ; true ; String ; -; PLL_C_CNT_HIGH_4 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_4 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_4 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_4 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_4 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_4 ; true ; String ; -; PLL_C_CNT_HIGH_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_5 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_5 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_5 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_5 ; false ; String ; -; PLL_C_CNT_HIGH_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_6 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_6 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_6 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_6 ; false ; String ; -; PLL_C_CNT_HIGH_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_7 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_7 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_7 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_7 ; false ; String ; -; PLL_C_CNT_HIGH_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_8 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_8 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_8 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_8 ; false ; String ; -; PLL_C_CNT_FREQ_PS_STR_0 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_0 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_0 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_1 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_1 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_1 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_2 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_2 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_2 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_3 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_3 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_3 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_4 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_4 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_4 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_5 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_5 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_5 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_6 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_6 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_6 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_7 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_7 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_7 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_8 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_8 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_8 ; 50 ; Signed Integer ; -; PLL_C_CNT_OUT_EN_0 ; true ; String ; -; PLL_C_CNT_OUT_EN_1 ; true ; String ; -; PLL_C_CNT_OUT_EN_2 ; true ; String ; -; PLL_C_CNT_OUT_EN_3 ; true ; String ; -; PLL_C_CNT_OUT_EN_4 ; true ; String ; -; PLL_C_CNT_OUT_EN_5 ; false ; String ; -; PLL_C_CNT_OUT_EN_6 ; false ; String ; -; PLL_C_CNT_OUT_EN_7 ; false ; String ; -; PLL_C_CNT_OUT_EN_8 ; false ; String ; -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; HMC_AVL_PROTOCOL_ENUM ; CTRL_AVL_PROTOCOL_ST ; String ; -; HMC_CTRL_DIMM_TYPE ; component ; String ; -; PRI_HMC_CFG_ENABLE_ECC ; disable ; String ; -; PRI_HMC_CFG_REORDER_DATA ; enable ; String ; -; PRI_HMC_CFG_REORDER_READ ; enable ; String ; -; PRI_HMC_CFG_REORDER_RDATA ; enable ; String ; -; PRI_HMC_CFG_STARVE_LIMIT ; 10 ; Signed Integer ; -; PRI_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; PRI_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; PRI_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; PRI_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; PRI_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; PRI_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; PRI_HMC_CFG_SLOT_ROTATE_EN ; 0 ; Signed Integer ; -; PRI_HMC_CFG_SLOT_OFFSET ; 2 ; Signed Integer ; -; PRI_HMC_CFG_COL_CMD_SLOT ; 2 ; Signed Integer ; -; PRI_HMC_CFG_ROW_CMD_SLOT ; 1 ; Signed Integer ; -; PRI_HMC_CFG_ENABLE_RC ; disable ; String ; -; PRI_HMC_CFG_CS_TO_CHIP_MAPPING ; 33825 ; Signed Integer ; -; PRI_HMC_CFG_RB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; PRI_HMC_CFG_WB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; PRI_HMC_CFG_TCL ; 20 ; Signed Integer ; -; PRI_HMC_CFG_POWER_SAVING_EXIT_CYC ; 3 ; Signed Integer ; -; PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 14 ; Signed Integer ; -; PRI_HMC_CFG_WRITE_ODT_CHIP ; 1 ; Signed Integer ; -; PRI_HMC_CFG_READ_ODT_CHIP ; 0 ; Signed Integer ; -; PRI_HMC_CFG_WR_ODT_ON ; 0 ; Signed Integer ; -; PRI_HMC_CFG_RD_ODT_ON ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_ODT_PERIOD ; 6 ; Signed Integer ; -; PRI_HMC_CFG_RD_ODT_PERIOD ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ0 ; 15 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ1 ; 240 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ2 ; 3840 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ3 ; 61440 ; Signed Integer ; -; PRI_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 512 ; Signed Integer ; -; PRI_HMC_CFG_DQSTRK_TO_VALID_LAST ; 24 ; Signed Integer ; -; PRI_HMC_CFG_DQSTRK_TO_VALID ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RFSH_WARN_THRESHOLD ; 4 ; Signed Integer ; -; PRI_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; PRI_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; PRI_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; PRI_HMC_CFG_SB_DDR4_MR3 ; 197120 ; Signed Integer ; -; PRI_HMC_CFG_SB_DDR4_MR4 ; 264192 ; Signed Integer ; -; PRI_HMC_CFG_SB_DDR4_MR5 ; 5152 ; Signed Integer ; -; PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; PRI_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; PRI_HMC_CFG_ACT_TO_RDWR ; 8 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_PCH ; 18 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT ; 26 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 4 ; Signed Integer ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD ; 3 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 4 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_BG ; 2 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_BG ; 7 ; Signed Integer ; -; PRI_HMC_CFG_RD_TO_PCH ; 5 ; Signed Integer ; -; PRI_HMC_CFG_RD_AP_TO_VALID ; 13 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 3 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_BG ; 2 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD ; 17 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 5 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_BG ; 15 ; Signed Integer ; -; PRI_HMC_CFG_WR_TO_PCH ; 19 ; Signed Integer ; -; PRI_HMC_CFG_WR_AP_TO_VALID ; 27 ; Signed Integer ; -; PRI_HMC_CFG_PCH_TO_VALID ; 8 ; Signed Integer ; -; PRI_HMC_CFG_PCH_ALL_TO_VALID ; 8 ; Signed Integer ; -; PRI_HMC_CFG_ARF_TO_VALID ; 140 ; Signed Integer ; -; PRI_HMC_CFG_PDN_TO_VALID ; 4 ; Signed Integer ; -; PRI_HMC_CFG_SRF_TO_VALID ; 513 ; Signed Integer ; -; PRI_HMC_CFG_SRF_TO_ZQ_CAL ; 449 ; Signed Integer ; -; PRI_HMC_CFG_ARF_PERIOD ; 4161 ; Signed Integer ; -; PRI_HMC_CFG_PDN_PERIOD ; 0 ; Signed Integer ; -; PRI_HMC_CFG_ZQCL_TO_VALID ; 257 ; Signed Integer ; -; PRI_HMC_CFG_ZQCS_TO_VALID ; 65 ; Signed Integer ; -; PRI_HMC_CFG_MRS_TO_VALID ; 7 ; Signed Integer ; -; PRI_HMC_CFG_MPS_TO_VALID ; 768 ; Signed Integer ; -; PRI_HMC_CFG_MRR_TO_VALID ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MPR_TO_VALID ; 16 ; Signed Integer ; -; PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 5 ; Signed Integer ; -; PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 6 ; Signed Integer ; -; PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 0 ; Signed Integer ; -; PRI_HMC_CFG_MMR_CMD_TO_VALID ; 16 ; Signed Integer ; -; PRI_HMC_CFG_4_ACT_TO_ACT ; 15 ; Signed Integer ; -; PRI_HMC_CFG_16_ACT_TO_ACT ; 0 ; Signed Integer ; -; SEC_HMC_CFG_ENABLE_ECC ; disable ; String ; -; SEC_HMC_CFG_REORDER_DATA ; enable ; String ; -; SEC_HMC_CFG_REORDER_READ ; enable ; String ; -; SEC_HMC_CFG_REORDER_RDATA ; enable ; String ; -; SEC_HMC_CFG_STARVE_LIMIT ; 10 ; Signed Integer ; -; SEC_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; SEC_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; SEC_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; SEC_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; SEC_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; SEC_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; SEC_HMC_CFG_SLOT_ROTATE_EN ; 0 ; Signed Integer ; -; SEC_HMC_CFG_SLOT_OFFSET ; 2 ; Signed Integer ; -; SEC_HMC_CFG_COL_CMD_SLOT ; 2 ; Signed Integer ; -; SEC_HMC_CFG_ROW_CMD_SLOT ; 1 ; Signed Integer ; -; SEC_HMC_CFG_ENABLE_RC ; disable ; String ; -; SEC_HMC_CFG_CS_TO_CHIP_MAPPING ; 33825 ; Signed Integer ; -; SEC_HMC_CFG_RB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; SEC_HMC_CFG_WB_RESERVED_ENTRY ; 8 ; Signed Integer ; -; SEC_HMC_CFG_TCL ; 20 ; Signed Integer ; -; SEC_HMC_CFG_POWER_SAVING_EXIT_CYC ; 3 ; Signed Integer ; -; SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 14 ; Signed Integer ; -; SEC_HMC_CFG_WRITE_ODT_CHIP ; 1 ; Signed Integer ; -; SEC_HMC_CFG_READ_ODT_CHIP ; 0 ; Signed Integer ; -; SEC_HMC_CFG_WR_ODT_ON ; 0 ; Signed Integer ; -; SEC_HMC_CFG_RD_ODT_ON ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_ODT_PERIOD ; 6 ; Signed Integer ; -; SEC_HMC_CFG_RD_ODT_PERIOD ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ0 ; 15 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ1 ; 240 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ2 ; 3840 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ3 ; 61440 ; Signed Integer ; -; SEC_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 512 ; Signed Integer ; -; SEC_HMC_CFG_DQSTRK_TO_VALID_LAST ; 24 ; Signed Integer ; -; SEC_HMC_CFG_DQSTRK_TO_VALID ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RFSH_WARN_THRESHOLD ; 4 ; Signed Integer ; -; SEC_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; SEC_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; SEC_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; SEC_HMC_CFG_SB_DDR4_MR3 ; 197120 ; Signed Integer ; -; SEC_HMC_CFG_SB_DDR4_MR4 ; 264192 ; Signed Integer ; -; SEC_HMC_CFG_SB_DDR4_MR5 ; 5152 ; Signed Integer ; -; SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; SEC_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; SEC_HMC_CFG_ACT_TO_RDWR ; 8 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_PCH ; 18 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT ; 26 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 4 ; Signed Integer ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD ; 3 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 4 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_BG ; 2 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_BG ; 7 ; Signed Integer ; -; SEC_HMC_CFG_RD_TO_PCH ; 5 ; Signed Integer ; -; SEC_HMC_CFG_RD_AP_TO_VALID ; 13 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 3 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_BG ; 2 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD ; 17 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 5 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_BG ; 15 ; Signed Integer ; -; SEC_HMC_CFG_WR_TO_PCH ; 19 ; Signed Integer ; -; SEC_HMC_CFG_WR_AP_TO_VALID ; 27 ; Signed Integer ; -; SEC_HMC_CFG_PCH_TO_VALID ; 8 ; Signed Integer ; -; SEC_HMC_CFG_PCH_ALL_TO_VALID ; 8 ; Signed Integer ; -; SEC_HMC_CFG_ARF_TO_VALID ; 140 ; Signed Integer ; -; SEC_HMC_CFG_PDN_TO_VALID ; 4 ; Signed Integer ; -; SEC_HMC_CFG_SRF_TO_VALID ; 513 ; Signed Integer ; -; SEC_HMC_CFG_SRF_TO_ZQ_CAL ; 449 ; Signed Integer ; -; SEC_HMC_CFG_ARF_PERIOD ; 4161 ; Signed Integer ; -; SEC_HMC_CFG_PDN_PERIOD ; 0 ; Signed Integer ; -; SEC_HMC_CFG_ZQCL_TO_VALID ; 257 ; Signed Integer ; -; SEC_HMC_CFG_ZQCS_TO_VALID ; 65 ; Signed Integer ; -; SEC_HMC_CFG_MRS_TO_VALID ; 7 ; Signed Integer ; -; SEC_HMC_CFG_MPS_TO_VALID ; 768 ; Signed Integer ; -; SEC_HMC_CFG_MRR_TO_VALID ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MPR_TO_VALID ; 16 ; Signed Integer ; -; SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 5 ; Signed Integer ; -; SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 6 ; Signed Integer ; -; SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 0 ; Signed Integer ; -; SEC_HMC_CFG_MMR_CMD_TO_VALID ; 16 ; Signed Integer ; -; SEC_HMC_CFG_4_ACT_TO_ACT ; 15 ; Signed Integer ; -; SEC_HMC_CFG_16_ACT_TO_ACT ; 0 ; Signed Integer ; -; PREAMBLE_MODE ; preamble_one_cycle ; String ; -; DBI_WR_ENABLE ; false ; String ; -; DBI_RD_ENABLE ; true ; String ; -; CRC_EN ; crc_disable ; String ; -; SWAP_DQS_A_B ; false ; String ; -; DQS_PACK_MODE ; packed ; String ; -; OCT_SIZE ; 2 ; Signed Integer ; -; DBC_WB_RESERVED_ENTRY ; 40 ; Signed Integer ; -; DLL_MODE ; ctl_dynamic ; String ; -; DLL_CODEWORD ; 0 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; AC_PIN_MAP_SCHEME ; use_0_1_2_lane ; String ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; PRI_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PORT_CLKS_SHARING_MASTER_OUT_WIDTH ; 32 ; Signed Integer ; -; PORT_CLKS_SHARING_SLAVE_IN_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_CK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_A_WIDTH ; 17 ; Signed Integer ; -; PORT_MEM_BA_WIDTH ; 2 ; Signed Integer ; -; PORT_MEM_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_C_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CKE_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ODT_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RESET_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PAR_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DOFF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK0_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK1_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CFG_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AP_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AINV_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_D_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQ_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_DBI_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_Q_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQS_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQS_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_QK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ALERT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_WLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_SEQ_BUSY_WIDTH ; 4 ; Signed Integer ; -; PORT_AFI_ADDR_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_C_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CKE_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RM_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ODT_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RST_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_PAR_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DOFF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LD_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RW_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LBK0_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_LBK1_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_CFG_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_AP_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_AINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DM_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_DBI_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_DBI_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_DINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_DINV_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_DQS_BURST_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_VALID_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_EN_FULL_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RDATA_VALID_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_RRANK_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_WRANK_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_ALERT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_AFI_PE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AST_CMD_DATA_WIDTH ; 58 ; Signed Integer ; -; PORT_CTRL_AST_WR_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_CTRL_AST_RD_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_CTRL_AMM_RDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_ADDRESS_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_WDATA_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_BCOUNT_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_BYTEEN_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_BANK_WIDTH ; 16 ; Signed Integer ; -; PORT_CTRL_SELF_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PORT_CTRL_ECC_WRITE_INFO_WIDTH ; 15 ; Signed Integer ; -; PORT_CTRL_ECC_READ_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_CMD_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_WB_POINTER_WIDTH ; 12 ; Signed Integer ; -; PORT_CTRL_ECC_RDATA_ID_WIDTH ; 13 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH ; 10 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_WIDTH ; 4096 ; Signed Integer ; -; PORT_HPS_EMIF_E2H_WIDTH ; 4096 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_GP_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_E2H_GP_WIDTH ; 1 ; Signed Integer ; -; PORT_CAL_DEBUG_ADDRESS_WIDTH ; 24 ; Signed Integer ; -; PORT_CAL_DEBUG_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_DEBUG_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH ; 24 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_OUT_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_ADDRESS_WIDTH ; 16 ; Signed Integer ; -; PORT_CAL_MASTER_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_MASTER_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_IN_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH ; 9 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PLL_CNTSEL_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH ; 3 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH ; 2 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH ; 2 ; Signed Integer ; -; PORT_VJI_IR_IN_WIDTH ; 1 ; Signed Integer ; -; PORT_VJI_IR_OUT_WIDTH ; 1 ; Signed Integer ; -; LANES_USAGE_AUTOGEN_WCNT ; 4 ; Signed Integer ; -; LANES_USAGE_3 ; 0 ; Signed Integer ; -; LANES_USAGE_2 ; 0 ; Signed Integer ; -; LANES_USAGE_1 ; 0 ; Signed Integer ; -; LANES_USAGE_0 ; 11980873 ; Signed Integer ; -; PINS_USAGE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_USAGE_12 ; 0 ; Signed Integer ; -; PINS_USAGE_11 ; 0 ; Signed Integer ; -; PINS_USAGE_10 ; 0 ; Signed Integer ; -; PINS_USAGE_9 ; 0 ; Signed Integer ; -; PINS_USAGE_8 ; 0 ; Signed Integer ; -; PINS_USAGE_7 ; 0 ; Signed Integer ; -; PINS_USAGE_6 ; 0 ; Signed Integer ; -; PINS_USAGE_5 ; 0 ; Signed Integer ; -; PINS_USAGE_4 ; 0 ; Signed Integer ; -; PINS_USAGE_3 ; 63 ; Signed Integer ; -; PINS_USAGE_2 ; 1056960510 ; Signed Integer ; -; PINS_USAGE_1 ; 1073479739 ; Signed Integer ; -; PINS_USAGE_0 ; 956300126 ; Signed Integer ; -; PINS_RATE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_RATE_12 ; 0 ; Signed Integer ; -; PINS_RATE_11 ; 0 ; Signed Integer ; -; PINS_RATE_10 ; 0 ; Signed Integer ; -; PINS_RATE_9 ; 0 ; Signed Integer ; -; PINS_RATE_8 ; 0 ; Signed Integer ; -; PINS_RATE_7 ; 0 ; Signed Integer ; -; PINS_RATE_6 ; 0 ; Signed Integer ; -; PINS_RATE_5 ; 0 ; Signed Integer ; -; PINS_RATE_4 ; 0 ; Signed Integer ; -; PINS_RATE_3 ; 0 ; Signed Integer ; -; PINS_RATE_2 ; 0 ; Signed Integer ; -; PINS_RATE_1 ; 262203 ; Signed Integer ; -; PINS_RATE_0 ; 956299358 ; Signed Integer ; -; PINS_WDB_AUTOGEN_WCNT ; 39 ; Signed Integer ; -; PINS_WDB_38 ; 0 ; Signed Integer ; -; PINS_WDB_37 ; 0 ; Signed Integer ; -; PINS_WDB_36 ; 0 ; Signed Integer ; -; PINS_WDB_35 ; 0 ; Signed Integer ; -; PINS_WDB_34 ; 0 ; Signed Integer ; -; PINS_WDB_33 ; 0 ; Signed Integer ; -; PINS_WDB_32 ; 0 ; Signed Integer ; -; PINS_WDB_31 ; 0 ; Signed Integer ; -; PINS_WDB_30 ; 0 ; Signed Integer ; -; PINS_WDB_29 ; 0 ; Signed Integer ; -; PINS_WDB_28 ; 0 ; Signed Integer ; -; PINS_WDB_27 ; 0 ; Signed Integer ; -; PINS_WDB_26 ; 0 ; Signed Integer ; -; PINS_WDB_25 ; 0 ; Signed Integer ; -; PINS_WDB_24 ; 0 ; Signed Integer ; -; PINS_WDB_23 ; 0 ; Signed Integer ; -; PINS_WDB_22 ; 0 ; Signed Integer ; -; PINS_WDB_21 ; 0 ; Signed Integer ; -; PINS_WDB_20 ; 0 ; Signed Integer ; -; PINS_WDB_19 ; 0 ; Signed Integer ; -; PINS_WDB_18 ; 0 ; Signed Integer ; -; PINS_WDB_17 ; 0 ; Signed Integer ; -; PINS_WDB_16 ; 0 ; Signed Integer ; -; PINS_WDB_15 ; 0 ; Signed Integer ; -; PINS_WDB_14 ; 0 ; Signed Integer ; -; PINS_WDB_13 ; 0 ; Signed Integer ; -; PINS_WDB_12 ; 0 ; Signed Integer ; -; PINS_WDB_11 ; 0 ; Signed Integer ; -; PINS_WDB_10 ; 0 ; Signed Integer ; -; PINS_WDB_9 ; 224694 ; Signed Integer ; -; PINS_WDB_8 ; 316345782 ; Signed Integer ; -; PINS_WDB_7 ; 910912566 ; Signed Integer ; -; PINS_WDB_6 ; 920202672 ; Signed Integer ; -; PINS_WDB_5 ; 920347830 ; Signed Integer ; -; PINS_WDB_4 ; 905969664 ; Signed Integer ; -; PINS_WDB_3 ; 37385 ; Signed Integer ; -; PINS_WDB_2 ; 153092681 ; Signed Integer ; -; PINS_WDB_1 ; 153391688 ; Signed Integer ; -; PINS_WDB_0 ; 151261768 ; Signed Integer ; -; PINS_DATA_IN_MODE_AUTOGEN_WCNT ; 39 ; Signed Integer ; -; PINS_DATA_IN_MODE_38 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_37 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_36 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_35 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_34 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_33 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_32 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_31 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_30 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_29 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_28 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_27 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_26 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_25 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_24 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_23 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_22 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_21 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_20 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_19 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_18 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_17 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_16 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_15 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_14 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_13 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_12 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_11 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_10 ; 0 ; Signed Integer ; -; PINS_DATA_IN_MODE_9 ; 37449 ; Signed Integer ; -; PINS_DATA_IN_MODE_8 ; 1059357257 ; Signed Integer ; -; PINS_DATA_IN_MODE_7 ; 167547401 ; Signed Integer ; -; PINS_DATA_IN_MODE_6 ; 153612872 ; Signed Integer ; -; PINS_DATA_IN_MODE_5 ; 153395145 ; Signed Integer ; -; PINS_DATA_IN_MODE_4 ; 150994944 ; Signed Integer ; -; PINS_DATA_IN_MODE_3 ; 37385 ; Signed Integer ; -; PINS_DATA_IN_MODE_2 ; 153092681 ; Signed Integer ; -; PINS_DATA_IN_MODE_1 ; 153391688 ; Signed Integer ; -; PINS_DATA_IN_MODE_0 ; 1057231432 ; Signed Integer ; -; PINS_C2L_DRIVEN_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_C2L_DRIVEN_12 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_11 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_10 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_9 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_8 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_7 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_6 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_5 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_4 ; 0 ; Signed Integer ; -; PINS_C2L_DRIVEN_3 ; 63 ; Signed Integer ; -; PINS_C2L_DRIVEN_2 ; 251457486 ; Signed Integer ; -; PINS_C2L_DRIVEN_1 ; 1060634624 ; Signed Integer ; -; PINS_C2L_DRIVEN_0 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_IN_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_IN_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_IN_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_OUT_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_DB_OE_BYPASS_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_DB_OE_BYPASS_12 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_11 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_10 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_9 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_8 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_7 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_6 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_5 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_4 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_3 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_2 ; 0 ; Signed Integer ; -; PINS_DB_OE_BYPASS_1 ; 262203 ; Signed Integer ; -; PINS_DB_OE_BYPASS_0 ; 956300126 ; Signed Integer ; -; PINS_INVERT_WR_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_INVERT_WR_12 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_11 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_10 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_9 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_8 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_7 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_6 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_5 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_4 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_3 ; 0 ; Signed Integer ; -; PINS_INVERT_WR_2 ; 537002016 ; Signed Integer ; -; PINS_INVERT_WR_1 ; 8388608 ; Signed Integer ; -; PINS_INVERT_WR_0 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_INVERT_OE_12 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_11 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_10 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_9 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_8 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_7 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_6 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_5 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_4 ; 0 ; Signed Integer ; -; PINS_INVERT_OE_3 ; 63 ; Signed Integer ; -; PINS_INVERT_OE_2 ; 1056960510 ; Signed Integer ; -; PINS_INVERT_OE_1 ; 1073217595 ; Signed Integer ; -; PINS_INVERT_OE_0 ; 956300126 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_12 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_11 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_10 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_9 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_8 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_7 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_6 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_5 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_4 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_3 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_2 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_1 ; 0 ; Signed Integer ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA_0 ; 768 ; Signed Integer ; -; PINS_OCT_MODE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_OCT_MODE_12 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_11 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_10 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_9 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_8 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_7 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_6 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_5 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_4 ; 0 ; Signed Integer ; -; PINS_OCT_MODE_3 ; 63 ; Signed Integer ; -; PINS_OCT_MODE_2 ; 1056960510 ; Signed Integer ; -; PINS_OCT_MODE_1 ; 1073217536 ; Signed Integer ; -; PINS_OCT_MODE_0 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PINS_GPIO_MODE_12 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_11 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_10 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_9 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_8 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_7 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_6 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_5 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_4 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_3 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_2 ; 0 ; Signed Integer ; -; PINS_GPIO_MODE_1 ; 262144 ; Signed Integer ; -; PINS_GPIO_MODE_0 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT ; 129 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_128 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_127 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_126 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_125 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_124 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_123 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_122 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_121 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_120 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_119 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_118 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_117 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_116 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_115 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_114 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_113 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_112 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_111 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_110 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_109 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_108 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_107 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_106 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_105 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_104 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_103 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_102 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_101 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_100 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_99 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_98 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_97 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_96 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_95 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_94 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_93 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_92 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_91 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_90 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_89 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_88 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_87 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_86 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_85 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_84 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_83 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_82 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_81 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_80 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_79 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_78 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_77 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_76 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_75 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_74 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_73 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_72 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_71 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_70 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_69 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_68 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_67 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_66 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_65 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_64 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_63 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_62 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_61 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_60 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_59 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_58 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_57 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_56 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_55 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_54 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_53 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_52 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_51 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_50 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_49 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_48 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_47 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_46 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_45 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_44 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_43 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_42 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_41 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_40 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_39 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_38 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_37 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_36 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_35 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_34 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_33 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_32 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_31 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_30 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_29 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_28 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_27 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_26 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_25 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_24 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_23 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_22 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_21 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_20 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_19 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_18 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_17 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_16 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_15 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_14 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_13 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_12 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_11 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_10 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_9 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_8 ; 0 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_7 ; 5127 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_6 ; 10510361 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_5 ; 27295780 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_4 ; 38836263 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_3 ; 41985066 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_2 ; 45133869 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_1 ; 48282684 ; Signed Integer ; -; UNUSED_MEM_PINS_PINLOC_0 ; 75583511 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT ; 11 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_10 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_9 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_8 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_7 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_6 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_5 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_4 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_3 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_2 ; 0 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_1 ; 1 ; Signed Integer ; -; UNUSED_DQS_BUSES_LANELOC_0 ; 2100228 ; Signed Integer ; -; CENTER_TIDS_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; CENTER_TIDS_2 ; 0 ; Signed Integer ; -; CENTER_TIDS_1 ; 0 ; Signed Integer ; -; CENTER_TIDS_0 ; 6148 ; Signed Integer ; -; HMC_TIDS_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; HMC_TIDS_2 ; 0 ; Signed Integer ; -; HMC_TIDS_1 ; 0 ; Signed Integer ; -; HMC_TIDS_0 ; 6661 ; Signed Integer ; -; LANE_TIDS_AUTOGEN_WCNT ; 10 ; Signed Integer ; -; LANE_TIDS_9 ; 0 ; Signed Integer ; -; LANE_TIDS_8 ; 0 ; Signed Integer ; -; LANE_TIDS_7 ; 0 ; Signed Integer ; -; LANE_TIDS_6 ; 0 ; Signed Integer ; -; LANE_TIDS_5 ; 0 ; Signed Integer ; -; LANE_TIDS_4 ; 0 ; Signed Integer ; -; LANE_TIDS_3 ; 0 ; Signed Integer ; -; LANE_TIDS_2 ; 88 ; Signed Integer ; -; LANE_TIDS_1 ; 168067584 ; Signed Integer ; -; LANE_TIDS_0 ; 403177984 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CK_PINLOC_0 ; 8193 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CK_N_PINLOC_0 ; 9217 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DK_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DK_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DKB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_K_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_K_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_K_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_AUTOGEN_WCNT ; 17 ; Signed Integer ; -; PORT_MEM_A_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_A_PINLOC_5 ; 32536605 ; Signed Integer ; -; PORT_MEM_A_PINLOC_4 ; 29387799 ; Signed Integer ; -; PORT_MEM_A_PINLOC_3 ; 23090196 ; Signed Integer ; -; PORT_MEM_A_PINLOC_2 ; 19941393 ; Signed Integer ; -; PORT_MEM_A_PINLOC_1 ; 16792590 ; Signed Integer ; -; PORT_MEM_A_PINLOC_0 ; 13643793 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BA_PINLOC_0 ; 35685378 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BG_PINLOC_0 ; 35841 ; Signed Integer ; -; PORT_MEM_C_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_C_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_C_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CKE_PINLOC_0 ; 6145 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CS_N_PINLOC_0 ; 2049 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RM_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ODT_PINLOC_0 ; 4097 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RAS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CAS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_WE_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_RESET_N_PINLOC_0 ; 1025 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ACT_N_PINLOC_0 ; 3073 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_PAR_PINLOC_0 ; 11265 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_AUTOGEN_WCNT ; 17 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_REF_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_DOFF_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LBK0_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_LBK1_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_CFG_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_AP_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_AP_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT ; 1 ; Signed Integer ; -; PORT_MEM_AINV_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DM_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_BWS_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_D_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_D_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_10 ; 98661468 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_9 ; 95512663 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_8 ; 90264658 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_7 ; 85016655 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_6 ; 81865802 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_5 ; 76617797 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_4 ; 71371842 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_3 ; 66123837 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_2 ; 60875832 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_1 ; 57727027 ; Signed Integer ; -; PORT_MEM_DQ_PINLOC_0 ; 52479008 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT ; 7 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_1 ; 97363 ; Signed Integer ; -; PORT_MEM_DBI_N_PINLOC_0 ; 74509316 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DQA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DQB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DINVA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT ; 3 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_DINVB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_AUTOGEN_WCNT ; 49 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_48 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_47 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_46 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_45 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_44 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_43 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_42 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_41 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_40 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_39 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_38 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_37 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_36 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_35 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_34 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_33 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_32 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_31 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_30 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_29 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_28 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_27 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_26 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_25 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_24 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_23 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_22 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_21 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_20 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_19 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_18 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_17 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_16 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_15 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_14 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_13 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_Q_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_1 ; 90188 ; Signed Integer ; -; PORT_MEM_DQS_PINLOC_0 ; 67162116 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT ; 13 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_12 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_11 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_10 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_9 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_8 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_7 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_6 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_1 ; 91213 ; Signed Integer ; -; PORT_MEM_DQS_N_PINLOC_0 ; 68211716 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QK_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QK_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKA_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT ; 6 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_5 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_4 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_3 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_2 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_QKB_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_CQ_N_PINLOC_0 ; 0 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_ALERT_N_PINLOC_0 ; 49153 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT ; 2 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_1 ; 0 ; Signed Integer ; -; PORT_MEM_PE_N_PINLOC_0 ; 0 ; Signed Integer ; -+--------------------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst ; -+----------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PORT_DFT_NF_PLL_CNTSEL_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH ; 3 ; Signed Integer ; -; PLL_REF_CLK_FREQ_PS_STR_FROM_API ; 3752 ps ; String ; -; PLL_VCO_FREQ_PS_STR_FROM_API ; 938 ps ; String ; -; PLL_M_CNT_HIGH ; 2 ; Signed Integer ; -; PLL_M_CNT_LOW ; 2 ; Signed Integer ; -; PLL_N_CNT_HIGH ; 256 ; Signed Integer ; -; PLL_N_CNT_LOW ; 256 ; Signed Integer ; -; PLL_M_CNT_BYPASS_EN ; false ; String ; -; PLL_N_CNT_BYPASS_EN ; true ; String ; -; PLL_M_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_N_CNT_EVEN_DUTY_EN ; false ; String ; -; PLL_FBCLK_MUX_1 ; pll_fbclk_mux_1_glb ; String ; -; PLL_FBCLK_MUX_2 ; pll_fbclk_mux_2_m_cnt ; String ; -; PLL_M_CNT_IN_SRC ; c_m_cnt_in_src_ph_mux_clk ; String ; -; PLL_CP_SETTING ; pll_cp_setting15 ; String ; -; PLL_BW_CTRL ; pll_bw_res_setting2 ; String ; -; PLL_BW_SEL ; high ; String ; -; PLL_C_CNT_HIGH_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_0 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_0 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_0 ; false ; String ; -; PLL_C_CNT_HIGH_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_1 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_1 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_1 ; false ; String ; -; PLL_C_CNT_HIGH_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_LOW_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_2 ; 1 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_2 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_2 ; false ; String ; -; PLL_C_CNT_HIGH_3 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_3 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_3 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_3 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_3 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_3 ; true ; String ; -; PLL_C_CNT_HIGH_4 ; 4 ; Signed Integer ; -; PLL_C_CNT_LOW_4 ; 3 ; Signed Integer ; -; PLL_C_CNT_PRST_4 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_4 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_4 ; false ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_4 ; true ; String ; -; PLL_C_CNT_HIGH_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_5 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_5 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_5 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_5 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_5 ; false ; String ; -; PLL_C_CNT_HIGH_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_6 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_6 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_6 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_6 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_6 ; false ; String ; -; PLL_C_CNT_HIGH_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_7 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_7 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_7 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_7 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_7 ; false ; String ; -; PLL_C_CNT_HIGH_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_LOW_8 ; 256 ; Signed Integer ; -; PLL_C_CNT_PRST_8 ; 1 ; Signed Integer ; -; PLL_C_CNT_PH_MUX_PRST_8 ; 0 ; Signed Integer ; -; PLL_C_CNT_BYPASS_EN_8 ; true ; String ; -; PLL_C_CNT_EVEN_DUTY_EN_8 ; false ; String ; -; PLL_C_CNT_FREQ_PS_STR_0 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_0 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_0 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_1 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_1 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_1 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_2 ; 1876 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_2 ; 117 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_2 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_3 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_3 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_3 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_4 ; 6566 ps ; String ; -; PLL_C_CNT_PHASE_PS_STR_4 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_4 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_5 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_5 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_5 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_6 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_6 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_6 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_7 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_7 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_7 ; 50 ; Signed Integer ; -; PLL_C_CNT_FREQ_PS_STR_8 ; 0.0 MHz ; String ; -; PLL_C_CNT_PHASE_PS_STR_8 ; 0 ps ; String ; -; PLL_C_CNT_DUTY_CYCLE_8 ; 50 ; Signed Integer ; -; PLL_C_CNT_OUT_EN_0 ; true ; String ; -; PLL_C_CNT_OUT_EN_1 ; true ; String ; -; PLL_C_CNT_OUT_EN_2 ; true ; String ; -; PLL_C_CNT_OUT_EN_3 ; true ; String ; -; PLL_C_CNT_OUT_EN_4 ; true ; String ; -; PLL_C_CNT_OUT_EN_5 ; false ; String ; -; PLL_C_CNT_OUT_EN_6 ; false ; String ; -; PLL_C_CNT_OUT_EN_7 ; false ; String ; -; PLL_C_CNT_OUT_EN_8 ; false ; String ; -+----------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll_extra_clks:pll_extra_clks_inst ; -+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PLL_NUM_OF_EXTRA_CLKS ; 0 ; Signed Integer ; -; DIAG_SIM_REGTEST_MODE ; 0 ; Signed Integer ; -+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst ; -+------------------------+--------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; PLL_REF_CLK_FREQ_PS ; 3752 ; Signed Integer ; -; PHY_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_USERMODE_OCT ; 0 ; Signed Integer ; -; PHY_PERIODIC_OCT_RECAL ; 0 ; Signed Integer ; -; PHY_CONFIG_ENUM ; CONFIG_PHY_AND_HARD_CTRL ; String ; -; IS_HPS ; 1 ; Signed Integer ; -+------------------------+--------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hps_clks_rsts:hps.hps_clks_rsts_inst ; -+------------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IS_VID ; 0 ; Signed Integer ; -; PORT_CLKS_SHARING_MASTER_OUT_WIDTH ; 32 ; Signed Integer ; -; PORT_CLKS_SHARING_SLAVE_IN_WIDTH ; 32 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH ; 2 ; Signed Integer ; -; PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_GP_WIDTH ; 2 ; Signed Integer ; -; PHY_USERMODE_OCT ; 0 ; Signed Integer ; -; PHY_HPS_ENABLE_EARLY_RELEASE ; 1 ; Signed Integer ; -+------------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst ; -+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; PROTOCOL_ENUM ; PROTOCOL_DDR4 ; String ; -; MEM_FORMAT_ENUM ; MEM_FORMAT_DISCRETE ; String ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; PINS_IN_RTL_TILES ; 96 ; Signed Integer ; -; LANES_IN_RTL_TILES ; 8 ; Signed Integer ; -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; DQS_BUS_MODE_ENUM ; DQS_BUS_MODE_X8_X9 ; String ; -; UNUSED_MEM_PINS_PINLOC ; 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; Unsigned Binary ; -; UNUSED_DQS_BUSES_LANELOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001000000000110000000100 ; Unsigned Binary ; -; PORT_MEM_CK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_K_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_A_WIDTH ; 17 ; Signed Integer ; -; PORT_MEM_BA_WIDTH ; 2 ; Signed Integer ; -; PORT_MEM_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_C_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CKE_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ODT_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RESET_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PAR_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DOFF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK0_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LBK1_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CFG_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AP_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AINV_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_D_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQ_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_DBI_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_Q_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQS_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_DQS_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_QK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QK_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CQ_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ALERT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_PE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000001 ; Unsigned Binary ; -; PORT_MEM_CK_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000001 ; Unsigned Binary ; -; PORT_MEM_DK_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DK_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DKA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DKA_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DKB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DKB_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_K_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_K_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_A_PINLOC ; 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PORT_MEM_C_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CKE_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000001 ; Unsigned Binary ; -; PORT_MEM_CS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001 ; Unsigned Binary ; -; PORT_MEM_RM_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_ODT_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000001 ; Unsigned Binary ; -; PORT_MEM_RAS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CAS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_WE_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RESET_N_PINLOC ; 000000000000000000000000000000000000000000000000010000000001 ; Unsigned Binary ; -; PORT_MEM_ACT_N_PINLOC ; 000000000000000000000000000000000000000000000000110000000001 ; Unsigned Binary ; -; PORT_MEM_PAR_PINLOC ; 000000000000000000000000000000000000000000000010110000000001 ; Unsigned Binary ; -; PORT_MEM_CA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_REF_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_WPS_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RPS_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DOFF_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LDA_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LDB_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RWA_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RWB_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LBK0_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LBK1_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CFG_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_AP_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_AINV_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DM_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_BWS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_D_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DQ_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DBI_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111110001010011000100011100001110110000000100 ; Unsigned Binary ; -; PORT_MEM_DQA_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DQB_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DINVA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DINVB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_Q_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DQS_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110000001001100000100000000001101000000000100 ; Unsigned Binary ; -; PORT_MEM_DQS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110010001001101000100000100001101010000000100 ; Unsigned Binary ; -; PORT_MEM_QK_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QK_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKA_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKB_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CQ_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CQ_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_ALERT_N_PINLOC ; 000000000000000000000000000000000000000000001100000000000001 ; Unsigned Binary ; -; PORT_MEM_PE_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PHY_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_AC_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_CK_CALIBRATED_OCT ; 1 ; Signed Integer ; -; PHY_DATA_CALIBRATED_OCT ; 1 ; Signed Integer ; -+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_df_o:gen_mem_ck.inst[0].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[0].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[1].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[2].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[3].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[4].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[5].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[6].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[7].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[8].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[9].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[10].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[11].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[12].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[13].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[14].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[15].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[16].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[0].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_ba.inst[1].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_bg.inst[0].b ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cke.inst[0].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_cs_n.inst[0].b ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_odt.inst[0].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 0 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_act_n.inst[0].b ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_par.inst[0].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[0].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[1].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[2].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[3].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[4].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[5].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[6].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[7].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[8].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[9].b ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[10].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[11].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[12].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[13].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[14].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[15].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[16].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[17].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[18].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[19].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[20].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[21].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[22].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[23].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[24].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[25].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[26].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[27].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[28].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[29].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[30].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[31].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[0].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[1].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[2].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dbi_n.inst[3].b ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_i:gen_mem_alert_n.inst[0].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 0 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[1].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[2].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[3].b ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OCT_CONTROL_WIDTH ; 16 ; Signed Integer ; -; CALIBRATED_OCT ; 1 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux:io_aux_inst ; -+---------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SILICON_REV ; 20nm4 ; String ; -; IS_HPS ; 1 ; Signed Integer ; -; SEQ_CODE_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_cal.hex ; String ; -; SEQ_SYNTH_OSC_FREQ_MHZ ; 450 ; Signed Integer ; -; SEQ_SYNTH_PARAMS_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_synth.hex ; String ; -; SEQ_SYNTH_CPU_CLK_DIVIDE ; 2 ; Signed Integer ; -; SEQ_SYNTH_CAL_CLK_DIVIDE ; 8 ; Signed Integer ; -; SEQ_SIM_OSC_FREQ_MHZ ; 2123 ; Signed Integer ; -; SEQ_SIM_PARAMS_HEX_FILENAME ; a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_seq_params_sim.hex ; String ; -; SEQ_SIM_CPU_CLK_DIVIDE ; 1 ; Signed Integer ; -; SEQ_SIM_CAL_CLK_DIVIDE ; 32 ; Signed Integer ; -; DIAG_SYNTH_FOR_SIM ; 0 ; Signed Integer ; -; DIAG_ECLIPSE_DEBUG ; 0 ; Signed Integer ; -; DIAG_EXPORT_VJI ; 0 ; Signed Integer ; -; DIAG_INTERFACE_ID ; 0 ; Signed Integer ; -; DIAG_VERBOSE_IOAUX ; 0 ; Signed Integer ; -; PORT_CAL_DEBUG_ADDRESS_WIDTH ; 24 ; Signed Integer ; -; PORT_CAL_DEBUG_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_DEBUG_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_DEBUG_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_ADDRESS_WIDTH ; 16 ; Signed Integer ; -; PORT_CAL_MASTER_BYTEEN_WIDTH ; 4 ; Signed Integer ; -; PORT_CAL_MASTER_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CAL_MASTER_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_IN_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH ; 8 ; Signed Integer ; -+---------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; Parameter Name ; Value ; Type ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; DIAG_SYNTH_FOR_SIM ; 0 ; Signed Integer ; -; DIAG_CPA_OUT_1_EN ; 0 ; Signed Integer ; -; DIAG_FAST_SIM ; 1 ; Signed Integer ; -; IS_HPS ; 1 ; Signed Integer ; -; SILICON_REV ; 20nm4 ; String ; -; PROTOCOL_ENUM ; PROTOCOL_DDR4 ; String ; -; PHY_PING_PONG_EN ; 0 ; Signed Integer ; -; DQS_BUS_MODE_ENUM ; DQS_BUS_MODE_X8_X9 ; String ; -; USER_CLK_RATIO ; 2 ; Signed Integer ; -; PHY_HMC_CLK_RATIO ; 2 ; Signed Integer ; -; C2P_P2C_CLK_RATIO ; 2 ; Signed Integer ; -; PLL_VCO_TO_MEM_CLK_FREQ_RATIO ; 1 ; Signed Integer ; -; PLL_VCO_FREQ_MHZ_INT ; 1067 ; Signed Integer ; -; MEM_BURST_LENGTH ; 8 ; Signed Integer ; -; MEM_DATA_MASK_EN ; 1 ; Signed Integer ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; PINS_IN_RTL_TILES ; 96 ; Signed Integer ; -; LANES_IN_RTL_TILES ; 8 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; AC_PIN_MAP_SCHEME ; use_0_1_2_lane ; String ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; PRI_HMC_DBC_SHADOW_LANE_INDEX ; 3 ; Signed Integer ; -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; HMC_AVL_PROTOCOL_ENUM ; CTRL_AVL_PROTOCOL_ST ; String ; -; HMC_CTRL_DIMM_TYPE ; component ; String ; -; PRI_HMC_CFG_ENABLE_ECC ; disable ; String ; -; PRI_HMC_CFG_REORDER_DATA ; enable ; String ; -; PRI_HMC_CFG_REORDER_READ ; enable ; String ; -; PRI_HMC_CFG_REORDER_RDATA ; enable ; String ; -; PRI_HMC_CFG_STARVE_LIMIT ; 001010 ; Unsigned Binary ; -; PRI_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; PRI_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; PRI_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; PRI_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; PRI_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; PRI_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; PRI_HMC_CFG_SLOT_ROTATE_EN ; 00 ; Unsigned Binary ; -; PRI_HMC_CFG_SLOT_OFFSET ; 10 ; Unsigned Binary ; -; PRI_HMC_CFG_COL_CMD_SLOT ; 0010 ; Unsigned Binary ; -; PRI_HMC_CFG_ROW_CMD_SLOT ; 0001 ; Unsigned Binary ; -; PRI_HMC_CFG_ENABLE_RC ; disable ; String ; -; PRI_HMC_CFG_CS_TO_CHIP_MAPPING ; 1000010000100001 ; Unsigned Binary ; -; PRI_HMC_CFG_RB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; PRI_HMC_CFG_WB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; PRI_HMC_CFG_TCL ; 0010100 ; Unsigned Binary ; -; PRI_HMC_CFG_POWER_SAVING_EXIT_CYC ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 001110 ; Unsigned Binary ; -; PRI_HMC_CFG_WRITE_ODT_CHIP ; 0000000000000001 ; Unsigned Binary ; -; PRI_HMC_CFG_READ_ODT_CHIP ; 0000000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_ODT_ON ; 000000 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_ODT_ON ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_ODT_PERIOD ; 000110 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_ODT_PERIOD ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ0 ; 0000000000001111 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ1 ; 0000000011110000 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ2 ; 0000111100000000 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ3 ; 1111000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 0000001000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_DQSTRK_TO_VALID_LAST ; 00011000 ; Unsigned Binary ; -; PRI_HMC_CFG_DQSTRK_TO_VALID ; 00000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RFSH_WARN_THRESHOLD ; 0000100 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; PRI_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; PRI_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; PRI_HMC_CFG_SB_DDR4_MR3 ; 00110000001000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_DDR4_MR4 ; 01000000100000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_DDR4_MR5 ; 0001010000100000 ; Unsigned Binary ; -; PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Unsigned Binary ; -; PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; PRI_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; PRI_HMC_CFG_ACT_TO_RDWR ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_PCH ; 010010 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT ; 011010 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_BG ; 000010 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_BG ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_PCH ; 000101 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_AP_TO_VALID ; 001101 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_BG ; 000010 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD ; 010001 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 000101 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_BG ; 001111 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_PCH ; 010011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_AP_TO_VALID ; 011011 ; Unsigned Binary ; -; PRI_HMC_CFG_PCH_TO_VALID ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_PCH_ALL_TO_VALID ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_ARF_TO_VALID ; 10001100 ; Unsigned Binary ; -; PRI_HMC_CFG_PDN_TO_VALID ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_TO_VALID ; 1000000001 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_TO_ZQ_CAL ; 0111000001 ; Unsigned Binary ; -; PRI_HMC_CFG_ARF_PERIOD ; 1000001000001 ; Unsigned Binary ; -; PRI_HMC_CFG_PDN_PERIOD ; 0000000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_ZQCL_TO_VALID ; 100000001 ; Unsigned Binary ; -; PRI_HMC_CFG_ZQCS_TO_VALID ; 1000001 ; Unsigned Binary ; -; PRI_HMC_CFG_MRS_TO_VALID ; 0111 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_TO_VALID ; 1100000000 ; Unsigned Binary ; -; PRI_HMC_CFG_MRR_TO_VALID ; 0000 ; Unsigned Binary ; -; PRI_HMC_CFG_MPR_TO_VALID ; 10000 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 0101 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 0110 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 000 ; Unsigned Binary ; -; PRI_HMC_CFG_MMR_CMD_TO_VALID ; 00010000 ; Unsigned Binary ; -; PRI_HMC_CFG_4_ACT_TO_ACT ; 00001111 ; Unsigned Binary ; -; PRI_HMC_CFG_16_ACT_TO_ACT ; 00000000 ; Unsigned Binary ; -; SEC_HMC_CFG_ENABLE_ECC ; disable ; String ; -; SEC_HMC_CFG_REORDER_DATA ; enable ; String ; -; SEC_HMC_CFG_REORDER_READ ; enable ; String ; -; SEC_HMC_CFG_REORDER_RDATA ; enable ; String ; -; SEC_HMC_CFG_STARVE_LIMIT ; 001010 ; Unsigned Binary ; -; SEC_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; SEC_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; SEC_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; SEC_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; SEC_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; SEC_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; SEC_HMC_CFG_SLOT_ROTATE_EN ; 00 ; Unsigned Binary ; -; SEC_HMC_CFG_SLOT_OFFSET ; 10 ; Unsigned Binary ; -; SEC_HMC_CFG_COL_CMD_SLOT ; 0010 ; Unsigned Binary ; -; SEC_HMC_CFG_ROW_CMD_SLOT ; 0001 ; Unsigned Binary ; -; SEC_HMC_CFG_ENABLE_RC ; disable ; String ; -; SEC_HMC_CFG_CS_TO_CHIP_MAPPING ; 1000010000100001 ; Unsigned Binary ; -; SEC_HMC_CFG_RB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; SEC_HMC_CFG_WB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; SEC_HMC_CFG_TCL ; 0010100 ; Unsigned Binary ; -; SEC_HMC_CFG_POWER_SAVING_EXIT_CYC ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 001110 ; Unsigned Binary ; -; SEC_HMC_CFG_WRITE_ODT_CHIP ; 0000000000000001 ; Unsigned Binary ; -; SEC_HMC_CFG_READ_ODT_CHIP ; 0000000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_ODT_ON ; 000000 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_ODT_ON ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_ODT_PERIOD ; 000110 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_ODT_PERIOD ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ0 ; 0000000000001111 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ1 ; 0000000011110000 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ2 ; 0000111100000000 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ3 ; 1111000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 0000001000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_DQSTRK_TO_VALID_LAST ; 00011000 ; Unsigned Binary ; -; SEC_HMC_CFG_DQSTRK_TO_VALID ; 00000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RFSH_WARN_THRESHOLD ; 0000100 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; SEC_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; SEC_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; SEC_HMC_CFG_SB_DDR4_MR3 ; 00110000001000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_DDR4_MR4 ; 01000000100000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_DDR4_MR5 ; 0001010000100000 ; Unsigned Binary ; -; SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Unsigned Binary ; -; SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; SEC_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; SEC_HMC_CFG_ACT_TO_RDWR ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_PCH ; 010010 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT ; 011010 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_BG ; 000010 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_BG ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_PCH ; 000101 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_AP_TO_VALID ; 001101 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_BG ; 000010 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD ; 010001 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 000101 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_BG ; 001111 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_PCH ; 010011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_AP_TO_VALID ; 011011 ; Unsigned Binary ; -; SEC_HMC_CFG_PCH_TO_VALID ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_PCH_ALL_TO_VALID ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_ARF_TO_VALID ; 10001100 ; Unsigned Binary ; -; SEC_HMC_CFG_PDN_TO_VALID ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_TO_VALID ; 1000000001 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_TO_ZQ_CAL ; 0111000001 ; Unsigned Binary ; -; SEC_HMC_CFG_ARF_PERIOD ; 1000001000001 ; Unsigned Binary ; -; SEC_HMC_CFG_PDN_PERIOD ; 0000000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_ZQCL_TO_VALID ; 100000001 ; Unsigned Binary ; -; SEC_HMC_CFG_ZQCS_TO_VALID ; 1000001 ; Unsigned Binary ; -; SEC_HMC_CFG_MRS_TO_VALID ; 0111 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_TO_VALID ; 1100000000 ; Unsigned Binary ; -; SEC_HMC_CFG_MRR_TO_VALID ; 0000 ; Unsigned Binary ; -; SEC_HMC_CFG_MPR_TO_VALID ; 10000 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 0101 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 0110 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 000 ; Unsigned Binary ; -; SEC_HMC_CFG_MMR_CMD_TO_VALID ; 00010000 ; Unsigned Binary ; -; SEC_HMC_CFG_4_ACT_TO_ACT ; 00001111 ; Unsigned Binary ; -; SEC_HMC_CFG_16_ACT_TO_ACT ; 00000000 ; Unsigned Binary ; -; LANES_USAGE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101101101000001001001 ; Unsigned Binary ; -; PINS_USAGE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111111000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_RATE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111100001011110 ; Unsigned Binary ; -; PINS_WDB ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110110110110110110010010110110110000110110110110110110010010110110110000110110110110110110010010110110110000110110110110110110010010110110110110000000000000000000000000000000000000001001001000001001001001001000000000001001001001001001001001001001001001001000001001000001000001001001001000 ; Unsigned Binary ; -; PINS_DB_IN_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_DB_OUT_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_DB_OE_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_INVERT_WR ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000100000000000100000000000100000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PINS_INVERT_OE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111110000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000 ; Unsigned Binary ; -; PINS_DATA_IN_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001001001001001111111001001001000001001001001001001111111001001001000001001001001001001111111001001001000001001001001001001111111001001001001000000000000000000000000000000000000001001001000001001001001001000000000001001001001001001001001001001001001001000111111000001000001001001001000 ; Unsigned Binary ; -; PINS_OCT_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111110000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PINS_GPIO_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; CENTER_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000001100000000100 ; Unsigned Binary ; -; HMC_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000001101000000101 ; Unsigned Binary ; -; LANE_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011000001010000001001000001000000000011000000010000000001000000000 ; Unsigned Binary ; -; PREAMBLE_MODE ; preamble_one_cycle ; String ; -; DBI_WR_ENABLE ; false ; String ; -; DBI_RD_ENABLE ; true ; String ; -; CRC_EN ; crc_disable ; String ; -; SWAP_DQS_A_B ; false ; String ; -; DQS_PACK_MODE ; packed ; String ; -; OCT_SIZE ; 2 ; Signed Integer ; -; DBC_WB_RESERVED_ENTRY ; 0101000 ; Unsigned Binary ; -; DLL_MODE ; ctl_dynamic ; String ; -; DLL_CODEWORD ; 0 ; Signed Integer ; -; PORT_MEM_DQ_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_DQS_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH ; 9 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_MEM_A_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100000111100000011101000001110000000110110000010111000001011000000101010000010100000001001100000100100000010001000001000000000011110000001110000000110100000011000000010001 ; Unsigned Binary ; -; PORT_MEM_BA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000001000010000000010 ; Unsigned Binary ; -; PORT_MEM_BG_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000001 ; Unsigned Binary ; -; PORT_MEM_CS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001 ; Unsigned Binary ; -; PORT_MEM_ACT_N_PINLOC ; 000000000000000000000000000000000000000000000000110000000001 ; Unsigned Binary ; -; PORT_MEM_DQ_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DM_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DBI_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111110001010011000100011100001110110000000100 ; Unsigned Binary ; -; PORT_MEM_RAS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CAS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_WE_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_REF_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_WPS_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RPS_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_BWS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DQA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DQB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_Q_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_D_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RWA_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_RWB_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_QKB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LDA_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_LDB_N_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_CK_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000001 ; Unsigned Binary ; -; PORT_MEM_DINVA_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DINVB_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_AINV_PINLOC ; 000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_A_WIDTH ; 17 ; Signed Integer ; -; PORT_MEM_BA_WIDTH ; 2 ; Signed Integer ; -; PORT_MEM_BG_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_ACT_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DBI_N_WIDTH ; 4 ; Signed Integer ; -; PORT_MEM_RAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CAS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WE_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DM_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_REF_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_WPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RPS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_BWS_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DQB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_Q_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_D_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_RWB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_QKB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDA_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_LDB_N_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_CK_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVA_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_DINVB_WIDTH ; 1 ; Signed Integer ; -; PORT_MEM_AINV_WIDTH ; 1 ; Signed Integer ; -; DIAG_USE_ABSTRACT_PHY ; 0 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_WLAT ; 8 ; Signed Integer ; -; DIAG_ABSTRACT_PHY_RLAT ; 19 ; Signed Integer ; -; ABPHY_WRITE_PROTOCOL ; 0 ; Signed Integer ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; Parameter Name ; Value ; Type ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; DIAG_SYNTH_FOR_SIM ; 0 ; Signed Integer ; -; DIAG_CPA_OUT_1_EN ; 0 ; Signed Integer ; -; DIAG_FAST_SIM ; 1 ; Signed Integer ; -; IS_HPS ; 1 ; Signed Integer ; -; SILICON_REV ; 20nm4 ; String ; -; PROTOCOL_ENUM ; PROTOCOL_DDR4 ; String ; -; PHY_PING_PONG_EN ; 0 ; Signed Integer ; -; DQS_BUS_MODE_ENUM ; DQS_BUS_MODE_X8_X9 ; String ; -; USER_CLK_RATIO ; 2 ; Signed Integer ; -; PHY_HMC_CLK_RATIO ; 2 ; Signed Integer ; -; C2P_P2C_CLK_RATIO ; 2 ; Signed Integer ; -; PLL_VCO_TO_MEM_CLK_FREQ_RATIO ; 1 ; Signed Integer ; -; PLL_VCO_FREQ_MHZ_INT ; 1067 ; Signed Integer ; -; MEM_BURST_LENGTH ; 8 ; Signed Integer ; -; MEM_DATA_MASK_EN ; 1 ; Signed Integer ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; PINS_IN_RTL_TILES ; 96 ; Signed Integer ; -; LANES_IN_RTL_TILES ; 8 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; AC_PIN_MAP_SCHEME ; use_0_1_2_lane ; String ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; PRI_HMC_DBC_SHADOW_LANE_INDEX ; 3 ; Signed Integer ; -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; HMC_AVL_PROTOCOL_ENUM ; CTRL_AVL_PROTOCOL_ST ; String ; -; HMC_CTRL_DIMM_TYPE ; component ; String ; -; PRI_HMC_CFG_ENABLE_ECC ; disable ; String ; -; PRI_HMC_CFG_REORDER_DATA ; enable ; String ; -; PRI_HMC_CFG_REORDER_READ ; enable ; String ; -; PRI_HMC_CFG_REORDER_RDATA ; enable ; String ; -; PRI_HMC_CFG_STARVE_LIMIT ; 001010 ; Unsigned Binary ; -; PRI_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; PRI_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; PRI_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; PRI_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; PRI_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; PRI_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; PRI_HMC_CFG_SLOT_ROTATE_EN ; 00 ; Unsigned Binary ; -; PRI_HMC_CFG_SLOT_OFFSET ; 10 ; Unsigned Binary ; -; PRI_HMC_CFG_COL_CMD_SLOT ; 0010 ; Unsigned Binary ; -; PRI_HMC_CFG_ROW_CMD_SLOT ; 0001 ; Unsigned Binary ; -; PRI_HMC_CFG_ENABLE_RC ; disable ; String ; -; PRI_HMC_CFG_CS_TO_CHIP_MAPPING ; 1000010000100001 ; Unsigned Binary ; -; PRI_HMC_CFG_RB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; PRI_HMC_CFG_WB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; PRI_HMC_CFG_TCL ; 0010100 ; Unsigned Binary ; -; PRI_HMC_CFG_POWER_SAVING_EXIT_CYC ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 001110 ; Unsigned Binary ; -; PRI_HMC_CFG_WRITE_ODT_CHIP ; 0000000000000001 ; Unsigned Binary ; -; PRI_HMC_CFG_READ_ODT_CHIP ; 0000000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_ODT_ON ; 000000 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_ODT_ON ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_ODT_PERIOD ; 000110 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_ODT_PERIOD ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ0 ; 0000000000001111 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ1 ; 0000000011110000 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ2 ; 0000111100000000 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_REFRESH_SEQ3 ; 1111000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; PRI_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 0000001000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_DQSTRK_TO_VALID_LAST ; 00011000 ; Unsigned Binary ; -; PRI_HMC_CFG_DQSTRK_TO_VALID ; 00000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RFSH_WARN_THRESHOLD ; 0000100 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; PRI_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; PRI_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; PRI_HMC_CFG_SB_DDR4_MR3 ; 00110000001000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_DDR4_MR4 ; 01000000100000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_SB_DDR4_MR5 ; 0001010000100000 ; Unsigned Binary ; -; PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Unsigned Binary ; -; PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; PRI_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; PRI_HMC_CFG_ACT_TO_RDWR ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_PCH ; 010010 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT ; 011010 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_RD_DIFF_BG ; 000010 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_WR_DIFF_BG ; 000111 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_TO_PCH ; 000101 ; Unsigned Binary ; -; PRI_HMC_CFG_RD_AP_TO_VALID ; 001101 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 000011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_WR_DIFF_BG ; 000010 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD ; 010001 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 000101 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_RD_DIFF_BG ; 001111 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_TO_PCH ; 010011 ; Unsigned Binary ; -; PRI_HMC_CFG_WR_AP_TO_VALID ; 011011 ; Unsigned Binary ; -; PRI_HMC_CFG_PCH_TO_VALID ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_PCH_ALL_TO_VALID ; 001000 ; Unsigned Binary ; -; PRI_HMC_CFG_ARF_TO_VALID ; 10001100 ; Unsigned Binary ; -; PRI_HMC_CFG_PDN_TO_VALID ; 000100 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_TO_VALID ; 1000000001 ; Unsigned Binary ; -; PRI_HMC_CFG_SRF_TO_ZQ_CAL ; 0111000001 ; Unsigned Binary ; -; PRI_HMC_CFG_ARF_PERIOD ; 1000001000001 ; Unsigned Binary ; -; PRI_HMC_CFG_PDN_PERIOD ; 0000000000000000 ; Unsigned Binary ; -; PRI_HMC_CFG_ZQCL_TO_VALID ; 100000001 ; Unsigned Binary ; -; PRI_HMC_CFG_ZQCS_TO_VALID ; 1000001 ; Unsigned Binary ; -; PRI_HMC_CFG_MRS_TO_VALID ; 0111 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_TO_VALID ; 1100000000 ; Unsigned Binary ; -; PRI_HMC_CFG_MRR_TO_VALID ; 0000 ; Unsigned Binary ; -; PRI_HMC_CFG_MPR_TO_VALID ; 10000 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 0101 ; Unsigned Binary ; -; PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 0110 ; Unsigned Binary ; -; PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 000 ; Unsigned Binary ; -; PRI_HMC_CFG_MMR_CMD_TO_VALID ; 00010000 ; Unsigned Binary ; -; PRI_HMC_CFG_4_ACT_TO_ACT ; 00001111 ; Unsigned Binary ; -; PRI_HMC_CFG_16_ACT_TO_ACT ; 00000000 ; Unsigned Binary ; -; SEC_HMC_CFG_ENABLE_ECC ; disable ; String ; -; SEC_HMC_CFG_REORDER_DATA ; enable ; String ; -; SEC_HMC_CFG_REORDER_READ ; enable ; String ; -; SEC_HMC_CFG_REORDER_RDATA ; enable ; String ; -; SEC_HMC_CFG_STARVE_LIMIT ; 001010 ; Unsigned Binary ; -; SEC_HMC_CFG_DQS_TRACKING_EN ; disable ; String ; -; SEC_HMC_CFG_ARBITER_TYPE ; twot ; String ; -; SEC_HMC_CFG_OPEN_PAGE_EN ; enable ; String ; -; SEC_HMC_CFG_GEAR_DOWN_EN ; disable ; String ; -; SEC_HMC_CFG_RLD3_MULTIBANK_MODE ; singlebank ; String ; -; SEC_HMC_CFG_PING_PONG_MODE ; pingpong_off ; String ; -; SEC_HMC_CFG_SLOT_ROTATE_EN ; 00 ; Unsigned Binary ; -; SEC_HMC_CFG_SLOT_OFFSET ; 10 ; Unsigned Binary ; -; SEC_HMC_CFG_COL_CMD_SLOT ; 0010 ; Unsigned Binary ; -; SEC_HMC_CFG_ROW_CMD_SLOT ; 0001 ; Unsigned Binary ; -; SEC_HMC_CFG_ENABLE_RC ; disable ; String ; -; SEC_HMC_CFG_CS_TO_CHIP_MAPPING ; 1000010000100001 ; Unsigned Binary ; -; SEC_HMC_CFG_RB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; SEC_HMC_CFG_WB_RESERVED_ENTRY ; 0001000 ; Unsigned Binary ; -; SEC_HMC_CFG_TCL ; 0010100 ; Unsigned Binary ; -; SEC_HMC_CFG_POWER_SAVING_EXIT_CYC ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC ; 001110 ; Unsigned Binary ; -; SEC_HMC_CFG_WRITE_ODT_CHIP ; 0000000000000001 ; Unsigned Binary ; -; SEC_HMC_CFG_READ_ODT_CHIP ; 0000000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_ODT_ON ; 000000 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_ODT_ON ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_ODT_PERIOD ; 000110 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_ODT_PERIOD ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ0 ; 0000000000001111 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ1 ; 0000000011110000 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ2 ; 0000111100000000 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_REFRESH_SEQ3 ; 1111000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_ZQCAL_DISABLE ; disable ; String ; -; SEC_HMC_CFG_MPS_DQSTRK_DISABLE ; disable ; String ; -; SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ; disable ; String ; -; SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL ; 0000001000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_DQSTRK_TO_VALID_LAST ; 00011000 ; Unsigned Binary ; -; SEC_HMC_CFG_DQSTRK_TO_VALID ; 00000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RFSH_WARN_THRESHOLD ; 0000100 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_CG_DISABLE ; disable ; String ; -; SEC_HMC_CFG_USER_RFSH_EN ; disable ; String ; -; SEC_HMC_CFG_SRF_AUTOEXIT_EN ; enable ; String ; -; SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ; presrfexit ; String ; -; SEC_HMC_CFG_SB_DDR4_MR3 ; 00110000001000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_DDR4_MR4 ; 01000000100000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_SB_DDR4_MR5 ; 0001010000100000 ; Unsigned Binary ; -; SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR ; 0 ; Unsigned Binary ; -; SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ; col_width_10 ; String ; -; SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ; row_width_15 ; String ; -; SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ; bank_width_2 ; String ; -; SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ; bg_width_1 ; String ; -; SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ; cs_width_0 ; String ; -; SEC_HMC_CFG_ADDR_ORDER ; chip_row_bank_col ; String ; -; SEC_HMC_CFG_ACT_TO_RDWR ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_PCH ; 010010 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT ; 011010 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_RD_DIFF_BG ; 000010 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_WR_DIFF_BG ; 000111 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_TO_PCH ; 000101 ; Unsigned Binary ; -; SEC_HMC_CFG_RD_AP_TO_VALID ; 001101 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP ; 000011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_WR_DIFF_BG ; 000010 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD ; 010001 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP ; 000101 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_RD_DIFF_BG ; 001111 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_TO_PCH ; 010011 ; Unsigned Binary ; -; SEC_HMC_CFG_WR_AP_TO_VALID ; 011011 ; Unsigned Binary ; -; SEC_HMC_CFG_PCH_TO_VALID ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_PCH_ALL_TO_VALID ; 001000 ; Unsigned Binary ; -; SEC_HMC_CFG_ARF_TO_VALID ; 10001100 ; Unsigned Binary ; -; SEC_HMC_CFG_PDN_TO_VALID ; 000100 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_TO_VALID ; 1000000001 ; Unsigned Binary ; -; SEC_HMC_CFG_SRF_TO_ZQ_CAL ; 0111000001 ; Unsigned Binary ; -; SEC_HMC_CFG_ARF_PERIOD ; 1000001000001 ; Unsigned Binary ; -; SEC_HMC_CFG_PDN_PERIOD ; 0000000000000000 ; Unsigned Binary ; -; SEC_HMC_CFG_ZQCL_TO_VALID ; 100000001 ; Unsigned Binary ; -; SEC_HMC_CFG_ZQCS_TO_VALID ; 1000001 ; Unsigned Binary ; -; SEC_HMC_CFG_MRS_TO_VALID ; 0111 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_TO_VALID ; 1100000000 ; Unsigned Binary ; -; SEC_HMC_CFG_MRR_TO_VALID ; 0000 ; Unsigned Binary ; -; SEC_HMC_CFG_MPR_TO_VALID ; 10000 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE ; 0101 ; Unsigned Binary ; -; SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS ; 0110 ; Unsigned Binary ; -; SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY ; 000 ; Unsigned Binary ; -; SEC_HMC_CFG_MMR_CMD_TO_VALID ; 00010000 ; Unsigned Binary ; -; SEC_HMC_CFG_4_ACT_TO_ACT ; 00001111 ; Unsigned Binary ; -; SEC_HMC_CFG_16_ACT_TO_ACT ; 00000000 ; Unsigned Binary ; -; LANES_USAGE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101101101000001001001 ; Unsigned Binary ; -; PINS_USAGE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111111000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_RATE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111100001011110 ; Unsigned Binary ; -; PINS_WDB ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110110110110110110010010110110110000110110110110110110010010110110110000110110110110110110010010110110110000110110110110110110010010110110110110000000000000000000000000000000000000001001001000001001001001001000000000001001001001001001001001001001001001001000001001000001000001001001001000 ; Unsigned Binary ; -; PINS_DB_IN_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_DB_OUT_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_DB_OE_BYPASS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_INVERT_WR ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000100000000000100000000000100000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PINS_INVERT_OE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111110000000000000111011111000111111111111101101011110 ; Unsigned Binary ; -; PINS_AC_HMC_DATA_OVERRIDE_ENA ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000 ; Unsigned Binary ; -; PINS_DATA_IN_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001001001001001111111001001001000001001001001001001111111001001001000001001001001001001111111001001001000001001001001001001111111001001001001000000000000000000000000000000000000001001001000001001001001001000000000001001001001001001001001001001001001001000111111000001000001001001001000 ; Unsigned Binary ; -; PINS_OCT_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110111111111110111111111110111111111110000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PINS_GPIO_MODE ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; CENTER_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000001100000000100 ; Unsigned Binary ; -; HMC_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000001101000000101 ; Unsigned Binary ; -; LANE_TIDS ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011000001010000001001000001000000000011000000010000000001000000000 ; Unsigned Binary ; -; PREAMBLE_MODE ; preamble_one_cycle ; String ; -; DBI_WR_ENABLE ; false ; String ; -; DBI_RD_ENABLE ; true ; String ; -; CRC_EN ; crc_disable ; String ; -; SWAP_DQS_A_B ; false ; String ; -; DQS_PACK_MODE ; packed ; String ; -; OCT_SIZE ; 2 ; Signed Integer ; -; DBC_WB_RESERVED_ENTRY ; 0101000 ; Unsigned Binary ; -; DLL_MODE ; ctl_dynamic ; String ; -; DLL_CODEWORD ; 0 ; Signed Integer ; -; PORT_MEM_DQ_WIDTH ; 32 ; Signed Integer ; -; PORT_MEM_DQS_WIDTH ; 4 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH ; 9 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH ; 8 ; Signed Integer ; -+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_abphy_mux:altera_emif_arch_nf_abphy_mux_inst ; -+--------------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DIAG_USE_ABSTRACT_PHY ; 0 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; PINS_PER_LANE ; 12 ; Signed Integer ; -; PINS_IN_RTL_TILES ; 96 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH ; 8 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH ; 9 ; Signed Integer ; -; PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH ; 8 ; Signed Integer ; -; LANES_IN_RTL_TILES ; 8 ; Signed Integer ; -+--------------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst ; -+----------------------------+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------------+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PHY_CONFIG_ENUM ; CONFIG_PHY_AND_HARD_CTRL ; String ; -; USER_CLK_RATIO ; 2 ; Signed Integer ; -; REGISTER_AFI ; 0 ; Signed Integer ; -; PORT_AFI_RLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_WLAT_WIDTH ; 6 ; Signed Integer ; -; PORT_AFI_SEQ_BUSY_WIDTH ; 4 ; Signed Integer ; -; PORT_HPS_EMIF_H2E_GP_WIDTH ; 2 ; Signed Integer ; -; PORT_HPS_EMIF_E2H_GP_WIDTH ; 1 ; Signed Integer ; -; PHY_USERMODE_OCT ; 0 ; Signed Integer ; -; PHY_PERIODIC_OCT_RECAL ; 0 ; Signed Integer ; -; PHY_HAS_DCC ; 1 ; Signed Integer ; -; IS_HPS ; 1 ; Signed Integer ; -+----------------------------+--------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_req_regs ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 1 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_refresh_done_regs ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_long_idle_regs ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_rlat_regs ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 6 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_wlat_regs ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 6 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_seq_busy_regs ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 0 ; Signed Integer ; -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_success_regs ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 3 ; Signed Integer ; -; WIDTH ; 1 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_fail_regs ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; REGISTER ; 3 ; Signed Integer ; -; WIDTH ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_avl_if:hmc_avl_if_inst ; -+-------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; HMC_AVL_PROTOCOL_ENUM ; CTRL_AVL_PROTOCOL_ST ; String ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; PRI_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_HMC_DBC_SHADOW_LANE_INDEX ; 3 ; Signed Integer ; -; PORT_CTRL_AST_CMD_DATA_WIDTH ; 58 ; Signed Integer ; -; PORT_CTRL_AMM_ADDRESS_WIDTH ; 1 ; Signed Integer ; -; PORT_CTRL_AMM_BCOUNT_WIDTH ; 1 ; Signed Integer ; -+-------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_sideband_if:hmc_sideband_if_inst ; -+-----------------------------------+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------------+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PHY_PING_PONG_EN ; 0 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; PRI_AC_TILE_INDEX ; 0 ; Signed Integer ; -; SEC_AC_TILE_INDEX ; 0 ; Signed Integer ; -; PRI_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; PRI_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_RDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_RDATA_LANE_INDEX ; 0 ; Signed Integer ; -; SEC_WDATA_TILE_INDEX ; 1 ; Signed Integer ; -; SEC_WDATA_LANE_INDEX ; 0 ; Signed Integer ; -; PRI_HMC_DBC_SHADOW_LANE_INDEX ; 3 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PORT_CTRL_USER_REFRESH_BANK_WIDTH ; 16 ; Signed Integer ; -; PORT_CTRL_SELF_REFRESH_REQ_WIDTH ; 4 ; Signed Integer ; -; PRI_HMC_CFG_ENABLE_ECC ; disable ; String ; -; SEC_HMC_CFG_ENABLE_ECC ; disable ; String ; -; PORT_CTRL_ECC_WRITE_INFO_WIDTH ; 15 ; Signed Integer ; -; PORT_CTRL_ECC_READ_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_CMD_INFO_WIDTH ; 3 ; Signed Integer ; -; PORT_CTRL_ECC_WB_POINTER_WIDTH ; 12 ; Signed Integer ; -; PORT_CTRL_ECC_RDATA_ID_WIDTH ; 13 ; Signed Integer ; -+-----------------------------------+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_mmr_if:hmc_mmr_if_inst ; -+-----------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH ; 10 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_RDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_WDATA_WIDTH ; 32 ; Signed Integer ; -; PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH ; 2 ; Signed Integer ; -+-----------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_ast_data_if:hmc.hmc_ast.data_if_inst ; -+-----------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -; PINS_PER_LANE ; 12 ; Signed Integer ; -; LANES_PER_TILE ; 4 ; Signed Integer ; -; NUM_OF_RTL_TILES ; 2 ; Signed Integer ; -; NUM_OF_HMC_PORTS ; 1 ; Signed Integer ; -; PORT_CTRL_AST_WR_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_CTRL_AST_RD_DATA_WIDTH ; 128 ; Signed Integer ; -; PORT_MEM_D_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_DQ_PINLOC ; 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; Unsigned Binary ; -; PORT_MEM_Q_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DM_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PORT_MEM_DBI_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111110001010011000100011100001110110000000100 ; Unsigned Binary ; -; PORT_MEM_BWS_N_PINLOC ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -; PINS_C2L_DRIVEN ; 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111001110111111001110111111001110111111001110000000000000000000000000000000000000000000000000 ; Unsigned Binary ; -+-----------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m ; -+----------------+-------+--------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------+ -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -; EXPORT_JTAG ; 0 ; Signed Integer ; -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; TCK_FREQ_MHZ ; 20 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; -+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sld_mfg_id ; 110 ; Signed Integer ; -; sld_type_id ; 132 ; Signed Integer ; -; sld_version ; 1 ; Signed Integer ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_auto_instance_index ; YES ; String ; -; sld_ir_width ; 3 ; Signed Integer ; -; sld_sim_n_scan ; 0 ; Signed Integer ; -; sld_sim_action ; ; String ; -; sld_sim_total_length ; 0 ; Signed Integer ; -; lpm_type ; sld_virtual_jtag_basic ; String ; -; lpm_hint ; UNUSED ; String ; -+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 3 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 8 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 1 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; -+------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; PIPELINE_READY ; 1 ; Signed Integer ; -+------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FIFO_DEPTH ; 64 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 3 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 1 ; Signed Integer ; -; DATA_WIDTH ; 8 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -; FIFO_WIDTHU ; 1 ; Signed Integer ; -; FAST_VER ; 0 ; Signed Integer ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; -+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller ; -+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 1 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1 ; -+----------------+----------+---------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+----------+---------------------------------------------------------------------------------------------+ -; WRITE_MAX ; 7 ; Signed Integer ; -; READ_MAX ; 8 ; Signed Integer ; -; SLAVE_ADDR_T ; 00111000 ; Unsigned Binary ; -; P_CONF1 ; 00001001 ; Unsigned Binary ; -; P_CONF2 ; 00001010 ; Unsigned Binary ; -; P_RATE ; 00001011 ; Unsigned Binary ; -; P_MFG_ID ; 11111110 ; Unsigned Binary ; -; P_DEV_ID ; 11111111 ; Unsigned Binary ; -; P_LOCT1_H ; 00000000 ; Unsigned Binary ; -; P_LOCT1_L ; 00010000 ; Unsigned Binary ; -; P_REMT1_H ; 00000001 ; Unsigned Binary ; -; P_REMT1_L ; 00010001 ; Unsigned Binary ; -; P_REMT2_H ; 00000010 ; Unsigned Binary ; -; P_REMT2_L ; 00010010 ; Unsigned Binary ; -; P_STATUS ; 00001000 ; Unsigned Binary ; -; SLAVE_ADDR_F ; 10010000 ; Unsigned Binary ; -; P_SPEED ; 00000000 ; Unsigned Binary ; -; P_CONFIG ; 00000010 ; Unsigned Binary ; -; P_DAC ; 00000110 ; Unsigned Binary ; -; P_TACH0 ; 00001100 ; Unsigned Binary ; -; P_ALARM_ENABLE ; 00001000 ; Unsigned Binary ; -; P_GPIO_DEF ; 00000100 ; Unsigned Binary ; -; P_ALARM ; 00001010 ; Unsigned Binary ; -; P_TaC ; 00010110 ; Unsigned Binary ; -; KSCALE ; 4 ; Signed Integer ; -+----------------+----------+---------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL ; -+----------------+-------+-------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------+ -; TEMP_60C ; 60 ; Signed Integer ; -; TEMP_55C ; 55 ; Signed Integer ; -; TEMP_50C ; 50 ; Signed Integer ; -; TEMP_45C ; 45 ; Signed Integer ; -; TEMP_40C ; 40 ; Signed Integer ; -; TEMP_35C ; 35 ; Signed Integer ; -; TEMP_30C ; 30 ; Signed Integer ; -; RPM_3000 ; 3000 ; Signed Integer ; -; RPM_3500 ; 3500 ; Signed Integer ; -; RPM_4000 ; 4000 ; Signed Integer ; -; RPM_4500 ; 4500 ; Signed Integer ; -; RPM_5000 ; 5000 ; Signed Integer ; -; RPM_5500 ; 5500 ; Signed Integer ; -; RPM_6000 ; 6000 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m ; -+----------------+-------+-----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------+ -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -; EXPORT_JTAG ; 0 ; Signed Integer ; -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; TCK_FREQ_MHZ ; 20 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; -+-------------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sld_mfg_id ; 110 ; Signed Integer ; -; sld_type_id ; 132 ; Signed Integer ; -; sld_version ; 1 ; Signed Integer ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_auto_instance_index ; YES ; String ; -; sld_ir_width ; 3 ; Signed Integer ; -; sld_sim_n_scan ; 0 ; Signed Integer ; -; sld_sim_action ; ; String ; -; sld_sim_total_length ; 0 ; Signed Integer ; -; lpm_type ; sld_virtual_jtag_basic ; String ; -; lpm_hint ; UNUSED ; String ; -+-------------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 3 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 8 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 1 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; -+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; PIPELINE_READY ; 1 ; Signed Integer ; -+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_sc_fifo:fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FIFO_DEPTH ; 64 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 3 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 1 ; Signed Integer ; -; DATA_WIDTH ; 8 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_bytes_to_packets:b2p ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_st_packets_to_bytes:p2b ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto ; -+-----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -; FIFO_WIDTHU ; 1 ; Signed Integer ; -; FAST_VER ; 0 ; Signed Integer ; -+-----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; -+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller ; -+---------------------------+----------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+------------------------------------------------------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 1 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge ; -+---------------------+-------+-------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; SYMBOL_WIDTH ; 8 ; Signed Integer ; -; HDL_ADDR_WIDTH ; 10 ; Signed Integer ; -; BURSTCOUNT_WIDTH ; 1 ; Signed Integer ; -; COMMAND_FIFO_DEPTH ; 4 ; Signed Integer ; -; RESPONSE_FIFO_DEPTH ; 4 ; Signed Integer ; -; MASTER_SYNC_DEPTH ; 2 ; Signed Integer ; -; SLAVE_SYNC_DEPTH ; 2 ; Signed Integer ; -; BYTEEN_WIDTH ; 4 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 50 ; Signed Integer ; -; FIFO_DEPTH ; 4 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_IN_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_OUT_FILL_LEVEL ; 0 ; Signed Integer ; -; WR_SYNC_DEPTH ; 2 ; Signed Integer ; -; RD_SYNC_DEPTH ; 2 ; Signed Integer ; -; STREAM_ALMOST_FULL ; 0 ; Signed Integer ; -; STREAM_ALMOST_EMPTY ; 0 ; Signed Integer ; -; BACKPRESSURE_DURING_RESET ; 1 ; Signed Integer ; -; LOOKAHEAD_POINTERS ; 0 ; Signed Integer ; -; PIPELINE_POINTERS ; 0 ; Signed Integer ; -; USE_SPACE_AVAIL_IF ; 0 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 32 ; Signed Integer ; -; FIFO_DEPTH ; 4 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_IN_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_OUT_FILL_LEVEL ; 0 ; Signed Integer ; -; WR_SYNC_DEPTH ; 2 ; Signed Integer ; -; RD_SYNC_DEPTH ; 2 ; Signed Integer ; -; STREAM_ALMOST_FULL ; 0 ; Signed Integer ; -; STREAM_ALMOST_EMPTY ; 0 ; Signed Integer ; -; BACKPRESSURE_DURING_RESET ; 0 ; Signed Integer ; -; LOOKAHEAD_POINTERS ; 0 ; Signed Integer ; -; PIPELINE_POINTERS ; 0 ; Signed Integer ; -; USE_SPACE_AVAIL_IF ; 1 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 3 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[0].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[1].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[2].u ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -; EXPORT_JTAG ; 0 ; Signed Integer ; -; USE_PLI ; 0 ; Signed Integer ; -; PLI_PORT ; 50000 ; Signed Integer ; -+----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; TCK_FREQ_MHZ ; 20 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sld_mfg_id ; 110 ; Signed Integer ; -; sld_type_id ; 132 ; Signed Integer ; -; sld_version ; 1 ; Signed Integer ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_auto_instance_index ; YES ; String ; -; sld_ir_width ; 3 ; Signed Integer ; -; sld_sim_n_scan ; 0 ; Signed Integer ; -; sld_sim_action ; ; String ; -; sld_sim_total_length ; 0 ; Signed Integer ; -; lpm_type ; sld_virtual_jtag_basic ; String ; -; lpm_hint ; UNUSED ; String ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ; -+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PURPOSE ; 1 ; Signed Integer ; -; UPSTREAM_FIFO_SIZE ; 0 ; Signed Integer ; -; DOWNSTREAM_FIFO_SIZE ; 64 ; Signed Integer ; -; MGMT_CHANNEL_WIDTH ; -1 ; Signed Integer ; -+----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 3 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 8 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 1 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 3 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; PIPELINE_READY ; 1 ; Signed Integer ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNC_DEPTH ; 8 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_sc_fifo:fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 8 ; Signed Integer ; -; FIFO_DEPTH ; 64 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 3 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 1 ; Signed Integer ; -; DATA_WIDTH ; 8 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_bytes_to_packets:b2p ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_st_packets_to_bytes:p2b ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -; CHANNEL_WIDTH ; 8 ; Signed Integer ; -; ENCODING ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto ; -+-----------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -; FIFO_DEPTHS ; 2 ; Signed Integer ; -; FIFO_WIDTHU ; 1 ; Signed Integer ; -; FAST_VER ; 0 ; Signed Integer ; -+-----------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; EXPORT_MASTER_SIGNALS ; 0 ; Signed Integer ; -+-----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller ; -+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 1 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altsource_probe_top:issp ; -+-------------------------+-----------------+----------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+-----------------+----------------------------------------+ -; lpm_type ; altsource_probe ; String ; -; lpm_hint ; UNUSED ; String ; -; sld_auto_instance_index ; YES ; String ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_node_info_parameter ; 4746752 ; Signed Integer ; -; sld_ir_width ; 4 ; Signed Integer ; -; instance_id ; RST ; String ; -; probe_width ; 0 ; Signed Integer ; -; source_width ; 3 ; Signed Integer ; -; source_initial_value ; 0 ; String ; -; enable_metastability ; YES ; String ; -+-------------------------+-----------------+----------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl ; -+-------------------------+-----------------+------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+-----------------+------------------------------------------------------------------+ -; lpm_type ; altsource_probe ; String ; -; lpm_hint ; UNUSED ; String ; -; sld_auto_instance_index ; YES ; String ; -; sld_instance_index ; 0 ; Signed Integer ; -; SLD_NODE_INFO ; 4746752 ; Signed Integer ; -; sld_ir_width ; 4 ; Signed Integer ; -; instance_id ; RST ; String ; -; probe_width ; 0 ; Signed Integer ; -; source_width ; 3 ; Signed Integer ; -; source_initial_value ; 0 ; String ; -; enable_metastability ; YES ; String ; -+-------------------------+-----------------+------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2 ; -+----------------+------------------------------+-----------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+------------------------------+-----------------------------------------------------------------------------+ -; INIT_FILE ; a10s_ghrd_onchip_memory2.hex ; String ; -+----------------+------------------------------+-----------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram ; -+------------------------------------+------------------------------+-----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+------------------------------+-----------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 8 ; Signed Integer ; -; WIDTHAD_A ; 18 ; Signed Integer ; -; NUMWORDS_A ; 262144 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Signed Integer ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; a10s_ghrd_onchip_memory2.hex ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 262144 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Arria 10 ; Untyped ; -; CBXI_PARAMETER ; altsyncram_0jk1 ; Untyped ; -+------------------------------------+------------------------------+-----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f ; -+-------------------+-------+----------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------+ -; DATA_WIDTH ; 32 ; Signed Integer ; -; SYMBOL_WIDTH ; 8 ; Signed Integer ; -; RESPONSE_WIDTH ; 2 ; Signed Integer ; -; HDL_ADDR_WIDTH ; 9 ; Signed Integer ; -; BURSTCOUNT_WIDTH ; 1 ; Signed Integer ; -; PIPELINE_COMMAND ; 1 ; Signed Integer ; -; PIPELINE_RESPONSE ; 1 ; Signed Integer ; -; BYTEEN_WIDTH ; 4 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 10 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 18 ; Signed Integer ; -; AV_DATA_W ; 8 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 1 ; Signed Integer ; -; AV_READLATENCY ; 1 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 1 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 0 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; UAV_DATA_W ; 8 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; ID_WIDTH ; 4 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; RDATA_WIDTH ; 64 ; Signed Integer ; -; WDATA_WIDTH ; 64 ; Signed Integer ; -; ADDR_USER_WIDTH ; 5 ; Signed Integer ; -; DATA_USER_WIDTH ; 1 ; Signed Integer ; -; AXI_LOCK_WIDTH ; 2 ; Signed Integer ; -; AXI_BURST_LENGTH_WIDTH ; 4 ; Signed Integer ; -; WRITE_ISSUING_CAPABILITY ; 8 ; Signed Integer ; -; READ_ISSUING_CAPABILITY ; 8 ; Signed Integer ; -; AXI_VERSION ; AXI3 ; String ; -; PKT_THREAD_ID_H ; 144 ; Signed Integer ; -; PKT_THREAD_ID_L ; 141 ; Signed Integer ; -; PKT_QOS_H ; 138 ; Signed Integer ; -; PKT_QOS_L ; 138 ; Signed Integer ; -; PKT_BEGIN_BURST ; 137 ; Signed Integer ; -; PKT_CACHE_H ; 151 ; Signed Integer ; -; PKT_CACHE_L ; 148 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 135 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 131 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 136 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 136 ; Signed Integer ; -; PKT_PROTECTION_H ; 147 ; Signed Integer ; -; PKT_PROTECTION_L ; 145 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 128 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 126 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 130 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 129 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 152 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 153 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 125 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 118 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; PKT_ADDR_H ; 103 ; Signed Integer ; -; PKT_ADDR_L ; 72 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 109 ; Signed Integer ; -; PKT_TRANS_LOCK ; 108 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 104 ; Signed Integer ; -; PKT_TRANS_POSTED ; 105 ; Signed Integer ; -; PKT_TRANS_WRITE ; 106 ; Signed Integer ; -; PKT_TRANS_READ ; 107 ; Signed Integer ; -; PKT_DATA_H ; 63 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 71 ; Signed Integer ; -; PKT_BYTEEN_L ; 64 ; Signed Integer ; -; PKT_SRC_ID_H ; 139 ; Signed Integer ; -; PKT_SRC_ID_L ; 139 ; Signed Integer ; -; PKT_DEST_ID_H ; 140 ; Signed Integer ; -; PKT_DEST_ID_L ; 140 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 156 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 154 ; Signed Integer ; -; ST_DATA_W ; 157 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 8 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_ADDR_W ; 32 ; Signed Integer ; -; PKT_DATA_W ; 64 ; Signed Integer ; -; PKT_BYTEEN_W ; 8 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 1 ; Signed Integer ; -; NUMSYMBOLS ; 8 ; Signed Integer ; -; SELECT_BITS ; 3 ; Signed Integer ; -; IN_DATA_W ; 44 ; Signed Integer ; -; OUT_DATA_W ; 35 ; Signed Integer ; -+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 101 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_SRC_ID_H ; 103 ; Signed Integer ; -; PKT_SRC_ID_L ; 103 ; Signed Integer ; -; PKT_DEST_ID_H ; 104 ; Signed Integer ; -; PKT_DEST_ID_L ; 104 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 89 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 82 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 111 ; Signed Integer ; -; PKT_PROTECTION_L ; 109 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 117 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 116 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 92 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 90 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 118 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 120 ; Signed Integer ; -; ST_DATA_W ; 121 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; ADDR_W ; 32 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 122 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 122 ; Signed Integer ; -; FIFO_DEPTH ; 9 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 122 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 34 ; Signed Integer ; -; FIFO_DEPTH ; 16 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 3 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 1 ; Signed Integer ; -; DATA_WIDTH ; 34 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 7 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 8 ; Signed Integer ; -; PKT_BYTEEN_L ; 8 ; Signed Integer ; -; PKT_ADDR_H ; 40 ; Signed Integer ; -; PKT_ADDR_L ; 9 ; Signed Integer ; -; PKT_TRANS_LOCK ; 45 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 41 ; Signed Integer ; -; PKT_TRANS_POSTED ; 42 ; Signed Integer ; -; PKT_TRANS_WRITE ; 43 ; Signed Integer ; -; PKT_TRANS_READ ; 44 ; Signed Integer ; -; PKT_SRC_ID_H ; 76 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 77 ; Signed Integer ; -; PKT_DEST_ID_L ; 77 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 62 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 47 ; Signed Integer ; -; PKT_PROTECTION_H ; 84 ; Signed Integer ; -; PKT_PROTECTION_L ; 82 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 90 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 89 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 65 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 63 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 91 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 93 ; Signed Integer ; -; ST_DATA_W ; 94 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; ADDR_W ; 32 ; Signed Integer ; -; AVS_DATA_W ; 8 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 1 ; Signed Integer ; -; PKT_SYMBOLS ; 1 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 1 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 95 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_SYMBOLS ; 1 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 95 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 95 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 10 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 0 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 10 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router_001|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002|a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003|a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 105 ; Signed Integer ; -; PKT_DEST_ID_H ; 140 ; Signed Integer ; -; PKT_DEST_ID_L ; 140 ; Signed Integer ; -; PKT_SRC_ID_H ; 139 ; Signed Integer ; -; PKT_SRC_ID_L ; 139 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; PKT_BYTEEN_H ; 71 ; Signed Integer ; -; PKT_BYTEEN_L ; 64 ; Signed Integer ; -; PKT_TRANS_WRITE ; 106 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 157 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 8 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 2 ; Signed Integer ; -; PREVENT_HAZARDS ; 0 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_rd_limiter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 105 ; Signed Integer ; -; PKT_DEST_ID_H ; 140 ; Signed Integer ; -; PKT_DEST_ID_L ; 140 ; Signed Integer ; -; PKT_SRC_ID_H ; 139 ; Signed Integer ; -; PKT_SRC_ID_L ; 139 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; PKT_BYTEEN_H ; 71 ; Signed Integer ; -; PKT_BYTEEN_L ; 64 ; Signed Integer ; -; PKT_TRANS_WRITE ; 106 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 157 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 8 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 2 ; Signed Integer ; -; PREVENT_HAZARDS ; 0 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADAPTER_VERSION ; 13.1 ; String ; -; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ; -; PKT_BEGIN_BURST ; 101 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 89 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 82 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 94 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 93 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 92 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 90 ; Signed Integer ; -; ST_DATA_W ; 121 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 76 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 89 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 101 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 89 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 82 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 94 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 93 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 92 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 90 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; ST_DATA_W ; 121 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 76 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 89 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; TYPE_W ; 0 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 4 ; Signed Integer ; -; SELECT_BITS ; 2 ; Signed Integer ; -; IN_DATA_W ; 35 ; Signed Integer ; -; OUT_DATA_W ; 34 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 8 ; Signed Integer ; -; PIPELINE_POSITION ; 2 ; Signed Integer ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADAPTER_VERSION ; 13.1 ; String ; -; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ; -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 40 ; Signed Integer ; -; PKT_ADDR_L ; 9 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 47 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 62 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 41 ; Signed Integer ; -; PKT_TRANS_WRITE ; 43 ; Signed Integer ; -; PKT_TRANS_READ ; 44 ; Signed Integer ; -; PKT_BYTEEN_H ; 8 ; Signed Integer ; -; PKT_BYTEEN_L ; 8 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 66 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 65 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 63 ; Signed Integer ; -; ST_DATA_W ; 94 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 47 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 62 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 40 ; Signed Integer ; -; PKT_ADDR_L ; 9 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 47 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 62 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 41 ; Signed Integer ; -; PKT_TRANS_WRITE ; 43 ; Signed Integer ; -; PKT_TRANS_READ ; 44 ; Signed Integer ; -; PKT_BYTEEN_H ; 8 ; Signed Integer ; -; PKT_BYTEEN_L ; 8 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 66 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 65 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 63 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; ST_DATA_W ; 94 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 47 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 62 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; TYPE_W ; 0 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 1 ; Signed Integer ; -; SELECT_BITS ; 0 ; Signed Integer ; -; IN_DATA_W ; 35 ; Signed Integer ; -; OUT_DATA_W ; 32 ; Signed Integer ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 8 ; Signed Integer ; -; PIPELINE_POSITION ; 2 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 9 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb ; -+----------------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001|altera_merlin_arbitrator:arb ; -+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 36 ; Signed Integer ; -; IN_PKT_ADDR_H ; 67 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 31 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 81 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 82 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 89 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 90 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 92 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 116 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 117 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 93 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 94 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 118 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 120 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; IN_ST_DATA_W ; 121 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 72 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 103 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 63 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 64 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 71 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 104 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 126 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 128 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 152 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 153 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 109 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 129 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 130 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 154 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 156 ; Signed Integer ; -; OUT_ST_DATA_W ; 157 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 1 ; Signed Integer ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 9 ; Signed Integer ; -; IN_PKT_ADDR_H ; 40 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 7 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 8 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 8 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 41 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 47 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 62 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 63 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 65 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 89 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 90 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 46 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 66 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 67 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 91 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 93 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 43 ; Signed Integer ; -; IN_ST_DATA_W ; 94 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 72 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 103 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 63 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 64 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 71 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 104 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 126 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 128 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 152 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 153 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 109 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 129 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 130 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 154 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 156 ; Signed Integer ; -; OUT_ST_DATA_W ; 157 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 1 ; Signed Integer ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; BYTE_CNT_W ; 8 ; Signed Integer ; -; PKT_SYMBOLS ; 1 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 72 ; Signed Integer ; -; IN_PKT_ADDR_H ; 103 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 63 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 64 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 71 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 104 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 118 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 125 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 126 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 128 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 152 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 153 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 109 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 129 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 130 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 154 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 156 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 106 ; Signed Integer ; -; IN_ST_DATA_W ; 157 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 67 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 31 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 81 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 90 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 92 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 116 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 117 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 93 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 94 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 118 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 120 ; Signed Integer ; -; OUT_ST_DATA_W ; 121 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 1 ; Signed Integer ; -+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 8 ; Signed Integer ; -; SELECT_BITS ; 3 ; Signed Integer ; -; IN_DATA_W ; 44 ; Signed Integer ; -; OUT_DATA_W ; 35 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 72 ; Signed Integer ; -; IN_PKT_ADDR_H ; 103 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 63 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 64 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 71 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 104 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 110 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 117 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 118 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 125 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 126 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 128 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 152 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 153 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 109 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 129 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 130 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 154 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 156 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 106 ; Signed Integer ; -; IN_ST_DATA_W ; 157 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 9 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 40 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 7 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 8 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 8 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 41 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 47 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 63 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 65 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 89 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 90 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 46 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 66 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 67 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 91 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 93 ; Signed Integer ; -; OUT_ST_DATA_W ; 94 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 1 ; Signed Integer ; -+-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 8 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 8 ; Signed Integer ; -; SELECT_BITS ; 3 ; Signed Integer ; -; IN_DATA_W ; 44 ; Signed Integer ; -; OUT_DATA_W ; 35 ; Signed Integer ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 157 ; Signed Integer ; -; BITS_PER_SYMBOL ; 157 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 161 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 157 ; Signed Integer ; -; BITS_PER_SYMBOL ; 157 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 161 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 157 ; Signed Integer ; -; BITS_PER_SYMBOL ; 157 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 161 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 157 ; Signed Integer ; -; BITS_PER_SYMBOL ; 157 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 161 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 10 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 10 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 10 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 32 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 9 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ID_WIDTH ; 4 ; Signed Integer ; -; ADDR_WIDTH ; 21 ; Signed Integer ; -; RDATA_WIDTH ; 32 ; Signed Integer ; -; WDATA_WIDTH ; 32 ; Signed Integer ; -; ADDR_USER_WIDTH ; 5 ; Signed Integer ; -; DATA_USER_WIDTH ; 1 ; Signed Integer ; -; AXI_LOCK_WIDTH ; 2 ; Signed Integer ; -; AXI_BURST_LENGTH_WIDTH ; 4 ; Signed Integer ; -; WRITE_ISSUING_CAPABILITY ; 8 ; Signed Integer ; -; READ_ISSUING_CAPABILITY ; 8 ; Signed Integer ; -; AXI_VERSION ; AXI3 ; String ; -; PKT_THREAD_ID_H ; 106 ; Signed Integer ; -; PKT_THREAD_ID_L ; 103 ; Signed Integer ; -; PKT_QOS_H ; 100 ; Signed Integer ; -; PKT_QOS_L ; 100 ; Signed Integer ; -; PKT_BEGIN_BURST ; 99 ; Signed Integer ; -; PKT_CACHE_H ; 113 ; Signed Integer ; -; PKT_CACHE_L ; 110 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 97 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 93 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 98 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 98 ; Signed Integer ; -; PKT_PROTECTION_H ; 109 ; Signed Integer ; -; PKT_PROTECTION_L ; 107 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 90 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 88 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 91 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 114 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 115 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 80 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 101 ; Signed Integer ; -; PKT_SRC_ID_L ; 101 ; Signed Integer ; -; PKT_DEST_ID_H ; 102 ; Signed Integer ; -; PKT_DEST_ID_L ; 102 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 118 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 116 ; Signed Integer ; -; ST_DATA_W ; 119 ; Signed Integer ; -; ST_CHANNEL_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 7 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 7 ; Signed Integer ; -; PKT_ADDR_W ; 32 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 7 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 1 ; Signed Integer ; -; NUMSYMBOLS ; 4 ; Signed Integer ; -; SELECT_BITS ; 2 ; Signed Integer ; -; IN_DATA_W ; 43 ; Signed Integer ; -; OUT_DATA_W ; 34 ; Signed Integer ; -+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 100 ; Signed Integer ; -; PKT_QOS_L ; 100 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 98 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 98 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 97 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 93 ; Signed Integer ; -; PKT_CACHE_H ; 113 ; Signed Integer ; -; PKT_CACHE_L ; 110 ; Signed Integer ; -; PKT_THREAD_ID_H ; 106 ; Signed Integer ; -; PKT_THREAD_ID_L ; 103 ; Signed Integer ; -; PKT_BEGIN_BURST ; 99 ; Signed Integer ; -; PKT_PROTECTION_H ; 109 ; Signed Integer ; -; PKT_PROTECTION_L ; 107 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 80 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 90 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 88 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 91 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 101 ; Signed Integer ; -; PKT_SRC_ID_L ; 101 ; Signed Integer ; -; PKT_DEST_ID_H ; 102 ; Signed Integer ; -; PKT_DEST_ID_L ; 102 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 114 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 115 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 116 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 118 ; Signed Integer ; -; ST_DATA_W ; 119 ; Signed Integer ; -; ST_CHANNEL_W ; 3 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 127 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 7 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 7 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 32 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -; PKT_BURST_SIZE_W ; 3 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 99 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_SRC_ID_H ; 101 ; Signed Integer ; -; PKT_SRC_ID_L ; 101 ; Signed Integer ; -; PKT_DEST_ID_H ; 102 ; Signed Integer ; -; PKT_DEST_ID_L ; 102 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 81 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 80 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 109 ; Signed Integer ; -; PKT_PROTECTION_L ; 107 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 115 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 114 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 90 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 88 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 116 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 118 ; Signed Integer ; -; ST_DATA_W ; 119 ; Signed Integer ; -; ST_CHANNEL_W ; 3 ; Signed Integer ; -; ADDR_W ; 32 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 120 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 7 ; Signed Integer ; -; BYTE_CNT_W ; 7 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 120 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 120 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 34 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 0 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 34 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_001|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router_002|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003|a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; ADAPTER_VERSION ; 13.1 ; String ; -; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ; -; PKT_BEGIN_BURST ; 99 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 80 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 81 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 91 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 90 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 88 ; Signed Integer ; -; ST_DATA_W ; 119 ; Signed Integer ; -; ST_CHANNEL_W ; 3 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 76 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 87 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 99 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 80 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 81 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 91 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 90 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 88 ; Signed Integer ; -; IN_NARROW_SIZE ; 1 ; Signed Integer ; -; OUT_NARROW_SIZE ; 0 ; Signed Integer ; -; OUT_FIXED ; 0 ; Signed Integer ; -; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; -; ST_DATA_W ; 119 ; Signed Integer ; -; ST_CHANNEL_W ; 3 ; Signed Integer ; -; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ; -; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ; -; PIPE_INPUTS ; 0 ; Signed Integer ; -; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; -; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ; -; OUT_BYTE_CNT_H ; 76 ; Signed Integer ; -; OUT_BURSTWRAP_H ; 87 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; TYPE_W ; 0 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 4 ; Signed Integer ; -; SELECT_BITS ; 2 ; Signed Integer ; -; IN_DATA_W ; 35 ; Signed Integer ; -; OUT_DATA_W ; 34 ; Signed Integer ; -+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 7 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BYTE_CNT_W ; 7 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 7 ; Signed Integer ; -; PIPELINE_POSITION ; 2 ; Signed Integer ; -+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 3 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 6 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator ; -+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 9 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; USE_BURSTCOUNT ; 1 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 6 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 1 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 1 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 9 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 63 ; Signed Integer ; -; PKT_QOS_L ; 63 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 61 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 61 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 60 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 60 ; Signed Integer ; -; PKT_CACHE_H ; 77 ; Signed Integer ; -; PKT_CACHE_L ; 74 ; Signed Integer ; -; PKT_THREAD_ID_H ; 70 ; Signed Integer ; -; PKT_THREAD_ID_L ; 70 ; Signed Integer ; -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 59 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 58 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 50 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 1 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 1 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 9 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 3 ; Signed Integer ; -; PKT_DEST_ID_W ; 3 ; Signed Integer ; -; PKT_BURST_SIZE_W ; 3 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; ADDR_W ; 9 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 84 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 9 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 84 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; ADDR_W ; 9 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 84 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 9 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 84 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; ADDR_W ; 9 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 84 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 9 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 84 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; ADDR_W ; 9 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 84 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 9 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 84 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 62 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 44 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 49 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 45 ; Signed Integer ; -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 48 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 54 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_PROTECTION_H ; 73 ; Signed Integer ; -; PKT_PROTECTION_L ; 71 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 79 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 78 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 57 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 55 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 80 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 82 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; ADDR_W ; 9 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 84 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 9 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 84 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router|a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_002|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_003|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_004|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_005|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 46 ; Signed Integer ; -; PKT_DEST_ID_H ; 69 ; Signed Integer ; -; PKT_DEST_ID_L ; 67 ; Signed Integer ; -; PKT_SRC_ID_H ; 66 ; Signed Integer ; -; PKT_SRC_ID_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 53 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 51 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_TRANS_WRITE ; 47 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 83 ; Signed Integer ; -; ST_CHANNEL_W ; 5 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 1 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 5 ; Signed Integer ; -; PREVENT_HAZARDS ; 0 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 5 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 10 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_002 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_003 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_004 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 10 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_ADDRESS_W ; 10 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; USE_BURSTCOUNT ; 1 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 1 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 10 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 1 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 10 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 64 ; Signed Integer ; -; PKT_QOS_L ; 64 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 62 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 62 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 61 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 61 ; Signed Integer ; -; PKT_CACHE_H ; 74 ; Signed Integer ; -; PKT_CACHE_L ; 71 ; Signed Integer ; -; PKT_THREAD_ID_H ; 67 ; Signed Integer ; -; PKT_THREAD_ID_L ; 67 ; Signed Integer ; -; PKT_BEGIN_BURST ; 63 ; Signed Integer ; -; PKT_PROTECTION_H ; 70 ; Signed Integer ; -; PKT_PROTECTION_L ; 68 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 55 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 52 ; Signed Integer ; -; PKT_ADDR_H ; 45 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 58 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 56 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 60 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 59 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 51 ; Signed Integer ; -; PKT_TRANS_LOCK ; 50 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 46 ; Signed Integer ; -; PKT_TRANS_POSTED ; 47 ; Signed Integer ; -; PKT_TRANS_WRITE ; 48 ; Signed Integer ; -; PKT_TRANS_READ ; 49 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 65 ; Signed Integer ; -; PKT_SRC_ID_L ; 65 ; Signed Integer ; -; PKT_DEST_ID_H ; 66 ; Signed Integer ; -; PKT_DEST_ID_L ; 66 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 75 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 76 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 77 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 79 ; Signed Integer ; -; ST_DATA_W ; 80 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 1 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 1 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 10 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -; PKT_BURST_SIZE_W ; 3 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 63 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 45 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 50 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 46 ; Signed Integer ; -; PKT_TRANS_POSTED ; 47 ; Signed Integer ; -; PKT_TRANS_WRITE ; 48 ; Signed Integer ; -; PKT_TRANS_READ ; 49 ; Signed Integer ; -; PKT_SRC_ID_H ; 65 ; Signed Integer ; -; PKT_SRC_ID_L ; 65 ; Signed Integer ; -; PKT_DEST_ID_H ; 66 ; Signed Integer ; -; PKT_DEST_ID_L ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 55 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 52 ; Signed Integer ; -; PKT_PROTECTION_H ; 70 ; Signed Integer ; -; PKT_PROTECTION_L ; 68 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 76 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 75 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 58 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 56 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 77 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 79 ; Signed Integer ; -; ST_DATA_W ; 80 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; ADDR_W ; 10 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 81 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 10 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 81 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 81 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 34 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 0 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 34 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 63 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 45 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 50 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 46 ; Signed Integer ; -; PKT_TRANS_POSTED ; 47 ; Signed Integer ; -; PKT_TRANS_WRITE ; 48 ; Signed Integer ; -; PKT_TRANS_READ ; 49 ; Signed Integer ; -; PKT_SRC_ID_H ; 65 ; Signed Integer ; -; PKT_SRC_ID_L ; 65 ; Signed Integer ; -; PKT_DEST_ID_H ; 66 ; Signed Integer ; -; PKT_DEST_ID_L ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 55 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 55 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 52 ; Signed Integer ; -; PKT_PROTECTION_H ; 70 ; Signed Integer ; -; PKT_PROTECTION_L ; 68 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 76 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 75 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 58 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 56 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 77 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 79 ; Signed Integer ; -; ST_DATA_W ; 80 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; ADDR_W ; 10 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 81 ; Signed Integer ; -; ECC_ENABLE ; 0 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 10 ; Signed Integer ; -; BURSTWRAP_W ; 1 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 81 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 81 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 34 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 0 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 34 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router|a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_002|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 47 ; Signed Integer ; -; PKT_DEST_ID_H ; 66 ; Signed Integer ; -; PKT_DEST_ID_L ; 66 ; Signed Integer ; -; PKT_SRC_ID_H ; 65 ; Signed Integer ; -; PKT_SRC_ID_L ; 65 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 54 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 52 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_TRANS_WRITE ; 48 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 80 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 5 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 2 ; Signed Integer ; -; PREVENT_HAZARDS ; 0 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 80 ; Signed Integer ; -; BITS_PER_SYMBOL ; 80 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 80 ; Signed Integer ; -; BITS_PER_SYMBOL ; 80 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 80 ; Signed Integer ; -; BITS_PER_SYMBOL ; 80 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003 ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 80 ; Signed Integer ; -; BITS_PER_SYMBOL ; 80 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_CHANNEL ; 1 ; Signed Integer ; -; CHANNEL_WIDTH ; 2 ; Signed Integer ; -; USE_ERROR ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 1 ; Signed Integer ; -; VALID_SYNC_DEPTH ; 2 ; Signed Integer ; -; READY_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 84 ; Signed Integer ; -; FORWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; BACKWARD_SYNC_DEPTH ; 2 ; Signed Integer ; -; USE_OUTPUT_PIPELINE ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:out_to_in_synchronizer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -; rst_value ; 0 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter_001 ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; inBitsPerSymbol ; 34 ; Signed Integer ; -; inUsePackets ; 0 ; Signed Integer ; -; inDataWidth ; 34 ; Signed Integer ; -; inChannelWidth ; 0 ; Signed Integer ; -; inErrorWidth ; 0 ; Signed Integer ; -; inUseEmptyPort ; 0 ; Signed Integer ; -; inUseValid ; 1 ; Signed Integer ; -; inUseReady ; 1 ; Signed Integer ; -; inReadyLatency ; 0 ; Signed Integer ; -; outDataWidth ; 34 ; Signed Integer ; -; outChannelWidth ; 0 ; Signed Integer ; -; outErrorWidth ; 1 ; Signed Integer ; -; outUseEmptyPort ; 0 ; Signed Integer ; -; outUseValid ; 1 ; Signed Integer ; -; outUseReady ; 1 ; Signed Integer ; -; outReadyLatency ; 0 ; Signed Integer ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_translator:hps_m_master_translator ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 32 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 104 ; Signed Integer ; -; PKT_QOS_L ; 104 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 102 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 102 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 101 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 97 ; Signed Integer ; -; PKT_CACHE_H ; 114 ; Signed Integer ; -; PKT_CACHE_L ; 111 ; Signed Integer ; -; PKT_THREAD_ID_H ; 107 ; Signed Integer ; -; PKT_THREAD_ID_L ; 107 ; Signed Integer ; -; PKT_BEGIN_BURST ; 103 ; Signed Integer ; -; PKT_PROTECTION_H ; 110 ; Signed Integer ; -; PKT_PROTECTION_L ; 108 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 105 ; Signed Integer ; -; PKT_SRC_ID_L ; 105 ; Signed Integer ; -; PKT_DEST_ID_H ; 106 ; Signed Integer ; -; PKT_DEST_ID_L ; 106 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 1 ; Signed Integer ; -; BURSTWRAP_VALUE ; 511 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 9 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 32 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -; PKT_BURST_SIZE_W ; 3 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; PKT_QOS_H ; 212 ; Signed Integer ; -; PKT_QOS_L ; 212 ; Signed Integer ; -; PKT_THREAD_ID_H ; 215 ; Signed Integer ; -; PKT_THREAD_ID_L ; 215 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; PKT_BEGIN_BURST ; 211 ; Signed Integer ; -; PKT_CACHE_H ; 222 ; Signed Integer ; -; PKT_CACHE_L ; 219 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 210 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 210 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 209 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 205 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; PKT_PROTECTION_H ; 218 ; Signed Integer ; -; PKT_PROTECTION_L ; 216 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; PKT_ADDR_H ; 175 ; Signed Integer ; -; PKT_ADDR_L ; 144 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; PKT_TRANS_LOCK ; 180 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; PKT_TRANS_POSTED ; 177 ; Signed Integer ; -; PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; PKT_TRANS_READ ; 179 ; Signed Integer ; -; PKT_DATA_H ; 127 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 143 ; Signed Integer ; -; PKT_BYTEEN_L ; 128 ; Signed Integer ; -; PKT_SRC_ID_H ; 213 ; Signed Integer ; -; PKT_SRC_ID_L ; 213 ; Signed Integer ; -; PKT_DEST_ID_H ; 214 ; Signed Integer ; -; PKT_DEST_ID_L ; 214 ; Signed Integer ; -; ST_DATA_W ; 228 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; RDATA_WIDTH ; 128 ; Signed Integer ; -; WDATA_WIDTH ; 128 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; AXI_SLAVE_ID_W ; 4 ; Signed Integer ; -; ADDR_USER_WIDTH ; 5 ; Signed Integer ; -; WRITE_ACCEPTANCE_CAPABILITY ; 8 ; Signed Integer ; -; READ_ACCEPTANCE_CAPABILITY ; 8 ; Signed Integer ; -; PASS_ID_TO_SLAVE ; 0 ; Signed Integer ; -; AXI_VERSION ; AXI3 ; String ; -; RESPONSE_W ; 2 ; Signed Integer ; -; AXI_WSTRB_W ; 16 ; Signed Integer ; -; PKT_DATA_W ; 128 ; Signed Integer ; -; NUMSYMBOLS ; 16 ; Signed Integer ; -; DATA_USER_WIDTH ; 1 ; Signed Integer ; -; AXI_LOCK_WIDTH ; 2 ; Signed Integer ; -; AXI_BURST_LENGTH_WIDTH ; 4 ; Signed Integer ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_address_alignment:check_and_align_address_to_size ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 16 ; Signed Integer ; -; SELECT_BITS ; 4 ; Signed Integer ; -; IN_DATA_W ; 45 ; Signed Integer ; -; OUT_DATA_W ; 36 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_burst_uncompressor:read_burst_uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 16 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 229 ; Signed Integer ; -; FIFO_DEPTH ; 8 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 229 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 229 ; Signed Integer ; -; FIFO_DEPTH ; 8 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 229 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_DEST_ID_H ; 106 ; Signed Integer ; -; PKT_DEST_ID_L ; 106 ; Signed Integer ; -; PKT_SRC_ID_H ; 105 ; Signed Integer ; -; PKT_SRC_ID_L ; 105 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 8 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 2 ; Signed Integer ; -; PREVENT_HAZARDS ; 1 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 36 ; Signed Integer ; -; IN_PKT_ADDR_H ; 67 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 31 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; IN_ST_DATA_W ; 120 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 144 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 175 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 127 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; OUT_ST_DATA_W ; 228 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 36 ; Signed Integer ; -; IN_PKT_ADDR_H ; 67 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 31 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; IN_ST_DATA_W ; 120 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 144 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 175 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 127 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; OUT_ST_DATA_W ; 228 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 144 ; Signed Integer ; -; IN_PKT_ADDR_H ; 175 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 127 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; IN_ST_DATA_W ; 228 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 67 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 31 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; OUT_ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 1 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_rsp_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 144 ; Signed Integer ; -; IN_PKT_ADDR_H ; 175 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 127 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; IN_ST_DATA_W ; 228 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 67 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 31 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; OUT_ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 1 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_translator:f2sdram_m_master_translator ; -+-----------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 32 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_ADDRESS_W ; 32 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 1 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -+-----------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 104 ; Signed Integer ; -; PKT_QOS_L ; 104 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 102 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 102 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 101 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 97 ; Signed Integer ; -; PKT_CACHE_H ; 114 ; Signed Integer ; -; PKT_CACHE_L ; 111 ; Signed Integer ; -; PKT_THREAD_ID_H ; 107 ; Signed Integer ; -; PKT_THREAD_ID_L ; 107 ; Signed Integer ; -; PKT_BEGIN_BURST ; 103 ; Signed Integer ; -; PKT_PROTECTION_H ; 110 ; Signed Integer ; -; PKT_PROTECTION_L ; 108 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_ADDR_H ; 67 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; PKT_TRANS_LOCK ; 72 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 71 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 105 ; Signed Integer ; -; PKT_SRC_ID_L ; 105 ; Signed Integer ; -; PKT_DEST_ID_H ; 106 ; Signed Integer ; -; PKT_DEST_ID_L ; 106 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 1 ; Signed Integer ; -; BURSTWRAP_VALUE ; 511 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 9 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 32 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 1 ; Signed Integer ; -; PKT_DEST_ID_W ; 1 ; Signed Integer ; -; PKT_BURST_SIZE_W ; 3 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; PKT_QOS_H ; 212 ; Signed Integer ; -; PKT_QOS_L ; 212 ; Signed Integer ; -; PKT_THREAD_ID_H ; 215 ; Signed Integer ; -; PKT_THREAD_ID_L ; 215 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; PKT_BEGIN_BURST ; 211 ; Signed Integer ; -; PKT_CACHE_H ; 222 ; Signed Integer ; -; PKT_CACHE_L ; 219 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 210 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 210 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 209 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 205 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; PKT_PROTECTION_H ; 218 ; Signed Integer ; -; PKT_PROTECTION_L ; 216 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; PKT_ADDR_H ; 175 ; Signed Integer ; -; PKT_ADDR_L ; 144 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; PKT_TRANS_LOCK ; 180 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; PKT_TRANS_POSTED ; 177 ; Signed Integer ; -; PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; PKT_TRANS_READ ; 179 ; Signed Integer ; -; PKT_DATA_H ; 127 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 143 ; Signed Integer ; -; PKT_BYTEEN_L ; 128 ; Signed Integer ; -; PKT_SRC_ID_H ; 213 ; Signed Integer ; -; PKT_SRC_ID_L ; 213 ; Signed Integer ; -; PKT_DEST_ID_H ; 214 ; Signed Integer ; -; PKT_DEST_ID_L ; 214 ; Signed Integer ; -; ST_DATA_W ; 228 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; RDATA_WIDTH ; 128 ; Signed Integer ; -; WDATA_WIDTH ; 128 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; AXI_SLAVE_ID_W ; 4 ; Signed Integer ; -; ADDR_USER_WIDTH ; 5 ; Signed Integer ; -; WRITE_ACCEPTANCE_CAPABILITY ; 8 ; Signed Integer ; -; READ_ACCEPTANCE_CAPABILITY ; 8 ; Signed Integer ; -; PASS_ID_TO_SLAVE ; 0 ; Signed Integer ; -; AXI_VERSION ; AXI3 ; String ; -; RESPONSE_W ; 2 ; Signed Integer ; -; AXI_WSTRB_W ; 16 ; Signed Integer ; -; PKT_DATA_W ; 128 ; Signed Integer ; -; NUMSYMBOLS ; 16 ; Signed Integer ; -; DATA_USER_WIDTH ; 1 ; Signed Integer ; -; AXI_LOCK_WIDTH ; 2 ; Signed Integer ; -; AXI_BURST_LENGTH_WIDTH ; 4 ; Signed Integer ; -+-----------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_merlin_address_alignment:check_and_align_address_to_size ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; TYPE_W ; 2 ; Signed Integer ; -; SIZE_W ; 3 ; Signed Integer ; -; INCREMENT_ADDRESS ; 0 ; Signed Integer ; -; NUMSYMBOLS ; 16 ; Signed Integer ; -; SELECT_BITS ; 4 ; Signed Integer ; -; IN_DATA_W ; 45 ; Signed Integer ; -; OUT_DATA_W ; 36 ; Signed Integer ; -+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_merlin_burst_uncompressor:read_burst_uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 16 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:write_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 229 ; Signed Integer ; -; FIFO_DEPTH ; 8 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 229 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent|altera_avalon_sc_fifo:read_rsp_fifo ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 229 ; Signed Integer ; -; FIFO_DEPTH ; 8 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 0 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 229 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_002|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_traffic_limiter:f2sdram_m_master_limiter ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_TRANS_POSTED ; 69 ; Signed Integer ; -; PKT_DEST_ID_H ; 106 ; Signed Integer ; -; PKT_DEST_ID_L ; 106 ; Signed Integer ; -; PKT_SRC_ID_H ; 105 ; Signed Integer ; -; PKT_SRC_ID_L ; 105 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; PKT_TRANS_READ ; 0 ; Signed Integer ; -; ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; MAX_OUTSTANDING_RESPONSES ; 8 ; Signed Integer ; -; PIPELINED ; 0 ; Signed Integer ; -; ENFORCE_ORDER ; 1 ; Signed Integer ; -; VALID_WIDTH ; 2 ; Signed Integer ; -; PREVENT_HAZARDS ; 1 ; Signed Integer ; -; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ; -; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ; -; REORDER ; 0 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 36 ; Signed Integer ; -; IN_PKT_ADDR_H ; 67 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 31 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; IN_ST_DATA_W ; 120 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 144 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 175 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 127 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; OUT_ST_DATA_W ; 228 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 36 ; Signed Integer ; -; IN_PKT_ADDR_H ; 67 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 31 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 83 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 91 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 70 ; Signed Integer ; -; IN_ST_DATA_W ; 120 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 144 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 175 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 127 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; OUT_ST_DATA_W ; 228 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; -; PACKING ; 0 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 0 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 32 ; Signed Integer ; -; BURSTWRAP_W ; 9 ; Signed Integer ; -; BYTE_CNT_W ; 9 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_rsp_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 144 ; Signed Integer ; -; IN_PKT_ADDR_H ; 175 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 127 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; IN_ST_DATA_W ; 228 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 67 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 31 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; OUT_ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 1 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_rsp_width_adapter ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; IN_PKT_ADDR_L ; 144 ; Signed Integer ; -; IN_PKT_ADDR_H ; 175 ; Signed Integer ; -; IN_PKT_DATA_L ; 0 ; Signed Integer ; -; IN_PKT_DATA_H ; 127 ; Signed Integer ; -; IN_PKT_BYTEEN_L ; 128 ; Signed Integer ; -; IN_PKT_BYTEEN_H ; 143 ; Signed Integer ; -; IN_PKT_TRANS_COMPRESSED_READ ; 176 ; Signed Integer ; -; IN_PKT_BYTE_CNT_L ; 182 ; Signed Integer ; -; IN_PKT_BYTE_CNT_H ; 190 ; Signed Integer ; -; IN_PKT_BURSTWRAP_L ; 191 ; Signed Integer ; -; IN_PKT_BURSTWRAP_H ; 199 ; Signed Integer ; -; IN_PKT_BURST_SIZE_L ; 200 ; Signed Integer ; -; IN_PKT_BURST_SIZE_H ; 202 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_L ; 223 ; Signed Integer ; -; IN_PKT_RESPONSE_STATUS_H ; 224 ; Signed Integer ; -; IN_PKT_TRANS_EXCLUSIVE ; 181 ; Signed Integer ; -; IN_PKT_BURST_TYPE_L ; 203 ; Signed Integer ; -; IN_PKT_BURST_TYPE_H ; 204 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_L ; 225 ; Signed Integer ; -; IN_PKT_ORI_BURST_SIZE_H ; 227 ; Signed Integer ; -; IN_PKT_TRANS_WRITE ; 178 ; Signed Integer ; -; IN_ST_DATA_W ; 228 ; Signed Integer ; -; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; -; OUT_PKT_ADDR_H ; 67 ; Signed Integer ; -; OUT_PKT_DATA_L ; 0 ; Signed Integer ; -; OUT_PKT_DATA_H ; 31 ; Signed Integer ; -; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; -; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; -; OUT_PKT_TRANS_COMPRESSED_READ ; 68 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_L ; 74 ; Signed Integer ; -; OUT_PKT_BYTE_CNT_H ; 82 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_L ; 92 ; Signed Integer ; -; OUT_PKT_BURST_SIZE_H ; 94 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_L ; 115 ; Signed Integer ; -; OUT_PKT_RESPONSE_STATUS_H ; 116 ; Signed Integer ; -; OUT_PKT_TRANS_EXCLUSIVE ; 73 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_L ; 95 ; Signed Integer ; -; OUT_PKT_BURST_TYPE_H ; 96 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_L ; 117 ; Signed Integer ; -; OUT_PKT_ORI_BURST_SIZE_H ; 119 ; Signed Integer ; -; OUT_ST_DATA_W ; 120 ; Signed Integer ; -; ST_CHANNEL_W ; 2 ; Signed Integer ; -; OPTIMIZE_FOR_RSP ; 1 ; Signed Integer ; -; PACKING ; 1 ; Signed Integer ; -; CONSTANT_BURST_SIZE ; 0 ; Signed Integer ; -; RESPONSE_PATH ; 1 ; Signed Integer ; -; ENABLE_ADDRESS_ALIGNMENT ; 0 ; Signed Integer ; -+-------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller ; -+---------------------------+----------+-----------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+-----------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 1 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+-----------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001 ; -+---------------------------+----------+---------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+---------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 1 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+---------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_002 ; -+---------------------------+-------+------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; none ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003 ; -+---------------------------+----------+---------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+----------+---------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 1 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+----------+---------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_req_sync_uq1 ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 0 ; Signed Integer ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_004 ; -+---------------------------+-------+------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; none ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: a10s_ghrd:u0|altera_reset_controller:rst_controller_005 ; -+---------------------------+-------+------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ; -; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; none ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ; -; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ; -; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ; -; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ; -; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: debounce:debounce_inst ; -+----------------+--------+-------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------+ -; WIDTH ; 2 ; Signed Integer ; -; POLARITY ; LOW ; String ; -; TIMEOUT ; 100000 ; Signed Integer ; -; TIMEOUT_WIDTH ; 32 ; Signed Integer ; -+----------------+--------+-------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altera_edge_detector:pulse_cold_reset ; -+-----------------------+-------+----------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+----------------------------------------------------+ -; PULSE_EXT ; 6 ; Signed Integer ; -; EDGE_TYPE ; 1 ; Signed Integer ; -; IGNORE_RST_WHILE_BUSY ; 1 ; Signed Integer ; -+-----------------------+-------+----------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altera_edge_detector:pulse_warm_reset ; -+-----------------------+-------+----------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+----------------------------------------------------+ -; PULSE_EXT ; 2 ; Signed Integer ; -; EDGE_TYPE ; 1 ; Signed Integer ; -; IGNORE_RST_WHILE_BUSY ; 1 ; Signed Integer ; -+-----------------------+-------+----------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altera_edge_detector:pulse_debug_reset ; -+-----------------------+-------+-----------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------+-------+-----------------------------------------------------+ -; PULSE_EXT ; 32 ; Signed Integer ; -; EDGE_TYPE ; 1 ; Signed Integer ; -; IGNORE_RST_WHILE_BUSY ; 1 ; Signed Integer ; -+-----------------------+-------+-----------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; altsyncram Parameter Settings by Entity Instance ; -+-------------------------------------------+----------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+-------------------------------------------+----------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 1 ; -; Entity Instance ; a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 262144 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -+-------------------------------------------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Elaboration Settings ; -+---------------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+---------------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; 10AS066K3F40E2SG ; ; -; Top-level entity name ; a10s ; a10s ; -; Family name ; Arria 10 ; Cyclone V ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto DSP Block Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; On ; On ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 3 ; 3 ; -; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Rows Reported in Synthesis Migration Checks ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Resource Aware Inference For Block RAM ; On ; On ; -; Automatic Parallel Synthesis ; On ; On ; -; Partial Reconfiguration Bitstream ID ; Off ; Off ; -; Disable DSP Negate Inferencing ; Off ; Off ; -+---------------------------------------------------------------------------------+--------------------+--------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_005" ; -+----------------+--------+----------+------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------+ -; clk ; Input ; Info ; Explicitly unconnected ; -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_004" ; -+----------------+--------+----------+------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------+ -; clk ; Input ; Info ; Explicitly unconnected ; -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_003" ; -+----------------+--------+----------+------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------+ -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_in1 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_002" ; -+----------------+--------+----------+------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------+ -; clk ; Input ; Info ; Explicitly unconnected ; -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller_001" ; -+----------------+--------+----------+------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------+ -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_in1 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ; -+----------+-------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+-------+----------+--------------------------------------------------------------------------------------------------+ -; reset_in ; Input ; Info ; Stuck at GND ; -+----------+-------+----------+--------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_reset_controller:rst_controller" ; -+----------------+-------+----------+---------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+-------+----------+---------------------------------------------+ -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+-------+----------+---------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_acw3b6a:irq_mapper_002" ; -+-------+-------+----------+----------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------+-------+----------+----------------------------------------------------------------------+ -; clk ; Input ; Info ; Explicitly unconnected ; -; reset ; Input ; Info ; Explicitly unconnected ; -+-------+-------+----------+----------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_4ipexzi:irq_mapper_001" ; -+-------+-------+----------+----------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------+-------+----------+----------------------------------------------------------------------+ -; clk ; Input ; Info ; Explicitly unconnected ; -; reset ; Input ; Info ; Explicitly unconnected ; -+-------+-------+----------+----------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_rsp_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_rsp_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_rd_cmd_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_width_adapter:arria10_hps_f2sdram0_data_wr_cmd_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_axi_slave_ni:arria10_hps_f2sdram0_data_agent" ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; awqos ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; awregion ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; wuser ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; buser ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; arqos ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; arregion ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ruser ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_agent:f2sdram_m_master_agent" ; -+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5|altera_merlin_master_translator:f2sdram_m_master_translator" ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_rsp_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_rd_cmd_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" ; -+----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sink_valid ; Input ; Info ; Stuck at GND ; -; sink_ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; sink_is_compressed ; Input ; Info ; Stuck at VCC ; -; sink_burstsize[2] ; Input ; Info ; Stuck at GND ; -; sink_burstsize[1] ; Input ; Info ; Stuck at VCC ; -; sink_burstsize[0] ; Input ; Info ; Stuck at GND ; -; source_startofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_addr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_burstwrap ; Output ; Info ; Explicitly unconnected ; -; source_byte_cnt ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_is_compressed ; Output ; Info ; Explicitly unconnected ; -; source_burstsize ; Output ; Info ; Explicitly unconnected ; -+----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter" ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode" ; -+---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_src_channel ; Output ; Info ; Explicitly unconnected ; -+---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:read_rsp_fifo" ; -+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; out_data[224..223] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; out_data[127..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; out_data[210] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; out_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; out_data[224..223] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; out_data[210] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_address_alignment:check_and_align_address_to_size" ; -+------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; in_data[44..35] ; Input ; Info ; Stuck at GND ; -; out_data[35..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; in_valid ; Input ; Info ; Explicitly unconnected ; -; in_sop ; Input ; Info ; Explicitly unconnected ; -; in_eop ; Input ; Info ; Explicitly unconnected ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -+------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent" ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; awqos ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; awregion ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; wuser ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; buser ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; arqos ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; arregion ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ruser ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent" ; -+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_translator:hps_m_master_translator" ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_003" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_002" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser_001" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser" ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router|a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rdata_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:fancmd_avalon_slave_0_1_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:fancmd_avalon_slave_0_1_agent" ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rdata_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent" ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent" ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:fancmd_avalon_slave_0_1_translator" ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator" ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_readdata[31..30] ; Input ; Info ; Stuck at VCC ; -; av_readdata[28..25] ; Input ; Info ; Stuck at VCC ; -; av_readdata[19..18] ; Input ; Info ; Stuck at VCC ; -; av_readdata[16..14] ; Input ; Info ; Stuck at VCC ; -; av_readdata[12..9] ; Input ; Info ; Stuck at VCC ; -; av_readdata[3..2] ; Input ; Info ; Stuck at VCC ; -; av_readdata[29] ; Input ; Info ; Stuck at GND ; -; av_readdata[24] ; Input ; Info ; Stuck at GND ; -; av_readdata[23] ; Input ; Info ; Stuck at VCC ; -; av_readdata[22] ; Input ; Info ; Stuck at GND ; -; av_readdata[21] ; Input ; Info ; Stuck at VCC ; -; av_readdata[20] ; Input ; Info ; Stuck at GND ; -; av_readdata[17] ; Input ; Info ; Stuck at GND ; -; av_readdata[13] ; Input ; Info ; Stuck at GND ; -; av_readdata[8] ; Input ; Info ; Stuck at GND ; -; av_readdata[7] ; Input ; Info ; Stuck at VCC ; -; av_readdata[6] ; Input ; Info ; Stuck at GND ; -; av_readdata[5] ; Input ; Info ; Stuck at VCC ; -; av_readdata[4] ; Input ; Info ; Stuck at GND ; -; av_readdata[1] ; Input ; Info ; Stuck at GND ; -; av_readdata[0] ; Input ; Info ; Stuck at VCC ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator" ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------+ -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; b[9..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router|a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:dipsw_pio_s1_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:dipsw_pio_s1_agent" ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:button_pio_s1_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:button_pio_s1_agent" ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:led_pio_s1_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:led_pio_s1_agent" ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:sysid_qsys_control_slave_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:sysid_qsys_control_slave_agent" ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent" ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent" ; -+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:dipsw_pio_s1_translator" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:button_pio_s1_translator" ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; b[5..3] ; Input ; Info ; Stuck at GND ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; cin ; Input ; Info ; Stuck at VCC ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[7] ; Input ; Info ; Stuck at GND ; -; b[7] ; Input ; Info ; Stuck at GND ; -; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; d[6..3] ; Input ; Info ; Stuck at GND ; -; d[1..0] ; Input ; Info ; Stuck at GND ; -; d[2] ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; clk ; Input ; Info ; Stuck at GND ; -; reset ; Input ; Info ; Stuck at GND ; -; in_valid ; Input ; Info ; Stuck at GND ; -; in_sop ; Input ; Info ; Stuck at GND ; -; in_eop ; Input ; Info ; Stuck at GND ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -; out_data[33..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003|a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_src_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -; default_src_channel ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent" ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent" ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; in_data[34..24] ; Input ; Info ; Stuck at GND ; -; out_data[33..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent" ; -+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ -; awqos ; Input ; Info ; Stuck at GND ; -; arqos ; Input ; Info ; Stuck at GND ; -; awregion ; Input ; Info ; Stuck at GND ; -; arregion ; Input ; Info ; Stuck at GND ; -; wuser ; Input ; Info ; Stuck at GND ; -; ruser ; Output ; Info ; Explicitly unconnected ; -; buser ; Output ; Info ; Explicitly unconnected ; -+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator" ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator" ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001" ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser" ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; out_error ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size" ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; in_data[43..35] ; Input ; Info ; Stuck at GND ; -; out_data[34..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; in_valid ; Input ; Info ; Explicitly unconnected ; -; in_sop ; Input ; Info ; Explicitly unconnected ; -; in_eop ; Input ; Info ; Explicitly unconnected ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -+------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter" ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size" ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; in_data[43..35] ; Input ; Info ; Stuck at GND ; -; out_data[34..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; in_valid ; Input ; Info ; Explicitly unconnected ; -; in_sop ; Input ; Info ; Explicitly unconnected ; -; in_eop ; Input ; Info ; Explicitly unconnected ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter" ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" ; -+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sink_valid ; Input ; Info ; Stuck at GND ; -; sink_ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; sink_is_compressed ; Input ; Info ; Stuck at VCC ; -; sink_burstsize ; Input ; Info ; Stuck at GND ; -; source_startofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_addr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_burstwrap ; Output ; Info ; Explicitly unconnected ; -; source_byte_cnt ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_is_compressed ; Output ; Info ; Explicitly unconnected ; -; source_burstsize ; Output ; Info ; Explicitly unconnected ; -+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter" ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" ; -+----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sink_valid ; Input ; Info ; Stuck at GND ; -; sink_ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; sink_is_compressed ; Input ; Info ; Stuck at VCC ; -; sink_burstsize[2] ; Input ; Info ; Stuck at GND ; -; sink_burstsize[1] ; Input ; Info ; Stuck at VCC ; -; sink_burstsize[0] ; Input ; Info ; Stuck at GND ; -; source_startofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_addr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_burstwrap ; Output ; Info ; Explicitly unconnected ; -; source_byte_cnt ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; source_is_compressed ; Output ; Info ; Explicitly unconnected ; -; source_burstsize ; Output ; Info ; Explicitly unconnected ; -+----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter" ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ -; in_command_size_data ; Input ; Info ; Stuck at GND ; -+----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; b[3..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; b[3..2] ; Input ; Info ; Stuck at GND ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; d[7..1] ; Input ; Info ; Stuck at GND ; -; d[0] ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" ; -+-----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; clk ; Input ; Info ; Stuck at GND ; -; reset ; Input ; Info ; Stuck at GND ; -; in_valid ; Input ; Info ; Stuck at GND ; -; in_sop ; Input ; Info ; Stuck at GND ; -; in_eop ; Input ; Info ; Stuck at GND ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -+-----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" ; -+------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff[7..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff[7..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff[7..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff[7..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" ; -+------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; cin ; Input ; Info ; Stuck at VCC ; -+------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; a[8] ; Input ; Info ; Stuck at GND ; -; b[8] ; Input ; Info ; Stuck at GND ; -; diff[7..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; d[7..3] ; Input ; Info ; Stuck at GND ; -; d[1..0] ; Input ; Info ; Stuck at GND ; -; d[2] ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; clk ; Input ; Info ; Stuck at GND ; -; reset ; Input ; Info ; Stuck at GND ; -; in_valid ; Input ; Info ; Stuck at GND ; -; in_sop ; Input ; Info ; Stuck at GND ; -; in_eop ; Input ; Info ; Stuck at GND ; -; out_ready ; Input ; Info ; Explicitly unconnected ; -; out_data[33..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003|a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_src_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002|a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode:the_default_decode" ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Explicitly unconnected ; -; default_src_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent" ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo" ; -+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent" ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" ; -+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; out_data[34..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent" ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+ -; awqos ; Input ; Info ; Stuck at GND ; -; arqos ; Input ; Info ; Stuck at GND ; -; awregion ; Input ; Info ; Stuck at GND ; -; arregion ; Input ; Info ; Stuck at GND ; -; wuser ; Input ; Info ; Stuck at GND ; -; ruser ; Output ; Info ; Explicitly unconnected ; -; buser ; Output ; Info ; Explicitly unconnected ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator" ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator" ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f" ; -+-------------+--------+----------+-----------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------+--------+----------+-----------------------------------------+ -; s0_response ; Output ; Info ; Explicitly unconnected ; -; m0_response ; Input ; Info ; Stuck at GND ; -+-------------+--------+----------+-----------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2" ; -+--------+-------+----------+--------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+-------+----------+--------------------------------------------------------------------------------+ -; freeze ; Input ; Info ; Stuck at GND ; -+--------+-------+----------+--------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl" ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_e1dr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_cir ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_uir ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_tlr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altsource_probe_top:issp" ; -+------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; source_ena ; Input ; Info ; Stuck at VCC ; -; probe ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:hps_m" ; -+--------------------+--------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-------------------------------------------------------+ -; master_reset_reset ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; in_ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; out_ready ; Input ; Info ; Stuck at VCC ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; in_channel ; Input ; Info ; Stuck at GND ; -; in_csr_address ; Input ; Info ; Stuck at GND ; -; in_csr_read ; Input ; Info ; Stuck at GND ; -; in_csr_write ; Input ; Info ; Stuck at GND ; -; in_csr_writedata ; Input ; Info ; Stuck at GND ; -; out_csr_address ; Input ; Info ; Stuck at GND ; -; out_csr_read ; Input ; Info ; Stuck at GND ; -; out_csr_write ; Input ; Info ; Stuck at GND ; -; out_csr_writedata ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_endofpacket ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_channel ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; in_csr_readdata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_csr_readdata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_full_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_full_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_empty_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_empty_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; in_empty ; Input ; Info ; Stuck at GND ; -; in_error ; Input ; Info ; Stuck at GND ; -; in_channel ; Input ; Info ; Stuck at GND ; -; in_csr_address ; Input ; Info ; Stuck at GND ; -; in_csr_read ; Input ; Info ; Stuck at GND ; -; in_csr_write ; Input ; Info ; Stuck at GND ; -; in_csr_writedata ; Input ; Info ; Stuck at GND ; -; out_csr_address ; Input ; Info ; Stuck at GND ; -; out_csr_read ; Input ; Info ; Stuck at GND ; -; out_csr_write ; Input ; Info ; Stuck at GND ; -; out_csr_writedata ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_endofpacket ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_channel ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; in_csr_readdata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; out_csr_readdata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_full_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_full_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_empty_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; almost_empty_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; space_avail_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:fpga_m" ; -+--------------------+--------+----------+--------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+--------------------------------------------------------+ -; master_reset_reset ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+--------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|CLOCKMEM:mm" ; -+------------------+--------+----------+------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+------------------------------------------------------------------------+ -; CLK_FREQ[11..9] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[31..15] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[13..12] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[8..6] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[4..0] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[14] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[5] ; Input ; Info ; Stuck at VCC ; -; CK_OUT ; Output ; Info ; Explicitly unconnected ; -+------------------+--------+----------+------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL" ; -+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+ -; SPEED_RPM ; Output ; Warning ; Output or bidir port (16 bits) is wider than the port expression (13 bits) it drives; bit(s) "SPEED_RPM[15..13]" have no fanouts ; -; FPGA_CURR_C ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; CNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; LEV ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; FAN_DAC ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd" ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_NUM ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (8 bits) it drives. The 24 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -; BYTE_NUM[7..0] ; Input ; Info ; Stuck at GND ; -; DATA ; Output ; Warning ; Output or bidir port (16 bits) is wider than the port expression (8 bits) it drives; bit(s) "DATA[15..8]" have no fanouts ; -; ST ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ACK_OK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; CNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; A ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; BYTE ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt" ; -+--------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; ST ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ACK_OK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; CNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; BYTE ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd" ; -+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; LIGHT_INT ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ACK_OK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400" ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; CLK_FREQ[6..2] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[31..7] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[1] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[0] ; Input ; Info ; Stuck at VCC ; -; CK_OUT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; I2C_LO0P ; Output ; Info ; Explicitly unconnected ; -; CONFIG[7..6] ; Input ; Info ; Stuck at GND ; -; CONFIG[5] ; Input ; Info ; Stuck at VCC ; -; CONFIG[4] ; Input ; Info ; Stuck at GND ; -; CONFIG[3] ; Input ; Info ; Stuck at VCC ; -; CONFIG[2] ; Input ; Info ; Stuck at GND ; -; CONFIG[1] ; Input ; Info ; Stuck at VCC ; -; CONFIG[0] ; Input ; Info ; Stuck at GND ; -; GPIO_DEF[7..4] ; Input ; Info ; Stuck at VCC ; -; GPIO_DEF[3] ; Input ; Info ; Stuck at GND ; -; GPIO_DEF[2] ; Input ; Info ; Stuck at VCC ; -; GPIO_DEF[1] ; Input ; Info ; Stuck at GND ; -; GPIO_DEF[0] ; Input ; Info ; Stuck at VCC ; -; ALARM_ENABLE[3..0] ; Input ; Info ; Stuck at VCC ; -; ALARM_ENABLE[7..4] ; Input ; Info ; Stuck at GND ; -; TACHOMETER[7..2] ; Input ; Info ; Stuck at GND ; -; TACHOMETER[1] ; Input ; Info ; Stuck at VCC ; -; TACHOMETER[0] ; Input ; Info ; Stuck at GND ; -; TACH0 ; Output ; Info ; Explicitly unconnected ; -; STATUS ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; RD_TR ; Input ; Info ; Explicitly unconnected ; -; SENS_DONE ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; MFG_ID ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DEV_ID ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; SLAVE_ADDR ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ST ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; CNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; WCNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; W_WORD_DATA ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; W_POINTER_REG ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; W_WORD_END ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; W_WORD_GO ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; WORD_ST ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; WORD_CNT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; WORD_BYTE ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; R_DATA ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp" ; -+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; MANU_AUTO_SW ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -; MANU_AUTO_SW[-1] ; Input ; Info ; Stuck at GND ; -; FPGA_T_ISM ; Input ; Info ; Explicitly unconnected ; -; BUSY_GO_HI ; Output ; Info ; Explicitly unconnected ; -; TEMP_BUSY ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; TEMP_UP_FLAG ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; FAN_INI ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_6000 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_5500 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_5000 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_4500 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_4000 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_3500 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; DAC_3000 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd|CLOCKMEM:k10" ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; CLK_FREQ[19..18] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[9..8] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[31..23] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[21..20] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[17..15] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[13..12] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[5..0] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[22] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[14] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[11] ; Input ; Info ; Stuck at VCC ; -; CLK_FREQ[10] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[7] ; Input ; Info ; Stuck at GND ; -; CLK_FREQ[6] ; Input ; Info ; Stuck at VCC ; -; CK_OUT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+------------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|HAN_FanTempControll:fancmd" ; -+----------+--------+----------+--------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+--------------------------------------+ -; Temp_OK ; Output ; Info ; Explicitly unconnected ; -; Temp_LOW ; Output ; Info ; Explicitly unconnected ; -; Temp_HI ; Output ; Info ; Explicitly unconnected ; -+----------+--------+----------+--------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_in ; Input ; Info ; Stuck at GND ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller" ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------+ -; reset_req ; Output ; Info ; Explicitly unconnected ; -; reset_req_in0 ; Input ; Info ; Stuck at GND ; -; reset_in1 ; Input ; Info ; Stuck at GND ; -; reset_req_in1 ; Input ; Info ; Stuck at GND ; -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_req_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_req_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_req_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_req_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_req_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_req_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_req_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_req_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_req_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_req_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_req_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_req_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_req_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -; reset_req_in15 ; Input ; Info ; Stuck at GND ; -+----------------+--------+----------+------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo" ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_startofpacket ; Input ; Info ; Stuck at GND ; -; in_endofpacket ; Input ; Info ; Stuck at GND ; -; out_startofpacket ; Output ; Info ; Explicitly unconnected ; -; out_endofpacket ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser" ; -+----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sense_pos_edge ; Input ; Info ; Stuck at VCC ; -+----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter" ; -+-----------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; out_valid ; Output ; Info ; Explicitly unconnected ; -+-----------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover" ; -+-----------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; in_ready ; Output ; Info ; Explicitly unconnected ; -; out_ready ; Input ; Info ; Stuck at VCC ; -+-----------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" ; -+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; din ; Input ; Info ; Stuck at VCC ; -+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer" ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer" ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer" ; -+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" ; -+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; din ; Input ; Info ; Stuck at VCC ; -+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" ; -+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; tms ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_tlr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_rti ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdrs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_udr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sirs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_uir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node" ; -+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ir_out ; Input ; Warning ; Input port expression (1 bits) is smaller than the input port (3 bits) it drives. Extra input bit(s) "ir_out[2..1]" will be connected to GND. ; -; ir_out ; Input ; Info ; Stuck at GND ; -; virtual_state_cir ; Output ; Info ; Explicitly unconnected ; -; virtual_state_e1dr ; Output ; Info ; Explicitly unconnected ; -; virtual_state_e2dr ; Output ; Info ; Explicitly unconnected ; -; virtual_state_pdr ; Output ; Info ; Explicitly unconnected ; -; virtual_state_uir ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master" ; -+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ -; source_ready ; Input ; Info ; Stuck at VCC ; -; mgmt_valid ; Output ; Info ; Explicitly unconnected ; -; mgmt_channel ; Output ; Info ; Explicitly unconnected ; -; mgmt_data ; Output ; Info ; Explicitly unconnected ; -; jtag_tck ; Input ; Info ; Stuck at GND ; -; jtag_tms ; Input ; Info ; Stuck at GND ; -; jtag_tdi ; Input ; Info ; Stuck at GND ; -; jtag_tdo ; Output ; Info ; Explicitly unconnected ; -; jtag_ena ; Input ; Info ; Stuck at GND ; -; jtag_usr1 ; Input ; Info ; Stuck at GND ; -; jtag_clr ; Input ; Info ; Stuck at GND ; -; jtag_clrn ; Input ; Info ; Stuck at GND ; -; jtag_state_tlr ; Input ; Info ; Stuck at GND ; -; jtag_state_rti ; Input ; Info ; Stuck at GND ; -; jtag_state_sdrs ; Input ; Info ; Stuck at GND ; -; jtag_state_cdr ; Input ; Info ; Stuck at GND ; -; jtag_state_sdr ; Input ; Info ; Stuck at GND ; -; jtag_state_e1dr ; Input ; Info ; Stuck at GND ; -; jtag_state_pdr ; Input ; Info ; Stuck at GND ; -; jtag_state_e2dr ; Input ; Info ; Stuck at GND ; -; jtag_state_udr ; Input ; Info ; Stuck at GND ; -; jtag_state_sirs ; Input ; Info ; Stuck at GND ; -; jtag_state_cir ; Input ; Info ; Stuck at GND ; -; jtag_state_sir ; Input ; Info ; Stuck at GND ; -; jtag_state_e1ir ; Input ; Info ; Stuck at GND ; -; jtag_state_pir ; Input ; Info ; Stuck at GND ; -; jtag_state_e2ir ; Input ; Info ; Stuck at GND ; -; jtag_state_uir ; Input ; Info ; Stuck at GND ; -; jtag_ir_in ; Input ; Info ; Stuck at GND ; -; jtag_irq ; Output ; Info ; Explicitly unconnected ; -; jtag_ir_out ; Output ; Info ; Explicitly unconnected ; -; debug_reset ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m" ; -+--------------------+--------+----------+-----------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------+ -; master_reset_reset ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst" ; -+------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; dcc_stable ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_abphy_mux:altera_emif_arch_nf_abphy_mux_inst" ; -+---------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; phy_reset_n_abphy ; Input ; Info ; Stuck at GND ; -; phy_fb_clk_to_pll_abphy ; Input ; Info ; Stuck at GND ; -; core_clks_from_cpa_pri_abphy ; Input ; Info ; Stuck at GND ; -; core_clks_locked_cpa_pri_abphy ; Input ; Info ; Stuck at GND ; -; core_clks_from_cpa_sec_abphy ; Input ; Info ; Stuck at GND ; -; core_clks_locked_cpa_sec_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_avl_cmd_ready_0_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_avl_cmd_ready_1_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_avl_rdata_id_0_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_avl_rdata_id_1_abphy ; Input ; Info ; Stuck at GND ; -; l2core_rd_data_vld_avl0_abphy ; Input ; Info ; Stuck at GND ; -; l2core_wr_data_rdy_ast_abphy ; Input ; Info ; Stuck at GND ; -; l2core_wb_pointer_for_ecc_abphy ; Input ; Info ; Stuck at GND ; -; l2core_data_abphy ; Input ; Info ; Stuck at GND ; -; l2core_rdata_valid_abphy ; Input ; Info ; Stuck at GND ; -; l2core_afi_rlat_abphy ; Input ; Info ; Stuck at GND ; -; l2core_afi_wlat_abphy ; Input ; Info ; Stuck at GND ; -; t2c_afi_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_sideband_0_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_sideband_1_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_mmr_0_abphy ; Input ; Info ; Stuck at GND ; -; ctl2core_mmr_1_abphy ; Input ; Info ; Stuck at GND ; -; l2b_data_abphy ; Input ; Info ; Stuck at GND ; -; l2b_oe_abphy ; Input ; Info ; Stuck at GND ; -; l2b_dtc_abphy ; Input ; Info ; Stuck at GND ; -; pa_dprio_block_select_abphy ; Input ; Info ; Stuck at GND ; -; pa_dprio_readdata_abphy ; Input ; Info ; Stuck at GND ; -; runAbstractPhySim ; Input ; Info ; Stuck at GND ; -+---------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst" ; -+--------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; runAbstractPhySim ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; core_clks_from_cpa_pri ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; core_clks_locked_cpa_pri ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; core_clks_from_cpa_sec ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; core_clks_locked_cpa_sec ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; core2l_rdata_en_full ; Input ; Info ; Stuck at GND ; -; core2l_mrnk_read ; Input ; Info ; Stuck at GND ; -; core2l_mrnk_write ; Input ; Info ; Stuck at GND ; -; l2core_rdata_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; l2core_afi_rlat ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; l2core_afi_wlat ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch" ; -+--------------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; mem_c ; Output ; Info ; Explicitly unconnected ; -; mem_rm ; Output ; Info ; Explicitly unconnected ; -; mem_dk ; Output ; Info ; Explicitly unconnected ; -; mem_dk_n ; Output ; Info ; Explicitly unconnected ; -; mem_dka ; Output ; Info ; Explicitly unconnected ; -; mem_dka_n ; Output ; Info ; Explicitly unconnected ; -; mem_dkb ; Output ; Info ; Explicitly unconnected ; -; mem_dkb_n ; Output ; Info ; Explicitly unconnected ; -; mem_k ; Output ; Info ; Explicitly unconnected ; -; mem_k_n ; Output ; Info ; Explicitly unconnected ; -; mem_ras_n ; Output ; Info ; Explicitly unconnected ; -; mem_cas_n ; Output ; Info ; Explicitly unconnected ; -; mem_we_n ; Output ; Info ; Explicitly unconnected ; -; mem_ca ; Output ; Info ; Explicitly unconnected ; -; mem_ref_n ; Output ; Info ; Explicitly unconnected ; -; mem_wps_n ; Output ; Info ; Explicitly unconnected ; -; mem_rps_n ; Output ; Info ; Explicitly unconnected ; -; mem_doff_n ; Output ; Info ; Explicitly unconnected ; -; mem_lda_n ; Output ; Info ; Explicitly unconnected ; -; mem_ldb_n ; Output ; Info ; Explicitly unconnected ; -; mem_rwa_n ; Output ; Info ; Explicitly unconnected ; -; mem_rwb_n ; Output ; Info ; Explicitly unconnected ; -; mem_lbk0_n ; Output ; Info ; Explicitly unconnected ; -; mem_lbk1_n ; Output ; Info ; Explicitly unconnected ; -; mem_cfg_n ; Output ; Info ; Explicitly unconnected ; -; mem_ap ; Output ; Info ; Explicitly unconnected ; -; mem_ainv ; Output ; Info ; Explicitly unconnected ; -; mem_dm ; Output ; Info ; Explicitly unconnected ; -; mem_bws_n ; Output ; Info ; Explicitly unconnected ; -; mem_d ; Output ; Info ; Explicitly unconnected ; -; mem_dqa ; Bidir ; Info ; Explicitly unconnected ; -; mem_dqb ; Bidir ; Info ; Explicitly unconnected ; -; mem_dinva ; Bidir ; Info ; Explicitly unconnected ; -; mem_dinvb ; Bidir ; Info ; Explicitly unconnected ; -; mem_q ; Input ; Info ; Stuck at GND ; -; mem_qk ; Input ; Info ; Stuck at GND ; -; mem_qk_n ; Input ; Info ; Stuck at GND ; -; mem_qka ; Input ; Info ; Stuck at GND ; -; mem_qka_n ; Input ; Info ; Stuck at GND ; -; mem_qkb ; Input ; Info ; Stuck at GND ; -; mem_qkb_n ; Input ; Info ; Stuck at GND ; -; mem_cq ; Input ; Info ; Stuck at GND ; -; mem_cq_n ; Input ; Info ; Stuck at GND ; -; mem_pe_n ; Input ; Info ; Stuck at GND ; -; vid_cal_done_persist ; Input ; Info ; Stuck at GND ; -; afi_reset_n ; Output ; Info ; Explicitly unconnected ; -; afi_clk ; Output ; Info ; Explicitly unconnected ; -; afi_half_clk ; Output ; Info ; Explicitly unconnected ; -; emif_usr_half_clk ; Output ; Info ; Explicitly unconnected ; -; emif_usr_reset_n_sec ; Output ; Info ; Explicitly unconnected ; -; emif_usr_clk_sec ; Output ; Info ; Explicitly unconnected ; -; emif_usr_half_clk_sec ; Output ; Info ; Explicitly unconnected ; -; cal_master_reset_n ; Output ; Info ; Explicitly unconnected ; -; cal_master_clk ; Output ; Info ; Explicitly unconnected ; -; cal_slave_reset_n ; Output ; Info ; Explicitly unconnected ; -; cal_slave_clk ; Output ; Info ; Explicitly unconnected ; -; cal_slave_reset_n_in ; Input ; Info ; Stuck at GND ; -; cal_slave_clk_in ; Input ; Info ; Stuck at GND ; -; cal_debug_reset_n ; Input ; Info ; Stuck at GND ; -; cal_debug_clk ; Input ; Info ; Stuck at GND ; -; cal_debug_out_reset_n ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_clk ; Output ; Info ; Explicitly unconnected ; -; clks_sharing_master_out ; Output ; Info ; Explicitly unconnected ; -; clks_sharing_slave_in ; Input ; Info ; Stuck at GND ; -; afi_cal_success ; Output ; Info ; Explicitly unconnected ; -; afi_cal_fail ; Output ; Info ; Explicitly unconnected ; -; afi_cal_req ; Input ; Info ; Stuck at GND ; -; afi_rlat ; Output ; Info ; Explicitly unconnected ; -; afi_wlat ; Output ; Info ; Explicitly unconnected ; -; afi_seq_busy ; Output ; Info ; Explicitly unconnected ; -; afi_ctl_refresh_done ; Input ; Info ; Stuck at GND ; -; afi_ctl_long_idle ; Input ; Info ; Stuck at GND ; -; afi_mps_req ; Input ; Info ; Stuck at GND ; -; afi_mps_ack ; Output ; Info ; Explicitly unconnected ; -; afi_addr ; Input ; Info ; Stuck at GND ; -; afi_ba ; Input ; Info ; Stuck at GND ; -; afi_bg ; Input ; Info ; Stuck at GND ; -; afi_c ; Input ; Info ; Stuck at GND ; -; afi_cke ; Input ; Info ; Stuck at GND ; -; afi_cs_n ; Input ; Info ; Stuck at GND ; -; afi_rm ; Input ; Info ; Stuck at GND ; -; afi_odt ; Input ; Info ; Stuck at GND ; -; afi_ras_n ; Input ; Info ; Stuck at GND ; -; afi_cas_n ; Input ; Info ; Stuck at GND ; -; afi_we_n ; Input ; Info ; Stuck at GND ; -; afi_rst_n ; Input ; Info ; Stuck at GND ; -; afi_act_n ; Input ; Info ; Stuck at GND ; -; afi_par ; Input ; Info ; Stuck at GND ; -; afi_ca ; Input ; Info ; Stuck at GND ; -; afi_ref_n ; Input ; Info ; Stuck at GND ; -; afi_wps_n ; Input ; Info ; Stuck at GND ; -; afi_rps_n ; Input ; Info ; Stuck at GND ; -; afi_doff_n ; Input ; Info ; Stuck at GND ; -; afi_ld_n ; Input ; Info ; Stuck at GND ; -; afi_rw_n ; Input ; Info ; Stuck at GND ; -; afi_lbk0_n ; Input ; Info ; Stuck at GND ; -; afi_lbk1_n ; Input ; Info ; Stuck at GND ; -; afi_cfg_n ; Input ; Info ; Stuck at GND ; -; afi_ap ; Input ; Info ; Stuck at GND ; -; afi_ainv ; Input ; Info ; Stuck at GND ; -; afi_dm ; Input ; Info ; Stuck at GND ; -; afi_dm_n ; Input ; Info ; Stuck at GND ; -; afi_bws_n ; Input ; Info ; Stuck at GND ; -; afi_rdata_dbi_n ; Output ; Info ; Explicitly unconnected ; -; afi_wdata_dbi_n ; Input ; Info ; Stuck at GND ; -; afi_rdata_dinv ; Output ; Info ; Explicitly unconnected ; -; afi_wdata_dinv ; Input ; Info ; Stuck at GND ; -; afi_dqs_burst ; Input ; Info ; Stuck at GND ; -; afi_wdata_valid ; Input ; Info ; Stuck at GND ; -; afi_wdata ; Input ; Info ; Stuck at GND ; -; afi_rdata_en_full ; Input ; Info ; Stuck at GND ; -; afi_rdata ; Output ; Info ; Explicitly unconnected ; -; afi_rdata_valid ; Output ; Info ; Explicitly unconnected ; -; afi_rrank ; Input ; Info ; Stuck at GND ; -; afi_wrank ; Input ; Info ; Stuck at GND ; -; afi_alert_n ; Output ; Info ; Explicitly unconnected ; -; afi_pe_n ; Output ; Info ; Explicitly unconnected ; -; amm_ready_0 ; Output ; Info ; Explicitly unconnected ; -; amm_read_0 ; Input ; Info ; Stuck at GND ; -; amm_write_0 ; Input ; Info ; Stuck at GND ; -; amm_address_0 ; Input ; Info ; Stuck at GND ; -; amm_readdata_0 ; Output ; Info ; Explicitly unconnected ; -; amm_writedata_0 ; Input ; Info ; Stuck at GND ; -; amm_burstcount_0 ; Input ; Info ; Stuck at GND ; -; amm_byteenable_0 ; Input ; Info ; Stuck at GND ; -; amm_beginbursttransfer_0 ; Input ; Info ; Stuck at GND ; -; amm_readdatavalid_0 ; Output ; Info ; Explicitly unconnected ; -; amm_ready_1 ; Output ; Info ; Explicitly unconnected ; -; amm_read_1 ; Input ; Info ; Stuck at GND ; -; amm_write_1 ; Input ; Info ; Stuck at GND ; -; amm_address_1 ; Input ; Info ; Stuck at GND ; -; amm_readdata_1 ; Output ; Info ; Explicitly unconnected ; -; amm_writedata_1 ; Input ; Info ; Stuck at GND ; -; amm_burstcount_1 ; Input ; Info ; Stuck at GND ; -; amm_byteenable_1 ; Input ; Info ; Stuck at GND ; -; amm_beginbursttransfer_1 ; Input ; Info ; Stuck at GND ; -; amm_readdatavalid_1 ; Output ; Info ; Explicitly unconnected ; -; ctrl_user_priority_hi_0 ; Input ; Info ; Stuck at GND ; -; ctrl_user_priority_hi_1 ; Input ; Info ; Stuck at GND ; -; ctrl_auto_precharge_req_0 ; Input ; Info ; Stuck at GND ; -; ctrl_auto_precharge_req_1 ; Input ; Info ; Stuck at GND ; -; ctrl_user_refresh_req ; Input ; Info ; Stuck at GND ; -; ctrl_user_refresh_bank ; Input ; Info ; Stuck at GND ; -; ctrl_user_refresh_ack ; Output ; Info ; Explicitly unconnected ; -; ctrl_self_refresh_req ; Input ; Info ; Stuck at GND ; -; ctrl_self_refresh_ack ; Output ; Info ; Explicitly unconnected ; -; ctrl_will_refresh ; Output ; Info ; Explicitly unconnected ; -; ctrl_deep_power_down_req ; Input ; Info ; Stuck at GND ; -; ctrl_deep_power_down_ack ; Output ; Info ; Explicitly unconnected ; -; ctrl_power_down_ack ; Output ; Info ; Explicitly unconnected ; -; ctrl_zq_cal_long_req ; Input ; Info ; Stuck at GND ; -; ctrl_zq_cal_short_req ; Input ; Info ; Stuck at GND ; -; ctrl_zq_cal_ack ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_write_info_0 ; Input ; Info ; Stuck at GND ; -; ctrl_ecc_rdata_id_0 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_read_info_0 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_cmd_info_0 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_idle_0 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_wr_pointer_info_0 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_write_info_1 ; Input ; Info ; Stuck at GND ; -; ctrl_ecc_rdata_id_1 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_read_info_1 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_cmd_info_1 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_idle_1 ; Output ; Info ; Explicitly unconnected ; -; ctrl_ecc_wr_pointer_info_1 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_waitrequest_0 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_read_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_write_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_address_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_readdata_0 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_writedata_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_burstcount_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_beginbursttransfer_0 ; Input ; Info ; Stuck at GND ; -; mmr_slave_readdatavalid_0 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_waitrequest_1 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_read_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_write_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_address_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_readdata_1 ; Output ; Info ; Explicitly unconnected ; -; mmr_slave_writedata_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_burstcount_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_beginbursttransfer_1 ; Input ; Info ; Stuck at GND ; -; mmr_slave_readdatavalid_1 ; Output ; Info ; Explicitly unconnected ; -; cal_debug_waitrequest ; Output ; Info ; Explicitly unconnected ; -; cal_debug_read ; Input ; Info ; Stuck at GND ; -; cal_debug_write ; Input ; Info ; Stuck at GND ; -; cal_debug_addr ; Input ; Info ; Stuck at GND ; -; cal_debug_read_data ; Output ; Info ; Explicitly unconnected ; -; cal_debug_write_data ; Input ; Info ; Stuck at GND ; -; cal_debug_byteenable ; Input ; Info ; Stuck at GND ; -; cal_debug_read_data_valid ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_waitrequest ; Input ; Info ; Stuck at GND ; -; cal_debug_out_read ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_write ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_addr ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_read_data ; Input ; Info ; Stuck at GND ; -; cal_debug_out_write_data ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_byteenable ; Output ; Info ; Explicitly unconnected ; -; cal_debug_out_read_data_valid ; Input ; Info ; Stuck at GND ; -; cal_master_waitrequest ; Input ; Info ; Stuck at GND ; -; cal_master_read ; Output ; Info ; Explicitly unconnected ; -; cal_master_write ; Output ; Info ; Explicitly unconnected ; -; cal_master_addr ; Output ; Info ; Explicitly unconnected ; -; cal_master_read_data ; Input ; Info ; Stuck at GND ; -; cal_master_write_data ; Output ; Info ; Explicitly unconnected ; -; cal_master_byteenable ; Output ; Info ; Explicitly unconnected ; -; cal_master_read_data_valid ; Input ; Info ; Stuck at GND ; -; cal_master_burstcount ; Output ; Info ; Explicitly unconnected ; -; cal_master_debugaccess ; Output ; Info ; Explicitly unconnected ; -; ioaux_pio_in ; Input ; Info ; Stuck at GND ; -; ioaux_pio_out ; Output ; Info ; Explicitly unconnected ; -; pa_dprio_clk ; Input ; Info ; Stuck at GND ; -; pa_dprio_read ; Input ; Info ; Stuck at GND ; -; pa_dprio_reg_addr ; Input ; Info ; Stuck at GND ; -; pa_dprio_rst_n ; Input ; Info ; Stuck at GND ; -; pa_dprio_write ; Input ; Info ; Stuck at GND ; -; pa_dprio_writedata ; Input ; Info ; Stuck at GND ; -; pa_dprio_block_select ; Output ; Info ; Explicitly unconnected ; -; pa_dprio_readdata ; Output ; Info ; Explicitly unconnected ; -; pll_phase_en ; Input ; Info ; Stuck at GND ; -; pll_up_dn ; Input ; Info ; Stuck at GND ; -; pll_cnt_sel ; Input ; Info ; Stuck at GND ; -; pll_num_phase_shifts ; Input ; Info ; Stuck at GND ; -; pll_phase_done ; Output ; Info ; Explicitly unconnected ; -; dft_core_clk_buf_out ; Output ; Info ; Explicitly unconnected ; -; dft_core_clk_locked ; Output ; Info ; Explicitly unconnected ; -; local_cal_success ; Output ; Info ; Explicitly unconnected ; -; local_cal_fail ; Output ; Info ; Explicitly unconnected ; -; emif_usr_reset_n ; Output ; Info ; Explicitly unconnected ; -; emif_usr_clk ; Output ; Info ; Explicitly unconnected ; -; ast_cmd_valid_0 ; Input ; Info ; Stuck at GND ; -; ast_cmd_ready_0 ; Output ; Info ; Explicitly unconnected ; -; ast_cmd_data_0 ; Input ; Info ; Stuck at GND ; -; ast_cmd_valid_1 ; Input ; Info ; Stuck at GND ; -; ast_cmd_ready_1 ; Output ; Info ; Explicitly unconnected ; -; ast_cmd_data_1 ; Input ; Info ; Stuck at GND ; -; ast_wr_valid_0 ; Input ; Info ; Stuck at GND ; -; ast_wr_ready_0 ; Output ; Info ; Explicitly unconnected ; -; ast_wr_data_0 ; Input ; Info ; Stuck at GND ; -; ast_wr_valid_1 ; Input ; Info ; Stuck at GND ; -; ast_wr_ready_1 ; Output ; Info ; Explicitly unconnected ; -; ast_wr_data_1 ; Input ; Info ; Stuck at GND ; -; ast_rd_valid_0 ; Output ; Info ; Explicitly unconnected ; -; ast_rd_ready_0 ; Input ; Info ; Stuck at GND ; -; ast_rd_data_0 ; Output ; Info ; Explicitly unconnected ; -; ast_rd_valid_1 ; Output ; Info ; Explicitly unconnected ; -; ast_rd_ready_1 ; Input ; Info ; Stuck at GND ; -; ast_rd_data_1 ; Output ; Info ; Explicitly unconnected ; -; pll_extra_clk_0 ; Output ; Info ; Explicitly unconnected ; -; pll_extra_clk_1 ; Output ; Info ; Explicitly unconnected ; -; pll_extra_clk_2 ; Output ; Info ; Explicitly unconnected ; -; pll_extra_clk_3 ; Output ; Info ; Explicitly unconnected ; -; pll_locked ; Output ; Info ; Explicitly unconnected ; -+--------------------------------+--------+----------+-------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw" ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar" ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2" ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; f_w_data ; Input ; Warning ; Input port expression (128 bits) is wider than the input port (16 bits) it drives. The 112 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -; f_w_strb ; Input ; Warning ; Input port expression (16 bits) is wider than the input port (2 bits) it drives. The 14 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -; s_r_data ; Input ; Warning ; Input port expression (128 bits) is wider than the input port (16 bits) it drives. The 112 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -; f_r_data ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (128 bits) it drives. The 112 most-significant bit(s) in the port expression will be connected to GND. ; -; s_w_data ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (128 bits) it drives. The 112 most-significant bit(s) in the port expression will be connected to GND. ; -; s_w_strb ; Output ; Warning ; Output or bidir port (2 bits) is smaller than the port expression (16 bits) it drives. The 14 most-significant bit(s) in the port expression will be connected to GND. ; -+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram" ; -+-----------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; fpga2sdram2_ar_len ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_aw_clk ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_r_clk ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_user ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_w_valid ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_prot ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_lock ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_addr ; Input ; Info ; Stuck at GND ; -; fpga2sdram_port_size_config[2..1] ; Input ; Info ; Stuck at VCC ; -; fpga2sdram_port_size_config[3] ; Input ; Info ; Stuck at GND ; -; fpga2sdram_port_size_config[0] ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_cache ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_size ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_b_ready ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_burst ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_w_data ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_prot ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_cache ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_size ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_burst ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_w_id ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_id ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_ar_clk ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_r_ready ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_valid ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_id ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_w_last ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_aw_len ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_rst_n ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_valid ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_w_clk ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_clk ; Input ; Info ; Stuck at GND ; -; f2s_sdram2_b_clk ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_user ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_w_strb ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_lock ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_addr ; Input ; Info ; Stuck at GND ; -; fpga2sdram2_ar_ready ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_aw_ready ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_b_id ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_b_resp ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_b_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_r_data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_r_id ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_r_last ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_r_resp ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_r_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; fpga2sdram2_w_ready ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+-----------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_b" ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r" ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w" ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_aw" ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_ar" ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins" ; -+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; s_w_strb ; Input ; Warning ; Input port expression (16 bits) is wider than the input port (8 bits) it drives. The 8 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga" ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; port_size_config_0 ; Input ; Info ; Stuck at VCC ; -; port_size_config_1 ; Input ; Info ; Stuck at GND ; -; port_size_config_2 ; Input ; Info ; Stuck at VCC ; -; port_size_config_3 ; Input ; Info ; Stuck at GND ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w" ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_aw" ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar" ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; aw_addr ; Output ; Warning ; Output or bidir port (32 bits) is wider than the port expression (21 bits) it drives; bit(s) "aw_addr[31..21]" have no fanouts ; -; port_size_config_0 ; Input ; Info ; Stuck at VCC ; -; port_size_config_1 ; Input ; Info ; Stuck at VCC ; -; ar_addr ; Output ; Warning ; Output or bidir port (32 bits) is wider than the port expression (21 bits) it drives; bit(s) "ar_addr[31..21]" have no fanouts ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b" ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_targ ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_aw" ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar" ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; readylatency_init ; Input ; Info ; Stuck at GND ; -+-------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps" ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; port_size_config_0 ; Input ; Info ; Stuck at GND ; -; port_size_config_1 ; Input ; Info ; Stuck at VCC ; -; port_size_config_2 ; Input ; Info ; Stuck at VCC ; -; port_size_config_3 ; Input ; Info ; Stuck at VCC ; -+--------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface|hps_emif_interface_to_ddr:inst" ; -+-------------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; mmr_addr ; Output ; Info ; Explicitly unconnected ; -; mmr_be ; Output ; Info ; Explicitly unconnected ; -; mmr_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; mmr_burst_count ; Output ; Info ; Explicitly unconnected ; -; mmr_rdata ; Input ; Info ; Stuck at VCC ; -; mmr_rdata_valid ; Input ; Info ; Stuck at VCC ; -; mmr_read ; Output ; Info ; Explicitly unconnected ; -; mmr_waitrequest ; Input ; Info ; Stuck at VCC ; -; mmr_wdata ; Output ; Info ; Explicitly unconnected ; -; mmr_write ; Output ; Info ; Explicitly unconnected ; -; afi_cal_success ; Input ; Info ; Stuck at VCC ; -; clk_out_hps ; Input ; Info ; Stuck at VCC ; -; fb_clk_hps ; Output ; Info ; Explicitly unconnected ; -; afi_core2seq ; Output ; Info ; Explicitly unconnected ; -; afi_seq2core ; Input ; Info ; Stuck at VCC ; -; dbc2core_wr_data_rdy_pl[8..7] ; Input ; Info ; Stuck at GND ; -; pll_locked ; Input ; Info ; Stuck at VCC ; -; cdata_upper ; Input ; Info ; Stuck at VCC ; -; ref_clkin_hps ; Output ; Info ; Explicitly unconnected ; -; global_reset_n ; Output ; Info ; Explicitly unconnected ; -; iod_upper ; Output ; Info ; Explicitly unconnected ; -+-------------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[1].state_machine_counter" ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; c_idle ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter" ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; c_idle ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------+--------+----------+--------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "a10s_ghrd:u0" ; -+----------------------------------------+--------+----------+------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------------------------+--------+----------+------------------------+ -; f2h_stm_hw_events_stm_hwevents[27..4] ; Input ; Info ; Stuck at GND ; -; fancmd_status_led_writeresponsevalid_n ; Output ; Info ; Explicitly unconnected ; -+----------------------------------------+--------+----------+------------------------+ - - -+---------------------------------+ -; Analysis & Elaboration Messages ; -+---------------------------------+ -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected -Info (16260): Previously generated files were detected in the Platform Designer file generation directory ("D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/"). -Info (16261): Skipped generation of the Platform Designer file "D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd.qsys" based on the current IP regeneration policy. You can review your IP regeneration policy in the IP Settings page of the Settings dialog box. -Warning (10275): Verilog HDL Module Instantiation warning at a10s.v(503): ignored dangling comma in List of Port Connections File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 503 -Info (12021): Found 1 design units, including 1 entities, in source file a10s.v - Info (12023): Found entity 1: a10s File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 31 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/temp_fan_loop.v - Info (12023): Found entity 1: TEMP_FAN_LOOP File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/seg7_lut_v.v - Info (12023): Found entity 1: SEG7_LUT_V File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/SEG7_LUT_V.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/reset_dely.v - Info (12023): Found entity 1: RESET_DELY File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/RESET_DELY.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/i2c_write_pointer.v - Info (12023): Found entity 1: I2C_WRITE_POINTER File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_POINTER.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/i2c_write_byte.v - Info (12023): Found entity 1: I2C_WRITE_BYTE File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_BYTE.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/i2c_read_data.v - Info (12023): Found entity 1: I2C_READ_DATA File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/fan_temp_i2c.v - Info (12023): Found entity 1: FAN_TEMP_I2C File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/i2c_read_byte.v - Info (12023): Found entity 1: I2C_READ_BYTE File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_BYTE.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/fan_temp_core.v - Info (12023): Found entity 1: FAN_TEMP_CORE File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_CORE.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/fan_onoff.v - Info (12023): Found entity 1: FAN_ONOFF File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/autofan/clockmem.v - Info (12023): Found entity 1: CLOCKMEM File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/CLOCKMEM.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file ip/debounce/debounce.v - Info (12023): Found entity 1: debounce File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/debounce/debounce.v Line: 13 -Info (12021): Found 1 design units, including 1 entities, in source file ip/edge_detect/altera_edge_detector.v - Info (12023): Found entity 1: altera_edge_detector File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/edge_detect/altera_edge_detector.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/synth/a10s_ghrd.v - Info (12023): Found entity 1: a10s_ghrd File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 6 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/synth/a10s_ghrd_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_s3yuekq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_irq_mapper_181_s3yuekq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_s3yuekq.sv Line: 31 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_4ipexzi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_irq_mapper_181_4ipexzi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_4ipexzi.sv Line: 31 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci.v - Info (12023): Found entity 1: a10s_ghrd_altera_emif_a10_hps_181_oeawlci File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_emif_a10_hps_181_oeawlci_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv - Info (12023): Found entity 1: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux.sv - Info (12023): Found entity 1: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux.sv Line: 15 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sv Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv - Info (12023): Found entity 1: altera_emif_arch_nf_bufs File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 18 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_i.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_udir_se_i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_i.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_o.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_udir_se_o File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_o.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_i.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_udir_df_i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_i.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_o.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_udir_df_o File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_o.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_cp_i.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_udir_cp_i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_cp_i.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_df.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_bdir_df File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_df.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_se.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_bdir_se File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_se.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_unused.sv - Info (12023): Found entity 1: altera_emif_arch_nf_buf_unused File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_unused.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll.sv - Info (12023): Found entity 1: altera_emif_arch_nf_pll File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll.sv Line: 30 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_fast_sim.sv - Info (12023): Found entity 1: altera_emif_arch_nf_pll_fast_sim File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_fast_sim.sv Line: 30 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_extra_clks.sv - Info (12023): Found entity 1: altera_emif_arch_nf_pll_extra_clks File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_extra_clks.sv Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_oct.sv - Info (12023): Found entity 1: altera_emif_arch_nf_oct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_oct.sv Line: 16 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_core_clks_rsts.sv - Info (12023): Found entity 1: altera_emif_arch_nf_core_clks_rsts File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_core_clks_rsts.sv Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hps_clks_rsts.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hps_clks_rsts File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hps_clks_rsts.sv Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv - Info (12023): Found entity 1: altera_emif_arch_nf_io_tiles_wrap File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles.sv - Info (12023): Found entity 1: altera_emif_arch_nf_io_tiles File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles.sv Line: 448 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_abphy.sv - Info (12023): Found entity 1: altera_emif_arch_nf_io_tiles_abphy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_abphy.sv Line: 344 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_abphy_mux.sv - Info (12023): Found entity 1: altera_emif_arch_nf_abphy_mux File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_abphy_mux.sv Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_avl_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hmc_avl_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_avl_if.sv Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_sideband_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hmc_sideband_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_sideband_if.sv Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_mmr_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hmc_mmr_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_mmr_if.sv Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_amm_data_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hmc_amm_data_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_amm_data_if.sv Line: 47 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_ast_data_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_hmc_ast_data_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_ast_data_if.sv Line: 47 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_afi_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_afi_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_afi_if.sv Line: 105 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv - Info (12023): Found entity 1: altera_emif_arch_nf_seq_if File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv Line: 20 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_regs.sv - Info (12023): Found entity 1: altera_emif_arch_nf_regs File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_regs.sv Line: 26 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct.sv - Info (12023): Found entity 1: altera_oct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct.sv Line: 16 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct_um_fsm.sv - Info (12023): Found entity 1: altera_oct_um_fsm File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_oct_um_fsm.sv Line: 16 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy.v - Info (12023): Found entity 1: a10s_ghrd_altera_arria10_hps_181_paoasmy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_arria10_hps_181_paoasmy_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_arria10_interface_generator_140_q66yweq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 14 -Info (12021): Found 16 design units, including 16 entities, in source file a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v - Info (12023): Found entity 1: hps_emif_interface_to_ddr File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 20 - Info (12023): Found entity 2: a10_hps_emif_interface File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 898 - Info (12023): Found entity 3: twentynm_hps_rl_interface_fpga2hps File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 969 - Info (12023): Found entity 4: twentynm_hps_rl_interface_hps2fpga File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1248 - Info (12023): Found entity 5: twentynm_hps_rl_interface_hps2fpga_light_weight File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1503 - Info (12023): Found entity 6: twentynm_hps_rl_mode0_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1748 - Info (12023): Found entity 7: twentynm_hps_rl_mode1_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 2583 - Info (12023): Found entity 8: twentynm_hps_rl_mode2_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 3421 - Info (12023): Found entity 9: twentynm_hps_rl_mode3_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 4016 - Info (12023): Found entity 10: s2f_rl_adp File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 4855 - Info (12023): Found entity 11: f2s_rl_adp File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5242 - Info (12023): Found entity 12: full_reg_slice File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5632 - Info (12023): Found entity 13: twentynm_hps_rl_mode0es_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5726 - Info (12023): Found entity 14: twentynm_hps_rl_mode1es_fpga2sdram File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 6327 - Info (12023): Found entity 15: f2s_rl_delay_adp File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 6936 - Info (12023): Found entity 16: alentar File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7207 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca.v - Info (12023): Found entity 1: a10s_ghrd_altera_arria10_hps_io_181_vma6nca File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_arria10_hps_io_181_vma6nca_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi.sv Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_72qrvsa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_72qrvsa_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_72qrvsa_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq.sv Line: 51 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv - Info (12023): Found entity 1: altera_merlin_arbitrator File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv Line: 103 - Info (12023): Found entity 2: altera_merlin_arb_adder File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv Line: 228 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv - Info (12023): Found entity 1: altera_merlin_width_adapter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 25 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_address_alignment.sv - Info (12023): Found entity 1: altera_merlin_address_alignment File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_address_alignment.sv Line: 26 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_burst_uncompressor.sv - Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_burst_uncompressor.sv Line: 40 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_edscloq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_edscloq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_edscloq.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_master_translator_181/synth/altera_merlin_master_translator.sv - Info (12023): Found entity 1: altera_merlin_master_translator File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_master_translator_181/synth/altera_merlin_master_translator.sv Line: 32 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_master_agent_181/synth/altera_merlin_master_agent.sv - Info (12023): Found entity 1: altera_merlin_master_agent File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_master_agent_181/synth/altera_merlin_master_agent.sv Line: 28 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_p6yk37i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_traffic_limiter.sv - Info (12023): Found entity 1: altera_merlin_traffic_limiter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_traffic_limiter.sv Line: 49 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_reorder_memory.sv - Info (12023): Found entity 1: altera_merlin_reorder_memory File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_reorder_memory.sv Line: 28 - Info (12023): Found entity 2: memory_pointer_controller File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_merlin_reorder_memory.sv Line: 185 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_sc_fifo.v - Info (12023): Found entity 1: altera_avalon_sc_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_sc_fifo.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_st_pipeline_base.v - Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_traffic_limiter_181/synth/altera_avalon_st_pipeline_base.v Line: 22 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_raxibmi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv - Info (12023): Found entity 1: altera_merlin_axi_slave_ni File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_burst_uncompressor.sv - Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_burst_uncompressor.sv Line: 40 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_avalon_sc_fifo.v - Info (12023): Found entity 1: altera_avalon_sc_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_avalon_sc_fifo.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_address_alignment.sv - Info (12023): Found entity 1: altera_merlin_address_alignment File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_address_alignment.sv Line: 26 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_2w3xhoq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_2w3xhoq_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv - Info (12023): Found entity 1: altera_merlin_burst_adapter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_uncmpr.sv - Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_uncmpr.sv Line: 39 -Info (12021): Found 5 design units, including 5 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv - Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 40 - Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 55 - Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 77 - Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 98 - Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 264 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_new.sv - Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_new.sv Line: 25 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_incr_burst_converter.sv - Info (12023): Found entity 1: altera_incr_burst_converter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_incr_burst_converter.sv Line: 28 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_wrap_burst_converter.sv - Info (12023): Found entity 1: altera_wrap_burst_converter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_wrap_burst_converter.sv Line: 27 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_default_burst_converter.sv - Info (12023): Found entity 1: altera_default_burst_converter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_default_burst_converter.sv Line: 30 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_address_alignment.sv - Info (12023): Found entity 1: altera_merlin_address_alignment File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_address_alignment.sv Line: 26 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_stage.sv - Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_stage.sv Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_base.v - Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_avalon_st_pipeline_base.v Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_zoswswa.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_zoswswa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_zoswswa.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_axi_master_ni.sv - Info (12023): Found entity 1: altera_merlin_axi_master_ni File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_axi_master_ni.sv Line: 27 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_address_alignment.sv - Info (12023): Found entity 1: altera_merlin_address_alignment File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_address_alignment.sv Line: 26 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_6bjmpii.sv - Info (12023): Found entity 1: a10s_ghrd_error_adapter_181_6bjmpii File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_6bjmpii.sv Line: 66 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_sc_fifo_181/synth/altera_avalon_sc_fifo.v - Info (12023): Found entity 1: altera_avalon_sc_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_sc_fifo_181/synth/altera_avalon_sc_fifo.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_slave_translator_181/synth/altera_merlin_slave_translator.sv - Info (12023): Found entity 1: altera_merlin_slave_translator File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_translator_181/synth/altera_merlin_slave_translator.sv Line: 35 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_yloihfq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q.sv Line: 43 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_4abqbui File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv - Info (12023): Found entity 1: altera_merlin_slave_agent File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 34 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_burst_uncompressor.sv - Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_burst_uncompressor.sv Line: 40 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_b3m6h3q.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_pio_181_b3m6h3q File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_b3m6h3q.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_ss6apia File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_ss6apia_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_st_adapter_181_sc7osri File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_avalon_st_adapter_181_sc7osri_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_rr5nq7i.sv - Info (12023): Found entity 1: a10s_ghrd_error_adapter_181_rr5nq7i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/error_adapter_181/synth/a10s_ghrd_error_adapter_181_rr5nq7i.sv Line: 66 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.v - Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.v Line: 24 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_clock_crosser.v - Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_clock_crosser.v Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_pipeline_base.v - Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_pipeline_base.v Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_std_synchronizer_nocut.v - Info (12023): Found entity 1: altera_std_synchronizer_nocut File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_std_synchronizer_nocut.v Line: 44 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_owhafhq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_owhafhq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_owhafhq.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly.sv Line: 43 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_6b3wcra File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv Line: 84 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_dpsqb6i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv Line: 84 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_zkknbwi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_sysid_qsys_181/synth/a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_sysid_qsys_181/synth/a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy.v Line: 34 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_opfju6i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_opfju6i_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi.sv Line: 43 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_kb2i2hi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq.sv Line: 51 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_f3wfhna File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_na6njny.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_pio_181_na6njny File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_na6njny.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v - Info (12023): Found entity 1: a10s_ghrd_altera_jtag_avalon_master_181_winiqja File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_jtag_avalon_master_181_winiqja_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_xiycpqq.sv - Info (12023): Found entity 1: a10s_ghrd_channel_adapter_181_xiycpqq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_xiycpqq.sv Line: 55 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v - Info (12023): Found entity 1: altera_avalon_st_jtag_interface File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v Line: 20 -Info (12021): Found 3 design units, including 3 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v - Info (12023): Found entity 1: altera_jtag_control_signal_crosser File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 30 - Info (12023): Found entity 2: altera_jtag_src_crosser File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 72 - Info (12023): Found entity 3: altera_jtag_dc_streaming File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 135 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v - Info (12023): Found entity 1: altera_jtag_sld_node File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v Line: 17 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v - Info (12023): Found entity 1: altera_jtag_streaming File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 18 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v - Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_std_synchronizer_nocut.v - Info (12023): Found entity 1: altera_std_synchronizer_nocut File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_std_synchronizer_nocut.v Line: 44 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_base.v - Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_base.v Line: 22 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_remover.v - Info (12023): Found entity 1: altera_avalon_st_idle_remover File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_remover.v Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_inserter.v - Info (12023): Found entity 1: altera_avalon_st_idle_inserter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_idle_inserter.v Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_stage.sv - Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_pipeline_stage.sv Line: 22 -Info (12021): Found 7 design units, including 7 entities, in source file a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v - Info (12023): Found entity 1: altera_avalon_packets_to_master File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 22 - Info (12023): Found entity 2: packets_to_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 142 - Info (12023): Found entity 3: fifo_buffer_single_clock_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 512 - Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 573 - Info (12023): Found entity 5: fifo_buffer File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 627 - Info (12023): Found entity 6: fifo_to_packet File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 697 - Info (12023): Found entity 7: packets_to_master File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 851 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_packets_to_bytes_181/synth/altera_avalon_st_packets_to_bytes.v - Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_packets_to_bytes_181/synth/altera_avalon_st_packets_to_bytes.v Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_st_bytes_to_packets_181/synth/altera_avalon_st_bytes_to_packets.v - Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_bytes_to_packets_181/synth/altera_avalon_st_bytes_to_packets.v Line: 19 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.v - Info (12023): Found entity 1: altera_reset_controller File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.v Line: 42 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_reset_controller_181/synth/altera_reset_synchronizer.v - Info (12023): Found entity 1: altera_reset_synchronizer File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_reset_controller_181/synth/altera_reset_synchronizer.v Line: 24 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/timing_adapter_181/synth/a10s_ghrd_timing_adapter_181_v2af63i.sv - Info (12023): Found entity 1: a10s_ghrd_timing_adapter_181_v2af63i File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/timing_adapter_181/synth/a10s_ghrd_timing_adapter_181_v2af63i.sv Line: 60 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_arrjpdi.sv - Info (12023): Found entity 1: a10s_ghrd_channel_adapter_181_arrjpdi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_arrjpdi.sv Line: 55 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_u6z2bzq.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_pio_181_u6z2bzq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_pio_181/synth/a10s_ghrd_altera_avalon_pio_181_u6z2bzq.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v - Info (12023): Found entity 1: interrupt_latency_counter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v Line: 18 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/interrupt_latency_counter_181/synth/irq_detector.v - Info (12023): Found entity 1: irq_detector File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/irq_detector.v Line: 18 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/interrupt_latency_counter_181/synth/state_machine_counter.v - Info (12023): Found entity 1: state_machine_counter File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/state_machine_counter.v Line: 18 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_mm_bridge_181/synth/altera_avalon_mm_bridge.v - Info (12023): Found entity 1: altera_avalon_mm_bridge File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_bridge_181/synth/altera_avalon_mm_bridge.v Line: 25 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v - Info (12023): Found entity 1: altsource_probe_top File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v Line: 14 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_gwzlhmy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_gwzlhmy_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy_cfg.v Line: 1 -Warning (10229): Verilog HDL Expression warning at sevenSigDispaly.sv(81): truncated literal to match 3 bits File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/SevenSigmentDisplay_10/synth/sevenSigDispaly.sv Line: 81 -Warning (10229): Verilog HDL Expression warning at sevenSigDispaly.sv(82): truncated literal to match 3 bits File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/SevenSigmentDisplay_10/synth/sevenSigDispaly.sv Line: 82 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/sevensigmentdisplay_10/synth/sevensigdispaly.sv - Info (12023): Found entity 1: sevenSigDisplay File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/SevenSigmentDisplay_10/synth/sevenSigDispaly.sv Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_mm_clock_crossing_bridge.v - Info (12023): Found entity 1: altera_avalon_mm_clock_crossing_bridge File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_mm_clock_crossing_bridge.v Line: 30 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.v - Info (12023): Found entity 1: altera_avalon_dc_fifo File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.v Line: 13 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_dcfifo_synchronizer_bundle.v - Info (12023): Found entity 1: altera_dcfifo_synchronizer_bundle File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_dcfifo_synchronizer_bundle.v Line: 8 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_std_synchronizer_nocut.v - Info (12023): Found entity 1: altera_std_synchronizer_nocut File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_std_synchronizer_nocut.v Line: 44 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v - Info (12023): Found entity 1: a10s_ghrd_altera_mm_interconnect_181_6tzbopq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq_cfg.v - Info (12022): Found design unit 1: a10s_ghrd_altera_mm_interconnect_181_6tzbopq_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja.sv Line: 51 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi.sv Line: 43 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_demultiplexer_181/synth/a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq.sv Line: 43 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_a35vlui File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv Line: 84 -Info (12021): Found 2 design units, including 2 entities, in source file a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv - Info (12023): Found entity 1: a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv Line: 45 - Info (12023): Found entity 2: a10s_ghrd_altera_merlin_router_181_45pxmci File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv Line: 84 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v - Info (12023): Found entity 1: a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v Line: 21 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/han_fancontroll_10/synth/han_fantempcontroll.sv - Info (12023): Found entity 1: HAN_FanTempControll File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 3 -Info (12021): Found 1 design units, including 1 entities, in source file a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_acw3b6a.sv - Info (12023): Found entity 1: a10s_ghrd_altera_irq_mapper_181_acw3b6a File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_irq_mapper_181/synth/a10s_ghrd_altera_irq_mapper_181_acw3b6a.sv Line: 31 -Warning (10236): Verilog HDL Implicit Net warning at a10s.v(394): created implicit net for "RESET_N" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 394 -Warning (10236): Verilog HDL Implicit Net warning at a10s.v(395): created implicit net for "MANU_AUTO_SW" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 395 -Warning (10236): Verilog HDL Implicit Net warning at FAN_TEMP_CORE.v(82): created implicit net for "FAN_ALERT_n" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_CORE.v Line: 82 -Warning (10236): Verilog HDL Implicit Net warning at altera_edge_detector.v(21): created implicit net for "reset_qual_n" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/edge_detect/altera_edge_detector.v Line: 21 -Info (12127): Elaborating entity "a10s" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at a10s.v(394): object "RESET_N" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 394 -Warning (10036): Verilog HDL or VHDL warning at a10s.v(395): object "MANU_AUTO_SW" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 395 -Warning (10034): Output port "FMC_DP_C2M_p" at a10s.v(185) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 185 -Warning (10034): Output port "ETH_TX_p" at a10s.v(267) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 267 -Warning (10034): Output port "ETH_MDC" at a10s.v(270) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 270 -Warning (10034): Output port "ETH_RST_n" at a10s.v(272) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 272 -Warning (10034): Output port "SMA_CLKOUT_p" at a10s.v(369) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 369 -Info (12128): Elaborating entity "a10s_ghrd" for hierarchy "a10s_ghrd:u0" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 503 -Info (12128): Elaborating entity "interrupt_latency_counter" for hierarchy "a10s_ghrd:u0|interrupt_latency_counter:ilc" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 369 -Warning (10230): Verilog HDL assignment warning at interrupt_latency_counter.v(93): truncated value with size 32 to match size of target (1) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v Line: 93 -Warning (10230): Verilog HDL assignment warning at interrupt_latency_counter.v(94): truncated value with size 32 to match size of target (6) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v Line: 94 -Info (12128): Elaborating entity "irq_detector" for hierarchy "a10s_ghrd:u0|interrupt_latency_counter:ilc|irq_detector:irq_detector_cicuit[0].irq_detector" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v Line: 235 -Info (12128): Elaborating entity "state_machine_counter" for hierarchy "a10s_ghrd:u0|interrupt_latency_counter:ilc|state_machine_counter:state_machine[0].state_machine_counter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/interrupt_latency_counter_181/synth/interrupt_latency_counter.v Line: 277 -Info (12128): Elaborating entity "a10s_ghrd_altera_arria10_hps_181_paoasmy" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 588 -Info (12128): Elaborating entity "a10s_ghrd_altera_arria10_interface_generator_140_q66yweq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy.v Line: 426 -Warning (10034): Output port "emif_gp_to_emif" at a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv(31) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 31 -Info (12128): Elaborating entity "a10_hps_emif_interface" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 301 -Info (12128): Elaborating entity "hps_emif_interface_to_ddr" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|a10_hps_emif_interface:emif_interface|hps_emif_interface_to_ddr:inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 960 -Info (12128): Elaborating entity "twentynm_hps_rl_interface_fpga2hps" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 452 -Info (12128): Elaborating entity "f2s_rl_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1144 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_ar" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5394 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5428 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5445 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5462 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:wdata_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1160 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:awaddr_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1161 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_cache_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1163 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_fpga2hps:fpga2hps|alentar:ar_ar_user" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1166 -Info (12128): Elaborating entity "twentynm_hps_rl_interface_hps2fpga_light_weight" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 598 -Info (12128): Elaborating entity "s2f_rl_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1677 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_ar" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5008 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_w" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5042 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_r" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5059 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga_light_weight:hps2fpga_light_weight|s2f_rl_adp:s2f_rl_adp_inst|full_reg_slice:i_s2f_b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5076 -Info (12128): Elaborating entity "twentynm_hps_rl_interface_hps2fpga" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 750 -Info (12128): Elaborating entity "s2f_rl_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1422 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_w" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5042 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|s2f_rl_adp:s2f_rl_adp_ins|full_reg_slice:i_s2f_r" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5059 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_interface_hps2fpga:hps2fpga|alentar:rdata_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 1429 -Info (12128): Elaborating entity "twentynm_hps_rl_mode2_fpga2sdram" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/a10s_ghrd_altera_arria10_interface_generator_140_q66yweq.sv Line: 995 -Info (12128): Elaborating entity "f2s_rl_delay_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 3838 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:wdata_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7051 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:awaddr_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7052 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_cache_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7054 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_ar_user" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7057 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_burst_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7064 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:ar_prot_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7068 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:aw_valid_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7073 -Info (12128): Elaborating entity "alentar" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_0|alentar:w_strb_alen" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7079 -Info (12128): Elaborating entity "f2s_rl_delay_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 3922 -Info (12128): Elaborating entity "f2s_rl_adp" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 7199 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_w" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5428 -Info (12128): Elaborating entity "full_reg_slice" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_interface_generator_140_q66yweq:fpga_interfaces|twentynm_hps_rl_mode2_fpga2sdram:f2sdram|f2s_rl_delay_adp:f2s_rl_adp_inst_2|f2s_rl_adp:f2s_rl_adp_inst|full_reg_slice:i_f2s_r" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_interface_generator_140/synth/hps_a10_lib.v Line: 5445 -Info (12128): Elaborating entity "a10s_ghrd_altera_arria10_hps_io_181_vma6nca" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_181/synth/a10s_ghrd_altera_arria10_hps_181_paoasmy.v Line: 471 -Info (12128): Elaborating entity "a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_arria10_hps_181_paoasmy:arria10_hps|a10s_ghrd_altera_arria10_hps_io_181_vma6nca:hps_io|a10s_ghrd_altera_arria10_interface_generator_140_lkc7nyi:border" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_arria10_hps_io_181/synth/a10s_ghrd_altera_arria10_hps_io_181_vma6nca.v Line: 97 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_pio_181_u6z2bzq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_u6z2bzq:button_pio" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 600 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_pio_181_na6njny" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_na6njny:dipsw_pio" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 612 -Info (12128): Elaborating entity "a10s_ghrd_altera_emif_a10_hps_181_oeawlci" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 638 -Info (12128): Elaborating entity "a10s_ghrd_altera_emif_arch_nf_181_ccplvsq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_a10_hps_181/synth/a10s_ghrd_altera_emif_a10_hps_181_oeawlci.v Line: 1819 -Info (12128): Elaborating entity "a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sv Line: 3576 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wl1_l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wl2_l2core_data" into its bus -Info (12128): Elaborating entity "altera_emif_arch_nf_pll" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2418 -Info (12128): Elaborating entity "altera_emif_arch_nf_pll_extra_clks" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_pll_extra_clks:pll_extra_clks_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2429 -Info (12128): Elaborating entity "altera_emif_arch_nf_oct" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_oct:oct_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2444 -Info (12128): Elaborating entity "altera_emif_arch_nf_hps_clks_rsts" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hps_clks_rsts:hps.hps_clks_rsts_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2462 -Info (12128): Elaborating entity "altera_emif_arch_nf_bufs" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2630 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_unused" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_unused:unused_pin[0].ub" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 241 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_udir_df_o" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_df_o:gen_mem_ck.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 263 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_udir_se_o" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_a.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 371 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_udir_se_o" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_o:gen_mem_reset_n.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 580 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_bdir_se" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_se:gen_mem_dq.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 963 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_udir_se_i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_udir_se_i:gen_mem_alert_n.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 1095 -Info (12128): Elaborating entity "altera_emif_arch_nf_buf_bdir_df" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_bufs:bufs_inst|altera_emif_arch_nf_buf_bdir_df:gen_mem_dqs.inst[0].b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv Line: 1134 -Info (12128): Elaborating entity "a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_io_aux:io_aux_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2667 -Info (12128): Elaborating entity "altera_emif_arch_nf_io_tiles_wrap" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 2989 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat" into its bus -Info (12128): Elaborating entity "altera_emif_arch_nf_io_tiles" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv Line: 836 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "all_tiles_t2l_phy_clk_phs" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "all_tiles_t2l_phy_clk" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_nonabphy" into its bus -Info (12128): Elaborating entity "altera_emif_arch_nf_abphy_mux" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_abphy_mux:altera_emif_arch_nf_abphy_mux_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv Line: 1201 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write_iotile_in" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_abphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_rdata_valid_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_rlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_afi_wlat_nonabphy" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_rdata_en_full" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_read" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_mrnk_write" into its bus -Info (12128): Elaborating entity "altera_emif_arch_nf_seq_if" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 3023 -Info (12128): Elaborating entity "altera_emif_arch_nf_regs" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_req_regs" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv Line: 83 -Info (12128): Elaborating entity "altera_emif_arch_nf_regs" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_ctl_refresh_done_regs" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv Line: 93 -Info (12128): Elaborating entity "altera_emif_arch_nf_regs" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_rlat_regs" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv Line: 167 -Info (12128): Elaborating entity "altera_emif_arch_nf_regs" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_seq_if:seq_if_inst|altera_emif_arch_nf_regs:afi_cal_success_regs" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv Line: 201 -Info (12128): Elaborating entity "altera_emif_arch_nf_hmc_avl_if" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_avl_if:hmc_avl_if_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 3049 -Info (12128): Elaborating entity "altera_emif_arch_nf_hmc_sideband_if" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_sideband_if:hmc_sideband_if_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 3081 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_wb_pointer_for_ecc" into its bus -Info (12128): Elaborating entity "altera_emif_arch_nf_hmc_mmr_if" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_mmr_if:hmc_mmr_if_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 3093 -Info (12128): Elaborating entity "altera_emif_arch_nf_hmc_ast_data_if" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_hmc_ast_data_if:hmc.hmc_ast.data_if_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top.sv Line: 3339 -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "l2core_data" into its bus -Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "core2l_oe" into its bus -Info (12128): Elaborating entity "a10s_ghrd_altera_jtag_avalon_master_181_winiqja" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 656 -Info (12128): Elaborating entity "altera_avalon_st_jtag_interface" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 145 -Info (12128): Elaborating entity "altera_jtag_sld_node" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v Line: 101 -Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v Line: 105 -Info (12130): Elaborated megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v Line: 105 -Info (12133): Instantiated megafunction "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" with the following parameter: File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_sld_node.v Line: 105 - Info (12134): Parameter "sld_mfg_id" = "110" - Info (12134): Parameter "sld_type_id" = "132" - Info (12134): Parameter "sld_version" = "1" - Info (12134): Parameter "sld_auto_instance_index" = "YES" - Info (12134): Parameter "sld_instance_index" = "0" - Info (12134): Parameter "sld_ir_width" = "3" - Info (12134): Parameter "sld_sim_action" = "" - Info (12134): Parameter "sld_sim_n_scan" = "0" - Info (12134): Parameter "sld_sim_total_length" = "0" -Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 151 -Info (12131): Elaborated megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 151 -Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 414 -Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232 -Info (12128): Elaborating entity "altera_jtag_dc_streaming" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v Line: 143 -Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 197 -Info (12130): Elaborated megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 197 -Info (12133): Instantiated megafunction "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" with the following parameter: File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 197 - Info (12134): Parameter "depth" = "3" -Info (12128): Elaborating entity "altera_jtag_streaming" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 226 -Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 231 -Info (12130): Elaborated megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 231 -Info (12133): Instantiated megafunction "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" with the following parameter: File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 231 - Info (12134): Parameter "depth" = "8" -Info (12128): Elaborating entity "altera_avalon_st_idle_remover" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 547 -Info (12128): Elaborating entity "altera_avalon_st_idle_inserter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_streaming.v Line: 564 -Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 246 -Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:in_to_out_synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v Line: 105 -Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer_nocut:out_to_in_synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v Line: 112 -Info (12128): Elaborating entity "altera_avalon_st_pipeline_base" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_clock_crosser.v Line: 129 -Info (12128): Elaborating entity "altera_jtag_src_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 259 -Info (12128): Elaborating entity "altera_jtag_control_signal_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_jtag_dc_streaming.v Line: 110 -Info (12128): Elaborating entity "a10s_ghrd_timing_adapter_181_v2af63i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_timing_adapter_181_v2af63i:timing_adt" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 155 -Warning (10036): Verilog HDL or VHDL warning at a10s_ghrd_timing_adapter_181_v2af63i.sv(82): object "in_ready" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/timing_adapter_181/synth/a10s_ghrd_timing_adapter_181_v2af63i.sv Line: 82 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_sc_fifo:fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 196 -Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_bytes_to_packets:b2p" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 213 -Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_st_packets_to_bytes:p2b" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 230 -Info (12128): Elaborating entity "altera_avalon_packets_to_master" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 257 -Info (12128): Elaborating entity "packets_to_master" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_avalon_packets_to_master:transacto|packets_to_master:p2m" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_packets_to_master_181/synth/altera_avalon_packets_to_master.v Line: 137 -Info (12128): Elaborating entity "a10s_ghrd_channel_adapter_181_arrjpdi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_channel_adapter_181_arrjpdi:b2p_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 273 -Warning (10036): Verilog HDL or VHDL warning at a10s_ghrd_channel_adapter_181_arrjpdi.sv(78): object "out_channel" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_arrjpdi.sv Line: 78 -Warning (10230): Verilog HDL assignment warning at a10s_ghrd_channel_adapter_181_arrjpdi.sv(90): truncated value with size 8 to match size of target (1) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/channel_adapter_181/synth/a10s_ghrd_channel_adapter_181_arrjpdi.sv Line: 90 -Info (12128): Elaborating entity "a10s_ghrd_channel_adapter_181_xiycpqq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|a10s_ghrd_channel_adapter_181_xiycpqq:p2b_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 289 -Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_avalon_master_181/synth/a10s_ghrd_altera_jtag_avalon_master_181_winiqja.v Line: 352 -Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.v Line: 208 -Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_jtag_avalon_master_181_winiqja:f2sdram_m|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.v Line: 220 -Info (12128): Elaborating entity "HAN_FanTempControll" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 671 -Info (12128): Elaborating entity "CLOCKMEM" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|CLOCKMEM:k10" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 108 -Info (12128): Elaborating entity "TEMP_FAN_LOOP" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 150 -Warning (10034): Output port "DAC_6000" at TEMP_FAN_LOOP.v(22) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 22 -Warning (10034): Output port "DAC_5500" at TEMP_FAN_LOOP.v(23) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 23 -Warning (10034): Output port "DAC_5000" at TEMP_FAN_LOOP.v(24) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 24 -Warning (10034): Output port "DAC_4500" at TEMP_FAN_LOOP.v(25) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 25 -Warning (10034): Output port "DAC_4000" at TEMP_FAN_LOOP.v(26) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 26 -Warning (10034): Output port "DAC_3500" at TEMP_FAN_LOOP.v(27) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 27 -Warning (10034): Output port "DAC_3000" at TEMP_FAN_LOOP.v(30) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 30 -Warning (10034): Output port "BUSY" at TEMP_FAN_LOOP.v(16) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 16 -Info (12128): Elaborating entity "FAN_TEMP_I2C" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 77 -Warning (10230): Verilog HDL assignment warning at FAN_TEMP_I2C.v(125): truncated value with size 32 to match size of target (13) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 125 -Warning (10230): Verilog HDL assignment warning at FAN_TEMP_I2C.v(126): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 126 -Warning (10230): Verilog HDL assignment warning at FAN_TEMP_I2C.v(130): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 130 -Warning (10230): Verilog HDL assignment warning at FAN_TEMP_I2C.v(232): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 232 -Warning (10230): Verilog HDL assignment warning at FAN_TEMP_I2C.v(295): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 295 -Info (12128): Elaborating entity "CLOCKMEM" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 137 -Info (12128): Elaborating entity "I2C_WRITE_BYTE" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_BYTE:wrd" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 356 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_BYTE.v(68): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_BYTE.v Line: 68 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_BYTE.v(137): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_BYTE.v Line: 137 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_BYTE.v(147): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_BYTE.v Line: 147 -Info (12128): Elaborating entity "I2C_WRITE_POINTER" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 369 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_POINTER.v(69): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_POINTER.v Line: 69 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_POINTER.v(133): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_POINTER.v Line: 133 -Warning (10230): Verilog HDL assignment warning at I2C_WRITE_POINTER.v(143): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_WRITE_POINTER.v Line: 143 -Info (12128): Elaborating entity "I2C_READ_DATA" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_READ_DATA:rd" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_TEMP_I2C.v Line: 383 -Warning (10230): Verilog HDL assignment warning at I2C_READ_DATA.v(56): truncated value with size 33 to match size of target (9) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 56 -Warning (10230): Verilog HDL assignment warning at I2C_READ_DATA.v(70): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 70 -Warning (10230): Verilog HDL assignment warning at I2C_READ_DATA.v(93): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 93 -Warning (10230): Verilog HDL assignment warning at I2C_READ_DATA.v(96): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 96 -Warning (10230): Verilog HDL assignment warning at I2C_READ_DATA.v(107): truncated value with size 32 to match size of target (8) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/I2C_READ_DATA.v Line: 107 -Info (12128): Elaborating entity "FAN_ONOFF" for hierarchy "a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/TEMP_FAN_LOOP.v Line: 108 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(68): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 68 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(97): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 97 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(99): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 99 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(100): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 100 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(101): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 101 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(102): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 102 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(103): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 103 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(104): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 104 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(107): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 107 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(108): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 108 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(109): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 109 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(110): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 110 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(111): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 111 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(112): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 112 -Warning (10230): Verilog HDL assignment warning at FAN_ONOFF.v(113): truncated value with size 32 to match size of target (16) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 113 -Warning (10034): Output port "CNT" at FAN_ONOFF.v(14) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 14 -Warning (10034): Output port "LEV" at FAN_ONOFF.v(15) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 15 -Warning (10034): Output port "FAN_DAC" at FAN_ONOFF.v(17) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 17 -Warning (10034): Output port "FAN_INI" at FAN_ONOFF.v(13) has no driver File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 13 -Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 725 -Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_mm_clock_crossing_bridge.v Line: 149 -Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.v Line: 373 -Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_dcfifo_synchronizer_bundle.v Line: 33 -Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_clock_crossing_bridge:h2fw_clockbridge|altera_avalon_dc_fifo:rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_mm_clock_crossing_bridge.v Line: 282 -Info (12128): Elaborating entity "altsource_probe_top" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 757 -Info (12128): Elaborating entity "altsource_probe" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v Line: 55 -Info (12130): Elaborated megafunction instantiation "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v Line: 55 -Info (12133): Instantiated megafunction "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl" with the following parameter: File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_in_system_sources_probes_181/synth/altsource_probe_top.v Line: 55 - Info (12134): Parameter "lpm_type" = "altsource_probe" - Info (12134): Parameter "lpm_hint" = "UNUSED" - Info (12134): Parameter "sld_auto_instance_index" = "YES" - Info (12134): Parameter "sld_instance_index" = "0" - Info (12134): Parameter "SLD_NODE_INFO" = "4746752" - Info (12134): Parameter "sld_ir_width" = "4" - Info (12134): Parameter "instance_id" = "RST" - Info (12134): Parameter "probe_width" = "0" - Info (12134): Parameter "source_width" = "3" - Info (12134): Parameter "source_initial_value" = "0" - Info (12134): Parameter "enable_metastability" = "YES" -Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|sld_jtag_endpoint_adapter:jtag_signal_adapter" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v Line: 168 -Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232 -Info (12128): Elaborating entity "altsource_probe_body" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v Line: 242 -Info (12128): Elaborating entity "altsource_probe_impl" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd Line: 535 -Info (12128): Elaborating entity "sld_rom_sr" for hierarchy "a10s_ghrd:u0|altsource_probe_top:issp|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_source_gen:wider_source_inst|sld_rom_sr:\instance_id_gen:rom_info_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd Line: 755 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_pio_181_b3m6h3q" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_pio_181_b3m6h3q:led_pio" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 768 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 781 -Info (12128): Elaborating entity "altsyncram" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v Line: 66 -Info (12130): Elaborated megafunction instantiation "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v Line: 66 -Info (12133): Instantiated megafunction "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram" with the following parameter: File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_onchip_memory2_181/synth/a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa.v Line: 66 - Info (12134): Parameter "byte_size" = "8" - Info (12134): Parameter "init_file" = "a10s_ghrd_onchip_memory2.hex" - Info (12134): Parameter "lpm_type" = "altsyncram" - Info (12134): Parameter "maximum_depth" = "262144" - Info (12134): Parameter "numwords_a" = "262144" - Info (12134): Parameter "operation_mode" = "SINGLE_PORT" - Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE" - Info (12134): Parameter "width_a" = "8" - Info (12134): Parameter "widthad_a" = "18" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0jk1.tdf - Info (12023): Found entity 1: altsyncram_0jk1 File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/altsyncram_0jk1.tdf Line: 31 -Info (12128): Elaborating entity "altsyncram_0jk1" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 -Info (12021): Found 1 design units, including 1 entities, in source file db/decode_afa.tdf - Info (12023): Found entity 1: decode_afa File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/decode_afa.tdf Line: 22 -Info (12128): Elaborating entity "decode_afa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|decode_afa:decode3" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/altsyncram_0jk1.tdf Line: 42 -Info (12021): Found 1 design units, including 1 entities, in source file db/mux_q9b.tdf - Info (12023): Found entity 1: mux_q9b File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/mux_q9b.tdf Line: 22 -Info (12128): Elaborating entity "mux_q9b" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_onchip_memory2_181_7kzxmpa:onchip_memory2|altsyncram:the_altsyncram|altsyncram_0jk1:auto_generated|mux_q9b:mux2" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/altsyncram_0jk1.tdf Line: 43 -Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "a10s_ghrd:u0|altera_avalon_mm_bridge:pb_lwh2f" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 815 -Info (12128): Elaborating entity "sevenSigDisplay" for hierarchy "a10s_ghrd:u0|sevenSigDisplay:sevensig" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 827 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_avalon_sysid_qsys_181_egruyfy:sysid_qsys" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 834 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_ss6apia" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 896 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:h2fw_clockbridge_s0_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 396 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_s1_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 460 -Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 588 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_axi_master_ni:arria10_hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_axi_master_ni.sv Line: 485 -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 672 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:h2fw_clockbridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 608 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 713 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:h2fw_clockbridge_s0_agent_rdata_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 754 -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 838 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 608 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 879 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_s1_agent_rdata_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 920 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_6b3wcra" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 936 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_6b3wcra:router|a10s_ghrd_altera_merlin_router_181_6b3wcra_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv Line: 180 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_zkknbwi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 968 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_zkknbwi:router_002|a10s_ghrd_altera_merlin_router_181_zkknbwi_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv Line: 181 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_dpsqb6i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 984 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_router_181_dpsqb6i:router_003|a10s_ghrd_altera_merlin_router_181_dpsqb6i_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv Line: 181 -Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_traffic_limiter:arria10_hps_h2f_axi_master_wr_limiter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1034 -Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1134 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv Line: 181 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 778 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 979 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 1004 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 157 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:h2fw_clockbridge_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 88 -Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1184 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv Line: 181 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 778 -Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(155): truncated value with size 4 to match size of target (2) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_address_alignment.sv Line: 155 -Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(259): truncated value with size 34 to match size of target (32) File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_address_alignment.sv Line: 259 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_unziy3i:cmd_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1207 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1253 -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y.sv Line: 287 -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_sgkkm3y:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv Line: 169 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_5zwuytq:rsp_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1299 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_demultiplexer_181_tdxkbly:rsp_demux_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1322 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_owhafhq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1345 -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_merlin_multiplexer_181_owhafhq:rsp_mux|altera_merlin_arbitrator:arb" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_owhafhq.sv Line: 310 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1434 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 283 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 742 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 743 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 954 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1500 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 283 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 742 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 743 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_rsp_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 954 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1566 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "data_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "byteen_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:h2fw_clockbridge_s0_cmd_width_adapter|altera_merlin_address_alignment:check_and_align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 388 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_merlin_width_adapter:onchip_memory2_s1_cmd_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1632 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "data_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "byteen_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1666 -Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.v Line: 149 -Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer_nocut:in_to_out_synchronizer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_clock_crosser.v Line: 105 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1797 -Info (12128): Elaborating entity "a10s_ghrd_error_adapter_181_6bjmpii" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi:avalon_st_adapter|a10s_ghrd_error_adapter_181_6bjmpii:error_adapter_0" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_bbfziwi.v Line: 200 -Info (12128): Elaborating entity "a10s_ghrd_altera_avalon_st_adapter_181_sc7osri" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_ss6apia.v Line: 1826 -Info (12128): Elaborating entity "a10s_ghrd_error_adapter_181_rr5nq7i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_ss6apia:mm_interconnect_0|a10s_ghrd_altera_avalon_st_adapter_181_sc7osri:avalon_st_adapter_001|a10s_ghrd_error_adapter_181_rr5nq7i:error_adapter_0" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_adapter_181/synth/a10s_ghrd_altera_avalon_st_adapter_181_sc7osri.v Line: 200 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_2w3xhoq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 958 -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_translator:fpga_m_master_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 282 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_translator:pb_lwh2f_s0_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 346 -Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 474 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_axi_master_ni:arria10_hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_master_ni_181/synth/altera_merlin_axi_master_ni.sv Line: 485 -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_master_agent:fpga_m_master_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 555 -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 639 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_slave_agent:pb_lwh2f_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 608 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 680 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_avalon_sc_fifo:pb_lwh2f_s0_agent_rdata_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 721 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_yloihfq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 737 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_yloihfq:router|a10s_ghrd_altera_merlin_router_181_yloihfq_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv Line: 174 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_4abqbui" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 785 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_router_181_4abqbui:router_003|a10s_ghrd_altera_merlin_router_181_4abqbui_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv Line: 181 -Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 835 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter.sv Line: 181 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 979 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 1004 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 157 -Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|altera_merlin_burst_adapter:pb_lwh2f_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_13_1.sv Line: 88 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_obrwnpa:cmd_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 852 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_zoswswa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 915 -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_zoswswa.sv Line: 301 -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_zoswswa:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv Line: 169 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_demultiplexer_181_yfxh77q:rsp_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 944 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_2w3xhoq:mm_interconnect_1|a10s_ghrd_altera_merlin_multiplexer_181_nzjnjka:rsp_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_2w3xhoq.v Line: 961 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_6tzbopq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 995 -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_translator:pb_lwh2f_m0_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 430 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:ilc_avalon_slave_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 494 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:sysid_qsys_control_slave_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 558 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_translator:led_pio_s1_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 622 -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_master_agent:pb_lwh2f_m0_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 831 -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 915 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_slave_agent:ilc_avalon_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 608 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_avalon_sc_fifo:ilc_avalon_slave_agent_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 956 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_45pxmci" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1472 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_45pxmci:router|a10s_ghrd_altera_merlin_router_181_45pxmci_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv Line: 188 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_a35vlui" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1488 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_router_181_a35vlui:router_001|a10s_ghrd_altera_merlin_router_181_a35vlui_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv Line: 173 -Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|altera_merlin_traffic_limiter:pb_lwh2f_m0_limiter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1602 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_xwdj4sq:cmd_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1643 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_3zqjrja:cmd_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1660 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_demultiplexer_181_jei7voi:rsp_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1745 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_6tzbopq.v Line: 1854 -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy.sv Line: 358 -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_6tzbopq:mm_interconnect_2|a10s_ghrd_altera_merlin_multiplexer_181_q7pijiy:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_multiplexer_181/synth/altera_merlin_arbitrator.sv Line: 169 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_opfju6i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1018 -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_translator:h2fw_clockbridge_m0_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 275 -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_translator:sevensig_avalon_slave_0_translator" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 339 -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_master_agent:h2fw_clockbridge_m0_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 484 -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 568 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_slave_agent:sevensig_avalon_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_slave_agent_181/synth/altera_merlin_slave_agent.sv Line: 608 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_sc_fifo:sevensig_avalon_slave_0_agent_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 609 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_f3wfhna" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 832 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_f3wfhna:router|a10s_ghrd_altera_merlin_router_181_f3wfhna_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv Line: 187 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_kb2i2hi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 848 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_router_181_kb2i2hi:router_001|a10s_ghrd_altera_merlin_router_181_kb2i2hi_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv Line: 173 -Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_merlin_traffic_limiter:h2fw_clockbridge_m0_limiter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 914 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_m2pcxaa:cmd_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 937 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_7bdlmwy:cmd_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 954 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_demultiplexer_181_obzeixi:rsp_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 988 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|a10s_ghrd_altera_merlin_multiplexer_181_qhf4euq:rsp_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 1028 -Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_opfju6i.v Line: 1062 -Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_opfju6i:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.v Line: 149 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_gwzlhmy" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1070 -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_master_agent:hps_m_master_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 323 -Info (12128): Elaborating entity "altera_merlin_axi_slave_ni" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 442 -Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_address_alignment:check_and_align_address_to_size" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv Line: 629 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_merlin_burst_uncompressor:read_burst_uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv Line: 757 -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_axi_slave_ni:arria10_hps_f2h_axi_slave_agent|altera_avalon_sc_fifo:write_rsp_fifo" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_axi_slave_ni_181/synth/altera_merlin_axi_slave_ni.sv Line: 798 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_raxibmi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 458 -Warning (10036): Verilog HDL or VHDL warning at a10s_ghrd_altera_merlin_router_181_raxibmi.sv(154): object "address" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 154 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_raxibmi:router|a10s_ghrd_altera_merlin_router_181_raxibmi_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 188 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_p6yk37i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 474 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_router_181_p6yk37i:router_001|a10s_ghrd_altera_merlin_router_181_p6yk37i_default_decode:the_default_decode" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv Line: 173 -Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_traffic_limiter:hps_m_master_limiter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 540 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_edscloq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_edscloq:cmd_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 563 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_3zss3fq:cmd_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 580 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_demultiplexer_181_477p4fa:rsp_demux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 614 -Info (12128): Elaborating entity "a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|a10s_ghrd_altera_merlin_multiplexer_181_qn4gn4i:rsp_mux" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 654 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 720 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 283 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 742 -Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 743 -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 954 -Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_gwzlhmy:mm_interconnect_4|altera_merlin_width_adapter:arria10_hps_f2h_axi_slave_wr_rsp_width_adapter" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_mm_interconnect_181/synth/a10s_ghrd_altera_mm_interconnect_181_gwzlhmy.v Line: 852 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "data_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Warning (10240): Verilog HDL Always Construct warning at altera_merlin_width_adapter.sv(459): inferring latch(es) for variable "byteen_reg", which holds its previous value in one or more paths through the always construct File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_width_adapter_181/synth/altera_merlin_width_adapter.sv Line: 459 -Info (12128): Elaborating entity "a10s_ghrd_altera_mm_interconnect_181_72qrvsa" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_mm_interconnect_181_72qrvsa:mm_interconnect_5" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1123 -Info (12128): Elaborating entity "a10s_ghrd_altera_irq_mapper_181_s3yuekq" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_s3yuekq:irq_mapper" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1131 -Info (12128): Elaborating entity "a10s_ghrd_altera_irq_mapper_181_4ipexzi" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_4ipexzi:irq_mapper_001" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1139 -Info (12128): Elaborating entity "a10s_ghrd_altera_irq_mapper_181_acw3b6a" for hierarchy "a10s_ghrd:u0|a10s_ghrd_altera_irq_mapper_181_acw3b6a:irq_mapper_002" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1145 -Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "a10s_ghrd:u0|altera_reset_controller:rst_controller" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1208 -Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "a10s_ghrd:u0|altera_reset_controller:rst_controller_002" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/synth/a10s_ghrd.v Line: 1334 -Info (12128): Elaborating entity "debounce" for hierarchy "debounce:debounce_inst" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 514 -Info (12128): Elaborating entity "altera_edge_detector" for hierarchy "altera_edge_detector:pulse_cold_reset" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 526 -Info (12128): Elaborating entity "altera_edge_detector" for hierarchy "altera_edge_detector:pulse_warm_reset" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 536 -Info (12128): Elaborating entity "altera_edge_detector" for hierarchy "altera_edge_detector:pulse_debug_reset" File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.v Line: 546 -Warning (12010): Port "ir_out" on the entity instantiation of "node" is connected to a signal of width 1. The formal width of the signal in the module is 3. The extra bits will be driven by GND. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v Line: 101 -Warning (12010): Port "ir_out" on the entity instantiation of "node" is connected to a signal of width 1. The formal width of the signal in the module is 3. The extra bits will be driven by GND. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.v Line: 101 -Info (11170): Starting IP generation for the debug fabric: alt_sld_fab. -Info (11172): 2019.12.16.18:02:45 Progress: Loading sldcaedf791/alt_sld_fab_wrapper_hw.tcl -Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG -Info (11172): Alt_sld_fab: "Transforming system: alt_sld_fab" -Info (11172): Alt_sld_fab: Running transform generation_view_transform -Info (11172): Alt_sld_fab: Running transform generation_view_transform took 0.000s -Info (11172): Alt_sld_fab: Running transform generation_view_transform -Info (11172): Alt_sld_fab: Running transform generation_view_transform took 0.000s -Info (11172): Presplit: Running transform generation_view_transform -Info (11172): Presplit: Running transform generation_view_transform took 0.000s -Info (11172): Splitter: Running transform generation_view_transform -Info (11172): Splitter: Running transform generation_view_transform took 0.000s -Info (11172): Jtagpins: Running transform generation_view_transform -Info (11172): Jtagpins: Running transform generation_view_transform took 0.000s -Info (11172): Sldfabric: Running transform generation_view_transform -Info (11172): Sldfabric: Running transform generation_view_transform took 0.000s -Info (11172): Ident: Running transform generation_view_transform -Info (11172): Ident: Running transform generation_view_transform took 0.000s -Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform -Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform took 0.053s -Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform -Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform took 0.012s -Info (11172): Alt_sld_fab: "Naming system components in system: alt_sld_fab" -Info (11172): Alt_sld_fab: "Processing generation queue" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_alt_sld_fab_181_vximuei" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_super_splitter_181_hav7emy" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_sld_splitter_181_zactcby" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_sld_jtag_hub_181_usvbikq" -Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_connection_identification_hub_181_knev7mq" -Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 8 files -Info (11171): Finished IP generation for the debug fabric: alt_sld_fab. -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldcaedf791/alt_sld_fab_181/synth/alt_sld_fab_alt_sld_fab_181_vximuei.v - Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_181_vximuei File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/alt_sld_fab_181/synth/alt_sld_fab_alt_sld_fab_181_vximuei.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sldcaedf791/alt_sld_fab_181/synth/alt_sld_fab_alt_sld_fab_181_vximuei_cfg.v - Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_181_vximuei_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/alt_sld_fab_181/synth/alt_sld_fab_alt_sld_fab_181_vximuei_cfg.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldcaedf791/altera_connection_identification_hub_181/synth/alt_sld_fab_altera_connection_identification_hub_181_knev7mq.sv - Info (12023): Found entity 1: alt_sld_fab_altera_connection_identification_hub_181_knev7mq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/altera_connection_identification_hub_181/synth/alt_sld_fab_altera_connection_identification_hub_181_knev7mq.sv Line: 33 -Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sldcaedf791/altera_sld_jtag_hub_181/synth/alt_sld_fab_altera_sld_jtag_hub_181_usvbikq.vhd - Info (12022): Found design unit 1: alt_sld_fab_altera_sld_jtag_hub_181_usvbikq-rtl File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/altera_sld_jtag_hub_181/synth/alt_sld_fab_altera_sld_jtag_hub_181_usvbikq.vhd Line: 222 - Info (12023): Found entity 1: alt_sld_fab_altera_sld_jtag_hub_181_usvbikq File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/altera_sld_jtag_hub_181/synth/alt_sld_fab_altera_sld_jtag_hub_181_usvbikq.vhd Line: 11 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldcaedf791/altera_sld_splitter_181/synth/alt_sld_fab_altera_sld_splitter_181_zactcby.sv - Info (12023): Found entity 1: alt_sld_fab_altera_sld_splitter_181_zactcby File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/altera_sld_splitter_181/synth/alt_sld_fab_altera_sld_splitter_181_zactcby.sv Line: 3 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldcaedf791/altera_super_splitter_181/synth/alt_sld_fab_altera_super_splitter_181_hav7emy.sv - Info (12023): Found entity 1: alt_sld_fab_altera_super_splitter_181_hav7emy File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/altera_super_splitter_181/synth/alt_sld_fab_altera_super_splitter_181_hav7emy.sv Line: 3 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldcaedf791/synth/alt_sld_fab.v - Info (12023): Found entity 1: alt_sld_fab File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/synth/alt_sld_fab.v Line: 9 -Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sldcaedf791/synth/alt_sld_fab_cfg.v - Info (12022): Found design unit 1: alt_sld_fab_cfg:config File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/db/ip/sldcaedf791/synth/alt_sld_fab_cfg.v Line: 1 -Warning (12241): 21 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Info (144001): Generated suppressed messages file D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.map.smsg - - -+--------------------------------------------+ -; Analysis & Elaboration Suppressed Messages ; -+--------------------------------------------+ -The suppressed messages can be found in D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/output_files/a10s.map.smsg. - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.map.smsg b/fpga/HAN_A10rsyocto/output_files/a10s.map.smsg deleted file mode 100644 index fc2b822..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.map.smsg +++ /dev/null @@ -1,30 +0,0 @@ -Warning (10268): Verilog HDL information at FAN_ONOFF.v(65): always construct contains both blocking and non-blocking assignments File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/IP/autofan/FAN_ONOFF.v Line: 65 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_p6yk37i.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_p6yk37i.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_p6yk37i.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_raxibmi.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_raxibmi.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_raxibmi.sv Line: 49 -Info (10281): Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object "BYTE_TO_WORD_SHIFT" differs only in case from object "byte_to_word_shift" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_merlin_burst_adapter_new.sv Line: 139 -Info (10281): Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object "addr_incr" differs only in case from object "ADDR_INCR" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_burst_adapter_181/synth/altera_wrap_burst_converter.sv Line: 279 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_yloihfq.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_yloihfq.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_yloihfq.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_4abqbui.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_4abqbui.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_4abqbui.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_6b3wcra.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_6b3wcra.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_6b3wcra.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_dpsqb6i.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_zkknbwi.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_zkknbwi.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_zkknbwi.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_kb2i2hi.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_f3wfhna.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_f3wfhna.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_f3wfhna.sv Line: 49 -Warning (10268): Verilog HDL information at sevenSigDispaly.sv(60): always construct contains both blocking and non-blocking assignments File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/SevenSigmentDisplay_10/synth/sevenSigDispaly.sv Line: 60 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_a35vlui.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_a35vlui.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_a35vlui.sv Line: 49 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_45pxmci.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv Line: 48 -Info (10281): Verilog HDL Declaration information at a10s_ghrd_altera_merlin_router_181_45pxmci.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/altera_merlin_router_181/synth/a10s_ghrd_altera_merlin_router_181_45pxmci.sv Line: 49 -Info (10281): Verilog HDL Declaration information at HAN_FanTempControll.sv(12): object "Temp_HI" differs only in case from object "temp_hi" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 12 -Info (10281): Verilog HDL Declaration information at HAN_FanTempControll.sv(13): object "Temp_OK" differs only in case from object "temp_ok" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 13 -Info (10281): Verilog HDL Declaration information at HAN_FanTempControll.sv(14): object "Temp_LOW" differs only in case from object "temp_low" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 14 -Info (10281): Verilog HDL Declaration information at HAN_FanTempControll.sv(17): object "Temp_LED" differs only in case from object "temp_led" in the same scope File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s_ghrd/HAN_FanControll_10/synth/HAN_FanTempControll.sv Line: 17 diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.map.summary b/fpga/HAN_A10rsyocto/output_files/a10s.map.summary deleted file mode 100644 index 3c13e3e..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.map.summary +++ /dev/null @@ -1,11 +0,0 @@ -Analysis & Elaboration Status : Successful - Mon Dec 16 18:02:56 2019 -Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition -Revision Name : a10s -Top-level Entity Name : a10s -Family : Arria 10 -Logic utilization (in ALMs) : N/A until Partition Merge -Total registers : N/A until Partition Merge -Total pins : N/A until Partition Merge -Total virtual pins : N/A until Partition Merge -Total block memory bits : N/A until Partition Merge -Total PLLs : N/A until Partition Merge diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.pin b/fpga/HAN_A10rsyocto/output_files/a10s.pin deleted file mode 100644 index 323cea8..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.pin +++ /dev/null @@ -1,1601 +0,0 @@ - -- Copyright (C) 2018 Intel Corporation. All rights reserved. - -- Your use of Intel Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Intel Program License - -- Subscription Agreement, the Intel Quartus Prime License Agreement, - -- the Intel FPGA IP License Agreement, or other applicable license - -- agreement, including, without limitation, that your use is for - -- the sole purpose of programming logic devices manufactured by - -- Intel and sold by Intel or its authorized distributors. Please - -- refer to the applicable agreement for further details. - -- - -- This is a Quartus Prime output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus Prime input file. This file cannot be used - -- to make Quartus Prime pin assignments - for instructions on how to make pin - -- assignments, please see Quartus Prime help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V. - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 2L: 1.8V - -- Bank 2K: 1.2V - -- Bank 2J: 1.2V - -- Bank 2I: 1.8V - -- Bank 2H: 1.8V - -- Bank 2G: 1.8V - -- Bank 2A: 1.8V - -- Bank 3H: 1.8V - -- Bank 3G: 1.8V - -- Bank 3F: 1.8V - -- Bank 3E: 1.2V - -- Bank 3D: 1.8V - -- Bank 3C: 1.8V - -- Bank 3B: 1.8V - -- Bank 3A: 1.8V - -- RREF : External reference resistor for the quad, MUST be connected to - -- GND via a 2k Ohm resistor. - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* - -- either individually through a 10k Ohm resistor to GND or tie all pins - -- together and connect through a single 10k Ohm resistor to GND. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - -- GXB_GND* : Unused GXB Receiver or dedicated reference clock pin. This pin - -- must be connected directly to GND. - -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin - -- must not be connected. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition -CHIP "a10s" ASSIGNED TO AN: 10AS066K3F40E2SG - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment : Package Delay ------------------------------------------------------------------------------------------------------------------------------ -FMC_HB_p[7] : A2 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[0] : A3 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[0] : A4 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[12] : A5 : bidir : 1.8 V : : 3G : Y : -- -GND : A6 : gnd : : : : : -- -FMC_HA_p[15] : A7 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[15] : A8 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[16] : A9 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[12] : A10 : bidir : 1.8 V : : 3H : Y : -- -GND : A11 : gnd : : : : : -- -FMC_HA_p[14] : A12 : bidir : 1.8 V : : 3H : Y : -- -VREFP_ADC : A13 : : : : : : -- -VREFN_ADC : A14 : : : : : : -- -DDR4H_DQ[13] : A15 : bidir : 1.2-V POD : : 2J : Y : 175ps -GND : A16 : gnd : : : : : -- -DDR4H_DQ[12] : A17 : bidir : 1.2-V POD : : 2J : Y : 177ps -DDR4H_DQ[14] : A18 : bidir : 1.2-V POD : : 2J : Y : 171ps -DDR4H_DQ[7] : A19 : bidir : 1.2-V POD : : 2J : Y : 178ps -DDR4H_DQS[0] : A20 : bidir : Differential 1.2-V POD : : 2J : Y : 180ps -GND : A21 : gnd : : : : : -- -DDR4H_DQ[3] : A22 : bidir : 1.2-V POD : : 2J : Y : 189ps -DDR4H_ALERT_n : A23 : input : SSTL-12 : : 2J : Y : 190ps -RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 2L : : -- -GND : A26 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : A27 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : A28 : : : : 2L : : -- -HPS_KEY : A29 : bidir : 1.8 V : : 2L : Y : -- -HPS_I2C0_SDAT : A30 : bidir : 1.8 V : : 2L : Y : -- -GND : A31 : gnd : : : : : -- -RREF : A32 : : : : : : -- -GND : A33 : gnd : : : : : -- -GND : A34 : gnd : : : : : -- -GND : A35 : gnd : : : : : -- -GXB_NC : A36 : : : : 1H : : -- -GXB_NC : A37 : : : : 1H : : -- -GND : A38 : gnd : : : : : -- -GND : AA1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3D : : -- -VCCIO3D : AA6 : power : : 1.8V : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3D : : -- -VCCIO3D : AA11 : power : : 1.8V : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3D : : -- -VREFB3DN0 : AA13 : power : : : 3D : : -- -VCC : AA14 : power : : 0.9V : : : -- -VCC : AA15 : power : : 0.9V : : : -- -GND : AA16 : gnd : : : : : -- -VCC : AA17 : power : : 0.9V : : : -- -VCC : AA18 : power : : 0.9V : : : -- -VCC : AA19 : power : : 0.9V : : : -- -VCC : AA20 : power : : 0.9V : : : -- -GND : AA21 : gnd : : : : : -- -VCC : AA22 : power : : 0.9V : : : -- -VCC : AA23 : power : : 0.9V : : : -- -VCC : AA24 : power : : 0.9V : : : -- -VREFB2IN0 : AA25 : power : : : 2I : : -- -GND : AA26 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AA27 : : : : 2I : : -- -GND : AA28 : gnd : : : : : -- -VCCH_GXBL : AA29 : power : : 1.8V : : : -- -VCCT_GXBL1E : AA30 : power : : 0.95V : : : -- -VCCT_GXBL1E : AA31 : power : : 0.95V : : : -- -GXB_GND* : AA32 : : : : 1E : : -- -GXB_GND* : AA33 : : : : 1E : : -- -GND : AA34 : gnd : : : : : -- -GND : AA35 : gnd : : : : : -- -GXB_GND* : AA36 : : : : 1E : : -- -GXB_GND* : AA37 : : : : 1E : : -- -GND : AA38 : gnd : : : : : -- -GND : AA39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3D : : -- -GND : AB3 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3D : : -- -VCCIO3D : AB8 : power : : 1.8V : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3D : : -- -GND : AB13 : gnd : : : : : -- -VCC : AB14 : power : : 0.9V : : : -- -VCC : AB15 : power : : 0.9V : : : -- -VCC : AB16 : power : : 0.9V : : : -- -VCC : AB17 : power : : 0.9V : : : -- -GND : AB18 : gnd : : : : : -- -VCC : AB19 : power : : 0.9V : : : -- -VCC : AB20 : power : : 0.9V : : : -- -VCC : AB21 : power : : 0.9V : : : -- -VCC : AB22 : power : : 0.9V : : : -- -GND : AB23 : gnd : : : : : -- -VCC : AB24 : power : : 0.9V : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 2I : : -- -GND : AB28 : gnd : : : : : -- -GND : AB29 : gnd : : : : : -- -GXB_GND* : AB30 : : : : 1E : : -- -GXB_GND* : AB31 : : : : 1E : : -- -GND : AB32 : gnd : : : : : -- -GND : AB33 : gnd : : : : : -- -GXB_GND* : AB34 : : : : 1E : : -- -GXB_GND* : AB35 : : : : 1E : : -- -GND : AB36 : gnd : : : : : -- -GND : AB37 : gnd : : : : : -- -GXB_NC : AB38 : : : : 1E : : -- -GXB_NC : AB39 : : : : 1E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 3D : : -- -GND : AC5 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC6 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3C : : -- -VCCIO3C : AC10 : power : : 1.8V : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3C : : -- -VREFB3CN0 : AC13 : power : : : 3C : : -- -VCCPT : AC14 : power : : 1.8V : : : -- -GND : AC15 : gnd : : : : : -- -VCCPT : AC16 : power : : 1.8V : : : -- -VCC : AC17 : power : : 0.9V : : : -- -VCC : AC18 : power : : 0.9V : : : -- -VCCPT : AC19 : power : : 1.8V : : : -- -GND : AC20 : gnd : : : : : -- -VCCPT : AC21 : power : : 1.8V : : : -- -VCC : AC22 : power : : 0.9V : : : -- -VCCPT : AC23 : power : : 1.8V : : : -- -VCCPT : AC24 : power : : 1.8V : : : -- -VCCIO2I : AC25 : power : : 1.8V : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 2I : : -- -GND : AC29 : gnd : : : : : -- -VCCR_GXBL1E : AC30 : power : : 0.95V : : : -- -VCCR_GXBL1E : AC31 : power : : 0.95V : : : -- -GXB_GND* : AC32 : : : : 1E : : -- -GXB_GND* : AC33 : : : : 1E : : -- -GND : AC34 : gnd : : : : : -- -GND : AC35 : gnd : : : : : -- -GXB_GND* : AC36 : : : : 1E : : -- -GXB_GND* : AC37 : : : : 1E : : -- -GND : AC38 : gnd : : : : : -- -GND : AC39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 3D : : -- -GND : AD2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3C : : -- -VCCIO3C : AD7 : power : : 1.8V : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3C : : -- -GND : AD12 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 3C : : -- -VCC : AD14 : power : : 0.9V : : : -- -DNU : AD15 : : : : : : -- -DNU : AD16 : : : : : : -- -GND : AD17 : gnd : : : : : -- -VCC : AD18 : power : : 0.9V : : : -- -VCC : AD19 : power : : 0.9V : : : -- -VCC : AD20 : power : : 0.9V : : : -- -VCC : AD21 : power : : 0.9V : : : -- -GND : AD22 : gnd : : : : : -- -VCC : AD23 : power : : 0.9V : : : -- -VCC : AD24 : power : : 0.9V : : : -- -SRC_DP_HPD : AD25 : bidir : 1.8 V : : 2I : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 2I : : -- -VCCIO2I : AD27 : power : : 1.8V : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 2I : : -- -GND : AD29 : gnd : : : : : -- -GXB_GND* : AD30 : : : : 1E : : -- -GXB_GND* : AD31 : : : : 1E : : -- -GND : AD32 : gnd : : : : : -- -GND : AD33 : gnd : : : : : -- -GXB_GND* : AD34 : : : : 1E : : -- -GXB_GND* : AD35 : : : : 1E : : -- -GND : AD36 : gnd : : : : : -- -GND : AD37 : gnd : : : : : -- -GXB_NC : AD38 : : : : 1E : : -- -GXB_NC : AD39 : : : : 1E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 3D : : -- -GND : AE4 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3C : : -- -GND : AE9 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3B : : -- -VREFB3BN0 : AE13 : power : : : 3B : : -- -GND : AE14 : gnd : : : : : -- -DNU : AE15 : : : : : : -- -GNDSENSE : AE16 : : : : : : -- -VCCLSENSE : AE17 : : : : : : -- -VCC : AE18 : power : : 0.9V : : : -- -GND : AE19 : gnd : : : : : -- -VCC : AE20 : power : : 0.9V : : : -- -VCC : AE21 : power : : 0.9V : : : -- -VCC : AE22 : power : : 0.9V : : : -- -VCC : AE23 : power : : 0.9V : : : -- -GND : AE24 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 2I : : -- -GND : AE28 : gnd : : : : : -- -VCCH_GXBL : AE29 : power : : 1.8V : : : -- -VCCT_GXBL1D : AE30 : power : : 0.95V : : : -- -VCCT_GXBL1D : AE31 : power : : 0.95V : : : -- -GXB_GND* : AE32 : : : : 1D : : -- -GXB_GND* : AE33 : : : : 1D : : -- -GND : AE34 : gnd : : : : : -- -GND : AE35 : gnd : : : : : -- -GXB_NC : AE36 : : : : 1E : : -- -GXB_NC : AE37 : : : : 1E : : -- -GND : AE38 : gnd : : : : : -- -GND : AE39 : gnd : : : : : -- -GND : AF1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3C : : -- -VCCIO3C : AF6 : power : : 1.8V : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3B : : -- -VCCIO3B : AF11 : power : : 1.8V : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B : : -- -VCC : AF14 : power : : 0.9V : : : -- -VCCP : AF15 : power : : 0.9V : : : -- -GND : AF16 : gnd : : : : : -- -VCC : AF17 : power : : 0.9V : : : -- -VCC : AF18 : power : : 0.9V : : : -- -VCC : AF19 : power : : 0.9V : : : -- -VCC : AF20 : power : : 0.9V : : : -- -GND : AF21 : gnd : : : : : -- -VCC : AF22 : power : : 0.9V : : : -- -VCC : AF23 : power : : 0.9V : : : -- -VCC : AF24 : power : : 0.9V : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 2I : : -- -VCCIO2I : AF26 : power : : 1.8V : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AF28 : : : : 2I : : -- -GND : AF29 : gnd : : : : : -- -GXB_GND* : AF30 : : : : 1D : : -- -GXB_GND* : AF31 : : : : 1D : : -- -GND : AF32 : gnd : : : : : -- -GND : AF33 : gnd : : : : : -- -GXB_GND* : AF34 : : : : 1D : : -- -GXB_GND* : AF35 : : : : 1D : : -- -GND : AF36 : gnd : : : : : -- -GND : AF37 : gnd : : : : : -- -GXB_NC : AF38 : : : : 1E : : -- -GXB_NC : AF39 : : : : 1E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3C : : -- -GND : AG3 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3C : : -- -GND : AG8 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG9 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B : : -- -GND : AG13 : gnd : : : : : -- -VREFB3AN0 : AG14 : power : : : 3A : : -- -VCCP : AG15 : power : : 0.9V : : : -- -VCCBAT : AG16 : power : : 1.8V : : : -- -VCCPGM : AG17 : power : : 1.8V : : : -- -GND : AG18 : gnd : : : : : -- -VCCP : AG19 : power : : 0.9V : : : -- -VCCP : AG20 : power : : 0.9V : : : -- -VCC : AG21 : power : : 0.9V : : : -- -VCCP : AG22 : power : : 0.9V : : : -- -GND : AG23 : gnd : : : : : -- -VCCP : AG24 : power : : 0.9V : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 2I : : -- -USBFX3_OTG_ID : AG26 : bidir : 1.8 V : : 2I : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AG27 : : : : 2I : : -- -GND : AG28 : gnd : : : : : -- -GND : AG29 : gnd : : : : : -- -VCCR_GXBL1D : AG30 : power : : 0.95V : : : -- -VCCR_GXBL1D : AG31 : power : : 0.95V : : : -- -GXB_GND* : AG32 : : : : 1D : : -- -GXB_GND* : AG33 : : : : 1D : : -- -GND : AG34 : gnd : : : : : -- -GND : AG35 : gnd : : : : : -- -GXB_NC : AG36 : : : : 1E : : -- -GXB_NC : AG37 : : : : 1E : : -- -GND : AG38 : gnd : : : : : -- -GND : AG39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH1 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3C : : -- -GND : AH5 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B : : -- -VCCIO3B : AH10 : power : : 1.8V : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3A : : -- -GND : AH15 : gnd : : : : : -- -FMC_HB_n[11] : AH16 : bidir : 1.8 V : : 2A : Y : -- -VCCPGM : AH17 : power : : 1.8V : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 2A : : -- -VREFB2AN0 : AH19 : power : : : 2A : : -- -GND : AH20 : gnd : : : : : -- -SMA_CLKIN_p(n) : AH21 : input : LVDS : : 2G : N : -- -VREFB2GN0 : AH22 : power : : : 2G : : -- -USBFX3_DQ[29] : AH23 : bidir : 1.8 V : : 2H : Y : -- -VREFB2HN0 : AH24 : power : : : 2H : : -- -GND : AH25 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 2I : : -- -I2C_INT : AH27 : bidir : 1.8 V : : 2I : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AH28 : : : : 2I : : -- -GND : AH29 : gnd : : : : : -- -GXB_GND* : AH30 : : : : 1D : : -- -GXB_GND* : AH31 : : : : 1D : : -- -GND : AH32 : gnd : : : : : -- -GND : AH33 : gnd : : : : : -- -GXB_GND* : AH34 : : : : 1D : : -- -GXB_GND* : AH35 : : : : 1D : : -- -GND : AH36 : gnd : : : : : -- -GND : AH37 : gnd : : : : : -- -GXB_NC : AH38 : : : : 1D : : -- -GXB_NC : AH39 : : : : 1D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3C : : -- -GND : AJ2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ3 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3C : : -- -GND : AJ7 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ8 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3A : : -- -VCCIO3A : AJ12 : power : : 1.8V : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ13 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3A : : -- -GND : AJ15 : : : : CSS : : -- -FMC_HB_p[11] : AJ16 : bidir : 1.8 V : : 2A : Y : -- -GND : AJ17 : gnd : : : : : -- -CLKUSR_100 : AJ18 : input : 1.8 V : : 2A : Y : -- -SW[0] : AJ19 : input : 1.8 V : : 2A : Y : -- -ETH_MDIO : AJ20 : bidir : 1.8 V : : 2G : Y : -- -SMA_CLKIN_p : AJ21 : input : LVDS : : 2G : Y : -- -GND : AJ22 : gnd : : : : : -- -USBFX3_DQ[28] : AJ23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_RESET_n : AJ24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[27] : AJ25 : bidir : 1.8 V : : 2H : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 2I : : -- -GND : AJ27 : gnd : : : : : -- -GND : AJ28 : gnd : : : : : -- -VCCH_GXBL : AJ29 : power : : 1.8V : : : -- -VCCT_GXBL1C : AJ30 : power : : 0.95V : : : -- -VCCT_GXBL1C : AJ31 : power : : 0.95V : : : -- -GXB_GND* : AJ32 : : : : 1D : : -- -GXB_GND* : AJ33 : : : : 1D : : -- -GND : AJ34 : gnd : : : : : -- -GND : AJ35 : gnd : : : : : -- -GXB_NC : AJ36 : : : : 1D : : -- -GXB_NC : AJ37 : : : : 1D : : -- -GND : AJ38 : gnd : : : : : -- -GND : AJ39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK1 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3C : : -- -GND : AK4 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK5 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B : : -- -VCCIO3B : AK9 : power : : 1.8V : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK10 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3A : : -- -GND : AK14 : gnd : : : : : -- -nIO_PULLUP : AK15 : input : : : CSS : : -- -FMC_HB_p[15] : AK16 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[15] : AK17 : bidir : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 2A : : -- -VCCIO2A : AK19 : power : : 1.8V : 2A : : -- -ETH_RST_n : AK20 : output : 1.8 V : : 2G : Y : -- -CDCM6208_SCL : AK21 : bidir : 1.8 V : : 2G : Y : -- -CDCM6208_SDA : AK22 : bidir : 1.8 V : : 2G : Y : -- -USBFX3_DQ[26] : AK23 : bidir : 1.8 V : : 2H : Y : -- -VCCIO2H : AK24 : power : : 1.8V : 2H : : -- -USBFX3_DQ[18] : AK25 : bidir : 1.8 V : : 2H : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 2I : : -- -HEX1_D[5] : AK27 : output : 1.8 V : : 2I : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 2I : : -- -GND : AK29 : gnd : : : : : -- -GXB_GND* : AK30 : : : : 1C : : -- -GXB_GND* : AK31 : : : : 1C : : -- -GND : AK32 : gnd : : : : : -- -GND : AK33 : gnd : : : : : -- -GXB_GND* : AK34 : : : : 1D : : -- -GXB_GND* : AK35 : : : : 1D : : -- -GND : AK36 : gnd : : : : : -- -GND : AK37 : gnd : : : : : -- -GXB_NC : AK38 : : : : 1D : : -- -GXB_NC : AK39 : : : : 1D : : -- -GND : AL1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL2 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL3 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL4 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL5 : : : : 3B : : -- -GND : AL6 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL7 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL8 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL9 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL10 : : : : 3A : : -- -VCCIO3A : AL11 : power : : 1.8V : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL12 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL13 : : : : 3A : : -- -altera_reserved_tck : AL14 : input : 1.8 V : : CSS : N : -- -GND : AL15 : : : : CSS : : -- -VCCIO2A : AL16 : power : : 1.8V : 2A : : -- -FMC_HB_n[10] : AL17 : bidir : 1.8 V : : 2A : Y : -- -FMC_GA[1] : AL18 : bidir : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL19 : : : : 2A : : -- -ETH_RX_p(n) : AL20 : input : LVDS : : 2G : N : -- -VCCIO2G : AL21 : power : : 1.8V : 2G : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL22 : : : : 2G : : -- -USBFX3_DQ[16] : AL23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL6 : AL24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL7_PKTEND_n : AL25 : bidir : 1.8 V : : 2H : Y : -- -GND : AL26 : gnd : : : : : -- -HEX1_D[4] : AL27 : output : 1.8 V : : 2I : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AL28 : : : : 2I : : -- -GND : AL29 : gnd : : : : : -- -VCCR_GXBL1C : AL30 : power : : 0.95V : : : -- -VCCR_GXBL1C : AL31 : power : : 0.95V : : : -- -GXB_GND* : AL32 : : : : 1C : : -- -GXB_GND* : AL33 : : : : 1C : : -- -GND : AL34 : gnd : : : : : -- -GND : AL35 : gnd : : : : : -- -GXB_NC : AL36 : : : : 1D : : -- -GXB_NC : AL37 : : : : 1D : : -- -GND : AL38 : gnd : : : : : -- -GND : AL39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM1 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM2 : : : : 3C : : -- -GND : AM3 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM4 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM5 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM6 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM7 : : : : 3B : : -- -GND : AM8 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM9 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM10 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM11 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM12 : : : : 3A : : -- -VCCIO3A : AM13 : power : : 1.8V : 3A : : -- -MSEL0 : AM14 : input : : : CSS : : -- -FMC_HB_p[18] : AM15 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[18] : AM16 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_p[10] : AM17 : bidir : 1.8 V : : 2A : Y : -- -VCCIO2A : AM18 : power : : 1.8V : 2A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM19 : : : : 2A : : -- -ETH_RX_p : AM20 : input : LVDS : : 2G : Y : -- -SMA_CLKOUT_p(n) : AM21 : output : LVDS : : 2G : N : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AM22 : : : : 2G : : -- -VCCIO2H : AM23 : power : : 1.8V : 2H : : -- -USBFX3_DQ[17] : AM24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[19] : AM25 : bidir : 1.8 V : : 2H : Y : -- -HEX1_D[6] : AM26 : output : 1.8 V : : 2I : Y : -- -HEX1_D[3] : AM27 : output : 1.8 V : : 2I : Y : -- -GND : AM28 : gnd : : : : : -- -GND : AM29 : gnd : : : : : -- -GXB_GND* : AM30 : : : : 1C : : -- -GXB_GND* : AM31 : : : : 1C : : -- -GND : AM32 : gnd : : : : : -- -GND : AM33 : gnd : : : : : -- -GXB_GND* : AM34 : : : : 1C : : -- -GXB_GND* : AM35 : : : : 1C : : -- -GND : AM36 : gnd : : : : : -- -GND : AM37 : gnd : : : : : -- -GXB_NC : AM38 : : : : 1D : : -- -GXB_NC : AM39 : : : : 1D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN1 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN2 : : : : 3C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN3 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN4 : : : : 3B : : -- -GND : AN5 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN6 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN7 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN8 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN9 : : : : 3A : : -- -GND : AN10 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN11 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN12 : : : : 3A : : -- -nCE : AN13 : : : : CSS : : -- -MSEL2 : AN14 : input : : : CSS : : -- -GND : AN15 : gnd : : : : : -- -FMC_HB_n[20] : AN16 : bidir : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN17 : : : : 2A : : -- -CPU_RESET_n : AN18 : input : 1.8 V : : 2A : Y : -- -ETH_TX_p(n) : AN19 : output : LVDS : : 2G : N : -- -VCCIO2G : AN20 : power : : 1.8V : 2G : : -- -SMA_CLKOUT_p : AN21 : output : LVDS : : 2G : Y : -- -USBFX3_CTL4_FLAGA : AN22 : bidir : 1.8 V : : 2G : Y : -- -USBFX3_CTL5_FLAGB : AN23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[24] : AN24 : bidir : 1.8 V : : 2H : Y : -- -VCCIO2H : AN25 : power : : 1.8V : 2H : : -- -USBFX3_DQ[25] : AN26 : bidir : 1.8 V : : 2H : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN27 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AN28 : : : : 2I : : -- -GND : AN29 : gnd : : : : : -- -GND : AN30 : gnd : : : : : -- -GND : AN31 : gnd : : : : : -- -GXB_GND* : AN32 : : : : 1C : : -- -GXB_GND* : AN33 : : : : 1C : : -- -GND : AN34 : gnd : : : : : -- -GND : AN35 : gnd : : : : : -- -GXB_NC : AN36 : : : : 1D : : -- -GXB_NC : AN37 : : : : 1D : : -- -GND : AN38 : gnd : : : : : -- -GND : AN39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP1 : : : : 3B : : -- -GND : AP2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP3 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP4 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP5 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP6 : : : : 3B : : -- -GND : AP7 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP8 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP9 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP10 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP11 : : : : 3A : : -- -GND : AP12 : gnd : : : : : -- -MSEL1 : AP13 : input : : : CSS : : -- -FMC_HB_p[14] : AP14 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[14] : AP15 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_p[20] : AP16 : bidir : 1.8 V : : 2A : Y : -- -GND : AP17 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP18 : : : : 2A : : -- -ETH_TX_p : AP19 : output : LVDS : : 2G : Y : -- -USBFX3_DQ[31] : AP20 : bidir : 1.8 V : : 2G : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP21 : : : : 2G : : -- -VCCIO2G : AP22 : power : : 1.8V : 2G : : -- -USBFX3_UART_TX : AP23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[15] : AP24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[23] : AP25 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[22] : AP26 : bidir : 1.8 V : : 2H : Y : -- -GND : AP27 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP28 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP29 : : : : 2I : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AP30 : : : : 2I : : -- -GND : AP31 : gnd : : : : : -- -GND : AP32 : gnd : : : : : -- -GND : AP33 : gnd : : : : : -- -GXB_GND* : AP34 : : : : 1C : : -- -GXB_GND* : AP35 : : : : 1C : : -- -GND : AP36 : gnd : : : : : -- -GND : AP37 : gnd : : : : : -- -GXB_NC : AP38 : : : : 1C : : -- -GXB_NC : AP39 : : : : 1C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR1 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR2 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR3 : : : : 3B : : -- -GND : AR4 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR5 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR6 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR7 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR8 : : : : 3A : : -- -GND : AR9 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR10 : : : : 3A : : -- -altera_reserved_tdo : AR11 : output : 1.8 V : : CSS : N : -- -altera_reserved_tdi : AR12 : input : 1.8 V : : CSS : N : -- -AS_DATA1 : AR13 : : : : CSS : : -- -GND : AR14 : gnd : : : : : -- -FMC_HB_p[19] : AR15 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[19] : AR16 : bidir : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR17 : : : : 2A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR18 : : : : 2A : : -- -GND : AR19 : gnd : : : : : -- -USBFX3_DQ[30] : AR20 : bidir : 1.8 V : : 2G : Y : -- -REFCLK1_SDA : AR21 : bidir : 1.8 V : : 2G : Y : -- -REFCLK1_SCL : AR22 : bidir : 1.8 V : : 2G : Y : -- -CLK_50_B2H : AR23 : input : 1.8 V : : 2H : Y : -- -GND : AR24 : gnd : : : : : -- -USBFX3_DQ[14] : AR25 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[21] : AR26 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL3_SLRD_n : AR27 : bidir : 1.8 V : : 2H : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AR28 : : : : 2I : : -- -GND : AR29 : gnd : : : : : -- -HEX1_D[2] : AR30 : output : 1.8 V : : 2I : Y : -- -HEX1_DP : AR31 : output : 1.8 V : : 2I : Y : -- -HEX0_D[1] : AR32 : output : 1.8 V : : 2I : Y : -- -GND : AR33 : gnd : : : : : -- -GND : AR34 : gnd : : : : : -- -GND : AR35 : gnd : : : : : -- -GXB_NC : AR36 : : : : 1C : : -- -GXB_NC : AR37 : : : : 1C : : -- -GND : AR38 : gnd : : : : : -- -GND : AR39 : gnd : : : : : -- -GND : AT1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT2 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT3 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT4 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT5 : : : : 3A : : -- -GND : AT6 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT7 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT8 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AT9 : : : : 3A : : -- -nCONFIG : AT10 : input : : : CSS : : -- -GND : AT11 : gnd : : : : : -- -AS_DATA0, ASDO : AT12 : : : : CSS : : -- -FMC_HB_p[9] : AT13 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[9] : AT14 : bidir : 1.8 V : : 2A : Y : -- -KEY[1] : AT15 : input : 1.8 V : : 2A : Y : -- -GND : AT16 : gnd : : : : : -- -FMC_HB_p[17] : AT17 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[17] : AT18 : bidir : 1.8 V : : 2A : Y : -- -ETH_MDC : AT19 : output : 1.8 V : : 2G : Y : -- -REFCLK0_SDA : AT20 : bidir : 1.8 V : : 2G : Y : -- -GND : AT21 : gnd : : : : : -- -USBFX3_CTL1_SLWR_n : AT22 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL12_A0 : AT23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[20] : AT24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL2_SLOE_n : AT25 : bidir : 1.8 V : : 2H : Y : -- -GND : AT26 : gnd : : : : : -- -USBFX3_PCLK : AT27 : bidir : 1.8 V : : 2H : Y : -- -HEX1_D[0] : AT28 : output : 1.8 V : : 2I : Y : -- -HEX1_D[1] : AT29 : output : 1.8 V : : 2I : Y : -- -HEX0_D[4] : AT30 : output : 1.8 V : : 2I : Y : -- -GND : AT31 : gnd : : : : : -- -HEX0_D[0] : AT32 : output : 1.8 V : : 2I : Y : -- -GND : AT33 : gnd : : : : : -- -GXB_GND* : AT34 : : : : 1C : : -- -GXB_GND* : AT35 : : : : 1C : : -- -GND : AT36 : gnd : : : : : -- -GND : AT37 : gnd : : : : : -- -GXB_NC : AT38 : : : : 1C : : -- -GXB_NC : AT39 : : : : 1C : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU1 : : : : 3B : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU2 : : : : 3B : : -- -GND : AU3 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU4 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU5 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU6 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AU7 : : : : 3A : : -- -GND : AU8 : gnd : : : : : -- -altera_reserved_ntrst : AU9 : input : 1.8 V : : CSS : N : -- -CONF_DONE : AU10 : bidir : : : CSS : : -- -nCSO1 : AU11 : : : : CSS : : -- -altera_reserved_tms : AU12 : input : 1.8 V : : CSS : N : -- -GND : AU13 : gnd : : : : : -- -FMC_HB_n[13] : AU14 : bidir : 1.8 V : : 2A : Y : -- -KEY[0] : AU15 : input : 1.8 V : : 2A : Y : -- -FMC_HB_p[16] : AU16 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[16] : AU17 : bidir : 1.8 V : : 2A : Y : -- -GND : AU18 : gnd : : : : : -- -ETH_INT_n : AU19 : input : 1.8 V : : 2G : Y : -- -REFCLK0_SCL : AU20 : bidir : 1.8 V : : 2G : Y : -- -USBFX3_DQ[0] : AU21 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL11_A1 : AU22 : input : 1.8 V : : 2H : Y : -- -GND : AU23 : gnd : : : : : -- -USBFX3_CTL10 : AU24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[13] : AU25 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[11] : AU26 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_UART_RX : AU27 : bidir : 1.8 V : : 2H : Y : -- -GND : AU28 : gnd : : : : : -- -HEX0_D[5] : AU29 : output : 1.8 V : : 2I : Y : -- -HEX0_D[3] : AU30 : output : 1.8 V : : 2I : Y : -- -HEX0_DP : AU31 : output : 1.8 V : : 2I : Y : -- -HEX0_D[2] : AU32 : output : 1.8 V : : 2I : Y : -- -GND : AU33 : gnd : : : : : -- -GND : AU34 : gnd : : : : : -- -GND : AU35 : gnd : : : : : -- -GXB_NC : AU36 : : : : 1C : : -- -GXB_NC : AU37 : : : : 1C : : -- -GND : AU38 : gnd : : : : : -- -GND : AU39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV1 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV2 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV3 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV4 : : : : 3A : : -- -GND : AV5 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV6 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV7 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AV8 : : : : 3A : : -- -nSTATUS : AV9 : : : : CSS : : -- -GND : AV10 : gnd : : : : : -- -AS_DATA2 : AV11 : : : : CSS : : -- -AS_DATA3 : AV12 : : : : CSS : : -- -FMC_HB_n[12] : AV13 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_p[13] : AV14 : bidir : 1.8 V : : 2A : Y : -- -GND : AV15 : gnd : : : : : -- -SW[1] : AV16 : input : 1.8 V : : 2A : Y : -- -FMC_CLK2_BIDIR_n : AV17 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_p[21] : AV18 : bidir : 1.8 V : : 2A : Y : -- -FMC_HB_n[21] : AV19 : bidir : 1.8 V : : 2A : Y : -- -GND : AV20 : gnd : : : : : -- -USBFX3_CTL8 : AV21 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_CTL9 : AV22 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[12] : AV23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[5] : AV24 : bidir : 1.8 V : : 2H : Y : -- -GND : AV25 : gnd : : : : : -- -USBFX3_CTL0_SLCS_n : AV26 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[9] : AV27 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[10] : AV28 : bidir : 1.8 V : : 2H : Y : -- -HEX0_D[6] : AV29 : output : 1.8 V : : 2I : Y : -- -GND : AV30 : gnd : : : : : -- -DNU : AV31 : : : : : : -- -DNU : AV32 : : : : : : -- -GND : AV33 : gnd : : : : : -- -GXB_GND* : AV34 : : : : 1C : : -- -GXB_GND* : AV35 : : : : 1C : : -- -GND : AV36 : gnd : : : : : -- -GND : AV37 : gnd : : : : : -- -GXB_NC : AV38 : : : : 1C : : -- -GXB_NC : AV39 : : : : 1C : : -- -GND : AW2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW3 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW4 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW5 : : : : 3A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW6 : : : : 3A : : -- -GND : AW7 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW8 : : : : 3A : : -- -nCSO0 : AW9 : : : : CSS : : -- -nCSO2 : AW10 : : : : CSS : : -- -DCLK : AW11 : bidir : : : CSS : : -- -GND : AW12 : gnd : : : : : -- -FMC_HB_p[12] : AW13 : bidir : 1.8 V : : 2A : Y : -- -FMC_CLK_M2C_p[1] : AW14 : input : 1.8 V : : 2A : Y : -- -FMC_CLK_M2C_n[1] : AW15 : input : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW16 : : : : 2A : : -- -GND : AW17 : gnd : : : : : -- -FMC_CLK2_BIDIR_p : AW18 : bidir : 1.8 V : : 2A : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW19 : : : : 2A : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : AW20 : : : : 2A : : -- -USBFX3_CTL15_INT_n : AW21 : bidir : 1.8 V : : 2H : Y : -- -GND : AW22 : gnd : : : : : -- -USBFX3_DQ[1] : AW23 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[2] : AW24 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[3] : AW25 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[4] : AW26 : bidir : 1.8 V : : 2H : Y : -- -GND : AW27 : gnd : : : : : -- -USBFX3_DQ[6] : AW28 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[8] : AW29 : bidir : 1.8 V : : 2H : Y : -- -USBFX3_DQ[7] : AW30 : bidir : 1.8 V : : 2H : Y : -- -GND : AW31 : gnd : : : : : -- -RREF : AW32 : : : : : : -- -GND : AW33 : gnd : : : : : -- -GND : AW34 : gnd : : : : : -- -GND : AW35 : gnd : : : : : -- -GXB_NC : AW36 : : : : 1C : : -- -GXB_NC : AW37 : : : : 1C : : -- -GND : AW38 : gnd : : : : : -- -FMC_HB_p[8] : B1 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[7] : B2 : bidir : 1.8 V : : 3F : Y : -- -GND : B3 : gnd : : : : : -- -FMC_LA_p[1] : B4 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[12] : B5 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[11] : B6 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[14] : B7 : bidir : 1.8 V : : 3G : Y : -- -GND : B8 : gnd : : : : : -- -FMC_HA_n[16] : B9 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[12] : B10 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[18] : B11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[14] : B12 : bidir : 1.8 V : : 3H : Y : -- -GND : B13 : gnd : : : : : -- -TEMPDIODEn : B14 : : : : : : -- -TEMPDIODEp : B15 : : : : : : -- -DDR4H_DQ[9] : B16 : bidir : 1.2-V POD : : 2J : Y : 184ps -DDR4H_DQS[1] : B17 : bidir : Differential 1.2-V POD : : 2J : Y : 173ps -GND : B18 : gnd : : : : : -- -DDR4H_DQ[5] : B19 : bidir : 1.2-V POD : : 2J : Y : 178ps -DDR4H_DQS_n[0] : B20 : bidir : Differential 1.2-V POD : : 2J : Y : 182ps -DDR4H_DQ[1] : B21 : bidir : 1.2-V POD : : 2J : Y : 179ps -RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 2J : : -- -GND : B23 : gnd : : : : : -- -LED[1] : B24 : output : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : B27 : : : : 2L : : -- -GND : B28 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : B29 : : : : 2L : : -- -HPS_I2C0_SCLK : B30 : bidir : 1.8 V : : 2L : Y : -- -GND : B31 : gnd : : : : : -- -GND : B32 : gnd : : : : : -- -GND : B33 : gnd : : : : : -- -GXB_GND* : B34 : : : : 1H : : -- -GXB_GND* : B35 : : : : 1H : : -- -GND : B36 : gnd : : : : : -- -GND : B37 : gnd : : : : : -- -GXB_NC : B38 : : : : 1H : : -- -GXB_NC : B39 : : : : 1H : : -- -FMC_CLK3_BIDIR_p : C1 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[8] : C2 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[1] : C3 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[21] : C4 : bidir : 1.8 V : : 3G : Y : -- -GND : C5 : gnd : : : : : -- -FMC_LA_n[11] : C6 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[14] : C7 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_p[22] : C8 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[21] : C9 : bidir : 1.8 V : : 3H : Y : -- -GND : C10 : gnd : : : : : -- -FMC_HA_n[18] : C11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[17] : C12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[17] : C13 : bidir : 1.8 V : : 3H : Y : -- -ADCGND : C14 : gnd : : : : : -- -GND : C15 : gnd : : : : : -- -DDR4H_DQ[23] : C16 : bidir : 1.2-V POD : : 2J : Y : 162ps -DDR4H_DQS_n[1] : C17 : bidir : Differential 1.2-V POD : : 2J : Y : 174ps -DDR4H_DQ[8] : C18 : bidir : 1.2-V POD : : 2J : Y : 168ps -DDR4H_DQ[0] : C19 : bidir : 1.2-V POD : : 2J : Y : 158ps -GND : C20 : gnd : : : : : -- -DDR4H_DQ[2] : C21 : bidir : 1.2-V POD : : 2J : Y : 174ps -DDR4H_DQ[29] : C22 : bidir : 1.2-V POD : : 2J : Y : 174ps -HPS_GPIO[1] : C23 : bidir : 1.8 V : : HPS : Y : -- -HPS_ENET_MDIO : C24 : bidir : 1.8 V : : 2L : Y : -- -GND : C25 : gnd : : : : : -- -LED[0] : C26 : output : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 2L : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 2L : : -- -GND : C30 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : C31 : : : : 2K : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : C32 : : : : 2K : : -- -GND : C33 : gnd : : : : : -- -GND : C34 : gnd : : : : : -- -GND : C35 : gnd : : : : : -- -FMC_DP_C2M_p[9](n) : C36 : output : High Speed Differential I/O : : 1H : N : -- -FMC_DP_C2M_p[9] : C37 : output : High Speed Differential I/O : : 1H : Y : -- -GND : C38 : gnd : : : : : -- -GND : C39 : gnd : : : : : -- -FMC_CLK3_BIDIR_n : D1 : bidir : 1.8 V : : 3F : Y : -- -GND : D2 : gnd : : : : : -- -FMC_HB_p[6] : D3 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[21] : D4 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[13] : D5 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[13] : D6 : bidir : 1.8 V : : 3G : Y : -- -GND : D7 : gnd : : : : : -- -FMC_HA_n[22] : D8 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[21] : D9 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[2] : D10 : bidir : 1.8 V : : 3H : Y : -- -CLK_50_B3H : D11 : input : 1.8 V : : 3H : Y : -- -GND : D12 : gnd : : : : : -- -FMC_HA_p[10] : D13 : bidir : 1.8 V : : 3H : Y : -- -VSIGP_0 : D14 : : : : : : -- -VSIGN_0 : D15 : : : : : : -- -DDR4H_DBI_n[2] : D16 : bidir : 1.2-V POD : : 2J : Y : 160ps -GND : D17 : gnd : : : : : -- -DDR4H_DQ[10] : D18 : bidir : 1.2-V POD : : 2J : Y : 173ps -DDR4H_DQ[4] : D19 : bidir : 1.2-V POD : : 2J : Y : 160ps -DDR4H_DQ[31] : D20 : bidir : 1.2-V POD : : 2J : Y : 137ps -DDR4H_DQ[25] : D21 : bidir : 1.2-V POD : : 2J : Y : 153ps -GND : D22 : gnd : : : : : -- -HPS_GPIO[0] : D23 : bidir : 1.8 V : : HPS : Y : -- -HPS_ENET_MDC : D24 : output : 1.8 V : : 2L : Y : -- -PM_ALERT_n : D25 : input : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 2L : : -- -GND : D27 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 2L : : -- -HPS_LED : D29 : bidir : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 2K : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : D31 : : : : 2K : : -- -GND : D32 : gnd : : : : : -- -GND : D33 : gnd : : : : : -- -GXB_GND* : D34 : : : : 1H : : -- -GXB_GND* : D35 : : : : 1H : : -- -GND : D36 : gnd : : : : : -- -GND : D37 : gnd : : : : : -- -FMC_DP_C2M_p[8](n) : D38 : output : High Speed Differential I/O : : 1H : N : -- -FMC_DP_C2M_p[8] : D39 : output : High Speed Differential I/O : : 1H : Y : -- -FMC_HB_p[0] : E1 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[0] : E2 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[6] : E3 : bidir : 1.8 V : : 3F : Y : -- -GND : E4 : gnd : : : : : -- -FMC_LA_p[16] : E5 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[15] : E6 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[15] : E7 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[10] : E8 : bidir : 1.8 V : : 3G : Y : -- -GND : E9 : gnd : : : : : -- -FMC_HA_n[2] : E10 : bidir : 1.8 V : : 3H : Y : -- -FMC_GA[0] : E11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[3] : E12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[10] : E13 : bidir : 1.8 V : : 3H : Y : -- -GND : E14 : gnd : : : : : -- -VSIGP_1 : E15 : : : : : : -- -VSIGN_1 : E16 : : : : : : -- -DDR4H_DQ[11] : E17 : bidir : 1.2-V POD : : 2J : Y : 153ps -DDR4H_DBI_n[1] : E18 : bidir : 1.2-V POD : : 2J : Y : 150ps -GND : E19 : gnd : : : : : -- -DDR4H_DBI_n[3] : E20 : bidir : 1.2-V POD : : 2J : Y : 145ps -DDR4H_DQ[28] : E21 : bidir : 1.2-V POD : : 2J : Y : 158ps -HPS_CLK1 : E22 : : : : HPS : : -- -HPS_DIO[3] : E23 : bidir : 1.8 V : : HPS : Y : -- -GND : E24 : gnd : : : : : -- -FAN_ALERT_n : E25 : input : 1.8 V : : 2L : Y : -- -MPU_INT : E26 : bidir : 1.8 V : : 2L : Y : -- -HPS_USB_DATA[2] : E27 : bidir : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 2K : : -- -GND : E29 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : E30 : : : : 2K : : -- -DDR4H_BG[0] : E31 : output : SSTL-12 : : 2K : Y : 175ps -DDR4H_BA[1] : E32 : output : SSTL-12 : : 2K : Y : 176ps -GND : E33 : gnd : : : : : -- -GND : E34 : gnd : : : : : -- -GND : E35 : gnd : : : : : -- -FMC_DP_C2M_p[7](n) : E36 : output : High Speed Differential I/O : : 1H : N : -- -FMC_DP_C2M_p[7] : E37 : output : High Speed Differential I/O : : 1H : Y : -- -GND : E38 : gnd : : : : : -- -GND : E39 : gnd : : : : : -- -GND : F1 : gnd : : : : : -- -FMC_LA_p[25] : F2 : bidir : 1.8 V : : 3F : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 3F : : -- -FMC_SDA : F4 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[16] : F5 : bidir : 1.8 V : : 3G : Y : -- -GND : F6 : gnd : : : : : -- -FMC_LA_p[20] : F7 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[10] : F8 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[17] : F9 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_p[20] : F10 : bidir : 1.8 V : : 3H : Y : -- -GND : F11 : gnd : : : : : -- -FMC_HA_n[3] : F12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[9] : F13 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[9] : F14 : bidir : 1.8 V : : 3H : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 2J : : -- -VCCIO2J : F16 : power : : 1.2V : 2J : : -- -DDR4H_DQ[26] : F17 : bidir : 1.2-V POD : : 2J : Y : 125ps -DDR4H_DQS[3] : F18 : bidir : Differential 1.2-V POD : : 2J : Y : 127ps -DDR4H_DQS_n[3] : F19 : bidir : Differential 1.2-V POD : : 2J : Y : 133ps -DDR4H_DQ[24] : F20 : bidir : 1.2-V POD : : 2J : Y : 133ps -GND : F21 : gnd : : : : : -- -HPS_DIO[1] : F22 : bidir : 1.8 V : : HPS : Y : -- -HPS_GPIO[2] : F23 : bidir : 1.8 V : : HPS : Y : -- -HPS_ENET_RX_DATA[2] : F24 : input : 1.8 V : : 2L : Y : -- -HPS_ENET_GTX_CLK : F25 : output : 1.8 V : : 2L : Y : -- -GND : F26 : gnd : : : : : -- -HPS_USB_DATA[3] : F27 : bidir : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 2K : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 2K : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 2K : : -- -GND : F31 : gnd : : : : : -- -GND : F32 : gnd : : : : : -- -GND : F33 : gnd : : : : : -- -FMC_DP_M2C_p[8](n) : F34 : input : High Speed Differential I/O : : 1H : N : -- -FMC_DP_M2C_p[8] : F35 : input : High Speed Differential I/O : : 1H : Y : -- -GND : F36 : gnd : : : : : -- -GND : F37 : gnd : : : : : -- -FMC_DP_C2M_p[6](n) : F38 : output : High Speed Differential I/O : : 1H : N : -- -FMC_DP_C2M_p[6] : F39 : output : High Speed Differential I/O : : 1H : Y : -- -FMC_LA_p[29] : G1 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[25] : G2 : bidir : 1.8 V : : 3F : Y : -- -GND : G3 : gnd : : : : : -- -FMC_HB_p[1] : G4 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_p[5] : G5 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[9] : G6 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[20] : G7 : bidir : 1.8 V : : 3G : Y : -- -VCCIO3G : G8 : power : : 1.8V : 3G : : -- -FMC_LA_n[17] : G9 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_n[20] : G10 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[23] : G11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[13] : G12 : bidir : 1.8 V : : 3H : Y : -- -VCCIO3H : G13 : power : : 1.8V : 3H : : -- -FMC_HA_p[11] : G14 : bidir : 1.8 V : : 3H : Y : -- -DDR4H_DQ[21] : G15 : bidir : 1.2-V POD : : 2J : Y : 149ps -DDR4H_DQ[17] : G16 : bidir : 1.2-V POD : : 2J : Y : 136ps -DDR4H_DQ[30] : G17 : bidir : 1.2-V POD : : 2J : Y : 127ps -GND : G18 : gnd : : : : : -- -DDR4H_DQ[6] : G19 : bidir : 1.2-V POD : : 2J : Y : 137ps -DDR4H_DQ[27] : G20 : bidir : 1.2-V POD : : 2J : Y : 136ps -HPS_DIO[4] : G21 : bidir : 1.8 V : : HPS : Y : -- -HPS_GPIO[3] : G22 : bidir : 1.8 V : : HPS : Y : -- -GND : G23 : gnd : : : : : -- -HPS_ENET_RX_DATA[3] : G24 : input : 1.8 V : : 2L : Y : -- -HPS_ENET_TX_EN : G25 : output : 1.8 V : : 2L : Y : -- -HPS_USB_DATA[1] : G26 : bidir : 1.8 V : : 2L : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 2K : : -- -GND : G28 : gnd : : : : : -- -DDR4H_A[13] : G29 : output : SSTL-12 : : 2K : Y : 179ps -RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 2K : : -- -GND : G31 : gnd : : : : : -- -FMC_DP_M2C_p[9](n) : G32 : input : High Speed Differential I/O : : 1H : N : -- -FMC_DP_M2C_p[9] : G33 : input : High Speed Differential I/O : : 1H : Y : -- -GND : G34 : gnd : : : : : -- -GND : G35 : gnd : : : : : -- -FMC_DP_C2M_p[5](n) : G36 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[5] : G37 : output : High Speed Differential I/O : : 1G : Y : -- -GND : G38 : gnd : : : : : -- -GND : G39 : gnd : : : : : -- -FMC_LA_n[29] : H1 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_p[4] : H2 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[4] : H3 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[1] : H4 : bidir : 1.8 V : : 3F : Y : -- -GND : H5 : gnd : : : : : -- -FMC_HB_n[5] : H6 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[9] : H7 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[6] : H8 : bidir : 1.8 V : : 3G : Y : -- -FMC_RZQ : H9 : input : 1.8 V : : 3G : Y : -- -GND : H10 : gnd : : : : : -- -FMC_HA_n[23] : H11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[13] : H12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[4] : H13 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[11] : H14 : bidir : 1.8 V : : 3H : Y : -- -VCCIO2J : H15 : power : : 1.2V : 2J : : -- -DDR4H_DQ[19] : H16 : bidir : 1.2-V POD : : 2J : Y : 137ps -DDR4H_DQ[18] : H17 : bidir : 1.2-V POD : : 2J : Y : 134ps -DDR4H_DBI_n[0] : H18 : bidir : 1.2-V POD : : 2J : Y : 129ps -GPIO2_IO7,NAND_ALE,QSPI_SS1,SPIM0_CLK,BOOTSEL0 : H19 : : : : HPS : : -- -GND : H20 : gnd : : : : : -- -HPS_DIO[5] : H21 : bidir : 1.8 V : : HPS : Y : -- -GPIO2_IO6,NAND_CLE,SDMMC_PWR_ENA,SPIM0_SS1_N,SPIS0_MISO,BOOTSEL1 : H22 : : : : HPS : : -- -HPS_ENET_RX_DATA[0] : H23 : input : 1.8 V : : 2L : Y : -- -HPS_ENET_TX_DATA[0] : H24 : output : 1.8 V : : 2L : Y : -- -VCCIO2L : H25 : power : : 1.8V : 2L : : -- -HPS_USB_NXT : H26 : input : 1.8 V : : 2L : Y : -- -DDR4H_BA[0] : H27 : output : SSTL-12 : : 2K : Y : 181ps -DDR4H_A[14] : H28 : output : SSTL-12 : : 2K : Y : 179ps -GND : H29 : gnd : : : : : -- -GND : H30 : gnd : : : : : -- -GND : H31 : gnd : : : : : -- -GND : H32 : gnd : : : : : -- -GND : H33 : gnd : : : : : -- -FMC_DP_M2C_p[6](n) : H34 : input : High Speed Differential I/O : : 1H : N : -- -FMC_DP_M2C_p[6] : H35 : input : High Speed Differential I/O : : 1H : Y : -- -GND : H36 : gnd : : : : : -- -GND : H37 : gnd : : : : : -- -FMC_DP_C2M_p[4](n) : H38 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[4] : H39 : output : High Speed Differential I/O : : 1G : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 3E : : -- -GND : J2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 3E : : -- -FMC_HB_p[3] : J4 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_n[3] : J5 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[28] : J6 : bidir : 1.8 V : : 3F : Y : -- -GND : J7 : gnd : : : : : -- -FMC_LA_n[6] : J8 : bidir : 1.8 V : : 3G : Y : -- -FMC_SCL : J9 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[5] : J10 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_p[5] : J11 : bidir : 1.8 V : : 3H : Y : -- -VCCIO3H : J12 : power : : 1.8V : 3H : : -- -FMC_HA_n[4] : J13 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[8] : J14 : bidir : 1.8 V : : 3H : Y : -- -DDR4H_DQ[20] : J15 : bidir : 1.2-V POD : : 2J : Y : 126ps -DDR4H_DQ[16] : J16 : bidir : 1.2-V POD : : 2J : Y : 134ps -VCCIO2J : J17 : power : : 1.2V : 2J : : -- -HPS_DIO[0] : J18 : bidir : 1.8 V : : HPS : Y : -- -HPS_TXD : J19 : output : 1.8 V : : HPS : Y : -- -VCCIOREF_HPS : J20 : power : : 1.8V : : : -- -HPS_nRST : J21 : : : : HPS : : -- -VCCIO2L : J22 : power : : 1.8V : 2L : : -- -HPS_ENET_RX_DATA[1] : J23 : input : 1.8 V : : 2L : Y : -- -HPS_ENET_TX_DATA[1] : J24 : output : 1.8 V : : 2L : Y : -- -HPS_USB_DIR : J25 : input : 1.8 V : : 2L : Y : -- -DDR4H_RZQ : J26 : input : 1.2 V : : 2K : Y : -- -GND : J27 : gnd : : : : : -- -GND : J28 : gnd : : : : : -- -VCCH_GXBL : J29 : power : : 1.8V : : : -- -VCCT_GXBL1H : J30 : power : : 0.95V : : : -- -VCCT_GXBL1H : J31 : power : : 0.95V : : : -- -FMC_DP_M2C_p[7](n) : J32 : input : High Speed Differential I/O : : 1H : N : -- -FMC_DP_M2C_p[7] : J33 : input : High Speed Differential I/O : : 1H : Y : -- -GND : J34 : gnd : : : : : -- -GND : J35 : gnd : : : : : -- -FMC_DP_C2M_p[3](n) : J36 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[3] : J37 : output : High Speed Differential I/O : : 1G : Y : -- -GND : J38 : gnd : : : : : -- -GND : J39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 3E : : -- -GND : K4 : gnd : : : : : -- -FMC_CLK_M2C_p[0] : K5 : input : 1.8 V : : 3F : Y : -- -FMC_LA_n[28] : K6 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[30] : K7 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[18] : K8 : bidir : 1.8 V : : 3G : Y : -- -VCCIO3G : K9 : power : : 1.8V : 3G : : -- -FMC_LA_n[5] : K10 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_n[5] : K11 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[0] : K12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[8] : K13 : bidir : 1.8 V : : 3H : Y : -- -VCCIO3H : K14 : power : : 1.8V : 3H : : -- -DDR4H_DQ[22] : K15 : bidir : 1.2-V POD : : 2J : Y : 125ps -RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 2J : : -- -DDR4H_DQ[15] : K17 : bidir : 1.2-V POD : : 2J : Y : 121ps -HPS_DIO[2] : K18 : bidir : 1.8 V : : HPS : Y : -- -GND : K19 : gnd : : : : : -- -VCCIO_HPS : K20 : power : : 1.8V : : : -- -HPS_nPOR : K21 : : : : HPS : : -- -HPS_ENET_RX_CLK : K22 : input : 1.8 V : : 2L : Y : -- -HPS_USB_DATA[6] : K23 : bidir : 1.8 V : : 2L : Y : -- -VCCIO2L : K24 : power : : 1.8V : 2L : : -- -HPS_USB_DATA[0] : K25 : bidir : 1.8 V : : 2L : Y : -- -DDR4H_A[12] : K26 : output : SSTL-12 : : 2K : Y : 173ps -RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 2K : : -- -DDR4H_A[15] : K28 : output : SSTL-12 : : 2K : Y : 176ps -GND : K29 : gnd : : : : : -- -FMC_GBTCLK_M2C_p[1](n) : K30 : input : LVDS : : 1H : N : -- -FMC_GBTCLK_M2C_p[1] : K31 : input : LVDS : : 1H : Y : -- -GND : K32 : gnd : : : : : -- -GND : K33 : gnd : : : : : -- -FMC_DP_M2C_p[4](n) : K34 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[4] : K35 : input : High Speed Differential I/O : : 1G : Y : -- -GND : K36 : gnd : : : : : -- -GND : K37 : gnd : : : : : -- -FMC_DP_C2M_p[2](n) : K38 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[2] : K39 : output : High Speed Differential I/O : : 1G : Y : -- -GND : L1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 3E : : -- -FMC_CLK_M2C_n[0] : L5 : input : 1.8 V : : 3F : Y : -- -GND : L6 : gnd : : : : : -- -FMC_LA_n[30] : L7 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[18] : L8 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[7] : L9 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[7] : L10 : bidir : 1.8 V : : 3G : Y : -- -GND : L11 : gnd : : : : : -- -FMC_HA_n[0] : L12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[7] : L13 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_n[7] : L14 : bidir : 1.8 V : : 3H : Y : -- -DDR4H_DQS[2] : L15 : bidir : Differential 1.2-V POD : : 2J : Y : 124ps -GND : L16 : gnd : : : : : -- -VCCL_HPS : L17 : power : : 0.9V : : : -- -VCCL_HPS : L18 : power : : 0.9V : : : -- -VCCL_HPS : L19 : power : : 0.9V : : : -- -HPS_RXD : L20 : input : 1.8 V : : HPS : Y : -- -GND : L21 : gnd : : : : : -- -HPS_ENET_RX_DV : L22 : input : 1.8 V : : 2L : Y : -- -HPS_USB_DATA[7] : L23 : bidir : 1.8 V : : 2L : Y : -- -HPS_USB_DATA[4] : L24 : bidir : 1.8 V : : 2L : Y : -- -HPS_USB_CLKOUT : L25 : input : 1.8 V : : 2L : Y : -- -GND : L26 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 2K : : -- -DDR4H_A[16] : L28 : output : SSTL-12 : : 2K : Y : 177ps -GND : L29 : gnd : : : : : -- -VCCR_GXBL1H : L30 : power : : 0.95V : : : -- -VCCR_GXBL1H : L31 : power : : 0.95V : : : -- -FMC_DP_M2C_p[5](n) : L32 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[5] : L33 : input : High Speed Differential I/O : : 1G : Y : -- -GND : L34 : gnd : : : : : -- -GND : L35 : gnd : : : : : -- -FMC_DP_C2M_p[1](n) : L36 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[1] : L37 : output : High Speed Differential I/O : : 1G : Y : -- -GND : L38 : gnd : : : : : -- -GND : L39 : gnd : : : : : -- -FPGA_I2C_SCL : M1 : bidir : 1.2 V : : 3E : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 3E : : -- -GND : M3 : gnd : : : : : -- -FPGA_I2C_SDA : M4 : bidir : 1.2 V : : 3E : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 3E : : -- -FMC_LA_p[32] : M6 : bidir : 1.8 V : : 3F : Y : -- -FMC_HA_p[19] : M7 : bidir : 1.8 V : : 3F : Y : -- -GND : M8 : gnd : : : : : -- -FMC_LA_p[8] : M9 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[3] : M10 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[3] : M11 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_p[1] : M12 : bidir : 1.8 V : : 3H : Y : -- -GND : M13 : gnd : : : : : -- -VREFB3HN0 : M14 : power : : : 3H : : -- -DDR4H_DQS_n[2] : M15 : bidir : Differential 1.2-V POD : : 2J : Y : 126ps -VREFB2JN0 : M16 : power : : : 2J : : -- -VCCL_HPS : M17 : power : : 0.9V : : : -- -GND : M18 : gnd : : : : : -- -VCCPLL_HPS : M19 : power : : 1.8V : : : -- -VREFB2LN0 : M20 : power : : : 2L : : -- -HPS_ENET_TX_DATA[3] : M21 : output : 1.8 V : : 2L : Y : -- -HPS_ENET_TX_DATA[2] : M22 : output : 1.8 V : : 2L : Y : -- -GND : M23 : gnd : : : : : -- -HPS_USB_DATA[5] : M24 : bidir : 1.8 V : : 2L : Y : -- -HPS_USB_STP : M25 : output : 1.8 V : : 2L : Y : -- -DDR4H_REFCLK_p(n) : M26 : input : LVDS : : 2K : N : -- -DDR4H_REFCLK_p : M27 : input : LVDS : : 2K : Y : -- -GND : M28 : gnd : : : : : -- -GND : M29 : gnd : : : : : -- -GXB_GND* : M30 : : : : 1H : : -- -GXB_GND* : M31 : : : : 1H : : -- -GND : M32 : gnd : : : : : -- -GND : M33 : gnd : : : : : -- -FMC_DP_M2C_p[2](n) : M34 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[2] : M35 : input : High Speed Differential I/O : : 1G : Y : -- -GND : M36 : gnd : : : : : -- -GND : M37 : gnd : : : : : -- -FMC_DP_C2M_p[0](n) : M38 : output : High Speed Differential I/O : : 1G : N : -- -FMC_DP_C2M_p[0] : M39 : output : High Speed Differential I/O : : 1G : Y : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 3E : : -- -GND : N5 : gnd : : : : : -- -FMC_LA_n[32] : N6 : bidir : 1.8 V : : 3F : Y : -- -FMC_HA_n[19] : N7 : bidir : 1.8 V : : 3F : Y : -- -FMC_HB_p[2] : N8 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[8] : N9 : bidir : 1.8 V : : 3G : Y : -- -VCCIO3G : N10 : power : : 1.8V : 3G : : -- -FMC_LA_p[33] : N11 : bidir : 1.8 V : : 3G : Y : -- -FMC_HA_n[1] : N12 : bidir : 1.8 V : : 3H : Y : -- -FMC_HA_p[6] : N13 : bidir : 1.8 V : : 3H : Y : -- -VCCP : N14 : power : : 0.9V : : : -- -GND : N15 : gnd : : : : : -- -VCCP : N16 : power : : 0.9V : : : -- -VCCP : N17 : power : : 0.9V : : : -- -VCC : N18 : power : : 0.9V : : : -- -VCCP : N19 : power : : 0.9V : : : -- -GND : N20 : gnd : : : : : -- -VCCP : N21 : power : : 0.9V : : : -- -VCC : N22 : power : : 0.9V : : : -- -VCCP : N23 : power : : 0.9V : : : -- -VCCP : N24 : power : : 0.9V : : : -- -GND : N25 : gnd : : : : : -- -DDR4H_A[4] : N26 : output : SSTL-12 : : 2K : Y : 245ps -DDR4H_A[3] : N27 : output : SSTL-12 : : 2K : Y : 232ps -GND : N28 : gnd : : : : : -- -VCCH_GXBL : N29 : power : : 1.8V : : : -- -VCCT_GXBL1G : N30 : power : : 0.95V : : : -- -VCCT_GXBL1G : N31 : power : : 0.95V : : : -- -FMC_DP_M2C_p[3](n) : N32 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[3] : N33 : input : High Speed Differential I/O : : 1G : Y : -- -GND : N34 : gnd : : : : : -- -GND : N35 : gnd : : : : : -- -GXB_NC : N36 : : : : 1F : : -- -GXB_NC : N37 : : : : 1F : : -- -GND : N38 : gnd : : : : : -- -GND : N39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 3E : : -- -GND : P2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3E : : -- -VCCIO3F : P7 : power : : 1.8V : 3F : : -- -FMC_HB_n[2] : P8 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[19] : P9 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[31] : P10 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[33] : P11 : bidir : 1.8 V : : 3G : Y : -- -GND : P12 : gnd : : : : : -- -FMC_HA_n[6] : P13 : bidir : 1.8 V : : 3H : Y : -- -VCC : P14 : power : : 0.9V : : : -- -VCC : P15 : power : : 0.9V : : : -- -VCC : P16 : power : : 0.9V : : : -- -GND : P17 : gnd : : : : : -- -VCC : P18 : power : : 0.9V : : : -- -VCC : P19 : power : : 0.9V : : : -- -VCC : P20 : power : : 0.9V : : : -- -VCC : P21 : power : : 0.9V : : : -- -GND : P22 : gnd : : : : : -- -VCC : P23 : power : : 0.9V : : : -- -VCC : P24 : power : : 0.9V : : : -- -VREFB2KN0 : P25 : power : : : 2K : : -- -DDR4H_A[5] : P26 : output : SSTL-12 : : 2K : Y : 248ps -VCCIO2K : P27 : power : : 1.2V : 2K : : -- -DDR4H_A[2] : P28 : output : SSTL-12 : : 2K : Y : 231ps -GND : P29 : gnd : : : : : -- -FMC_GBTCLK_M2C_p[0](n) : P30 : input : LVDS : : 1G : N : -- -FMC_GBTCLK_M2C_p[0] : P31 : input : LVDS : : 1G : Y : -- -GND : P32 : gnd : : : : : -- -GND : P33 : gnd : : : : : -- -FMC_DP_M2C_p[0](n) : P34 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[0] : P35 : input : High Speed Differential I/O : : 1G : Y : -- -GND : P36 : gnd : : : : : -- -GND : P37 : gnd : : : : : -- -GXB_NC : P38 : : : : 1F : : -- -GXB_NC : P39 : : : : 1F : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3E : : -- -GND : R4 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3E : : -- -FMC_LA_p[26] : R7 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[19] : R8 : bidir : 1.8 V : : 3F : Y : -- -VCCIO3F : R9 : power : : 1.8V : 3F : : -- -FMC_LA_n[31] : R10 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_p[24] : R11 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[24] : R12 : bidir : 1.8 V : : 3G : Y : -- -VREFB3GN0 : R13 : power : : : 3G : : -- -GND : R14 : gnd : : : : : -- -VCC : R15 : power : : 0.9V : : : -- -VCC : R16 : power : : 0.9V : : : -- -VCC : R17 : power : : 0.9V : : : -- -VCC : R18 : power : : 0.9V : : : -- -GND : R19 : gnd : : : : : -- -VCC : R20 : power : : 0.9V : : : -- -VCC : R21 : power : : 0.9V : : : -- -VCC : R22 : power : : 0.9V : : : -- -VCC : R23 : power : : 0.9V : : : -- -GND : R24 : gnd : : : : : -- -DDR4H_A[7] : R25 : output : SSTL-12 : : 2K : Y : 248ps -DDR4H_A[6] : R26 : output : SSTL-12 : : 2K : Y : 254ps -DDR4H_A[9] : R27 : output : SSTL-12 : : 2K : Y : 231ps -DDR4H_A[8] : R28 : output : SSTL-12 : : 2K : Y : 231ps -GND : R29 : gnd : : : : : -- -VCCR_GXBL1G : R30 : power : : 0.95V : : : -- -VCCR_GXBL1G : R31 : power : : 0.95V : : : -- -FMC_DP_M2C_p[1](n) : R32 : input : High Speed Differential I/O : : 1G : N : -- -FMC_DP_M2C_p[1] : R33 : input : High Speed Differential I/O : : 1G : Y : -- -GND : R34 : gnd : : : : : -- -GND : R35 : gnd : : : : : -- -GXB_NC : R36 : : : : 1F : : -- -GXB_NC : R37 : : : : 1F : : -- -GND : R38 : gnd : : : : : -- -GND : R39 : gnd : : : : : -- -GND : T1 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3E : : -- -GND : T6 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3E : : -- -FMC_LA_n[26] : T8 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[2] : T9 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[2] : T10 : bidir : 1.8 V : : 3F : Y : -- -VCCIO3F : T11 : power : : 1.8V : 3F : : -- -FMC_LA_p[27] : T12 : bidir : 1.8 V : : 3G : Y : -- -FMC_LA_n[27] : T13 : bidir : 1.8 V : : 3G : Y : -- -VCC : T14 : power : : 0.9V : : : -- -VCC : T15 : power : : 0.9V : : : -- -GND : T16 : gnd : : : : : -- -VCC : T17 : power : : 0.9V : : : -- -VCC : T18 : power : : 0.9V : : : -- -VCC : T19 : power : : 0.9V : : : -- -VCC : T20 : power : : 0.9V : : : -- -GND : T21 : gnd : : : : : -- -VCC : T22 : power : : 0.9V : : : -- -VCC : T23 : power : : 0.9V : : : -- -VCC : T24 : power : : 0.9V : : : -- -DDR4H_A[10] : T25 : output : SSTL-12 : : 2K : Y : 247ps -VCCIO2K : T26 : power : : 1.2V : 2K : : -- -DDR4H_PAR : T27 : output : SSTL-12 : : 2K : Y : 261ps -RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 2K : : -- -GND : T29 : gnd : : : : : -- -FMC_REFCLK_p(n) : T30 : input : LVDS : : 1G : N : -- -FMC_REFCLK_p : T31 : input : LVDS : : 1G : Y : -- -GND : T32 : gnd : : : : : -- -GND : T33 : gnd : : : : : -- -GXB_GND* : T34 : : : : 1F : : -- -GXB_GND* : T35 : : : : 1F : : -- -GND : T36 : gnd : : : : : -- -GND : T37 : gnd : : : : : -- -GXB_NC : T38 : : : : 1F : : -- -GXB_NC : T39 : : : : 1F : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 3D : : -- -GND : U3 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3E : : -- -GND : U8 : gnd : : : : : -- -FMC_LA_p[4] : U9 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[4] : U10 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_p[22] : U11 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[22] : U12 : bidir : 1.8 V : : 3F : Y : -- -GND : U13 : gnd : : : : : -- -VCCPT : U14 : power : : 1.8V : : : -- -VCCPT : U15 : power : : 1.8V : : : -- -VCC : U16 : power : : 0.9V : : : -- -VCCPT : U17 : power : : 1.8V : : : -- -GND : U18 : gnd : : : : : -- -VCCPT : U19 : power : : 1.8V : : : -- -VCC : U20 : power : : 0.9V : : : -- -VCC : U21 : power : : 0.9V : : : -- -VCCPT : U22 : power : : 1.8V : : : -- -GND : U23 : gnd : : : : : -- -VCCPT : U24 : power : : 1.8V : : : -- -DDR4H_A[11] : U25 : output : SSTL-12 : : 2K : Y : 246ps -DDR4H_CK : U26 : output : Differential 1.2-V SSTL : : 2K : Y : 230ps -DDR4H_A[0] : U27 : output : SSTL-12 : : 2K : Y : 224ps -GND : U28 : gnd : : : : : -- -VCCH_GXBL : U29 : power : : 1.8V : : : -- -VCCT_GXBL1F : U30 : power : : 0.95V : : : -- -VCCT_GXBL1F : U31 : power : : 0.95V : : : -- -GXB_GND* : U32 : : : : 1F : : -- -GXB_GND* : U33 : : : : 1F : : -- -GND : U34 : gnd : : : : : -- -GND : U35 : gnd : : : : : -- -GXB_NC : U36 : : : : 1F : : -- -GXB_NC : U37 : : : : 1F : : -- -GND : U38 : gnd : : : : : -- -GND : U39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3D : : -- -GND : V5 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3E : : -- -VCCIO3E : V10 : power : : 1.2V : 3E : : -- -FMC_LA_p[23] : V11 : bidir : 1.8 V : : 3F : Y : -- -FMC_LA_n[23] : V12 : bidir : 1.8 V : : 3F : Y : -- -VREFB3FN0 : V13 : power : : : 3F : : -- -VCC : V14 : power : : 0.9V : : : -- -GND : V15 : gnd : : : : : -- -VCC : V16 : power : : 0.9V : : : -- -VCC : V17 : power : : 0.9V : : : -- -VCC : V18 : power : : 0.9V : : : -- -VCC : V19 : power : : 0.9V : : : -- -GND : V20 : gnd : : : : : -- -VCC : V21 : power : : 0.9V : : : -- -VCC : V22 : power : : 0.9V : : : -- -VCC : V23 : power : : 0.9V : : : -- -VCC : V24 : power : : 0.9V : : : -- -VCCIO2K : V25 : power : : 1.2V : 2K : : -- -DDR4H_CK_n : V26 : output : Differential 1.2-V SSTL : : 2K : Y : 229ps -DDR4H_A[1] : V27 : output : SSTL-12 : : 2K : Y : 220ps -DDR4H_CKE : V28 : output : SSTL-12 : : 2K : Y : 230ps -GND : V29 : gnd : : : : : -- -GXB_GND* : V30 : : : : 1F : : -- -GXB_GND* : V31 : : : : 1F : : -- -GND : V32 : gnd : : : : : -- -GND : V33 : gnd : : : : : -- -GXB_GND* : V34 : : : : 1F : : -- -GXB_GND* : V35 : : : : 1F : : -- -GND : V36 : gnd : : : : : -- -GND : V37 : gnd : : : : : -- -GXB_NC : V38 : : : : 1F : : -- -GXB_NC : V39 : : : : 1F : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 3D : : -- -GND : W2 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3E : : -- -VCCIO3E : W7 : power : : 1.2V : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3E : : -- -GND : W12 : gnd : : : : : -- -VREFB3EN0 : W13 : power : : : 3E : : -- -VCCA_PLL : W14 : power : : 1.8V : : : -- -VCC : W15 : power : : 0.9V : : : -- -VCC : W16 : power : : 0.9V : : : -- -GND : W17 : gnd : : : : : -- -VCC : W18 : power : : 0.9V : : : -- -VCCA_PLL : W19 : power : : 1.8V : : : -- -VCC : W20 : power : : 0.9V : : : -- -VCC : W21 : power : : 0.9V : : : -- -GND : W22 : gnd : : : : : -- -VCC : W23 : power : : 0.9V : : : -- -VCC : W24 : power : : 0.9V : : : -- -DDR4H_CS_n : W25 : output : SSTL-12 : : 2K : Y : 189ps -RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 2K : : -- -GND : W27 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 2K : : -- -GND : W29 : gnd : : : : : -- -VCCR_GXBL1F : W30 : power : : 0.95V : : : -- -VCCR_GXBL1F : W31 : power : : 0.95V : : : -- -GXB_GND* : W32 : : : : 1F : : -- -GXB_GND* : W33 : : : : 1F : : -- -GND : W34 : gnd : : : : : -- -GND : W35 : gnd : : : : : -- -GXB_GND* : W36 : : : : 1F : : -- -GXB_GND* : W37 : : : : 1F : : -- -GND : W38 : gnd : : : : : -- -GND : W39 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3D : : -- -GND : Y4 : gnd : : : : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3D : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3E : : -- -VCCIO3E : Y9 : power : : 1.2V : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3E : : -- -RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3E : : -- -GND : Y14 : gnd : : : : : -- -VCCERAM : Y15 : power : : 0.9V : : : -- -VCCERAM : Y16 : power : : 0.9V : : : -- -VCC : Y17 : power : : 0.9V : : : -- -VCCERAM : Y18 : power : : 0.9V : : : -- -GND : Y19 : gnd : : : : : -- -VCCERAM : Y20 : power : : 0.9V : : : -- -VCC : Y21 : power : : 0.9V : : : -- -VCCERAM : Y22 : power : : 0.9V : : : -- -VCCERAM : Y23 : power : : 0.9V : : : -- -GND : Y24 : gnd : : : : : -- -DDR4H_ACT_n : Y25 : output : SSTL-12 : : 2K : Y : 192ps -DDR4H_RESET_n : Y26 : output : 1.2 V : : 2K : Y : 234ps -RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 2K : : -- -DDR4H_ODT : Y28 : output : SSTL-12 : : 2K : Y : 251ps -GND : Y29 : gnd : : : : : -- -GXB_GND* : Y30 : : : : 1F : : -- -GXB_GND* : Y31 : : : : 1F : : -- -GND : Y32 : gnd : : : : : -- -GND : Y33 : gnd : : : : : -- -GXB_GND* : Y34 : : : : 1F : : -- -GXB_GND* : Y35 : : : : 1F : : -- -GND : Y36 : gnd : : : : : -- -GND : Y37 : gnd : : : : : -- -GXB_NC : Y38 : : : : 1E : : -- -GXB_NC : Y39 : : : : 1E : : -- diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.sld b/fpga/HAN_A10rsyocto/output_files/a10s.sld deleted file mode 100644 index e91c21f..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.sld +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.sta.rpt b/fpga/HAN_A10rsyocto/output_files/a10s.sta.rpt deleted file mode 100644 index fdd983f..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.sta.rpt +++ /dev/null @@ -1,3263 +0,0 @@ -Timing Analyzer report for a10s -Mon Dec 16 14:07:35 2019 -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Slow 900mV 100C Model Fmax Summary - 7. Timing Closure Recommendations - 8. Slow 900mV 100C Model Setup Summary - 9. Slow 900mV 100C Model Hold Summary - 10. Slow 900mV 100C Model Recovery Summary - 11. Slow 900mV 100C Model Removal Summary - 12. Slow 900mV 100C Model Minimum Pulse Width Summary - 13. Slow 900mV 100C Model Net Delay Summary - 14. Slow 900mV 100C Model Metastability Summary - 15. u0|emif_a10_hps Read Capture - 16. u0|emif_a10_hps Write - 17. u0|emif_a10_hps Address/Command - 18. u0|emif_a10_hps DQS Gating - 19. u0|emif_a10_hps Write Levelling - 20. u0|emif_a10_hps - 21. Slow 900mV 0C Model Fmax Summary - 22. Slow 900mV 0C Model Setup Summary - 23. Slow 900mV 0C Model Hold Summary - 24. Slow 900mV 0C Model Recovery Summary - 25. Slow 900mV 0C Model Removal Summary - 26. Slow 900mV 0C Model Minimum Pulse Width Summary - 27. Slow 900mV 0C Model Net Delay Summary - 28. Slow 900mV 0C Model Metastability Summary - 29. u0|emif_a10_hps Read Capture - 30. u0|emif_a10_hps Write - 31. u0|emif_a10_hps Address/Command - 32. u0|emif_a10_hps DQS Gating - 33. u0|emif_a10_hps Write Levelling - 34. u0|emif_a10_hps - 35. Fast 900mV 100C Model Setup Summary - 36. Fast 900mV 100C Model Hold Summary - 37. Fast 900mV 100C Model Recovery Summary - 38. Fast 900mV 100C Model Removal Summary - 39. Fast 900mV 100C Model Minimum Pulse Width Summary - 40. Fast 900mV 100C Model Net Delay Summary - 41. Fast 900mV 100C Model Metastability Summary - 42. u0|emif_a10_hps Read Capture - 43. u0|emif_a10_hps Write - 44. u0|emif_a10_hps Address/Command - 45. u0|emif_a10_hps DQS Gating - 46. u0|emif_a10_hps Write Levelling - 47. u0|emif_a10_hps - 48. Fast 900mV 0C Model Setup Summary - 49. Fast 900mV 0C Model Hold Summary - 50. Fast 900mV 0C Model Recovery Summary - 51. Fast 900mV 0C Model Removal Summary - 52. Fast 900mV 0C Model Minimum Pulse Width Summary - 53. Fast 900mV 0C Model Net Delay Summary - 54. Fast 900mV 0C Model Metastability Summary - 55. u0|emif_a10_hps Read Capture - 56. u0|emif_a10_hps Write - 57. u0|emif_a10_hps Address/Command - 58. u0|emif_a10_hps DQS Gating - 59. u0|emif_a10_hps Write Levelling - 60. u0|emif_a10_hps - 61. Multicorner Timing Analysis Summary - 62. Board Trace Model Assignments - 63. Input Transition Times - 64. Signal Integrity Metrics (Slow 900mv 100c Model) - 65. Signal Integrity Metrics (Fast 900mv 0c Model) - 66. Setup Transfers - 67. Hold Transfers - 68. Recovery Transfers - 69. Removal Transfers - 70. Unconstrained Paths Summary - 71. Clock Status Summary - 72. Unconstrained Input Ports - 73. Unconstrained Output Ports - 74. Unconstrained Input Ports - 75. Unconstrained Output Ports - 76. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. - - - -+---------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+---------------------------------------------------------+ -; Quartus Prime Version ; Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; -; Timing Analyzer ; Timing Analyzer ; -; Revision Name ; a10s ; -; Device Family ; Arria 10 ; -; Device Name ; 10AS066K3F40E2SG ; -; Timing Models ; Final ; -; Delay Model ; Combined ; -; Rise/Fall Delays ; Enabled ; -+-----------------------+---------------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 6 ; -; ; ; -; Average used ; 1.11 ; -; Maximum used ; 6 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 2.1% ; -; Processor 3 ; 2.1% ; -; Processor 4 ; 2.1% ; -; Processor 5 ; 2.1% ; -; Processor 6 ; 2.1% ; -+----------------------------+-------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; SDC File List ; -+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+ -; a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -; a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -; a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -; a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -; a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -; a10s.sdc ; OK ; Mon Dec 16 14:07:29 2019 ; -+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+-----------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+-----------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; altera_reserved_tck ; Base ; 33.333 ; 30.0 MHz ; 0.000 ; 16.666 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; -; CLK_50_B2H ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLK_50_B2H } ; -; CLKUSR_100 ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { CLKUSR_100 } ; -; DDR4H_DQS[0]_IN ; Base ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; ; ; ; ; ; ; ; ; ; { DDR4H_DQS[0] } ; -; DDR4H_DQS[1]_IN ; Base ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; ; ; ; ; ; ; ; ; ; { DDR4H_DQS[1] } ; -; DDR4H_DQS[2]_IN ; Base ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; ; ; ; ; ; ; ; ; ; { DDR4H_DQS[2] } ; -; DDR4H_DQS[3]_IN ; Base ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; ; ; ; ; ; ; ; ; ; { DDR4H_DQS[3] } ; -; u0|emif_a10_hps_phy_clk_0 ; Generated ; 1.876 ; 533.05 MHz ; 0.117 ; 1.055 ; ; 2 ; 1 ; 22.5 ; ; ; ; false ; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|loaden[0] } ; -; u0|emif_a10_hps_phy_clk_1 ; Generated ; 1.876 ; 533.05 MHz ; 0.117 ; 1.055 ; ; 2 ; 1 ; 22.5 ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0] } ; -; u0|emif_a10_hps_phy_clk_l_0 ; Generated ; 1.876 ; 533.05 MHz ; 0.117 ; 1.055 ; ; 2 ; 1 ; 22.5 ; ; ; ; false ; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0] } ; -; u0|emif_a10_hps_phy_clk_l_1 ; Generated ; 1.876 ; 533.05 MHz ; 0.117 ; 1.055 ; ; 2 ; 1 ; 22.5 ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0] } ; -; u0|emif_a10_hps_ref_clock ; Base ; 3.752 ; 266.52 MHz ; 0.000 ; 1.876 ; ; ; ; ; ; ; ; ; ; ; { DDR4H_REFCLK_p } ; -; u0|emif_a10_hps_vco_clk_0 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 4 ; ; ; ; ; false ; u0|emif_a10_hps_ref_clock ; DDR4H_REFCLK_p ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] } ; -; u0|emif_a10_hps_vco_clk_1 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 4 ; ; ; ; ; false ; u0|emif_a10_hps_ref_clock ; DDR4H_REFCLK_p ; { u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] } ; -; u0|emif_a10_hps_wf_clk_0 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_1 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_2 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_3 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_4 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[1].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_5 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[2].lane_inst~out_phy_reg } ; -; u0|emif_a10_hps_wf_clk_6 ; Generated ; 0.938 ; 1066.1 MHz ; 0.000 ; 0.469 ; ; 1 ; 1 ; ; ; ; ; false ; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; { a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~out_phy_reg } ; -+-----------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------+ -; Slow 900mV 100C Model Fmax Summary ; -+------------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+---------------------+------+ -; 91.94 MHz ; 91.94 MHz ; altera_reserved_tck ; ; -; 133.94 MHz ; 133.94 MHz ; CLKUSR_100 ; ; -; 206.19 MHz ; 206.19 MHz ; CLK_50_B2H ; ; -+------------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - ----------------------------------- -; Timing Closure Recommendations ; ----------------------------------- -HTML report is unavailable in plain text report export. - - -+----------------------------------------------+ -; Slow 900mV 100C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 2.534 ; 0.000 ; -; altera_reserved_tck ; 11.228 ; 0.000 ; -; CLK_50_B2H ; 15.150 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 900mV 100C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.046 ; 0.000 ; -; CLKUSR_100 ; 0.052 ; 0.000 ; -; CLK_50_B2H ; 0.052 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 900mV 100C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 4.273 ; 0.000 ; -; CLK_50_B2H ; 17.058 ; 0.000 ; -; altera_reserved_tck ; 30.224 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 900mV 100C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; CLKUSR_100 ; 0.350 ; 0.000 ; -; CLK_50_B2H ; 0.555 ; 0.000 ; -; altera_reserved_tck ; 0.813 ; 0.000 ; -+---------------------+-------+---------------+ - - -+------------------------------------------------------+ -; Slow 900mV 100C Model Minimum Pulse Width Summary ; -+-----------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-----------------------------+--------+---------------+ -; DDR4H_DQS[0]_IN ; 0.182 ; 0.000 ; -; DDR4H_DQS[1]_IN ; 0.182 ; 0.000 ; -; DDR4H_DQS[2]_IN ; 0.183 ; 0.000 ; -; DDR4H_DQS[3]_IN ; 0.183 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_6 ; 0.376 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_3 ; 0.377 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_4 ; 0.377 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_5 ; 0.377 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_0 ; 0.456 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_2 ; 0.461 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_1 ; 0.462 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_0 ; 0.464 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_1 ; 0.464 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_0 ; 0.795 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_1 ; 0.795 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_0 ; 0.798 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_1 ; 0.798 ; 0.000 ; -; u0|emif_a10_hps_ref_clock ; 1.801 ; 0.000 ; -; CLKUSR_100 ; 4.430 ; 0.000 ; -; CLK_50_B2H ; 9.573 ; 0.000 ; -; altera_reserved_tck ; 16.536 ; 0.000 ; -+-----------------------------+--------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 900mV 100C Model Net Delay Summary ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; Name ; Slack ; Required ; Actual ; From ; To ; Type ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; set_net_delay ; 2.831 ; 8.000 ; 5.169 ; [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] ; [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] ; max ; -; set_net_delay ; 2.877 ; 8.000 ; 5.123 ; [get_registers *] ; [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] ; max ; -; set_net_delay ; 7.440 ; 8.000 ; 0.560 ; [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -; set_net_delay ; 7.611 ; 8.000 ; 0.389 ; [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ - - ------------------------------------------------ -; Slow 900mV 100C Model Metastability Summary ; ------------------------------------------------ -Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 97 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 -Worst Case Available Settling Time: 7.281 ns - -Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 - - - -+-------------------------------------+ -; u0|emif_a10_hps Read Capture ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.075 ; -; SSI ; 0.011 ; -; tDQSQ effect ; 0.058 ; -; tQH effect ; 0.058 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.046 ; -; Duty Cycle Distortion ; 0.018 ; -; Setup/Hold Time ; 0.017 ; -; EOL ; 0.026 ; -; Calibration Uncertainty ; 0.075 ; -; Skew Effect ; -0.002 ; -; Final Read Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Write ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.090 ; -; SSO ; 0.031 ; -; tDS effect ; 0.047 ; -; tDH effect ; 0.047 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.061 ; -; Skew Effect ; -0.002 ; -; Final Write Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Address/Command ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.150 ; -; SSO ; 0.028 ; -; tIS effect ; 0.062 ; -; tIH effect ; 0.087 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.093 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final CA Margin ; 0.411 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps DQS Gating ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 1.876 ; -; ISI ; 0.150 ; -; SSI ; 0.024 ; -; tDQSCK ; 0.350 ; -; Memory Calibration ; -0.140 ; -; Jitter Effects ; 0.152 ; -; Duty Cycle Distortion ; 0.000 ; -; EOL ; 0.003 ; -; Calibration Uncertainty ; 0.016 ; -; Tracking Uncertainty ; 0.083 ; -; Setup/Hold Time ; 0.000 ; -; Skew Effect ; -0.000 ; -; Final DQS Gating Margin ; 1.239 ; -+----------------------------+--------+ - - -+------------------------------------------+ -; u0|emif_a10_hps Write Levelling ; -+---------------------------------+--------+ -; Operation ; Margin ; -+---------------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.038 ; -; SSO ; 0.031 ; -; tDQSS/tDSS/tDSH Effect ; 0.383 ; -; Memory Calibration ; -0.153 ; -; tWLS/tWLH effect ; 0.000 ; -; Jitter Effects ; 0.159 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.000 ; -; Calibration Uncertainty ; 0.094 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final Write Levelling Margin ; 0.316 ; -+---------------------------------+--------+ - - -+--------------------------------------------------------------------------------------------------+ -; u0|emif_a10_hps ; -+-----------------------------------------------+-----------------------+-------------+------------+ -; Path ; Operating Condition ; Setup Slack ; Hold Slack ; -+-----------------------------------------------+-----------------------+-------------+------------+ -; Address/Command (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; 0.206 ; 0.206 ; -; Core (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; -- ; -- ; -; Core Recovery/Removal (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; -- ; -- ; -; DQS Gating (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; 0.62 ; 0.62 ; -; Read Capture (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; 0.043 ; 0.043 ; -; Write (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; 0.043 ; 0.043 ; -; Write Levelling (Slow 900mV 100C Model) ; Slow 900mV 100C Model ; 0.158 ; 0.158 ; -+-----------------------------------------------+-----------------------+-------------+------------+ - - -+-----------------------------------------------------------+ -; Slow 900mV 0C Model Fmax Summary ; -+------------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+---------------------+------+ -; 97.1 MHz ; 97.1 MHz ; altera_reserved_tck ; ; -; 141.32 MHz ; 141.32 MHz ; CLKUSR_100 ; ; -; 222.27 MHz ; 222.27 MHz ; CLK_50_B2H ; ; -+------------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+----------------------------------------------+ -; Slow 900mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 2.924 ; 0.000 ; -; altera_reserved_tck ; 11.517 ; 0.000 ; -; CLK_50_B2H ; 15.501 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 900mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; CLKUSR_100 ; 0.026 ; 0.000 ; -; altera_reserved_tck ; 0.038 ; 0.000 ; -; CLK_50_B2H ; 0.047 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 900mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 4.759 ; 0.000 ; -; CLK_50_B2H ; 17.257 ; 0.000 ; -; altera_reserved_tck ; 30.393 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 900mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; CLKUSR_100 ; 0.344 ; 0.000 ; -; CLK_50_B2H ; 0.499 ; 0.000 ; -; altera_reserved_tck ; 0.758 ; 0.000 ; -+---------------------+-------+---------------+ - - -+------------------------------------------------------+ -; Slow 900mV 0C Model Minimum Pulse Width Summary ; -+-----------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-----------------------------+--------+---------------+ -; DDR4H_DQS[2]_IN ; 0.143 ; 0.000 ; -; DDR4H_DQS[3]_IN ; 0.143 ; 0.000 ; -; DDR4H_DQS[0]_IN ; 0.144 ; 0.000 ; -; DDR4H_DQS[1]_IN ; 0.144 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_3 ; 0.395 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_4 ; 0.395 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_6 ; 0.395 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_5 ; 0.396 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_0 ; 0.432 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_1 ; 0.432 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_2 ; 0.432 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_0 ; 0.465 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_1 ; 0.465 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_0 ; 0.773 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_1 ; 0.773 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_0 ; 0.776 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_1 ; 0.776 ; 0.000 ; -; u0|emif_a10_hps_ref_clock ; 1.805 ; 0.000 ; -; CLKUSR_100 ; 4.529 ; 0.000 ; -; CLK_50_B2H ; 9.510 ; 0.000 ; -; altera_reserved_tck ; 16.469 ; 0.000 ; -+-----------------------------+--------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 900mV 0C Model Net Delay Summary ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; Name ; Slack ; Required ; Actual ; From ; To ; Type ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; set_net_delay ; 3.304 ; 8.000 ; 4.696 ; [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] ; [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] ; max ; -; set_net_delay ; 3.388 ; 8.000 ; 4.612 ; [get_registers *] ; [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] ; max ; -; set_net_delay ; 7.495 ; 8.000 ; 0.505 ; [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -; set_net_delay ; 7.647 ; 8.000 ; 0.353 ; [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ - - ---------------------------------------------- -; Slow 900mV 0C Model Metastability Summary ; ---------------------------------------------- -Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 97 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 -Worst Case Available Settling Time: 7.517 ns - -Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 - - - -+-------------------------------------+ -; u0|emif_a10_hps Read Capture ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.075 ; -; SSI ; 0.011 ; -; tDQSQ effect ; 0.058 ; -; tQH effect ; 0.058 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.046 ; -; Duty Cycle Distortion ; 0.018 ; -; Setup/Hold Time ; 0.017 ; -; EOL ; 0.026 ; -; Calibration Uncertainty ; 0.075 ; -; Skew Effect ; -0.002 ; -; Final Read Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Write ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.090 ; -; SSO ; 0.031 ; -; tDS effect ; 0.047 ; -; tDH effect ; 0.047 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.061 ; -; Skew Effect ; -0.002 ; -; Final Write Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Address/Command ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.150 ; -; SSO ; 0.028 ; -; tIS effect ; 0.062 ; -; tIH effect ; 0.087 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.093 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final CA Margin ; 0.411 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps DQS Gating ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 1.876 ; -; ISI ; 0.150 ; -; SSI ; 0.024 ; -; tDQSCK ; 0.350 ; -; Memory Calibration ; -0.140 ; -; Jitter Effects ; 0.152 ; -; Duty Cycle Distortion ; 0.000 ; -; EOL ; 0.003 ; -; Calibration Uncertainty ; 0.016 ; -; Tracking Uncertainty ; 0.083 ; -; Setup/Hold Time ; 0.000 ; -; Skew Effect ; -0.000 ; -; Final DQS Gating Margin ; 1.239 ; -+----------------------------+--------+ - - -+------------------------------------------+ -; u0|emif_a10_hps Write Levelling ; -+---------------------------------+--------+ -; Operation ; Margin ; -+---------------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.038 ; -; SSO ; 0.031 ; -; tDQSS/tDSS/tDSH Effect ; 0.383 ; -; Memory Calibration ; -0.153 ; -; tWLS/tWLH effect ; 0.000 ; -; Jitter Effects ; 0.159 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.000 ; -; Calibration Uncertainty ; 0.094 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final Write Levelling Margin ; 0.316 ; -+---------------------------------+--------+ - - -+----------------------------------------------------------------------------------------------+ -; u0|emif_a10_hps ; -+---------------------------------------------+---------------------+-------------+------------+ -; Path ; Operating Condition ; Setup Slack ; Hold Slack ; -+---------------------------------------------+---------------------+-------------+------------+ -; Address/Command (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; 0.206 ; 0.206 ; -; Core (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; -- ; -- ; -; Core Recovery/Removal (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; -- ; -- ; -; DQS Gating (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; 0.62 ; 0.62 ; -; Read Capture (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; 0.043 ; 0.043 ; -; Write (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; 0.043 ; 0.043 ; -; Write Levelling (Slow 900mV 0C Model) ; Slow 900mV 0C Model ; 0.158 ; 0.158 ; -+---------------------------------------------+---------------------+-------------+------------+ - - -+----------------------------------------------+ -; Fast 900mV 100C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 4.204 ; 0.000 ; -; altera_reserved_tck ; 12.766 ; 0.000 ; -; CLK_50_B2H ; 16.519 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 900mV 100C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.014 ; 0.000 ; -; CLKUSR_100 ; 0.017 ; 0.000 ; -; CLK_50_B2H ; 0.018 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Fast 900mV 100C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 5.723 ; 0.000 ; -; CLK_50_B2H ; 17.776 ; 0.000 ; -; altera_reserved_tck ; 31.083 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 900mV 100C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; CLKUSR_100 ; 0.194 ; 0.000 ; -; CLK_50_B2H ; 0.375 ; 0.000 ; -; altera_reserved_tck ; 0.526 ; 0.000 ; -+---------------------+-------+---------------+ - - -+------------------------------------------------------+ -; Fast 900mV 100C Model Minimum Pulse Width Summary ; -+-----------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-----------------------------+--------+---------------+ -; DDR4H_DQS[2]_IN ; 0.203 ; 0.000 ; -; DDR4H_DQS[3]_IN ; 0.203 ; 0.000 ; -; DDR4H_DQS[0]_IN ; 0.204 ; 0.000 ; -; DDR4H_DQS[1]_IN ; 0.204 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_3 ; 0.382 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_4 ; 0.382 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_5 ; 0.382 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_6 ; 0.382 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_0 ; 0.454 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_1 ; 0.457 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_2 ; 0.457 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_0 ; 0.466 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_1 ; 0.466 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_0 ; 0.885 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_1 ; 0.885 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_0 ; 0.886 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_1 ; 0.886 ; 0.000 ; -; u0|emif_a10_hps_ref_clock ; 1.828 ; 0.000 ; -; CLKUSR_100 ; 4.488 ; 0.000 ; -; CLK_50_B2H ; 9.675 ; 0.000 ; -; altera_reserved_tck ; 16.469 ; 0.000 ; -+-----------------------------+--------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 900mV 100C Model Net Delay Summary ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; Name ; Slack ; Required ; Actual ; From ; To ; Type ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; set_net_delay ; 3.900 ; 8.000 ; 4.100 ; [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] ; [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] ; max ; -; set_net_delay ; 3.948 ; 8.000 ; 4.052 ; [get_registers *] ; [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] ; max ; -; set_net_delay ; 7.615 ; 8.000 ; 0.385 ; [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -; set_net_delay ; 7.747 ; 8.000 ; 0.253 ; [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ - - ------------------------------------------------ -; Fast 900mV 100C Model Metastability Summary ; ------------------------------------------------ -Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 97 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 -Worst Case Available Settling Time: 7.796 ns - -Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 - - - -+-------------------------------------+ -; u0|emif_a10_hps Read Capture ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.075 ; -; SSI ; 0.011 ; -; tDQSQ effect ; 0.058 ; -; tQH effect ; 0.058 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.046 ; -; Duty Cycle Distortion ; 0.018 ; -; Setup/Hold Time ; 0.017 ; -; EOL ; 0.026 ; -; Calibration Uncertainty ; 0.075 ; -; Skew Effect ; -0.002 ; -; Final Read Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Write ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.090 ; -; SSO ; 0.031 ; -; tDS effect ; 0.047 ; -; tDH effect ; 0.047 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.061 ; -; Skew Effect ; -0.002 ; -; Final Write Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Address/Command ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.150 ; -; SSO ; 0.028 ; -; tIS effect ; 0.062 ; -; tIH effect ; 0.087 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.093 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final CA Margin ; 0.411 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps DQS Gating ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 1.876 ; -; ISI ; 0.150 ; -; SSI ; 0.024 ; -; tDQSCK ; 0.350 ; -; Memory Calibration ; -0.140 ; -; Jitter Effects ; 0.152 ; -; Duty Cycle Distortion ; 0.000 ; -; EOL ; 0.003 ; -; Calibration Uncertainty ; 0.016 ; -; Tracking Uncertainty ; 0.083 ; -; Setup/Hold Time ; 0.000 ; -; Skew Effect ; -0.000 ; -; Final DQS Gating Margin ; 1.239 ; -+----------------------------+--------+ - - -+------------------------------------------+ -; u0|emif_a10_hps Write Levelling ; -+---------------------------------+--------+ -; Operation ; Margin ; -+---------------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.038 ; -; SSO ; 0.031 ; -; tDQSS/tDSS/tDSH Effect ; 0.383 ; -; Memory Calibration ; -0.153 ; -; tWLS/tWLH effect ; 0.000 ; -; Jitter Effects ; 0.159 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.000 ; -; Calibration Uncertainty ; 0.094 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final Write Levelling Margin ; 0.316 ; -+---------------------------------+--------+ - - -+--------------------------------------------------------------------------------------------------+ -; u0|emif_a10_hps ; -+-----------------------------------------------+-----------------------+-------------+------------+ -; Path ; Operating Condition ; Setup Slack ; Hold Slack ; -+-----------------------------------------------+-----------------------+-------------+------------+ -; Address/Command (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; 0.206 ; 0.206 ; -; Core (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; -- ; -- ; -; Core Recovery/Removal (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; -- ; -- ; -; DQS Gating (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; 0.62 ; 0.62 ; -; Read Capture (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; 0.043 ; 0.043 ; -; Write (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; 0.043 ; 0.043 ; -; Write Levelling (Fast 900mV 100C Model) ; Fast 900mV 100C Model ; 0.158 ; 0.158 ; -+-----------------------------------------------+-----------------------+-------------+------------+ - - -+----------------------------------------------+ -; Fast 900mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 5.295 ; 0.000 ; -; altera_reserved_tck ; 13.449 ; 0.000 ; -; CLK_50_B2H ; 17.133 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 900mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.013 ; 0.000 ; -; CLKUSR_100 ; 0.015 ; 0.000 ; -; CLK_50_B2H ; 0.017 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Fast 900mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; CLKUSR_100 ; 6.498 ; 0.000 ; -; CLK_50_B2H ; 18.224 ; 0.000 ; -; altera_reserved_tck ; 31.500 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 900mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; CLKUSR_100 ; 0.160 ; 0.000 ; -; CLK_50_B2H ; 0.284 ; 0.000 ; -; altera_reserved_tck ; 0.411 ; 0.000 ; -+---------------------+-------+---------------+ - - -+------------------------------------------------------+ -; Fast 900mV 0C Model Minimum Pulse Width Summary ; -+-----------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-----------------------------+--------+---------------+ -; DDR4H_DQS[0]_IN ; 0.205 ; 0.000 ; -; DDR4H_DQS[1]_IN ; 0.206 ; 0.000 ; -; DDR4H_DQS[2]_IN ; 0.206 ; 0.000 ; -; DDR4H_DQS[3]_IN ; 0.206 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_3 ; 0.396 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_4 ; 0.396 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_5 ; 0.396 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_6 ; 0.396 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_0 ; 0.461 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_1 ; 0.463 ; 0.000 ; -; u0|emif_a10_hps_wf_clk_2 ; 0.463 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_0 ; 0.466 ; 0.000 ; -; u0|emif_a10_hps_vco_clk_1 ; 0.466 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_0 ; 0.889 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_1 ; 0.889 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_0 ; 0.889 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_1 ; 0.889 ; 0.000 ; -; u0|emif_a10_hps_ref_clock ; 1.836 ; 0.000 ; -; CLKUSR_100 ; 4.456 ; 0.000 ; -; CLK_50_B2H ; 9.669 ; 0.000 ; -; altera_reserved_tck ; 16.494 ; 0.000 ; -+-----------------------------+--------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 900mV 0C Model Net Delay Summary ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; Name ; Slack ; Required ; Actual ; From ; To ; Type ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ -; set_net_delay ; 4.648 ; 8.000 ; 3.352 ; [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] ; [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] ; max ; -; set_net_delay ; 4.773 ; 8.000 ; 3.227 ; [get_registers *] ; [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] ; max ; -; set_net_delay ; 7.703 ; 8.000 ; 0.297 ; [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -; set_net_delay ; 7.807 ; 8.000 ; 0.193 ; [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] ; [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] ; max ; -+---------------+-------+----------+--------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------+ - - ---------------------------------------------- -; Fast 900mV 0C Model Metastability Summary ; ---------------------------------------------- -Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 97 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 -Worst Case Available Settling Time: 8.172 ns - -Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 - - - -+-------------------------------------+ -; u0|emif_a10_hps Read Capture ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.075 ; -; SSI ; 0.011 ; -; tDQSQ effect ; 0.058 ; -; tQH effect ; 0.058 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.046 ; -; Duty Cycle Distortion ; 0.018 ; -; Setup/Hold Time ; 0.017 ; -; EOL ; 0.026 ; -; Calibration Uncertainty ; 0.075 ; -; Skew Effect ; -0.002 ; -; Final Read Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Write ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.469 ; -; ISI ; 0.090 ; -; SSO ; 0.031 ; -; tDS effect ; 0.047 ; -; tDH effect ; 0.047 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.061 ; -; Skew Effect ; -0.002 ; -; Final Write Margin ; 0.086 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps Address/Command ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.150 ; -; SSO ; 0.028 ; -; tIS effect ; 0.062 ; -; tIH effect ; 0.087 ; -; Memory Calibration ; -0.000 ; -; Jitter Effects ; 0.027 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.011 ; -; Calibration Uncertainty ; 0.093 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final CA Margin ; 0.411 ; -+----------------------------+--------+ - - -+-------------------------------------+ -; u0|emif_a10_hps DQS Gating ; -+----------------------------+--------+ -; Operation ; Margin ; -+----------------------------+--------+ -; Ideal Timing Window ; 1.876 ; -; ISI ; 0.150 ; -; SSI ; 0.024 ; -; tDQSCK ; 0.350 ; -; Memory Calibration ; -0.140 ; -; Jitter Effects ; 0.152 ; -; Duty Cycle Distortion ; 0.000 ; -; EOL ; 0.003 ; -; Calibration Uncertainty ; 0.016 ; -; Tracking Uncertainty ; 0.083 ; -; Setup/Hold Time ; 0.000 ; -; Skew Effect ; -0.000 ; -; Final DQS Gating Margin ; 1.239 ; -+----------------------------+--------+ - - -+------------------------------------------+ -; u0|emif_a10_hps Write Levelling ; -+---------------------------------+--------+ -; Operation ; Margin ; -+---------------------------------+--------+ -; Ideal Timing Window ; 0.938 ; -; ISI ; 0.038 ; -; SSO ; 0.031 ; -; tDQSS/tDSS/tDSH Effect ; 0.383 ; -; Memory Calibration ; -0.153 ; -; tWLS/tWLH effect ; 0.000 ; -; Jitter Effects ; 0.159 ; -; Duty Cycle Distortion ; 0.071 ; -; EOL ; 0.000 ; -; Calibration Uncertainty ; 0.094 ; -; PVT variation ; 0.000 ; -; Skew Effect ; -0.001 ; -; Final Write Levelling Margin ; 0.316 ; -+---------------------------------+--------+ - - -+----------------------------------------------------------------------------------------------+ -; u0|emif_a10_hps ; -+---------------------------------------------+---------------------+-------------+------------+ -; Path ; Operating Condition ; Setup Slack ; Hold Slack ; -+---------------------------------------------+---------------------+-------------+------------+ -; Address/Command (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; 0.206 ; 0.206 ; -; Core (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; -- ; -- ; -; Core Recovery/Removal (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; -- ; -- ; -; DQS Gating (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; 0.62 ; 0.62 ; -; Read Capture (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; 0.043 ; 0.043 ; -; Write (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; 0.043 ; 0.043 ; -; Write Levelling (Fast 900mV 0C Model) ; Fast 900mV 0C Model ; 0.158 ; 0.158 ; -+---------------------------------------------+---------------------+-------------+------------+ - - -+------------------------------------------------------------------------------------------+ -; Multicorner Timing Analysis Summary ; -+------------------------------+--------+-------+----------+---------+---------------------+ -; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; -+------------------------------+--------+-------+----------+---------+---------------------+ -; Worst-case Slack ; 2.534 ; 0.013 ; 4.273 ; 0.160 ; 0.143 ; -; CLKUSR_100 ; 2.534 ; 0.015 ; 4.273 ; 0.160 ; 4.430 ; -; CLK_50_B2H ; 15.150 ; 0.017 ; 17.058 ; 0.284 ; 9.510 ; -; DDR4H_DQS[0]_IN ; N/A ; N/A ; N/A ; N/A ; 0.144 ; -; DDR4H_DQS[1]_IN ; N/A ; N/A ; N/A ; N/A ; 0.144 ; -; DDR4H_DQS[2]_IN ; N/A ; N/A ; N/A ; N/A ; 0.143 ; -; DDR4H_DQS[3]_IN ; N/A ; N/A ; N/A ; N/A ; 0.143 ; -; altera_reserved_tck ; 11.228 ; 0.013 ; 30.224 ; 0.411 ; 16.469 ; -; u0|emif_a10_hps_phy_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.773 ; -; u0|emif_a10_hps_phy_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.773 ; -; u0|emif_a10_hps_phy_clk_l_0 ; N/A ; N/A ; N/A ; N/A ; 0.776 ; -; u0|emif_a10_hps_phy_clk_l_1 ; N/A ; N/A ; N/A ; N/A ; 0.776 ; -; u0|emif_a10_hps_ref_clock ; N/A ; N/A ; N/A ; N/A ; 1.801 ; -; u0|emif_a10_hps_vco_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.464 ; -; u0|emif_a10_hps_vco_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.464 ; -; u0|emif_a10_hps_wf_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.432 ; -; u0|emif_a10_hps_wf_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.432 ; -; u0|emif_a10_hps_wf_clk_2 ; N/A ; N/A ; N/A ; N/A ; 0.432 ; -; u0|emif_a10_hps_wf_clk_3 ; N/A ; N/A ; N/A ; N/A ; 0.377 ; -; u0|emif_a10_hps_wf_clk_4 ; N/A ; N/A ; N/A ; N/A ; 0.377 ; -; u0|emif_a10_hps_wf_clk_5 ; N/A ; N/A ; N/A ; N/A ; 0.377 ; -; u0|emif_a10_hps_wf_clk_6 ; N/A ; N/A ; N/A ; N/A ; 0.376 ; -; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -; CLKUSR_100 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; -; CLK_50_B2H ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; -; DDR4H_DQS[0]_IN ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; DDR4H_DQS[1]_IN ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; DDR4H_DQS[2]_IN ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; DDR4H_DQS[3]_IN ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; altera_reserved_tck ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; -; u0|emif_a10_hps_phy_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_phy_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_0 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_phy_clk_l_1 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_ref_clock ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_vco_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_vco_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_0 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_1 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_2 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_3 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_4 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_5 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; u0|emif_a10_hps_wf_clk_6 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -+------------------------------+--------+-------+----------+---------+---------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+----------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+----------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; LED[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LED[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_GTX_CLK ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_MDC ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_TX_DATA[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_TX_DATA[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_TX_DATA[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_TX_DATA[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_TX_EN ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_TXD ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_STP ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; SMA_CLKOUT_p ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; -; DDR4H_A[0] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[1] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[2] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[3] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[4] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[5] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[6] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[7] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[8] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[9] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[10] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[11] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[12] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[13] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[14] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[15] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_A[16] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_BA[0] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_BA[1] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_BG[0] ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_CK ; Differential 1.2-V SSTL ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; open ; n/a ; n/a ; n/a ; -; DDR4H_CK_n ; Differential 1.2-V SSTL ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; open ; n/a ; n/a ; n/a ; -; DDR4H_CKE ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_CS_n ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_RESET_n ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_ODT ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_PAR ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_ACT_n ; SSTL-12 ; 0 in ; 0 H/in ; 0 F/in ; 25 Ohm ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ETH_RST_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ETH_TX_p ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; -; ETH_MDC ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_D[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0_DP ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_D[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1_DP ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FPGA_I2C_SCL ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FPGA_I2C_SDA ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_GPIO[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_GPIO[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_GPIO[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_GPIO[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_KEY ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_LED ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_ENET_MDIO ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_USB_DATA[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_I2C0_SCLK ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_I2C0_SDAT ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQS[0] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS[1] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS[2] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS[3] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS_n[0] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS_n[1] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS_n[2] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQS_n[3] ; Differential 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; open ; n/a ; n/a ; n/a ; -; DDR4H_DQ[0] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[1] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[2] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[3] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[4] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[5] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[6] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[7] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[8] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[9] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[10] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[11] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[12] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[13] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[14] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[15] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[16] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[17] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[18] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[19] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[20] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[21] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[22] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[23] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[24] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[25] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[26] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[27] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[28] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[29] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[30] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DQ[31] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DBI_n[0] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DBI_n[1] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DBI_n[2] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; DDR4H_DBI_n[3] ; 1.2-V POD ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; 48 Ohm ; open ; open ; vccio ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HPS_DIO[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; I2C_INT ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; REFCLK0_SCL ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; REFCLK0_SDA ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; REFCLK1_SCL ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; REFCLK1_SDA ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; CDCM6208_SCL ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; CDCM6208_SDA ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_CLK2_BIDIR_p ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_CLK2_BIDIR_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_CLK3_BIDIR_p ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_CLK3_BIDIR_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[22] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_p[23] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[22] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HA_n[23] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_p[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_HB_n[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[22] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[23] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[24] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[25] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[26] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[27] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[28] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[29] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[30] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[31] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[32] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_p[33] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[22] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[23] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[24] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[25] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[26] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[27] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[28] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[29] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[30] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[31] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[32] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_LA_n[33] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_GA[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_GA[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_SCL ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; FMC_SDA ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ETH_MDIO ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; MPU_INT ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; SRC_DP_HPD ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_RESET_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_PCLK ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL0_SLCS_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_UART_TX ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_UART_RX ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL10 ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL12_A0 ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL15_INT_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL1_SLWR_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL2_SLOE_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL3_SLRD_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL4_FLAGA ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL5_FLAGB ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL6 ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL7_PKTEND_n ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL8 ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_CTL9 ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[0] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[1] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[2] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[3] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[4] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[5] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[6] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[7] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[8] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[9] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[10] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[11] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[12] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[13] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[14] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[15] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[16] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[17] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[18] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[19] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[20] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[21] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[22] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[23] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[24] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[25] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[26] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[27] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[28] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[29] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[30] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_DQ[31] ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; USBFX3_OTG_ID ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; altera_reserved_tdo ; 1.8 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; SMA_CLKOUT_p(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; -; ETH_TX_p(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; -+----------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ - - -+-------------------------------------------------------------------------------------+ -; Input Transition Times ; -+------------------------+------------------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+------------------------+------------------------+-----------------+-----------------+ -; CLK_50_B3H ; 1.8 V ; 1440 ps ; 1440 ps ; -; FAN_ALERT_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; PM_ALERT_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK_M2C_p[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK_M2C_p[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK_M2C_n[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK_M2C_n[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_GBTCLK_M2C_p[0] ; LVDS ; 1440 ps ; 1440 ps ; -; FMC_GBTCLK_M2C_p[1] ; LVDS ; 1440 ps ; 1440 ps ; -; FMC_REFCLK_p ; LVDS ; 1440 ps ; 1440 ps ; -; FMC_RZQ ; 1.8 V ; 1440 ps ; 1440 ps ; -; ETH_RX_p ; LVDS ; 1440 ps ; 1440 ps ; -; ETH_INT_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL11_A1 ; 1.8 V ; 1440 ps ; 1440 ps ; -; SMA_CLKIN_p ; LVDS ; 1440 ps ; 1440 ps ; -; FPGA_I2C_SCL ; 1.2 V ; 960 ps ; 960 ps ; -; FPGA_I2C_SDA ; 1.2 V ; 960 ps ; 960 ps ; -; HPS_GPIO[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_GPIO[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_GPIO[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_GPIO[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_KEY ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_LED ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_MDIO ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DATA[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_I2C0_SCLK ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_I2C0_SDAT ; 1.8 V ; 1440 ps ; 1440 ps ; -; DDR4H_DQS[0] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS[1] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS[2] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS[3] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS_n[0] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS_n[1] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS_n[2] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQS_n[3] ; Differential 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[0] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[1] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[2] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[3] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[4] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[5] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[6] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[7] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[8] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[9] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[10] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[11] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[12] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[13] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[14] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[15] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[16] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[17] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[18] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[19] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[20] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[21] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[22] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[23] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[24] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[25] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[26] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[27] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[28] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[29] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[30] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DQ[31] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DBI_n[0] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DBI_n[1] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DBI_n[2] ; 1.2-V POD ; 960 ps ; 960 ps ; -; DDR4H_DBI_n[3] ; 1.2-V POD ; 960 ps ; 960 ps ; -; HPS_DIO[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_DIO[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_DIO[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_DIO[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_DIO[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_DIO[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; I2C_INT ; 1.8 V ; 1440 ps ; 1440 ps ; -; REFCLK0_SCL ; 1.8 V ; 1440 ps ; 1440 ps ; -; REFCLK0_SDA ; 1.8 V ; 1440 ps ; 1440 ps ; -; REFCLK1_SCL ; 1.8 V ; 1440 ps ; 1440 ps ; -; REFCLK1_SDA ; 1.8 V ; 1440 ps ; 1440 ps ; -; CDCM6208_SCL ; 1.8 V ; 1440 ps ; 1440 ps ; -; CDCM6208_SDA ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK2_BIDIR_p ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK2_BIDIR_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK3_BIDIR_p ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_CLK3_BIDIR_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[22] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_p[23] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[22] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HA_n[23] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_p[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_HB_n[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[22] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[23] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[24] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[25] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[26] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[27] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[28] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[29] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[30] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[31] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[32] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_p[33] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[22] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[23] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[24] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[25] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[26] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[27] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[28] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[29] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[30] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[31] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[32] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_LA_n[33] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_GA[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_GA[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_SCL ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_SDA ; 1.8 V ; 1440 ps ; 1440 ps ; -; ETH_MDIO ; 1.8 V ; 1440 ps ; 1440 ps ; -; MPU_INT ; 1.8 V ; 1440 ps ; 1440 ps ; -; SRC_DP_HPD ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_RESET_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_PCLK ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL0_SLCS_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_UART_TX ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_UART_RX ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL10 ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL12_A0 ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL15_INT_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL1_SLWR_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL2_SLOE_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL3_SLRD_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL4_FLAGA ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL5_FLAGB ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL6 ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL7_PKTEND_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL8 ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_CTL9 ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[4] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[5] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[6] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[7] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[8] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[9] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[10] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[11] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[12] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[13] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[14] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[15] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[16] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[17] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[18] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[19] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[20] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[21] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[22] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[23] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[24] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[25] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[26] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[27] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[28] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[29] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[30] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_DQ[31] ; 1.8 V ; 1440 ps ; 1440 ps ; -; USBFX3_OTG_ID ; 1.8 V ; 1440 ps ; 1440 ps ; -; CLKUSR_100 ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_CLK ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_DV ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_DATA[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_DATA[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_DATA[2] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_ENET_RX_DATA[3] ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_RXD ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_CLKOUT ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_DIR ; 1.8 V ; 1440 ps ; 1440 ps ; -; HPS_USB_NXT ; 1.8 V ; 1440 ps ; 1440 ps ; -; DDR4H_ALERT_n ; SSTL-12 ; 960 ps ; 960 ps ; -; DDR4H_RZQ ; 1.2 V ; 960 ps ; 960 ps ; -; SW[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; SW[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; CLK_50_B2H ; 1.8 V ; 1440 ps ; 1440 ps ; -; KEY[0] ; 1.8 V ; 1440 ps ; 1440 ps ; -; KEY[1] ; 1.8 V ; 1440 ps ; 1440 ps ; -; CPU_RESET_n ; 1.8 V ; 1440 ps ; 1440 ps ; -; DDR4H_REFCLK_p ; LVDS ; 1440 ps ; 1440 ps ; -; altera_reserved_tms ; 1.8 V ; 1440 ps ; 1440 ps ; -; altera_reserved_tck ; 1.8 V ; 1440 ps ; 1440 ps ; -; altera_reserved_tdi ; 1.8 V ; 1440 ps ; 1440 ps ; -; altera_reserved_ntrst ; 1.8 V ; 1440 ps ; 1440 ps ; -; FMC_GBTCLK_M2C_p[0](n) ; LVDS ; 1440 ps ; 1440 ps ; -; FMC_GBTCLK_M2C_p[1](n) ; LVDS ; 1440 ps ; 1440 ps ; -; FMC_REFCLK_p(n) ; LVDS ; 1440 ps ; 1440 ps ; -; ETH_RX_p(n) ; LVDS ; 1440 ps ; 1440 ps ; -; SMA_CLKIN_p(n) ; LVDS ; 1440 ps ; 1440 ps ; -; DDR4H_REFCLK_p(n) ; LVDS ; 1440 ps ; 1440 ps ; -+------------------------+------------------------+-----------------+-----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 900mv 100c Model) ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LED[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; LED[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_GTX_CLK ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_MDC ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_TX_EN ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_TXD ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_STP ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; SMA_CLKOUT_p ; LVDS ; 0 s ; 0 s ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; -; DDR4H_A[0] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[1] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[2] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[3] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[4] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[5] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[6] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[7] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[8] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[9] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[10] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[11] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[12] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[13] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[14] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[15] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_A[16] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_BA[0] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_BA[1] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_BG[0] ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_CK ; Differential 1.2-V SSTL ; 0 s ; 0 s ; 1.1 V ; -1.1 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.33e-10 s ; No ; No ; 1.1 V ; -1.1 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.33e-10 s ; No ; No ; -; DDR4H_CK_n ; Differential 1.2-V SSTL ; 0 s ; 0 s ; 1.1 V ; -1.1 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.33e-10 s ; No ; No ; 1.1 V ; -1.1 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.33e-10 s ; No ; No ; -; DDR4H_CKE ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_CS_n ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_RESET_n ; 1.2 V ; 0 s ; 0 s ; 1.1 V ; 2.87e-06 V ; 1.16 V ; -0.0661 V ; 0.111 V ; 0.103 V ; 1.35e-10 s ; 1.32e-10 s ; No ; No ; 1.1 V ; 2.87e-06 V ; 1.16 V ; -0.0661 V ; 0.111 V ; 0.103 V ; 1.35e-10 s ; 1.32e-10 s ; No ; No ; -; DDR4H_ODT ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_PAR ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; DDR4H_ACT_n ; SSTL-12 ; 0 s ; 0 s ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; 1.1 V ; 3.15e-06 V ; 1.17 V ; -0.0632 V ; 0.118 V ; 0.115 V ; 1.32e-10 s ; 1.34e-10 s ; No ; No ; -; ETH_RST_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; ETH_TX_p ; LVDS ; 0 s ; 0 s ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; -; ETH_MDC ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_D[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX0_DP ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_D[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; HEX1_DP ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FPGA_I2C_SCL ; 1.2 V ; 0 s ; 0 s ; 1.1 V ; 4.31e-06 V ; 1.14 V ; -0.0587 V ; 0.092 V ; 0.2 V ; 2.37e-10 s ; 1.5e-10 s ; No ; No ; 1.1 V ; 4.31e-06 V ; 1.14 V ; -0.0587 V ; 0.092 V ; 0.2 V ; 2.37e-10 s ; 1.5e-10 s ; No ; No ; -; FPGA_I2C_SDA ; 1.2 V ; 0 s ; 0 s ; 1.1 V ; 4.31e-06 V ; 1.14 V ; -0.0587 V ; 0.092 V ; 0.2 V ; 2.37e-10 s ; 1.5e-10 s ; No ; No ; 1.1 V ; 4.31e-06 V ; 1.14 V ; -0.0587 V ; 0.092 V ; 0.2 V ; 2.37e-10 s ; 1.5e-10 s ; No ; No ; -; HPS_GPIO[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_GPIO[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_GPIO[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_GPIO[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_KEY ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_LED ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_ENET_MDIO ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_USB_DATA[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_I2C0_SCLK ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_I2C0_SDAT ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; DDR4H_DQS[0] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS[1] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS[2] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS[3] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[0] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[1] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[2] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[3] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; 0.669 V ; -0.669 V ; - ; - ; - ; - ; 9.64e-11 s ; 9.64e-11 s ; Yes ; Yes ; -; DDR4H_DQ[0] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[1] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[2] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[3] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[4] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[5] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[6] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[7] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[8] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[9] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[10] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[11] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[12] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[13] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[14] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[15] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[16] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[17] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[18] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[19] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[20] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[21] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[22] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[23] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[24] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[25] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[26] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[27] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[28] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[29] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[30] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DQ[31] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[0] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[1] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[2] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[3] ; 1.2-V POD ; 2.3e-11 s ; -4.23e-11 s ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; 1.1 V ; 0.435 V ; 1.11 V ; 0.385 V ; 0 V ; 0 V ; 8.36e-11 s ; 9.26e-11 s ; Yes ; Yes ; -; HPS_DIO[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_DIO[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_DIO[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_DIO[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_DIO[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; HPS_DIO[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; I2C_INT ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; REFCLK0_SCL ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; REFCLK0_SDA ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; REFCLK1_SCL ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; REFCLK1_SDA ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; CDCM6208_SCL ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; CDCM6208_SDA ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_CLK2_BIDIR_p ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_CLK2_BIDIR_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_CLK3_BIDIR_p ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_CLK3_BIDIR_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[22] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_p[23] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[22] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HA_n[23] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_HB_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[22] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[23] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[24] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[25] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[26] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[27] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[28] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[29] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[30] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[31] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[32] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_p[33] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[22] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[23] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[24] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[25] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[26] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[27] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[28] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[29] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[30] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[31] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[32] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_LA_n[33] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_GA[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_GA[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_SCL ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; FMC_SDA ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; ETH_MDIO ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; MPU_INT ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; SRC_DP_HPD ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; USBFX3_RESET_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_PCLK ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL0_SLCS_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_UART_TX ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_UART_RX ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL10 ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL12_A0 ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL15_INT_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL1_SLWR_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL2_SLOE_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL3_SLRD_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL4_FLAGA ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; USBFX3_CTL5_FLAGB ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL6 ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL7_PKTEND_n ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL8 ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_CTL9 ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[0] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[1] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[2] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[3] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[4] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[5] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[6] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[7] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[8] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[9] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[10] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[11] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[12] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[13] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[14] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[15] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[16] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[17] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[18] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[19] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[20] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[21] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[22] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[23] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[24] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[25] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[26] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[27] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[28] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[29] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; 1.66 V ; 2e-06 V ; 1.66 V ; -0.0207 V ; 0.09 V ; 0.184 V ; 3.69e-10 s ; 2.71e-10 s ; Yes ; No ; -; USBFX3_DQ[30] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; USBFX3_DQ[31] ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; USBFX3_OTG_ID ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; 1.66 V ; 4.43e-06 V ; 1.7 V ; -0.0552 V ; 0.108 V ; 0.08 V ; 2.35e-10 s ; 2.24e-10 s ; No ; No ; -; altera_reserved_tdo ; 1.8 V ; 0 s ; 0 s ; 1.66 V ; 3.7e-06 V ; 1.73 V ; -0.0751 V ; 0.178 V ; 0.161 V ; 1.41e-10 s ; 1.39e-10 s ; No ; No ; 1.66 V ; 3.7e-06 V ; 1.73 V ; -0.0751 V ; 0.178 V ; 0.161 V ; 1.41e-10 s ; 1.39e-10 s ; No ; No ; -; SMA_CLKOUT_p(n) ; LVDS ; 0 s ; 0 s ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; -; ETH_TX_p(n) ; LVDS ; 0 s ; 0 s ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; 0.718 V ; -0.718 V ; - ; - ; - ; - ; 6.75e-11 s ; 6.58e-11 s ; Yes ; Yes ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 900mv 0c Model) ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LED[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; LED[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_GTX_CLK ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_MDC ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_TX_DATA[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_TX_EN ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_TXD ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_STP ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; SMA_CLKOUT_p ; LVDS ; 0 s ; 0 s ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; -; DDR4H_A[0] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[1] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[2] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[3] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[4] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[5] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[6] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[7] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[8] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[9] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[10] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[11] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[12] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[13] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[14] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[15] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_A[16] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_BA[0] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_BA[1] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_BG[0] ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_CK ; Differential 1.2-V SSTL ; 0 s ; 0 s ; 1.26 V ; -1.26 V ; - ; - ; - ; - ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; -1.26 V ; - ; - ; - ; - ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_CK_n ; Differential 1.2-V SSTL ; 0 s ; 0 s ; 1.26 V ; -1.26 V ; - ; - ; - ; - ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; -1.26 V ; - ; - ; - ; - ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_CKE ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_CS_n ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_RESET_n ; 1.2 V ; 0 s ; 0 s ; 1.26 V ; 8.64e-08 V ; 1.45 V ; -0.196 V ; 0.227 V ; 0.245 V ; 3.86e-11 s ; 3.71e-11 s ; No ; No ; 1.26 V ; 8.64e-08 V ; 1.45 V ; -0.196 V ; 0.227 V ; 0.245 V ; 3.86e-11 s ; 3.71e-11 s ; No ; No ; -; DDR4H_ODT ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_PAR ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; DDR4H_ACT_n ; SSTL-12 ; 0 s ; 0 s ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; 1.26 V ; 1.54e-07 V ; 1.35 V ; -0.103 V ; 0.139 V ; 0.163 V ; 1.31e-10 s ; 1.31e-10 s ; No ; No ; -; ETH_RST_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; ETH_TX_p ; LVDS ; 0 s ; 0 s ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; -; ETH_MDC ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_D[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX0_DP ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_D[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; HEX1_DP ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FPGA_I2C_SCL ; 1.2 V ; 0 s ; 0 s ; 1.26 V ; 1.3e-07 V ; 1.37 V ; -0.127 V ; 0.128 V ; 0.149 V ; 1.28e-10 s ; 1.28e-10 s ; No ; No ; 1.26 V ; 1.3e-07 V ; 1.37 V ; -0.127 V ; 0.128 V ; 0.149 V ; 1.28e-10 s ; 1.28e-10 s ; No ; No ; -; FPGA_I2C_SDA ; 1.2 V ; 0 s ; 0 s ; 1.26 V ; 1.3e-07 V ; 1.37 V ; -0.127 V ; 0.128 V ; 0.149 V ; 1.28e-10 s ; 1.28e-10 s ; No ; No ; 1.26 V ; 1.3e-07 V ; 1.37 V ; -0.127 V ; 0.128 V ; 0.149 V ; 1.28e-10 s ; 1.28e-10 s ; No ; No ; -; HPS_GPIO[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_GPIO[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_GPIO[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_GPIO[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_KEY ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_LED ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_ENET_MDIO ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_USB_DATA[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_I2C0_SCLK ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_I2C0_SDAT ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; DDR4H_DQS[0] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS[1] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS[2] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS[3] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[0] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[1] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[2] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQS_n[3] ; Differential 1.2-V POD ; 0 s ; 0 s ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; 0.808 V ; -0.808 V ; - ; - ; - ; - ; 8.66e-11 s ; 8.66e-11 s ; Yes ; Yes ; -; DDR4H_DQ[0] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[1] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[2] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[3] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[4] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[5] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[6] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[7] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[8] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[9] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[10] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[11] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[12] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[13] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[14] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[15] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[16] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[17] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[18] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[19] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[20] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[21] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[22] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[23] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[24] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[25] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[26] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[27] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[28] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[29] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[30] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DQ[31] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[0] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[1] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[2] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; DDR4H_DBI_n[3] ; 1.2-V POD ; 1.78e-11 s ; -3.15e-11 s ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; 1.26 V ; 0.452 V ; 1.27 V ; 0.367 V ; 0.001 V ; 0 V ; 7.6e-11 s ; 8.7e-11 s ; Yes ; Yes ; -; HPS_DIO[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_DIO[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_DIO[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_DIO[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_DIO[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; HPS_DIO[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; I2C_INT ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; REFCLK0_SCL ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; REFCLK0_SDA ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; REFCLK1_SCL ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; REFCLK1_SDA ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; CDCM6208_SCL ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; CDCM6208_SDA ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_CLK2_BIDIR_p ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_CLK2_BIDIR_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_CLK3_BIDIR_p ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_CLK3_BIDIR_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[22] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_p[23] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[22] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HA_n[23] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_HB_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[22] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[23] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[24] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[25] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[26] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[27] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[28] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[29] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[30] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[31] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[32] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_p[33] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[22] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[23] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[24] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[25] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[26] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[27] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[28] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[29] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[30] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[31] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[32] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_LA_n[33] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_GA[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_GA[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_SCL ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; FMC_SDA ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; ETH_MDIO ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; MPU_INT ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; SRC_DP_HPD ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; USBFX3_RESET_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_PCLK ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL0_SLCS_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_UART_TX ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_UART_RX ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL10 ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL12_A0 ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL15_INT_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL1_SLWR_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL2_SLOE_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL3_SLRD_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL4_FLAGA ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; USBFX3_CTL5_FLAGB ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL6 ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL7_PKTEND_n ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL8 ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_CTL9 ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[0] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[1] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[2] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[3] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[4] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[5] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[6] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[7] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[8] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[9] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[10] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[11] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[12] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[13] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[14] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[15] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[16] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[17] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[18] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[19] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[20] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[21] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[22] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[23] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[24] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[25] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[26] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[27] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[28] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0574 V ; 0.078 V ; 0.206 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[29] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; 1.89 V ; 4.89e-08 V ; 1.91 V ; -0.0578 V ; 0.078 V ; 0.207 V ; 2.34e-10 s ; 1.53e-10 s ; Yes ; No ; -; USBFX3_DQ[30] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; USBFX3_DQ[31] ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; USBFX3_OTG_ID ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; 1.89 V ; 3.2e-07 V ; 2 V ; -0.181 V ; 0.163 V ; 0.18 V ; 1.29e-10 s ; 1.22e-10 s ; No ; No ; -; altera_reserved_tdo ; 1.8 V ; 0 s ; 0 s ; 1.89 V ; 2.67e-07 V ; 2.04 V ; -0.174 V ; 0.277 V ; 0.146 V ; 5.32e-11 s ; 1.16e-10 s ; No ; No ; 1.89 V ; 2.67e-07 V ; 2.04 V ; -0.174 V ; 0.277 V ; 0.146 V ; 5.32e-11 s ; 1.16e-10 s ; No ; No ; -; SMA_CLKOUT_p(n) ; LVDS ; 0 s ; 0 s ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; -; ETH_TX_p(n) ; LVDS ; 0 s ; 0 s ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; 0.976 V ; -0.976 V ; - ; - ; - ; - ; 4.59e-11 s ; 4.4e-11 s ; Yes ; Yes ; -+----------------------+-------------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+-----------------------------------------------------------------------------------------------------+ -; Setup Transfers ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 17627 ; 0 ; 146 ; 0 ; -; CLKUSR_100 ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLK_50_B2H ; 51736 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLK_50_B2H ; 102 ; 0 ; 0 ; 0 ; -; altera_reserved_tck ; CLKUSR_100 ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLKUSR_100 ; 91 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLKUSR_100 ; 282011 ; 0 ; 0 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[0]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[1]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[2]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[3]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps_ref_clock ; 0 ; 4 ; 0 ; 0 ; -; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps_ref_clock ; 0 ; 88 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_0 ; u0|emif_a10_hps_ref_clock ; 10 ; 10 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_1 ; u0|emif_a10_hps_ref_clock ; 8 ; 8 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_2 ; u0|emif_a10_hps_ref_clock ; 12 ; 12 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_3 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_4 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_5 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_6 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-----------------------------------------------------------------------------------------------------+ -; Hold Transfers ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 17627 ; 0 ; 146 ; 0 ; -; CLKUSR_100 ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLK_50_B2H ; 51736 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLK_50_B2H ; 102 ; 0 ; 0 ; 0 ; -; altera_reserved_tck ; CLKUSR_100 ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLKUSR_100 ; 91 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLKUSR_100 ; 282011 ; 0 ; 0 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[0]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[1]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[2]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_ref_clock ; DDR4H_DQS[3]_IN ; 9 ; 0 ; 9 ; 0 ; -; u0|emif_a10_hps_vco_clk_0 ; u0|emif_a10_hps_ref_clock ; 0 ; 4 ; 0 ; 0 ; -; u0|emif_a10_hps_vco_clk_1 ; u0|emif_a10_hps_ref_clock ; 0 ; 88 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_0 ; u0|emif_a10_hps_ref_clock ; 10 ; 10 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_1 ; u0|emif_a10_hps_ref_clock ; 8 ; 8 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_2 ; u0|emif_a10_hps_ref_clock ; 12 ; 12 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_3 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_4 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_5 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -; u0|emif_a10_hps_wf_clk_6 ; u0|emif_a10_hps_ref_clock ; 22 ; 22 ; 0 ; 0 ; -+---------------------------+---------------------------+------------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-----------------------------------------------------------------------------------------+ -; Recovery Transfers ; -+---------------------+---------------------+------------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+------------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 185 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLK_50_B2H ; 703 ; 0 ; 0 ; 0 ; -; altera_reserved_tck ; CLKUSR_100 ; false path ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLKUSR_100 ; 6464 ; 0 ; 0 ; 0 ; -+---------------------+---------------------+------------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-----------------------------------------------------------------------------------------+ -; Removal Transfers ; -+---------------------+---------------------+------------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+------------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 185 ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; -; CLK_50_B2H ; CLK_50_B2H ; 703 ; 0 ; 0 ; 0 ; -; altera_reserved_tck ; CLKUSR_100 ; false path ; 0 ; 0 ; 0 ; -; CLKUSR_100 ; CLKUSR_100 ; 6464 ; 0 ; 0 ; 0 ; -+---------------------+---------------------+------------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+------------------------------------------------+ -; Unconstrained Paths Summary ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 2 ; 2 ; -; Unconstrained Input Ports ; 8 ; 8 ; -; Unconstrained Input Port Paths ; 173 ; 173 ; -; Unconstrained Output Ports ; 21 ; 21 ; -; Unconstrained Output Port Paths ; 28 ; 28 ; -+---------------------------------+-------+------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Status Summary ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------+---------------+ -; Target ; Clock ; Type ; Status ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------+---------------+ -; CLKUSR_100 ; CLKUSR_100 ; Base ; Constrained ; -; CLK_50_B2H ; CLK_50_B2H ; Base ; Constrained ; -; DDR4H_DQS[0] ; DDR4H_DQS[0]_IN ; Base ; Constrained ; -; DDR4H_DQS[1] ; DDR4H_DQS[1]_IN ; Base ; Constrained ; -; DDR4H_DQS[2] ; DDR4H_DQS[2]_IN ; Base ; Constrained ; -; DDR4H_DQS[3] ; DDR4H_DQS[3]_IN ; Base ; Constrained ; -; DDR4H_REFCLK_p ; u0|emif_a10_hps_ref_clock ; Base ; Constrained ; -; a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ ; ; Base ; Unconstrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_0 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_2 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_1 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_3 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[1].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_4 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[2].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_5 ; Generated ; Constrained ; -; a10s_ghrd:u0|a10s_ghrd_altera_emif_a10_hps_181_oeawlci:emif_a10_hps|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq:arch|a10s_ghrd_altera_emif_arch_nf_181_ccplvsq_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~out_phy_reg ; u0|emif_a10_hps_wf_clk_6 ; Generated ; Constrained ; -; a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; ; Base ; Unconstrained ; -; altera_reserved_tck ; altera_reserved_tck ; Base ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|loaden[0] ; u0|emif_a10_hps_phy_clk_0 ; Generated ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0] ; u0|emif_a10_hps_phy_clk_l_0 ; Generated ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|vcoph[0] ; u0|emif_a10_hps_vco_clk_0 ; Generated ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0] ; u0|emif_a10_hps_phy_clk_1 ; Generated ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0] ; u0|emif_a10_hps_phy_clk_l_1 ; Generated ; Constrained ; -; u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|vcoph[0] ; u0|emif_a10_hps_vco_clk_1 ; Generated ; Constrained ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------+---------------+ - - -+--------------------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+-----------------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+-----------------------+--------------------------------------------------------------------------------------+ -; FPGA_I2C_SDA ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_ntrst ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tdi ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tms ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-----------------------+--------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+---------------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+---------------------+---------------------------------------------------------------------------------------+ -; FPGA_I2C_SCL ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; FPGA_I2C_SDA ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_DP ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_DP ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tdo ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+---------------------+---------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+-----------------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+-----------------------+--------------------------------------------------------------------------------------+ -; FPGA_I2C_SDA ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_ntrst ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tdi ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tms ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-----------------------+--------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+---------------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+---------------------+---------------------------------------------------------------------------------------+ -; FPGA_I2C_SCL ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; FPGA_I2C_SDA ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_DP ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX0_D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_DP ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; HEX1_D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; altera_reserved_tdo ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+---------------------+---------------------------------------------------------------------------------------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Timing Analyzer - Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition - Info: Processing started: Mon Dec 16 14:06:52 2019 -Info: Command: quartus_sta a10s -c a10s -Info: qsta_default_script.tcl version: #1 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected -Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 100 degrees C -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 30MHz - Info (332166): if { [string equal quartus_fit $::TimeQuestInfo(nameofexecutable)] } { set_max_delay -to [get_ports { altera_reserved_tdo } ] 0 } - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Info (332104): Reading SDC File: 'a10s_ghrd/altera_emif_arch_nf_181/synth/a10s_ghrd_altera_emif_arch_nf_181_ccplvsq.sdc' -Info (332151): Clock uncertainty is not calculated until you update the timing netlist. -Info: Initializing DDR database for CORE a10s_ghrd_altera_emif_arch_nf_181_ccplvsq -Info: Finding port-to-pin mapping for CORE: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq INSTANCE: u0|emif_a10_hps -Info (332104): Reading SDC File: 'a10s_ghrd/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_reset_controller_181/synth/altera_reset_controller.sdc' -Info (332104): Reading SDC File: 'a10s_ghrd/altera_avalon_mm_clock_crossing_bridge_181/synth/altera_avalon_dc_fifo.sdc' -Info (332104): Reading SDC File: 'a10s.sdc' -Warning (332174): Ignored filter at a10s.sdc(12): CLK_50_B3H could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 -Warning (332049): Ignored create_clock at a10s.sdc(12): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 - Info (332050): create_clock -period 20 [get_ports CLK_50_B3H] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 12 -Warning (332049): Ignored create_clock at a10s.sdc(15): Incorrect assignment for clock. Source node: DDR4H_REFCLK_p already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 15 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4H_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 15 -Warning (332174): Ignored filter at a10s.sdc(16): PCIE_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 -Warning (332049): Ignored create_clock at a10s.sdc(16): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 - Info (332050): create_clock -period "100.000000 MHz" [get_ports PCIE_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 16 -Warning (332174): Ignored filter at a10s.sdc(17): DDR4A_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 -Warning (332049): Ignored create_clock at a10s.sdc(17): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4A_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 17 -Warning (332174): Ignored filter at a10s.sdc(18): DDR4B_REFCLK_p could not be matched with a port File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 -Warning (332049): Ignored create_clock at a10s.sdc(18): Argument is an empty collection File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 - Info (332050): create_clock -period "266.666 MHz" [get_ports DDR4B_REFCLK_p] File: D:/Tresorit/Robin/Studium/12_Semester/M_A/HAN_Quartus/a10s_ghrd/a10s.sdc Line: 18 -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332099): You called derive_pll_clocks. User-defined clock found on pll: u0|emif_a10_hps|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. -Info (332151): Clock uncertainty is not calculated until you update the timing netlist. -Warning (332060): Node: a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|I2C_WRITE_POINTER:wpt|CNT[5] is being clocked by a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_TEMP_I2C:i2c1|CLOCKMEM:k400|CK_1HZ -Warning (332060): Node: a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out was determined to be a clock but was found without an associated clock assignment. - Info (13166): Latch a10s_ghrd:u0|HAN_FanTempControll:fancmd|TEMP_FAN_LOOP:lp|FAN_ONOFF:OL|rTEMP_BUSY~1 is being clocked by a10s_ghrd:u0|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out -Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o - Info (332098): Cell: u0|emif_a10_hps|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o -Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. -Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Analyzing Slow 900mV 100C Model -Info (332146): Worst-case setup slack is 2.534 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 2.534 0.000 CLKUSR_100 - Info (332119): 11.228 0.000 altera_reserved_tck - Info (332119): 15.150 0.000 CLK_50_B2H -Info (332146): Worst-case hold slack is 0.046 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.046 0.000 altera_reserved_tck - Info (332119): 0.052 0.000 CLKUSR_100 - Info (332119): 0.052 0.000 CLK_50_B2H -Info (332146): Worst-case recovery slack is 4.273 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 4.273 0.000 CLKUSR_100 - Info (332119): 17.058 0.000 CLK_50_B2H - Info (332119): 30.224 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.350 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.350 0.000 CLKUSR_100 - Info (332119): 0.555 0.000 CLK_50_B2H - Info (332119): 0.813 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 0.182 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.182 0.000 DDR4H_DQS[0]_IN - Info (332119): 0.182 0.000 DDR4H_DQS[1]_IN - Info (332119): 0.183 0.000 DDR4H_DQS[2]_IN - Info (332119): 0.183 0.000 DDR4H_DQS[3]_IN - Info (332119): 0.376 0.000 u0|emif_a10_hps_wf_clk_6 - Info (332119): 0.377 0.000 u0|emif_a10_hps_wf_clk_3 - Info (332119): 0.377 0.000 u0|emif_a10_hps_wf_clk_4 - Info (332119): 0.377 0.000 u0|emif_a10_hps_wf_clk_5 - Info (332119): 0.456 0.000 u0|emif_a10_hps_wf_clk_0 - Info (332119): 0.461 0.000 u0|emif_a10_hps_wf_clk_2 - Info (332119): 0.462 0.000 u0|emif_a10_hps_wf_clk_1 - Info (332119): 0.464 0.000 u0|emif_a10_hps_vco_clk_0 - Info (332119): 0.464 0.000 u0|emif_a10_hps_vco_clk_1 - Info (332119): 0.795 0.000 u0|emif_a10_hps_phy_clk_0 - Info (332119): 0.795 0.000 u0|emif_a10_hps_phy_clk_1 - Info (332119): 0.798 0.000 u0|emif_a10_hps_phy_clk_l_0 - Info (332119): 0.798 0.000 u0|emif_a10_hps_phy_clk_l_1 - Info (332119): 1.801 0.000 u0|emif_a10_hps_ref_clock - Info (332119): 4.430 0.000 CLKUSR_100 - Info (332119): 9.573 0.000 CLK_50_B2H - Info (332119): 16.536 0.000 altera_reserved_tck -Info (332163): Slow 900mV 100C Model Net Delay Summary - Info (332163): - Info (332163): Name Slack Req Actual From To Type - Info (332163): ============= ====== ====== ====== =============== =============== ==== - Info (332163): set_net_delay 2.831 8.000 5.169 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 2.877 8.000 5.123 [get_registers *] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.440 8.000 0.560 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.611 8.000 0.389 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max -Info (332114): Report Metastability: Found 97 synchronizer chains. - Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 97 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 - Info (332114): Worst Case Available Settling Time: 7.281 ns - Info (332114): - Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 -Info: Initializing DDR database for CORE a10s_ghrd_altera_emif_arch_nf_181_ccplvsq -Info: Finding port-to-pin mapping for CORE: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq INSTANCE: u0|emif_a10_hps -Info: Core: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq - Instance: u0|emif_a10_hps -Info: setup hold -Info: Address/Command (Slow 900mV 100C Model) | 0.206 0.206 -Info: Core (Slow 900mV 100C Model) | -- -- -Info: Core Recovery/Removal (Slow 900mV 100C Model) | -- -- -Info: DQS Gating (Slow 900mV 100C Model) | 0.62 0.62 -Info: Read Capture (Slow 900mV 100C Model) | 0.043 0.043 -Info: Write (Slow 900mV 100C Model) | 0.043 0.043 -Info: Write Levelling (Slow 900mV 100C Model) | 0.158 0.158 -Info: Analyzing Slow 900mV 0C Model -Info (332146): Worst-case setup slack is 2.924 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 2.924 0.000 CLKUSR_100 - Info (332119): 11.517 0.000 altera_reserved_tck - Info (332119): 15.501 0.000 CLK_50_B2H -Info (332146): Worst-case hold slack is 0.026 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.026 0.000 CLKUSR_100 - Info (332119): 0.038 0.000 altera_reserved_tck - Info (332119): 0.047 0.000 CLK_50_B2H -Info (332146): Worst-case recovery slack is 4.759 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 4.759 0.000 CLKUSR_100 - Info (332119): 17.257 0.000 CLK_50_B2H - Info (332119): 30.393 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.344 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.344 0.000 CLKUSR_100 - Info (332119): 0.499 0.000 CLK_50_B2H - Info (332119): 0.758 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 0.143 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.143 0.000 DDR4H_DQS[2]_IN - Info (332119): 0.143 0.000 DDR4H_DQS[3]_IN - Info (332119): 0.144 0.000 DDR4H_DQS[0]_IN - Info (332119): 0.144 0.000 DDR4H_DQS[1]_IN - Info (332119): 0.395 0.000 u0|emif_a10_hps_wf_clk_3 - Info (332119): 0.395 0.000 u0|emif_a10_hps_wf_clk_4 - Info (332119): 0.395 0.000 u0|emif_a10_hps_wf_clk_6 - Info (332119): 0.396 0.000 u0|emif_a10_hps_wf_clk_5 - Info (332119): 0.432 0.000 u0|emif_a10_hps_wf_clk_0 - Info (332119): 0.432 0.000 u0|emif_a10_hps_wf_clk_1 - Info (332119): 0.432 0.000 u0|emif_a10_hps_wf_clk_2 - Info (332119): 0.465 0.000 u0|emif_a10_hps_vco_clk_0 - Info (332119): 0.465 0.000 u0|emif_a10_hps_vco_clk_1 - Info (332119): 0.773 0.000 u0|emif_a10_hps_phy_clk_0 - Info (332119): 0.773 0.000 u0|emif_a10_hps_phy_clk_1 - Info (332119): 0.776 0.000 u0|emif_a10_hps_phy_clk_l_0 - Info (332119): 0.776 0.000 u0|emif_a10_hps_phy_clk_l_1 - Info (332119): 1.805 0.000 u0|emif_a10_hps_ref_clock - Info (332119): 4.529 0.000 CLKUSR_100 - Info (332119): 9.510 0.000 CLK_50_B2H - Info (332119): 16.469 0.000 altera_reserved_tck -Info (332163): Slow 900mV 0C Model Net Delay Summary - Info (332163): - Info (332163): Name Slack Req Actual From To Type - Info (332163): ============= ====== ====== ====== =============== =============== ==== - Info (332163): set_net_delay 3.304 8.000 4.696 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 3.388 8.000 4.612 [get_registers *] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.495 8.000 0.505 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.647 8.000 0.353 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max -Info (332114): Report Metastability: Found 97 synchronizer chains. - Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 97 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 - Info (332114): Worst Case Available Settling Time: 7.517 ns - Info (332114): - Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 -Info: Initializing DDR database for CORE a10s_ghrd_altera_emif_arch_nf_181_ccplvsq -Info: Finding port-to-pin mapping for CORE: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq INSTANCE: u0|emif_a10_hps -Info: Core: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq - Instance: u0|emif_a10_hps -Info: setup hold -Info: Address/Command (Slow 900mV 0C Model) | 0.206 0.206 -Info: Core (Slow 900mV 0C Model) | -- -- -Info: Core Recovery/Removal (Slow 900mV 0C Model) | -- -- -Info: DQS Gating (Slow 900mV 0C Model) | 0.62 0.62 -Info: Read Capture (Slow 900mV 0C Model) | 0.043 0.043 -Info: Write (Slow 900mV 0C Model) | 0.043 0.043 -Info: Write Levelling (Slow 900mV 0C Model) | 0.158 0.158 -Info: Analyzing Fast 900mV 100C Model -Info (332146): Worst-case setup slack is 4.204 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 4.204 0.000 CLKUSR_100 - Info (332119): 12.766 0.000 altera_reserved_tck - Info (332119): 16.519 0.000 CLK_50_B2H -Info (332146): Worst-case hold slack is 0.014 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.014 0.000 altera_reserved_tck - Info (332119): 0.017 0.000 CLKUSR_100 - Info (332119): 0.018 0.000 CLK_50_B2H -Info (332146): Worst-case recovery slack is 5.723 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 5.723 0.000 CLKUSR_100 - Info (332119): 17.776 0.000 CLK_50_B2H - Info (332119): 31.083 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.194 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.194 0.000 CLKUSR_100 - Info (332119): 0.375 0.000 CLK_50_B2H - Info (332119): 0.526 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 0.203 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.203 0.000 DDR4H_DQS[2]_IN - Info (332119): 0.203 0.000 DDR4H_DQS[3]_IN - Info (332119): 0.204 0.000 DDR4H_DQS[0]_IN - Info (332119): 0.204 0.000 DDR4H_DQS[1]_IN - Info (332119): 0.382 0.000 u0|emif_a10_hps_wf_clk_3 - Info (332119): 0.382 0.000 u0|emif_a10_hps_wf_clk_4 - Info (332119): 0.382 0.000 u0|emif_a10_hps_wf_clk_5 - Info (332119): 0.382 0.000 u0|emif_a10_hps_wf_clk_6 - Info (332119): 0.454 0.000 u0|emif_a10_hps_wf_clk_0 - Info (332119): 0.457 0.000 u0|emif_a10_hps_wf_clk_1 - Info (332119): 0.457 0.000 u0|emif_a10_hps_wf_clk_2 - Info (332119): 0.466 0.000 u0|emif_a10_hps_vco_clk_0 - Info (332119): 0.466 0.000 u0|emif_a10_hps_vco_clk_1 - Info (332119): 0.885 0.000 u0|emif_a10_hps_phy_clk_0 - Info (332119): 0.885 0.000 u0|emif_a10_hps_phy_clk_1 - Info (332119): 0.886 0.000 u0|emif_a10_hps_phy_clk_l_0 - Info (332119): 0.886 0.000 u0|emif_a10_hps_phy_clk_l_1 - Info (332119): 1.828 0.000 u0|emif_a10_hps_ref_clock - Info (332119): 4.488 0.000 CLKUSR_100 - Info (332119): 9.675 0.000 CLK_50_B2H - Info (332119): 16.469 0.000 altera_reserved_tck -Info (332163): Fast 900mV 100C Model Net Delay Summary - Info (332163): - Info (332163): Name Slack Req Actual From To Type - Info (332163): ============= ====== ====== ====== =============== =============== ==== - Info (332163): set_net_delay 3.900 8.000 4.100 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 3.948 8.000 4.052 [get_registers *] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.615 8.000 0.385 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.747 8.000 0.253 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max -Info (332114): Report Metastability: Found 97 synchronizer chains. - Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 97 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 - Info (332114): Worst Case Available Settling Time: 7.796 ns - Info (332114): - Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 -Info: Initializing DDR database for CORE a10s_ghrd_altera_emif_arch_nf_181_ccplvsq -Info: Finding port-to-pin mapping for CORE: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq INSTANCE: u0|emif_a10_hps -Info: Core: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq - Instance: u0|emif_a10_hps -Info: setup hold -Info: Address/Command (Fast 900mV 100C Model) | 0.206 0.206 -Info: Core (Fast 900mV 100C Model) | -- -- -Info: Core Recovery/Removal (Fast 900mV 100C Model) | -- -- -Info: DQS Gating (Fast 900mV 100C Model) | 0.62 0.62 -Info: Read Capture (Fast 900mV 100C Model) | 0.043 0.043 -Info: Write (Fast 900mV 100C Model) | 0.043 0.043 -Info: Write Levelling (Fast 900mV 100C Model) | 0.158 0.158 -Info: Analyzing Fast 900mV 0C Model -Info (332146): Worst-case setup slack is 5.295 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 5.295 0.000 CLKUSR_100 - Info (332119): 13.449 0.000 altera_reserved_tck - Info (332119): 17.133 0.000 CLK_50_B2H -Info (332146): Worst-case hold slack is 0.013 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.013 0.000 altera_reserved_tck - Info (332119): 0.015 0.000 CLKUSR_100 - Info (332119): 0.017 0.000 CLK_50_B2H -Info (332146): Worst-case recovery slack is 6.498 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 6.498 0.000 CLKUSR_100 - Info (332119): 18.224 0.000 CLK_50_B2H - Info (332119): 31.500 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.160 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.160 0.000 CLKUSR_100 - Info (332119): 0.284 0.000 CLK_50_B2H - Info (332119): 0.411 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 0.205 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 0.205 0.000 DDR4H_DQS[0]_IN - Info (332119): 0.206 0.000 DDR4H_DQS[1]_IN - Info (332119): 0.206 0.000 DDR4H_DQS[2]_IN - Info (332119): 0.206 0.000 DDR4H_DQS[3]_IN - Info (332119): 0.396 0.000 u0|emif_a10_hps_wf_clk_3 - Info (332119): 0.396 0.000 u0|emif_a10_hps_wf_clk_4 - Info (332119): 0.396 0.000 u0|emif_a10_hps_wf_clk_5 - Info (332119): 0.396 0.000 u0|emif_a10_hps_wf_clk_6 - Info (332119): 0.461 0.000 u0|emif_a10_hps_wf_clk_0 - Info (332119): 0.463 0.000 u0|emif_a10_hps_wf_clk_1 - Info (332119): 0.463 0.000 u0|emif_a10_hps_wf_clk_2 - Info (332119): 0.466 0.000 u0|emif_a10_hps_vco_clk_0 - Info (332119): 0.466 0.000 u0|emif_a10_hps_vco_clk_1 - Info (332119): 0.889 0.000 u0|emif_a10_hps_phy_clk_0 - Info (332119): 0.889 0.000 u0|emif_a10_hps_phy_clk_1 - Info (332119): 0.889 0.000 u0|emif_a10_hps_phy_clk_l_0 - Info (332119): 0.889 0.000 u0|emif_a10_hps_phy_clk_l_1 - Info (332119): 1.836 0.000 u0|emif_a10_hps_ref_clock - Info (332119): 4.456 0.000 CLKUSR_100 - Info (332119): 9.669 0.000 CLK_50_B2H - Info (332119): 16.494 0.000 altera_reserved_tck -Info (332163): Fast 900mV 0C Model Net Delay Summary - Info (332163): - Info (332163): Name Slack Req Actual From To Type - Info (332163): ============= ====== ====== ====== =============== =============== ==== - Info (332163): set_net_delay 4.648 8.000 3.352 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 4.773 8.000 3.227 [get_registers *] - Info (332163): [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.703 8.000 0.297 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max - Info (332163): - Info (332163): set_net_delay 7.807 8.000 0.193 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] - Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] - Info (332163): max -Info (332114): Report Metastability: Found 97 synchronizer chains. - Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 97 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.433 - Info (332114): Worst Case Available Settling Time: 8.172 ns - Info (332114): - Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 -Info: Initializing DDR database for CORE a10s_ghrd_altera_emif_arch_nf_181_ccplvsq -Info: Finding port-to-pin mapping for CORE: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq INSTANCE: u0|emif_a10_hps -Info: Core: a10s_ghrd_altera_emif_arch_nf_181_ccplvsq - Instance: u0|emif_a10_hps -Info: setup hold -Info: Address/Command (Fast 900mV 0C Model) | 0.206 0.206 -Info: Core (Fast 900mV 0C Model) | -- -- -Info: Core Recovery/Removal (Fast 900mV 0C Model) | -- -- -Info: DQS Gating (Fast 900mV 0C Model) | 0.62 0.62 -Info: Read Capture (Fast 900mV 0C Model) | 0.043 0.043 -Info: Write (Fast 900mV 0C Model) | 0.043 0.043 -Info: Write Levelling (Fast 900mV 0C Model) | 0.158 0.158 -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 8333 megabytes - Info: Processing ended: Mon Dec 16 14:07:35 2019 - Info: Elapsed time: 00:00:43 - Info: Total CPU time (on all processors): 00:01:28 - - diff --git a/fpga/HAN_A10rsyocto/output_files/a10s.sta.summary b/fpga/HAN_A10rsyocto/output_files/a10s.sta.summary deleted file mode 100644 index 0a7b081..0000000 --- a/fpga/HAN_A10rsyocto/output_files/a10s.sta.summary +++ /dev/null @@ -1,584 +0,0 @@ ------------------------------------------------------------- -Timing Analyzer Summary ------------------------------------------------------------- - -Type : Slow 900mV 100C Model Setup 'CLKUSR_100' -Slack : 2.534 -TNS : 0.000 - -Type : Slow 900mV 100C Model Setup 'altera_reserved_tck' -Slack : 11.228 -TNS : 0.000 - -Type : Slow 900mV 100C Model Setup 'CLK_50_B2H' -Slack : 15.150 -TNS : 0.000 - -Type : Slow 900mV 100C Model Hold 'altera_reserved_tck' -Slack : 0.046 -TNS : 0.000 - -Type : Slow 900mV 100C Model Hold 'CLKUSR_100' -Slack : 0.052 -TNS : 0.000 - -Type : Slow 900mV 100C Model Hold 'CLK_50_B2H' -Slack : 0.052 -TNS : 0.000 - -Type : Slow 900mV 100C Model Recovery 'CLKUSR_100' -Slack : 4.273 -TNS : 0.000 - -Type : Slow 900mV 100C Model Recovery 'CLK_50_B2H' -Slack : 17.058 -TNS : 0.000 - -Type : Slow 900mV 100C Model Recovery 'altera_reserved_tck' -Slack : 30.224 -TNS : 0.000 - -Type : Slow 900mV 100C Model Removal 'CLKUSR_100' -Slack : 0.350 -TNS : 0.000 - -Type : Slow 900mV 100C Model Removal 'CLK_50_B2H' -Slack : 0.555 -TNS : 0.000 - -Type : Slow 900mV 100C Model Removal 'altera_reserved_tck' -Slack : 0.813 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[0]_IN' -Slack : 0.182 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[1]_IN' -Slack : 0.182 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[2]_IN' -Slack : 0.183 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[3]_IN' -Slack : 0.183 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_6' -Slack : 0.376 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_3' -Slack : 0.377 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_4' -Slack : 0.377 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_5' -Slack : 0.377 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_0' -Slack : 0.456 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_2' -Slack : 0.461 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_1' -Slack : 0.462 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_0' -Slack : 0.464 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_1' -Slack : 0.464 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_0' -Slack : 0.795 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_1' -Slack : 0.795 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_0' -Slack : 0.798 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_1' -Slack : 0.798 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_ref_clock' -Slack : 1.801 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'CLKUSR_100' -Slack : 4.430 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'CLK_50_B2H' -Slack : 9.573 -TNS : 0.000 - -Type : Slow 900mV 100C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 16.536 -TNS : 0.000 - -Type : Slow 900mV 100C Model Net Delay 'set_net_delay' -Slack : 2.831 - -Type : Slow 900mV 100C Model Net Delay 'set_net_delay' -Slack : 2.877 - -Type : Slow 900mV 100C Model Net Delay 'set_net_delay' -Slack : 7.440 - -Type : Slow 900mV 100C Model Net Delay 'set_net_delay' -Slack : 7.611 - -Type : Slow 900mV 0C Model Setup 'CLKUSR_100' -Slack : 2.924 -TNS : 0.000 - -Type : Slow 900mV 0C Model Setup 'altera_reserved_tck' -Slack : 11.517 -TNS : 0.000 - -Type : Slow 900mV 0C Model Setup 'CLK_50_B2H' -Slack : 15.501 -TNS : 0.000 - -Type : Slow 900mV 0C Model Hold 'CLKUSR_100' -Slack : 0.026 -TNS : 0.000 - -Type : Slow 900mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.038 -TNS : 0.000 - -Type : Slow 900mV 0C Model Hold 'CLK_50_B2H' -Slack : 0.047 -TNS : 0.000 - -Type : Slow 900mV 0C Model Recovery 'CLKUSR_100' -Slack : 4.759 -TNS : 0.000 - -Type : Slow 900mV 0C Model Recovery 'CLK_50_B2H' -Slack : 17.257 -TNS : 0.000 - -Type : Slow 900mV 0C Model Recovery 'altera_reserved_tck' -Slack : 30.393 -TNS : 0.000 - -Type : Slow 900mV 0C Model Removal 'CLKUSR_100' -Slack : 0.344 -TNS : 0.000 - -Type : Slow 900mV 0C Model Removal 'CLK_50_B2H' -Slack : 0.499 -TNS : 0.000 - -Type : Slow 900mV 0C Model Removal 'altera_reserved_tck' -Slack : 0.758 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[2]_IN' -Slack : 0.143 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[3]_IN' -Slack : 0.143 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[0]_IN' -Slack : 0.144 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[1]_IN' -Slack : 0.144 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_3' -Slack : 0.395 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_4' -Slack : 0.395 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_6' -Slack : 0.395 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_5' -Slack : 0.396 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_0' -Slack : 0.432 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_1' -Slack : 0.432 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_2' -Slack : 0.432 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_0' -Slack : 0.465 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_1' -Slack : 0.465 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_0' -Slack : 0.773 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_1' -Slack : 0.773 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_0' -Slack : 0.776 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_1' -Slack : 0.776 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_ref_clock' -Slack : 1.805 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'CLKUSR_100' -Slack : 4.529 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'CLK_50_B2H' -Slack : 9.510 -TNS : 0.000 - -Type : Slow 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 16.469 -TNS : 0.000 - -Type : Slow 900mV 0C Model Net Delay 'set_net_delay' -Slack : 3.304 - -Type : Slow 900mV 0C Model Net Delay 'set_net_delay' -Slack : 3.388 - -Type : Slow 900mV 0C Model Net Delay 'set_net_delay' -Slack : 7.495 - -Type : Slow 900mV 0C Model Net Delay 'set_net_delay' -Slack : 7.647 - -Type : Fast 900mV 100C Model Setup 'CLKUSR_100' -Slack : 4.204 -TNS : 0.000 - -Type : Fast 900mV 100C Model Setup 'altera_reserved_tck' -Slack : 12.766 -TNS : 0.000 - -Type : Fast 900mV 100C Model Setup 'CLK_50_B2H' -Slack : 16.519 -TNS : 0.000 - -Type : Fast 900mV 100C Model Hold 'altera_reserved_tck' -Slack : 0.014 -TNS : 0.000 - -Type : Fast 900mV 100C Model Hold 'CLKUSR_100' -Slack : 0.017 -TNS : 0.000 - -Type : Fast 900mV 100C Model Hold 'CLK_50_B2H' -Slack : 0.018 -TNS : 0.000 - -Type : Fast 900mV 100C Model Recovery 'CLKUSR_100' -Slack : 5.723 -TNS : 0.000 - -Type : Fast 900mV 100C Model Recovery 'CLK_50_B2H' -Slack : 17.776 -TNS : 0.000 - -Type : Fast 900mV 100C Model Recovery 'altera_reserved_tck' -Slack : 31.083 -TNS : 0.000 - -Type : Fast 900mV 100C Model Removal 'CLKUSR_100' -Slack : 0.194 -TNS : 0.000 - -Type : Fast 900mV 100C Model Removal 'CLK_50_B2H' -Slack : 0.375 -TNS : 0.000 - -Type : Fast 900mV 100C Model Removal 'altera_reserved_tck' -Slack : 0.526 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[2]_IN' -Slack : 0.203 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[3]_IN' -Slack : 0.203 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[0]_IN' -Slack : 0.204 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'DDR4H_DQS[1]_IN' -Slack : 0.204 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_3' -Slack : 0.382 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_4' -Slack : 0.382 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_5' -Slack : 0.382 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_6' -Slack : 0.382 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_0' -Slack : 0.454 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_1' -Slack : 0.457 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_2' -Slack : 0.457 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_0' -Slack : 0.466 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_1' -Slack : 0.466 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_0' -Slack : 0.885 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_1' -Slack : 0.885 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_0' -Slack : 0.886 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_1' -Slack : 0.886 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'u0|emif_a10_hps_ref_clock' -Slack : 1.828 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'CLKUSR_100' -Slack : 4.488 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'CLK_50_B2H' -Slack : 9.675 -TNS : 0.000 - -Type : Fast 900mV 100C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 16.469 -TNS : 0.000 - -Type : Fast 900mV 100C Model Net Delay 'set_net_delay' -Slack : 3.900 - -Type : Fast 900mV 100C Model Net Delay 'set_net_delay' -Slack : 3.948 - -Type : Fast 900mV 100C Model Net Delay 'set_net_delay' -Slack : 7.615 - -Type : Fast 900mV 100C Model Net Delay 'set_net_delay' -Slack : 7.747 - -Type : Fast 900mV 0C Model Setup 'CLKUSR_100' -Slack : 5.295 -TNS : 0.000 - -Type : Fast 900mV 0C Model Setup 'altera_reserved_tck' -Slack : 13.449 -TNS : 0.000 - -Type : Fast 900mV 0C Model Setup 'CLK_50_B2H' -Slack : 17.133 -TNS : 0.000 - -Type : Fast 900mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.013 -TNS : 0.000 - -Type : Fast 900mV 0C Model Hold 'CLKUSR_100' -Slack : 0.015 -TNS : 0.000 - -Type : Fast 900mV 0C Model Hold 'CLK_50_B2H' -Slack : 0.017 -TNS : 0.000 - -Type : Fast 900mV 0C Model Recovery 'CLKUSR_100' -Slack : 6.498 -TNS : 0.000 - -Type : Fast 900mV 0C Model Recovery 'CLK_50_B2H' -Slack : 18.224 -TNS : 0.000 - -Type : Fast 900mV 0C Model Recovery 'altera_reserved_tck' -Slack : 31.500 -TNS : 0.000 - -Type : Fast 900mV 0C Model Removal 'CLKUSR_100' -Slack : 0.160 -TNS : 0.000 - -Type : Fast 900mV 0C Model Removal 'CLK_50_B2H' -Slack : 0.284 -TNS : 0.000 - -Type : Fast 900mV 0C Model Removal 'altera_reserved_tck' -Slack : 0.411 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[0]_IN' -Slack : 0.205 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[1]_IN' -Slack : 0.206 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[2]_IN' -Slack : 0.206 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'DDR4H_DQS[3]_IN' -Slack : 0.206 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_3' -Slack : 0.396 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_4' -Slack : 0.396 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_5' -Slack : 0.396 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_6' -Slack : 0.396 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_0' -Slack : 0.461 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_1' -Slack : 0.463 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_wf_clk_2' -Slack : 0.463 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_0' -Slack : 0.466 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_vco_clk_1' -Slack : 0.466 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_0' -Slack : 0.889 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_1' -Slack : 0.889 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_0' -Slack : 0.889 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_phy_clk_l_1' -Slack : 0.889 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'u0|emif_a10_hps_ref_clock' -Slack : 1.836 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'CLKUSR_100' -Slack : 4.456 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'CLK_50_B2H' -Slack : 9.669 -TNS : 0.000 - -Type : Fast 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 16.494 -TNS : 0.000 - -Type : Fast 900mV 0C Model Net Delay 'set_net_delay' -Slack : 4.648 - -Type : Fast 900mV 0C Model Net Delay 'set_net_delay' -Slack : 4.773 - -Type : Fast 900mV 0C Model Net Delay 'set_net_delay' -Slack : 7.703 - -Type : Fast 900mV 0C Model Net Delay 'set_net_delay' -Slack : 7.807 - ------------------------------------------------------------- -Info: see the "DDR report" for DDR timing results ------------------------------------------------------------- ------------------------------------------------------------- diff --git a/fpga/HAN_A10rsyocto/output_files/socfpga.core.rbf b/fpga/HAN_A10rsyocto/output_files/socfpga.core.rbf deleted file mode 100644 index df33a11..0000000 Binary files a/fpga/HAN_A10rsyocto/output_files/socfpga.core.rbf and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/output_files/socfpga.periph.rbf b/fpga/HAN_A10rsyocto/output_files/socfpga.periph.rbf deleted file mode 100644 index 0cbbc32..0000000 Binary files a/fpga/HAN_A10rsyocto/output_files/socfpga.periph.rbf and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/output_files/sof_to_rbf.bat b/fpga/HAN_A10rsyocto/output_files/sof_to_rbf.bat deleted file mode 100644 index 966c0c3..0000000 --- a/fpga/HAN_A10rsyocto/output_files/sof_to_rbf.bat +++ /dev/null @@ -1,2 +0,0 @@ -%QUARTUS_ROOTDIR%\\bin64\\quartus_cpf -c -o bitstream_compression=off a10s.sof socfpga.rbf -pause diff --git a/fpga/HAN_A10rsyocto/socfpga_arria10_a10s_vnc.dtb b/fpga/HAN_A10rsyocto/socfpga_arria10_a10s_vnc.dtb deleted file mode 100644 index 965dd0b..0000000 Binary files a/fpga/HAN_A10rsyocto/socfpga_arria10_a10s_vnc.dtb and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/Makefile b/fpga/HAN_A10rsyocto/software/uboot_bsp/Makefile deleted file mode 100644 index fec8a96..0000000 --- a/fpga/HAN_A10rsyocto/software/uboot_bsp/Makefile +++ /dev/null @@ -1,401 +0,0 @@ -#----------------------------------------------------------------------------- -# TOOLS -#----------------------------------------------------------------------------- - -CAT := cat -CP := cp -rf -CHMOD := chmod -DIFF := diff -DTC := dtc -ECHO := echo -PATCH := patch -MKDIR := mkdir -p -RM := rm -rf -TOUCH := touch -UNTAR := tar xzf - -#----------------------------------------------------------------------------- -# HELPER FUNCTIONS -#----------------------------------------------------------------------------- - -define stamp -@$(MKDIR) $(@D) -@$(TOUCH) $@ -endef - -define untar_recipe -$(UNTAR) $(if $1,$1,$(if $<,$<,$(error ERROR: no input provided to gnu make function untar_recipe))) -endef - - -#----------------------------------------------------------------------------- -# WINDOWS SUPPORT -#----------------------------------------------------------------------------- - -HOSTOS := $(shell uname -o 2>/dev/null | tr [:upper:] [:lower:]) - -ifeq ($(HOSTOS),cygwin) - -# When using UBoot build system on Windows -# use cygwin's GNU make -MAKE := $(shell cygpath -m "/bin/make") -MAKE_ARGS += MAKE=/bin/make - -CYGPATH := $(shell cygpath -m "$(shell which cygpath)") -MAKE_ARGS += CYGPATH=$(CYGPATH) - -UNAME_M := $(shell uname -m) -ifeq ($(UNAME_M),x86_64) -HOST_CROSS_COMPILE := x86_64-w64-mingw32- -else -HOST_CROSS_COMPILE := i686-pc-mingw32- -endif - -MAKE_ARGS += HOSTCC=$(HOST_CROSS_COMPILE)gcc HOSTSTRIP=$(HOST_CROSS_COMPILE)strip - -# Under cygwin, overload the untar_recipe function to use unix stype paths. This is required for cygwin tar -define untar_recipe -$(UNTAR) $(shell cygpath --unix "$(if $1,$1,$(if $<,$<,$(error ERROR: no input provided to gnu make function untar_recipe)))") -endef - -else # if HOSTOS != cygwin - -ifdef WINDIR -$(error ERROR: Windows build of preloader requires cygwin build environment. Ensure this makefile is executed from the SoC EDS Command Shell) -endif -ifdef windir -$(error ERROR: Windows build of preloader requires cygwin build environment. Ensure this makefile is executed from the SoC EDS Command Shell) -endif - -endif # HOSTOS == cygwin - - -#----------------------------------------------------------------------------- -# SETTINGS -#----------------------------------------------------------------------------- - -include config.mk - -#################### -# Static Settings - -DTS := devicetree.dts - -TGZ := $(SOCEDS_DEST_ROOT)/host_tools/altera/bootloaders/u-boot/uboot-socfpga.tar.gz - -PREBUILT_DIR := $(SOCEDS_DEST_ROOT)/host_tools/altera/bootloaders/u-boot/prebuilt - -CROSS_COMPILE := arm-altera-eabi- - -DEVICE_FAMILY := arria10 -#################### - -MKPIMAGE_HEADER_VERSION := 1 - -MAKE_ARGS += CROSS_COMPILE=$(CROSS_COMPILE) - -DTC_ARGS := - -DTB := $(patsubst %.dts,%.dtb,$(DTS)) - -PRELOADER_SRC_DIR := $(patsubst %.tar.gz,%,$(shell basename $(TGZ))) - -UBOOT_SRC_DIR = $(patsubst %.tar.gz,%,$(notdir $(TGZ))) - -UBOOT.ELF := $(UBOOT_SRC_DIR)/u-boot - -UBOOT.BINARY := $(UBOOT_SRC_DIR)/u-boot.bin - -UBOOT.BINARY_W_DTB := u-boot_w_dtb.bin - -UBOOT.MKPIMAGE_BINARY_W_DTB := uboot_w_dtb-mkpimage.bin - -UBOOT.MKPIMAGE_SIGNED_BINARY_W_DTB := uboot_w_dtb-mkpimage-signed.abin - -UBOOT.MKPIMAGE_ENCRYPTED_BINARY_W_DTB := uboot_w_dtb-mkpimage-encrypted.abin - -UBOOT.MKPIMAGE_ENCRYPTED_SIGNED_BINARY_W_DTB := uboot_w_dtb-mkpimage-encrypted-signed.abin - -SOCFPGA_BOARD_CONFIG.QSPI = socfpga_$(DEVICE_FAMILY)_qspi_defconfig -SOCFPGA_BOARD_CONFIG.NAND = socfpga_$(DEVICE_FAMILY)_nand_defconfig -SOCFPGA_BOARD_CONFIG.SDMMC = socfpga_$(DEVICE_FAMILY)_config -SOCFPGA_BOARD_CONFIG := $(SOCFPGA_BOARD_CONFIG.$(BOOT_DEVICE)) - -ifeq ($(SOCFPGA_BOARD_CONFIG),) -$(error ERROR: SOCFPGA_BOARD_CONFIG not set. Check your Settings and Regenerate your Bootloader) -endif - -STAMP_DIR ?= $(UBOOT_SRC_DIR) - -#----------------------------------------------------------------------------- -# TARGETS -#----------------------------------------------------------------------------- - -# On windows, we do not yet support building u-boot. -# Only dtb creation for uboot -# is supported -ifeq ($(HOSTOS),cygwin) -ifneq ($(DISABLE_UBOOT_BUILD),1) -$(error ERROR: DISABLE_UBOOT_BUILD is not set to 1. U-Boot Build is not supported on Windows. Generate your bootloader with --set uboot.disable_uboot_build true) -endif -endif - -.PHONY: all -all: $(DTB) $(UBOOT.MKPIMAGE_BINARY_W_DTB) - -ifeq ($(ENABLE_BOOTLOADER_SIGNING),1) -ifeq ($(ENABLE_BOOTLOADER_ENCRYPTION),1) -UBOOT.SECURE_BINARY := $(UBOOT.MKPIMAGE_ENCRYPTED_SIGNED_BINARY_W_DTB) -UBOOT.SECURE_BINARYx4 := $(patsubst %.abin,%-x4.abin,$(UBOOT.SECURE_BINARY)) -all: $(UBOOT.SECURE_BINARYx4) -endif -endif - -ifneq ($(ENABLE_BOOTLOADER_ENCRYPTION),1) -ifeq ($(ENABLE_BOOTLOADER_SIGNING),1) -UBOOT.SECURE_BINARY := $(UBOOT.MKPIMAGE_SIGNED_BINARY_W_DTB) -UBOOT.SECURE_BINARYx4 := $(patsubst %.abin,%-x4.abin,$(UBOOT.SECURE_BINARY)) -all: $(UBOOT.SECURE_BINARYx4) -endif -endif - -ifneq ($(ENABLE_BOOTLOADER_SIGNING),1) -ifeq ($(ENABLE_BOOTLOADER_ENCRYPTION),1) -UBOOT.SECURE_BINARY := $(UBOOT.MKPIMAGE_ENCRYPTED_BINARY_W_DTB) -UBOOT.SECURE_BINARYx4 := $(patsubst %.abin,%-x4.abin,$(UBOOT.SECURE_BINARY)) -all: $(UBOOT.SECURE_BINARYx4) -endif -endif - -################ -# Build DTB - -.PHONY: dtb -dtb: $(DTB) - -$(DTB): $(DTS) - $(DTC) -O dtb -o $@ -I dts $(DTC_ARGS) $< - -################ -# Untar - -UNTAR_SRC := $(STAMP_DIR)/.untar - -.PHONY: src -src: $(UNTAR_SRC) - -$(UNTAR_SRC): $(TGZ) - @$(RM) $(PRELOADER_SRC_DIR) - $(untar_recipe) - @$(CHMOD) -R 755 $(PRELOADER_SRC_DIR) - $(stamp) - - -################ -# Config - -CONFIG := $(STAMP_DIR)/.socfpga_config - -.PHONY: config -config: $(CONFIG) - -$(CONFIG): $(UNTAR_SRC) config.mk - $(MAKE) $(MAKE_ARGS) -C $(UBOOT_SRC_DIR) $(SOCFPGA_BOARD_CONFIG) - $(stamp) - - -################ -# Build - -.PHONY: uboot -uboot: $(UBOOT.BINARY) - -ifneq ($(DISABLE_UBOOT_BUILD),1) - -$(UBOOT.BINARY): $(CONFIG) - $(MAKE) $(MAKE_ARGS) -C $(UBOOT_SRC_DIR) all - -else # if uboot build is disabled, copy over a prebuilt u-boot binary that matches board config requested - -$(UBOOT.BINARY): $(PREBUILT_DIR)/$(SOCFPGA_BOARD_CONFIG)/u-boot.bin $(UBOOT.ELF) config.mk - @$(MKDIR) $(@D) - $(CP) $< $@ - -$(UBOOT.ELF): $(PREBUILT_DIR)/$(SOCFPGA_BOARD_CONFIG)/u-boot config.mk - @$(MKDIR) $(@D) - $(CP) $< $@ - -endif - - -$(UBOOT.BINARY_W_DTB): $(UBOOT.BINARY) $(DTB) - @$(MKDIR) $(@D) - $(CAT) $(UBOOT.BINARY) $(DTB) > $@ - -MKPIMAGE := mkpimage - -ifeq ($(ENABLE_BOOTLOADER_SIGNING),1) -MKPIMAGE_USE_SINGLE_IMAGE := 1 -endif -ifeq ($(ENABLE_BOOTLOADER_ENCRYPTION),1) -MKPIMAGE_USE_SINGLE_IMAGE := 1 -endif - -MKPIMAGE_ARGS += --header-version $(MKPIMAGE_HEADER_VERSION) -ifeq ($(MKPIMAGE_USE_SINGLE_IMAGE),1) -MKPIMAGE_ARGS += --alignment 0 -o $@ $< -else # use normal quad version of mkpimage -MKPIMAGE_ARGS += -o $@ $< $< $< $< -endif - -$(UBOOT.MKPIMAGE_BINARY_W_DTB): $(UBOOT.BINARY_W_DTB) - @$(MKDIR) $(@D) - $(MKPIMAGE) $(MKPIMAGE_ARGS) - -# Signing Flows are known not to work with RedHat 5, use RedHat >= 6 - -ALT_SIGN_ARGS += --rootkey-type=$(SIGNING_KEY_TYPE) -ALT_SIGN_ARGS += --keypair=$(SIGNING_KEY_PAIR_FILE) - -ifeq ($(SIGNING_KEY_TYPE),fpga) -ALT_SIGN_ARGS += --fpga-key-offset=$(SIGNING_KEY_FPGA_OFFSET) -endif - -# Add --pubkeyout=pubkeyout.bin if SIGN_KEY_TYPE is fpga or fuse -ifneq ($(filter fpga fuse,$(SIGNING_KEY_TYPE)),) -ALT_SIGN_ARGS += --pubkeyout=pubkeyout.bin -endif - -ALT_ENCRYPT_ARGS += --key="$(ENCRYPTION_KEY_FILE):$(ENCRYPTION_KEY_NAME)" - -$(UBOOT.MKPIMAGE_SIGNED_BINARY_W_DTB): $(UBOOT.MKPIMAGE_BINARY_W_DTB) $(SIGNING_KEY_PAIR_FILE) - alt-secure-boot sign $(ALT_SIGN_ARGS) --inputfile=$< --outputfile=$@ - -$(UBOOT.MKPIMAGE_ENCRYPTED_BINARY_W_DTB): $(UBOOT.MKPIMAGE_BINARY_W_DTB) $(ENCRYPTION_KEY_FILE) - alt-secure-boot encrypt $(ALT_ENCRYPT_ARGS) --inputfile=$< --outputfile=$@ - -$(UBOOT.MKPIMAGE_ENCRYPTED_SIGNED_BINARY_W_DTB): $(UBOOT.MKPIMAGE_ENCRYPTED_BINARY_W_DTB) $(SIGNING_KEY_PAIR_FILE) - alt-secure-boot sign $(ALT_SIGN_ARGS) --inputfile=$< --outputfile=$@ - - -ALT_IMAGE_CAT_ARGS += --alignment=256 - -ifneq ($(UBOOT.SECURE_BINARYx4),) -ifneq ($(UBOOT.SECURE_BINARY),) -$(UBOOT.SECURE_BINARYx4): $(UBOOT.SECURE_BINARY) - alt-image-cat $< $(ALT_IMAGE_CAT_ARGS) --output_image=$@ -endif -endif - -ifneq ($(SIGNING_KEY_PAIR_FILE),) -ifeq ($(wildcard $(SIGNING_KEY_PAIR_FILE)),) -$(SIGNING_KEY_PAIR_FILE): - $(error Error: Signing Key Pair File '$@' does not exist. Run 'make generate-signing-key-pair-file' to generate this file) -endif -endif - -.PHONY: generate-signing-key-pair-file -generate-signing-key-pair-file: -ifeq ($(SIGNING_KEY_PAIR_FILE),) - $(error ERROR: SIGNING_KEY_PAIR_FILE variable not set. Ensure bootloader signing is enabled) -endif -ifneq ($(wildcard $(SIGNING_KEY_PAIR_FILE)),) - $(error ERROR: Signing Key Pair File '$(SIGNING_KEY_PAIR_FILE)' already exists. Delete this file if you really want to regenerate it) -endif - openssl ecparam -genkey -name prime256v1 -out $(SIGNING_KEY_PAIR_FILE) - - -ifneq ($(ENCRYPTION_KEY_FILE),) -ifeq ($(wildcard $(ENCRYPTION_KEY_FILE)),) -$(ENCRYPTION_KEY_FILE): - $(error Error: Encryption Key File '$@' does not exist. Run 'make generate-example-encryption-key-file' to generate an example key file that can be used as a reference) -endif -endif - -.PHONY: generate-example-encryption-key-file -generate-example-encryption-key-file: -ifeq ($(ENCRYPTION_KEY_FILE),) - $(error ERROR: ENCRYPTION_KEY_FILE variable not set. Ensure bootloader encryption is enabled) -endif -ifneq ($(wildcard $(ENCRYPTION_KEY_FILE)),) - $(error ERROR: Encryption Key File '$(ENCRYPTION_KEY_FILE)' already exists. Delete this file if you really want to regenerate it) -endif - @echo '# This is an example key file' > $(ENCRYPTION_KEY_FILE) - @echo '# The .key file is a plain text file in which each line represents a key unless the line starts with "#"' >> $(ENCRYPTION_KEY_FILE) - @echo '# The "#" symbol is used to denote comments. Each valid key line has the following format:' >> $(ENCRYPTION_KEY_FILE) - @echo '# <256-bit hexadecimal key>.' >> $(ENCRYPTION_KEY_FILE) - @echo 'key1 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF' >> $(ENCRYPTION_KEY_FILE) - @echo 'key2 ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789' >> $(ENCRYPTION_KEY_FILE) - - -################ -# Clean - -CLEAN_FILES += $(DTB) $(CONFIG) $(UBOOT.ELF) $(UBOOT.BINARY) $(UBOOT.BINARY_W_DTB) $(UBOOT.MKPIMAGE_BINARY_W_DTB) $(UBOOT.MKPIMAGE_ENCRYPTED_BINARY_W_DTB) $(UBOOT.MKPIMAGE_SIGNED_BINARY_W_DTB) $(UBOOT.SECURE_BINARY) $(UBOOT.SECURE_BINARYx4) pubkeyout.bin - -.PHONY: clean -clean: -ifneq ($(wildcard $(UBOOT_SRC_DIR)/Makefile),) - $(MAKE) $(MAKE_ARGS) -C $(UBOOT_SRC_DIR) mrproper -endif - $(RM) $(CLEAN_FILES) - -.PHONY: clean-all -clean-all: - $(RM) $(UBOOT_SRC_DIR) $(CLEAN_FILES) - - - -############################################################################### -# -# Applying patch files -# - -# GNU MAKE >= 3.81 is required to apply patch files correctly -.SECONDEXPANSION: - -# Patch files are discovered in current directory and in the directory adjacent -# to the tarball (TGZ) directory - -PATCH.FILES := $(strip \ - $(sort $(wildcard $(patsubst %.tar.gz,%.patch,$(TGZ))/*.patch)) \ - $(sort $(wildcard $(patsubst %.tar.gz,%.patch,$(TGZ))/$(HOSTOS)/*.patch)) \ - $(sort $(wildcard $(abspath .)/*.patch)) \ - $(EXTRA_PATCH_FILES)) - -PATCH.APPLY_TARGETS := $(strip $(foreach patchfile,$(PATCH.FILES), \ - $(eval patchfile_target := $(notdir $(basename $(patchfile)))) \ - $(eval $(patchfile_target).PATCH_FILE := $(patchfile)) \ - $(PRELOADER_SRC_DIR)/.applypatch.$(patchfile_target) \ -)) - -.PHONY: patch-apply -patch-apply: $(PATCH.APPLY_TARGETS) - -$(PATCH.APPLY_TARGETS): $(PRELOADER_SRC_DIR)/.applypatch.%: $$(%.PATCH_FILE) $(UNTAR_SRC) - @$(ECHO) Applying Patch: $< - $(PATCH) -p1 --directory=$(PRELOADER_SRC_DIR) --input=$< - $(stamp) - -############################################################################### - - -############################################################################### -# -# Creating a patch file -# - -PATCH.USER_FILE := user.patch - -.PHONY: patch-create -patch-create: $(if $(PATCH.SKIP_CLEAN),,clean) -ifeq ($(wildcard $(PRELOADER_SRC_DIR).orig),) - $(error ERROR: $(PRELOADER_SRC_DIR).orig does not exist) -endif - $(DIFF) -rupN $(PRELOADER_SRC_DIR).orig/ $(PRELOADER_SRC_DIR)/ > $(PATCH.USER_FILE) || true -ifeq ($(HOSTOS),cygwin) - dos2unix $(PATCH.USER_FILE) -endif - $(CAT) $(PATCH.USER_FILE) - -############################################################################### diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/config.mk b/fpga/HAN_A10rsyocto/software/uboot_bsp/config.mk deleted file mode 100644 index 6fb1a24..0000000 --- a/fpga/HAN_A10rsyocto/software/uboot_bsp/config.mk +++ /dev/null @@ -1,77 +0,0 @@ -# Altera config.mk - -################################################################################ -# BSP Information # -################################################################################ - -# BSP type -# -BSP_TYPE := uboot - -# BSP version -# -BSP_VERSION := 1.0 - -# BSP settings File -# -BSP_SETTINGS_FILE := /home/daibitao/file2_svn/de10_advanced/test_revD/will/a10s_ghrd/software/uboot_bsp/settings.bsp - - -################################################################################ -# BSP Settings # -################################################################################ - -# Boot Source -# -# uboot.boot_device = SDMMC -# -BOOT_DEVICE := SDMMC - -# Disable the U-Boot build. This is useful if you only require the generated device tree source and device tree blob. This must be enabled on Windows because the uboot build is not yet supported on Windows. -# -# uboot.disable_uboot_build = 0 -# -DISABLE_UBOOT_BUILD := 0 - -# Encrypt Bootloader using key file specified -# -# uboot.secureboot.enable_bootloader_encryption = false -# -ENABLE_BOOTLOADER_ENCRYPTION := 0 - -# Sign Bootloader using key pair file specified -# -# uboot.secureboot.enable_bootloader_signing = false -# -ENABLE_BOOTLOADER_SIGNING := 0 - -# Key File used for Bootloader Encryption -# -# uboot.secureboot.encryption_key_file = encrypt.key -# -ENCRYPTION_KEY_FILE := encrypt.key - -# Key Name to use within Key File for Bootloader Encryption -# -# uboot.secureboot.encryption_key_name = key1 -# -ENCRYPTION_KEY_NAME := key1 - -# Offset from H2F Bridge Base Address (0xC0000000) to location of root-public-key -# -# uboot.secureboot.signing_key_fpga_offset = 0x0 -# -SIGNING_KEY_FPGA_OFFSET := 0x0 - -# Key Pair File to use when signing is enabled. You can generate this file with the command: 'make generate-signing-key-pair-file' -# -# uboot.secureboot.signing_key_pair_file = root_key.pem -# -SIGNING_KEY_PAIR_FILE := root_key.pem - -# Sign Bootloader using key pair file specified -# -# uboot.secureboot.signing_key_type = user -# -SIGNING_KEY_TYPE := user - diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dtb b/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dtb deleted file mode 100644 index 69e3e95..0000000 Binary files a/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dtb and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dts b/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dts deleted file mode 100644 index b3907e9..0000000 --- a/fpga/HAN_A10rsyocto/software/uboot_bsp/devicetree.dts +++ /dev/null @@ -1,328 +0,0 @@ -/* Insert your license and copyright header here. */ - -/dts-v1/; - -/* - * Bootloader: uboot - * Version: 1.0 - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ - - chosen { - cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */ - }; - - /* Clock sources */ - clocks { - #address-cells = <1>; - #size-cells = <1>; - - /* Clock source: altera_arria10_hps_eosc1 */ - altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "altera_arria10_hps_eosc1-clk"; - }; - - /* Clock source: altera_arria10_hps_cb_intosc_ls */ - altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <60000000>; - clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; - }; - - /* Clock source: altera_arria10_hps_f2h_free */ - altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "altera_arria10_hps_f2h_free-clk"; - }; - }; - - /* - * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver - * Version: 1.0 - * Binding: device - */ - i_clk_mgr: clock_manager@0xffd04000 { - compatible = "altr,socfpga-a10-clk-init"; - reg = <0xffd04000 0x00000200>; - reg-names = "soc_clock_manager_OCP_SLV"; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */ - mainpll { - vco0-psrc = <0>; /* Field: vco0.psrc */ - vco1-denom = <1>; /* Field: vco1.denom */ - vco1-numer = <159>; /* Field: vco1.numer */ - mpuclk-cnt = <0>; /* Field: mpuclk.cnt */ - mpuclk-src = <0>; /* Field: mpuclk.src */ - nocclk-cnt = <0>; /* Field: nocclk.cnt */ - nocclk-src = <0>; /* Field: nocclk.src */ - cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */ - cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ - cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */ - cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */ - cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */ - cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ - cntr7clk-src = <0>; /* Field: cntr7clk.src */ - cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ - cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ - cntr9clk-src = <0>; /* Field: cntr9clk.src */ - cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */ - nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */ - nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */ - nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */ - nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */ - nocdiv-cstraceclk = <0>; /* Field: nocdiv.cstraceclk */ - nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */ - }; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */ - perpll { - vco0-psrc = <0>; /* Field: vco0.psrc */ - vco1-denom = <1>; /* Field: vco1.denom */ - vco1-numer = <159>; /* Field: vco1.numer */ - cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */ - cntr2clk-src = <1>; /* Field: cntr2clk.src */ - cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ - cntr3clk-src = <1>; /* Field: cntr3clk.src */ - cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */ - cntr4clk-src = <1>; /* Field: cntr4clk.src */ - cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */ - cntr5clk-src = <1>; /* Field: cntr5clk.src */ - cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */ - cntr6clk-src = <1>; /* Field: cntr6clk.src */ - cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ - cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ - cntr8clk-src = <0>; /* Field: cntr8clk.src */ - cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ - emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */ - emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */ - emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */ - gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */ - }; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */ - alteragrp { - nocclk = <0x03840009>; /* Register: nocclk */ - mpuclk = <0x03840001>; /* Register: mpuclk */ - }; - }; - - /* - * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver - * Version: 1.0 - * Binding: pinmux - */ - i_io48_pin_mux: pinmux@0xffd07000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "pinctrl-single"; - reg = <0xffd07000 0x00000800>; - reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */ - shared { - reg = <0xffd07000 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */ - <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */ - <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */ - <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */ - <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */ - <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */ - <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */ - <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */ - <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */ - <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */ - <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */ - <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */ - <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */ - <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */ - <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */ - <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */ - <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */ - <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */ - <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */ - <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */ - <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */ - <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */ - <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */ - <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */ - <0x00000060 0x0000000a>, /* Register: pinmux_shared_io_q3_1 */ - <0x00000064 0x0000000f>, /* Register: pinmux_shared_io_q3_2 */ - <0x00000068 0x00000000>, /* Register: pinmux_shared_io_q3_3 */ - <0x0000006c 0x00000000>, /* Register: pinmux_shared_io_q3_4 */ - <0x00000070 0x0000000f>, /* Register: pinmux_shared_io_q3_5 */ - <0x00000074 0x0000000a>, /* Register: pinmux_shared_io_q3_6 */ - <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */ - <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */ - <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */ - <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */ - <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */ - <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */ - <0x00000090 0x0000000a>, /* Register: pinmux_shared_io_q4_1 */ - <0x00000094 0x0000000a>, /* Register: pinmux_shared_io_q4_2 */ - <0x00000098 0x0000000a>, /* Register: pinmux_shared_io_q4_3 */ - <0x0000009c 0x0000000a>, /* Register: pinmux_shared_io_q4_4 */ - <0x000000a0 0x0000000a>, /* Register: pinmux_shared_io_q4_5 */ - <0x000000a4 0x0000000a>, /* Register: pinmux_shared_io_q4_6 */ - <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */ - <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */ - <0x000000b0 0x0000000a>, /* Register: pinmux_shared_io_q4_9 */ - <0x000000b4 0x0000000a>, /* Register: pinmux_shared_io_q4_10 */ - <0x000000b8 0x0000000a>, /* Register: pinmux_shared_io_q4_11 */ - <0x000000bc 0x0000000a>; /* Register: pinmux_shared_io_q4_12 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ - dedicated { - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */ - <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */ - <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */ - <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */ - <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */ - <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */ - <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */ - <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */ - <0x0000002c 0x0000000f>, /* Register: pinmux_dedicated_io_12 */ - <0x00000030 0x0000000f>, /* Register: pinmux_dedicated_io_13 */ - <0x00000034 0x0000000f>, /* Register: pinmux_dedicated_io_14 */ - <0x00000038 0x0000000f>, /* Register: pinmux_dedicated_io_15 */ - <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */ - <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ - dedicated_cfg { - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x003f3f3f>; - pinctrl-single,pins = - <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */ - <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */ - <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */ - <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */ - <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */ - <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */ - <0x00000118 0x000a282a>, /* Register: configuration_dedicated_io_6 */ - <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */ - <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */ - <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */ - <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */ - <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */ - <0x00000130 0x000a282a>, /* Register: configuration_dedicated_io_12 */ - <0x00000134 0x000a282a>, /* Register: configuration_dedicated_io_13 */ - <0x00000138 0x000a282a>, /* Register: configuration_dedicated_io_14 */ - <0x0000013c 0x000a282a>, /* Register: configuration_dedicated_io_15 */ - <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */ - <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */ - fpga { - reg = <0xffd07400 0x00000100>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000001>; - pinctrl-single,pins = - <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */ - <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */ - <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */ - <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */ - <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */ - <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */ - <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */ - <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */ - <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */ - <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */ - <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */ - <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */ - <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */ - <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */ - <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */ - <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */ - <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */ - }; - }; - - /* - * Driver: altera_arria10_soc_noc_arria10_uboot_driver - * Version: 1.0 - * Binding: device - */ - i_noc: noc@0xffd10000 { - compatible = "altr,socfpga-a10-noc"; - reg = <0xffd10000 0x00008000>; - reg-names = "mpu_m0"; - - firewall { - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit - */ - mpu0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit - */ - l3-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit - */ - fpga2sdram0-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit - */ - fpga2sdram1-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit - */ - fpga2sdram2-0 = <0x00000000 0x0000ffff>; - }; - }; - - hps_fpgabridge0: fpgabridge@0 { - compatible = "altr,socfpga-hps2fpga-bridge"; - init-val = <1>; - }; - - hps_fpgabridge1: fpgabridge@1 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - init-val = <1>; - }; - - hps_fpgabridge2: fpgabridge@2 { - compatible = "altr,socfpga-fpga2hps-bridge"; - init-val = <1>; - }; - - hps_fpgabridge3: fpgabridge@3 { - compatible = "altr,socfpga-fpga2sdram0-bridge"; - init-val = <1>; - }; - - hps_fpgabridge4: fpgabridge@4 { - compatible = "altr,socfpga-fpga2sdram1-bridge"; - init-val = <0>; - }; - - hps_fpgabridge5: fpgabridge@5 { - compatible = "altr,socfpga-fpga2sdram2-bridge"; - init-val = <0>; - }; -}; diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/settings.bsp b/fpga/HAN_A10rsyocto/software/uboot_bsp/settings.bsp deleted file mode 100644 index fe40ce9..0000000 --- a/fpga/HAN_A10rsyocto/software/uboot_bsp/settings.bsp +++ /dev/null @@ -1,1426 +0,0 @@ - - - uboot - default - D:\Tresorit\Robin\FPGA\HAN_A10\Demonstration\SoC_FPGA\a10s_ghrd\software\uboot_bsp\settings.bsp - ..\..\hps_isw_handoff - default - cpu - 1.9 - - uboot.model - model - QuotedString - SOCFPGA Arria10 Dev Kit - SOCFPGA Arria10 Dev Kit - device_tree_property - Device tree model - none - false - - - - uboot.disable_uboot_build - DISABLE_UBOOT_BUILD - Boolean - 0 - 0 - config_mk_variable - Disable the U-Boot build. This is useful if you only require the generated device tree source and device tree blob. This must be enabled on Windows because the uboot build is not yet supported on Windows. - none - false - - - - uboot.boot_device - BOOT_DEVICE - UnquotedString - SDMMC - SDMMC - config_mk_variable - Boot Source - none - false - - - - uboot.external_fpga_config - chosen.external-fpga-config - BooleanDefineOnly - false - false - device_tree_property - Configure U-Boot to wait early on in the boot sequence for the FPGA to be brought to user mode by either a JTAG download or an externally connected flash. - none - false - - - - uboot.rbf_filename - chosen.cff-file - QuotedString - socfpga.rbf - socfpga.rbf - device_tree_property - Full FPGA .rbf filename. This setting is ignored when uboot.external_fpga_config setting is enabled. - none - false - - - - uboot.peripheral_rbf_filename - chosen.cff-file - QuotedString - periph.rbf - periph.rbf - device_tree_property - Peripheral .rbf filename. This setting is ignored when uboot.external_fpga_config setting is enabled. - none - false - - - - uboot.core_rbf_filename - chosen.cff-file - QuotedString - core.rbf - core.rbf - device_tree_property - Core .rbf filename. This setting is ignored when uboot.external_fpga_config setting is enabled. - none - false - - - - uboot.rbf_offset - chosen.cff-offset - HexNumber - 0x720000 - 0x720000 - device_tree_property - RBF offset address - none - false - - - - uboot.secureboot.enable_bootloader_signing - ENABLE_BOOTLOADER_SIGNING - Boolean - 0 - 0 - config_mk_variable - Sign Bootloader using key pair file specified - none - false - - - - uboot.secureboot.signing_key_type - SIGNING_KEY_TYPE - UnquotedString - user - user - config_mk_variable - Sign Bootloader using key pair file specified - none - false - - - - uboot.secureboot.signing_key_pair_file - SIGNING_KEY_PAIR_FILE - UnquotedString - root_key.pem - root_key.pem - config_mk_variable - Key Pair File to use when signing is enabled. You can generate this file with the command: 'make generate-signing-key-pair-file' - none - false - - - - uboot.secureboot.signing_key_fpga_offset - SIGNING_KEY_FPGA_OFFSET - HexNumber - 0x0 - 0x0 - config_mk_variable - Offset from H2F Bridge Base Address (0xC0000000) to location of root-public-key - none - false - - - - uboot.secureboot.enable_bootloader_encryption - ENABLE_BOOTLOADER_ENCRYPTION - Boolean - 0 - 0 - config_mk_variable - Encrypt Bootloader using key file specified - none - false - - - - uboot.secureboot.encryption_key_file - ENCRYPTION_KEY_FILE - UnquotedString - encrypt.key - encrypt.key - config_mk_variable - Key File used for Bootloader Encryption - none - false - - - - uboot.secureboot.encryption_key_name - ENCRYPTION_KEY_NAME - UnquotedString - key1 - key1 - config_mk_variable - Key Name to use within Key File for Bootloader Encryption - none - false - - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.mpuregion0enable - I_NOC_firewall.mpu0-enable - Boolean - 1 - 0 - none - Enable MPU Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.mpuregion1enable - I_NOC_firewall.mpu1-enable - Boolean - 0 - 0 - none - Enable MPU Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.mpuregion2enable - I_NOC_firewall.mpu2-enable - Boolean - 0 - 0 - none - Enable MPU Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.mpuregion3enable - I_NOC_firewall.mpu3-enable - Boolean - 0 - 0 - none - Enable MPU Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base - I_NOC_firewall.mpu0 - HexNumber - 0x0 - 0 - device_tree_property - Base for MPU Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit - I_NOC_firewall.mpu0 - HexNumber - 0xffff - 0 - device_tree_property - Limit for MPU Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion1addr.base - I_NOC_firewall.mpu1 - HexNumber - 0x0 - 0 - device_tree_property - Base for MPU Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion1addr.limit - I_NOC_firewall.mpu1 - HexNumber - 0x0 - 0 - device_tree_property - Limit for MPU Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion2addr.base - I_NOC_firewall.mpu2 - HexNumber - 0x0 - 0 - device_tree_property - Base for MPU Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion2addr.limit - I_NOC_firewall.mpu2 - HexNumber - 0x0 - 0 - device_tree_property - Limit for MPU Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion3addr.base - I_NOC_firewall.mpu3 - HexNumber - 0x0 - 0 - device_tree_property - Base for MPU Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion3addr.limit - I_NOC_firewall.mpu3 - HexNumber - 0x0 - 0 - device_tree_property - Limit for MPU Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion0enable - I_NOC_firewall.hpsregion0-enable - Boolean - 1 - 0 - none - Enable HPS Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion1enable - I_NOC_firewall.hpsregion1-enable - Boolean - 0 - 0 - none - Enable HPS Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion2enable - I_NOC_firewall.hpsregion2-enable - Boolean - 0 - 0 - none - Enable HPS Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion3enable - I_NOC_firewall.hpsregion3-enable - Boolean - 0 - 0 - none - Enable HPS Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion4enable - I_NOC_firewall.hpsregion4-enable - Boolean - 0 - 0 - none - Enable HPS Region 4 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion5enable - I_NOC_firewall.hpsregion5-enable - Boolean - 0 - 0 - none - Enable HPS Region 5 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion6enable - I_NOC_firewall.hpsregion6-enable - Boolean - 0 - 0 - none - Enable HPS Region 6 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.enable.hpsregion7enable - I_NOC_firewall.hpsregion7-enable - Boolean - 0 - 0 - none - Enable HPS Region 7 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base - I_NOC_firewall.l3-0 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit - I_NOC_firewall.l3-0 - HexNumber - 0xffff - 0 - device_tree_property - Limit for HPS Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion1addr.base - I_NOC_firewall.l3-1 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion1addr.limit - I_NOC_firewall.l3-1 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion2addr.base - I_NOC_firewall.l3-2 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion2addr.limit - I_NOC_firewall.l3-2 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion3addr.base - I_NOC_firewall.l3-3 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion3addr.limit - I_NOC_firewall.l3-3 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion4addr.base - I_NOC_firewall.l3-4 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 4 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion4addr.limit - I_NOC_firewall.l3-4 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 4 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion5addr.base - I_NOC_firewall.l3-5 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 5 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion5addr.limit - I_NOC_firewall.l3-5 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 5 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion6addr.base - I_NOC_firewall.l3-6 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 6 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion6addr.limit - I_NOC_firewall.l3-6 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 6 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion7addr.base - I_NOC_firewall.l3-7 - HexNumber - 0x0 - 0 - device_tree_property - Base for HPS Region 7 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion7addr.limit - I_NOC_firewall.l3-7 - HexNumber - 0x0 - 0 - device_tree_property - Limit for HPS Region 7 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram0region0 - I_NOC_firewall.fpga2sdram0-0-enable - Boolean - 1 - 0 - none - Enable FPGA2SDRAM0 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram0region1 - I_NOC_firewall.fpga2sdram0-1-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM0 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram0region2 - I_NOC_firewall.fpga2sdram0-2-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM0 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram0region3 - I_NOC_firewall.fpga2sdram0-3-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM0 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram1region0 - I_NOC_firewall.fpga2sdram1-0-enable - Boolean - 1 - 0 - none - Enable FPGA2SDRAM1 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram1region1 - I_NOC_firewall.fpga2sdram1-1-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM1 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram1region2 - I_NOC_firewall.fpga2sdram1-2-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM1 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram1region3 - I_NOC_firewall.fpga2sdram1-3-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM1 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram2region0 - I_NOC_firewall.fpga2sdram2-0-enable - Boolean - 1 - 0 - none - Enable FPGA2SDRAM2 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram2region1 - I_NOC_firewall.fpga2sdram2-1-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM2 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram2region2 - I_NOC_firewall.fpga2sdram2-2-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM2 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.enable.fpga2sdram2region3 - I_NOC_firewall.fpga2sdram2-3-enable - Boolean - 0 - 0 - none - Enable FPGA2SDRAM2 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base - I_NOC_firewall.fpga2sdram0-0 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM0 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit - I_NOC_firewall.fpga2sdram0-0 - HexNumber - 0xffff - 0 - device_tree_property - Limit for FPGA2SDRAM0 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region1addr.base - I_NOC_firewall.fpga2sdram0-1 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM0 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region1addr.limit - I_NOC_firewall.fpga2sdram0-1 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM0 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region2addr.base - I_NOC_firewall.fpga2sdram0-2 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM0 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region2addr.limit - I_NOC_firewall.fpga2sdram0-2 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM0 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region3addr.base - I_NOC_firewall.fpga2sdram0-3 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM0 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region3addr.limit - I_NOC_firewall.fpga2sdram0-3 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM0 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base - I_NOC_firewall.fpga2sdram1-0 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM1 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit - I_NOC_firewall.fpga2sdram1-0 - HexNumber - 0xffff - 0 - device_tree_property - Limit for FPGA2SDRAM1 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region1addr.base - I_NOC_firewall.fpga2sdram1-1 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM1 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region1addr.limit - I_NOC_firewall.fpga2sdram1-1 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM1 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region2addr.base - I_NOC_firewall.fpga2sdram1-2 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM1 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region2addr.limit - I_NOC_firewall.fpga2sdram1-2 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM1 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region3addr.base - I_NOC_firewall.fpga2sdram1-3 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM1 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region3addr.limit - I_NOC_firewall.fpga2sdram1-3 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM1 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base - I_NOC_firewall.fpga2sdram2-0 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM2 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit - I_NOC_firewall.fpga2sdram2-0 - HexNumber - 0xffff - 0 - device_tree_property - Limit for FPGA2SDRAM2 Region 0 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region1addr.base - I_NOC_firewall.fpga2sdram2-1 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM2 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region1addr.limit - I_NOC_firewall.fpga2sdram2-1 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM2 Region 1 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region2addr.base - I_NOC_firewall.fpga2sdram2-2 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM2 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region2addr.limit - I_NOC_firewall.fpga2sdram2-2 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM2 Region 2 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region3addr.base - I_NOC_firewall.fpga2sdram2-3 - HexNumber - 0x0 - 0 - device_tree_property - Base for FPGA2SDRAM2 Region 3 - none - false - module_setting - - - altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region3addr.limit - I_NOC_firewall.fpga2sdram2-3 - HexNumber - 0x0 - 0 - device_tree_property - Limit for FPGA2SDRAM2 Region 3 - none - false - module_setting - - - i_emac_EMAC0_CSR - 0xFF800000 - 0xFF801FFF - 8192 - - - - i_emac_EMAC1_CSR - 0xFF802000 - 0xFF803FFF - 8192 - - - - i_emac_EMAC2_CSR - 0xFF804000 - 0xFF805FFF - 8192 - - - - i_sdmmc - 0xFF808000 - 0xFF8083FF - 1024 - - - - i_qspi_QSPI_CSR - 0xFF809000 - 0xFF8090FF - 256 - - - - ecc_emac0_rx - 0xFF8C0800 - 0xFF8C0BFF - 1024 - - - - ecc_emac0_tx - 0xFF8C0C00 - 0xFF8C0FFF - 1024 - - - - ecc_emac1_rx - 0xFF8C1000 - 0xFF8C13FF - 1024 - - - - ecc_emac1_tx - 0xFF8C1400 - 0xFF8C17FF - 1024 - - - - ecc_emac2_rx - 0xFF8C1800 - 0xFF8C1BFF - 1024 - - - - ecc_emac2_tx - 0xFF8C1C00 - 0xFF8C1FFF - 1024 - - - - ecc_nandecc - 0xFF8C2000 - 0xFF8C23FF - 1024 - - - - ecc_nandr - 0xFF8C2400 - 0xFF8C27FF - 1024 - - - - ecc_nandw - 0xFF8C2800 - 0xFF8C2BFF - 1024 - - - - ecc_sdmmc - 0xFF8C2C00 - 0xFF8C2FFF - 1024 - - - - ecc_onchip_ram - 0xFF8C3000 - 0xFF8C33FF - 1024 - - - - ecc_dmac - 0xFF8C8000 - 0xFF8C83FF - 1024 - - - - ecc_qspi - 0xFF8C8400 - 0xFF8C87FF - 1024 - - - - ecc_otg0 - 0xFF8C8800 - 0xFF8C8BFF - 1024 - - - - ecc_otg1 - 0xFF8C8C00 - 0xFF8C8FFF - 1024 - - - - i_qspi_QSPI_XIP - 0xFFA00000 - 0xFFAFFFFF - 1048576 - - - - i_usbotg_0 - 0xFFB00000 - 0xFFB3FFFF - 262144 - - - - i_usbotg_1 - 0xFFB40000 - 0xFFB7FFFF - 262144 - - - - i_nand_NAND_CSR - 0xFFB80000 - 0xFFB807FF - 2048 - - - - i_nand_NAND_IND - 0xFFB90000 - 0xFFB9FFFF - 65536 - - - - i_uart_0 - 0xFFC02000 - 0xFFC020FF - 256 - - - - i_uart_1 - 0xFFC02100 - 0xFFC021FF - 256 - - - - i_i2c_0 - 0xFFC02200 - 0xFFC022FF - 256 - - - - i_i2c_1 - 0xFFC02300 - 0xFFC023FF - 256 - - - - i_i2c_emac_0 - 0xFFC02400 - 0xFFC024FF - 256 - - - - i_i2c_emac_1 - 0xFFC02500 - 0xFFC025FF - 256 - - - - i_i2c_emac_2 - 0xFFC02600 - 0xFFC026FF - 256 - - - - i_timer_sp_0 - 0xFFC02700 - 0xFFC027FF - 256 - - - - i_timer_sp_1 - 0xFFC02800 - 0xFFC028FF - 256 - - - - i_gpio_0 - 0xFFC02900 - 0xFFC0297F - 128 - - - - i_gpio_1 - 0xFFC02A00 - 0xFFC02A7F - 128 - - - - i_gpio_2 - 0xFFC02B00 - 0xFFC02B7F - 128 - - - - i_io48_hmc_mmr - 0xFFCFA000 - 0xFFCFAFFF - 4096 - - - - ecc_hmc - 0xFFCFB000 - 0xFFCFB7FF - 2048 - - - - i_sec_mgr_secmgr_OCP_RO - 0xFFCFE000 - 0xFFCFE3FF - 1024 - - - - i_fpga_mgr_soc_fpga_manager_Img_OCP_SLV - 0xFFCFE400 - 0xFFCFE7FF - 1024 - - - - i_timer_sys_0 - 0xFFD00000 - 0xFFD000FF - 256 - - - - i_timer_sys_1 - 0xFFD00100 - 0xFFD001FF - 256 - - - - i_watchdog_0 - 0xFFD00200 - 0xFFD002FF - 256 - - - - i_watchdog_1 - 0xFFD00300 - 0xFFD003FF - 256 - - - - i_sec_mgr_secmgr_OCP_SLV - 0xFFD02000 - 0xFFD02FFF - 4096 - - - - i_fpga_mgr_soc_fpga_manager_Csr_OCP_SLV - 0xFFD03000 - 0xFFD03FFF - 4096 - - - - i_clk_mgr - 0xFFD04000 - 0xFFD041FF - 512 - - - - i_rst_mgr - 0xFFD05000 - 0xFFD050FF - 256 - - - - i_sys_mgr - 0xFFD06000 - 0xFFD063FF - 1024 - - - - i_io48_pin_mux - 0xFFD07000 - 0xFFD077FF - 2048 - - - - i_noc - 0xFFD10000 - 0xFFD17FFF - 32768 - - - - i_dma_DMA_NS - 0xFFDA0000 - 0xFFDA0FFF - 4096 - - - - i_dma_DMA_S - 0xFFDA1000 - 0xFFDA1FFF - 4096 - - - - i_spis_0 - 0xFFDA2000 - 0xFFDA207F - 128 - - - - i_spis_1 - 0xFFDA3000 - 0xFFDA307F - 128 - - - - i_spim_0 - 0xFFDA4000 - 0xFFDA40FF - 256 - - - - i_spim_1 - 0xFFDA5000 - 0xFFDA50FF - 256 - - - - i_ram - 0xFFE00000 - 0xFFE3FFFF - 262144 - - - - i_rom - 0xFFFC0000 - 0xFFFDFFFF - 131072 - - - - mpu_reg_scu - 0xFFFFC000 - 0xFFFFDFFF - 8192 - - - - mpu_reg_l2 - 0xFFFFF000 - 0xFFFFFFFF - 4096 - - - \ No newline at end of file diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/u-boot_w_dtb.bin b/fpga/HAN_A10rsyocto/software/uboot_bsp/u-boot_w_dtb.bin deleted file mode 100644 index 980db49..0000000 Binary files a/fpga/HAN_A10rsyocto/software/uboot_bsp/u-boot_w_dtb.bin and /dev/null differ diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot.ds b/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot.ds deleted file mode 100644 index 46f90c9..0000000 --- a/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot.ds +++ /dev/null @@ -1,37 +0,0 @@ -############################################################ -# -# Copyright Altera 2015 -# All Rights Reserved -# File: uboot.ds -# -############################################################ - -# -# stop processor if running -# and then reset processor -# -stop -wait 5s -reset system -stop -wait 5s - -set trust-ro-sections-for-opcodes off - -# Load uboot elf -loadfile $sdir/uboot-socfpga/u-boot 0x0 -start -wait - -restore $sdir/devicetree.dtb binary &_end - -# -# set a breakpoint on board_init function -# -tbreak board_init - -# tell target to continue executing -continue - -# wait for breakpoint -wait 60s diff --git a/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot_w_dtb-mkpimage.bin b/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot_w_dtb-mkpimage.bin deleted file mode 100644 index e93a256..0000000 Binary files a/fpga/HAN_A10rsyocto/software/uboot_bsp/uboot_w_dtb-mkpimage.bin and /dev/null differ diff --git "a/fpga/HAN_A10rsyocto/\302\264HAN_OnBoard_DDR4_1GB.qprs" "b/fpga/HAN_A10rsyocto/\302\264HAN_OnBoard_DDR4_1GB.qprs" deleted file mode 100644 index c1b90b4..0000000 --- "a/fpga/HAN_A10rsyocto/\302\264HAN_OnBoard_DDR4_1GB.qprs" +++ /dev/null @@ -1,180 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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