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Zawrs

The WRS.NTO and WRS.STO instructions cause the hart to temporarily stall execution in a low-power state as long as the reservation set is valid and no pending interrupts, even if disabled, are observed. For WRS.STO the stall duration is bounded by an implementation defined short timeout. These instructions are available in all privilege modes. These instructions are not supported in a constrained LR/SC loop.

Encoding:

{reg: [
  {bits: 7, name: 'opcode', attr: ['SYSTEM(0x73)'] },
  {bits: 5, name: 'rd', attr: ['0'] },
  {bits: 3,  name: 'funct3', attr: ['0'] },
  {bits: 5,  name: 'rs1', attr: ['0'] },
  {bits: 12,  name: 'funct12', attr:['WRS.NTO(0x0d)', 'WRS.STO(0x1d)'] },
], config:{lanes: 1, hspace:1024}}

Operation:

Hart execution may be stalled while the following conditions are all satisfied:
    a) The reservation set is valid
    b) If `WRS.STO`, a "short" duration since start of stall has not elapsed
    c) No pending interrupt is observed (see the rules below)

While stalled, an implementation is permitted to occasionally terminate the stall and complete execution for any reason.

WRS.NTO and WRS.STO instructions follow the rules of the WFI instruction for resuming execution on a pending interrupt.

When the TW (Timeout Wait) bit in mstatus is set and WRS.NTO is executed in any privilege mode other than M mode, and it does not complete within an implementation-specific bounded time limit, the WRS.NTO instruction will cause an illegal instruction exception.

When executing in VS or VU mode, if the VTW bit is set in hstatus, the TW bit in mstatus is clear, and the WRS.NTO does not complete within an implementation-specific bounded time limit, the WRS.NTO instruction will cause a virtual instruction exception.

Note

Since the WRS.STO and WRS.NTO instructions can complete execution for reasons other than stores to the reservation set, software will likely need a means of looping until the required stores have occurred.

The duration of a WRS.STO instruction’s timeout may vary significantly within and among implementations. In typical implementations this duration should be roughly in the range of 10 to 100 times an on-chip cache miss latency or a cacheless access to main memory.

WRS.NTO, unlike WFI, is not specified to cause an illegal instruction exception if executed in U-mode when the governing TW bit is 0. WFI is typically not expected to be used in U-mode and on many systems may promptly cause an illegal instruction exception if used at U-mode. Unlike WFI, WRS.NTO is expected to be used by software in U-mode when waiting on memory but without a deadline for that wait.