From 675181f2d4840b9871afb3d320a0d3df86bdef94 Mon Sep 17 00:00:00 2001
From: Lin Sinan <sinan@isrc.iscas.ac.cn>
Date: Tue, 11 May 2021 02:06:07 +0300
Subject: [PATCH] [Hook] Add TARGET_VECTOR_MODE_SUPPORTED_P implementation

---
 gcc/config/riscv/riscv.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d489717b2a51..5b0b1419afe5 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5253,6 +5253,24 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
   return new_cost <= old_cost;
 }
 
+bool
+riscv_vector_mode_supported_p (enum machine_mode mode)
+{
+  /* a few instructions(e.g. kdmabb) in RV64P also supports V2HI */
+  if (mode == V2HImode)
+    return TARGET_ZPN;
+
+  if (mode == V4QImode)
+    return TARGET_ZPN && !TARGET_64BIT;
+
+  if (mode == V8QImode
+      || mode == V4HImode
+      || mode == V2SImode)
+    return TARGET_ZPN && TARGET_64BIT;
+
+  return false;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5436,6 +5454,10 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
 
+/* rvp */
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"