You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
{{ message }}
This repository has been archived by the owner on Feb 2, 2024. It is now read-only.
They would be a good starting point, as well as Embench. I think CSIBE might have a problem that it is only for object files, so doesn't make sense for RISC-V which does a lot of optimizations at link time.
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.
The number of temp/arg/saved registers and their location in/out of the 8 RVC registers needs quantitative support.
The text was updated successfully, but these errors were encountered: