diff --git a/src/counters.adoc b/src/counters.adoc index 20113866c..cf646c62b 100644 --- a/src/counters.adoc +++ b/src/counters.adoc @@ -147,22 +147,6 @@ As with other architectural mandates, it suffices to appear "as if" harts are synchronized to within one tick of the real-time clock, i.e., software is unable to observe that there is a greater delta between the real-time clock values observed on two harts. - -If, for example, the real-time clock increments at a frequency of 1 GHz, then -all harts must appear to be synchronized to within 1 nsec. -But it is also acceptable for this example implementation to only update the -real-time clock at, say, a frequency of 100 MHz with increments of 10 ticks. -As long as software cannot observe this seeming violation of the above -synchronization requirement, and software always observes time across harts to -be monotonically nondecreasing, then this implementation is compliant. - -A platform spec may then, for example, specify an apparent real-time clock -tick frequency (e.g. 1 GHz) and also a minimum update frequency (e.g. 100 MHz) -at which updated time values are guaranteed to be observable by software. -Software may read time more frequently, but it should only observe -monotonically nondecreasing values and it should observe a new value at least -once every 10 ns (corresponding to the 100 MHz update frequency in this -example). ==== The RDINSTRET pseudoinstruction reads the low XLEN bits of the `instret` CSR, which counts the number of instructions retired by this diff --git a/src/machine.adoc b/src/machine.adoc index 0469a1597..c8937383d 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -3,7 +3,7 @@ This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V -system. M-mode is used for low-level access to a hardware platform and +hart. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA contains a common core that is @@ -464,7 +464,7 @@ storage bit is required to represent either 00 or 11 in MPP. [[xlen-control]] ===== Base ISA Control in `mstatus` Register -For RV64 systems, the SXL and UXL fields are *WARL* fields that control the +For RV64 harts, the SXL and UXL fields are *WARL* fields that control the value of XLEN for S-mode and U-mode, respectively. The encoding of these fields is the same as the MXL field of `misa`, shown in <>. The effective XLEN in S-mode and @@ -778,7 +778,7 @@ If neither the `v` registers nor S-mode is implemented, then VS is read-only zero. If S-mode is implemented but the `v` registers are not, VS may optionally be read-only zero. -In systems without additional user extensions requiring new state, the +In harts without additional user extensions requiring new state, the XS field is read-only zero. Every additional extension with state provides a CSR field that encodes the equivalent of the XS states. The XS field represents a summary of all extensions' status as shown in @@ -1134,16 +1134,16 @@ delegation register (`medeleg`) is a 64-bit read/write register. The machine interrupt delegation register (`mideleg`) is an MXLEN-bit read/write register. -In systems with S-mode, the `medeleg` and `mideleg` registers must +In harts with S-mode, the `medeleg` and `mideleg` registers must exist, and setting a bit in `medeleg` or `mideleg` will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode -trap handler. In systems without S-mode, the `medeleg` and `mideleg` +trap handler. In harts without S-mode, the `medeleg` and `mideleg` registers should not exist. [NOTE] ==== In versions 1.9.1 and earlier , these registers existed but were -hardwired to zero in M-mode only, or M/U without N systems. There is no +hardwired to zero in M-mode only, or M/U without N harts. There is no reason to require they return zero in those cases, as the `misa` register indicates whether they exist. ==== @@ -1393,7 +1393,7 @@ M-mode includes a basic hardware performance-monitoring facility. The `mcycle` CSR counts the number of clock cycles executed by the processor core on which the hart is running. The `minstret` CSR counts the number of instructions the hart has retired. The `mcycle` and `minstret` -registers have 64-bit precision on all RV32 and RV64 systems. +registers have 64-bit precision on all RV32 and RV64 harts. The counter registers have an arbitrary value after the hart is reset, and can be written with a given value. Any CSR write takes effect after @@ -1457,9 +1457,9 @@ privilege mode (S-mode if implemented, otherwise U-mode). [NOTE] ==== The counter-enable bits support two common use cases with minimal -hardware. For systems that do not need high-performance timers and +hardware. For harts that do not need high-performance timers and counters, machine-mode software can trap accesses and implement all -features in software. For systems that need high-performance timers and +features in software. For harts that need high-performance timers and counters but are not concerned with obfuscating the underlying hardware counters, the counters can be directly exposed to lower privilege modes. ==== @@ -1480,10 +1480,10 @@ loads to the memory-mapped `mtime` register, or emulate this functionality on behalf of less-privileged modes in M-mode software. ==== -In systems with U-mode, the `mcounteren` must be implemented, but all +In harts with U-mode, the `mcounteren` must be implemented, but all fields are *WARL* and may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when -executing in a less-privileged mode. In systems without U-mode, the +executing in a less-privileged mode. In harts without U-mode, the `mcounteren` register should not exist. ==== Machine Counter-Inhibit CSR (`mcountinhibit`) @@ -1878,7 +1878,7 @@ contain the virtual address of the portion of the access that caused the fault. If `mtval` is written with a nonzero value when an instruction -access-fault or page-fault exception occurs on a system with +access-fault or page-fault exception occurs on a hart with variable-length instructions, then `mtval` will contain the virtual address of the portion of the instruction that caused the fault, while `mepc` will point to the beginning of the instruction. @@ -2878,7 +2878,7 @@ illegal. [NOTE] ==== -RV64 systems use `pmpcfg2`, rather than `pmpcfg1`, to hold +RV64 harts use `pmpcfg2`, rather than `pmpcfg1`, to hold configurations for PMP entries 8-15. This design reduces the cost of supporting multiple MXLEN values, since the configurations for PMP entries 8-11 appear in `pmpcfg2`[31:0] for both RV32 and RV64.