From 55816d56d5703eb88760ea4325d4985774fed989 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>
Date: Sat, 10 Feb 2024 18:43:55 -0600
Subject: [PATCH] HW error priority (#1223)

---
 src/machine.adoc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/machine.adoc b/src/machine.adoc
index 37fca0b9a..6804ca370 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -1847,7 +1847,10 @@ this context, "data" encompasses all types of information used within a RISC-V
 hart. Upon a hardware error exception, the `__x__epc` register is set to the
 address of the instruction that attempted to access corrupted data, while the
 `__x__tval` register is set either to 0 or to the virtual address of an
-instruction fetch, load, or store that attempted to access corrupted data.
+instruction fetch, load, or store that attempted to access corrupted data. The
+priority of Hardware Error exception is implementation-defined, but any given
+occurrence is generally expected to be recognized at the point in the overall
+priority order at which the hardware error is discovered.
 ====
 
 ==== Machine Trap Value Register (`mtval`)