From 7c4deed1f414f00fd332cadd5da219d772bb9ed7 Mon Sep 17 00:00:00 2001
From: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>
Date: Wed, 24 Jan 2024 15:51:09 -0800
Subject: [PATCH] [#379][vector] instruction constraints vgh* -> vg*

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>
---
 doc/vector/riscv-crypto-vector-instruction-constraints.adoc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/doc/vector/riscv-crypto-vector-instruction-constraints.adoc b/doc/vector/riscv-crypto-vector-instruction-constraints.adoc
index e5a8dcd4..f5a71331 100644
--- a/doc/vector/riscv-crypto-vector-instruction-constraints.adoc
+++ b/doc/vector/riscv-crypto-vector-instruction-constraints.adoc
@@ -17,7 +17,7 @@ Element Group Size (`EGS`).
 
 | vaes*   | 4
 | vsha2*  | 4
-| vgh*    | 4
+| vg*     | 4
 | vsm3*   | 8 
 | vsm4*   | 4
 
@@ -37,7 +37,7 @@ _illegal instruction exception_ is raised, even if `vl`=0.
 | vaes*   | 32 | 128
 | vsha2*  | 32 | 128
 | vsha2*  | 64 | 256
-| vgh*    | 32 | 128
+| vg*     | 32 | 128
 | vsm3*   | 32 | 256 
 | vsm4*   | 32 | 128
 
@@ -58,7 +58,7 @@ all other `SEW` values are _reserved_.
 | Zvknha: vsha2* | 32
 | Zvknhb: vsha2* | 32 or 64
 | vclmul[h]      | 64
-| vgh*           | 32
+| vg*            | 32
 | vsm3*          | 32
 | vsm4*          | 32