diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml new file mode 100644 index 000000000..692247778 --- /dev/null +++ b/arch/csr/Smcsrind/mireg.yaml @@ -0,0 +1,71 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg +long_name: Machine Indirect Register Alias +address: 0x351 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg-purpose + normative: true + text: | + The mireg machine indirect alias CSR is used to access another CSR's state + indirectly upon a read or write, as determined by the value of miselect. + - id: csr-mireg-unimplemented-miselect + normative: true + text: | + The behavior upon accessing mireg from M-mode, while miselect holds a value + that is not implemented, is UNSPECIFIED. + - id: csr-mireg-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + - id: csr-mireg-implemented-miselect + normative: true + text: | + Attempts to access mireg while miselect holds a number in an allocated and implemented range + results in a specific behavior that, for each combination of miselect and mireg, is defined by the + extension to which the miselect value is allocated. + - id: csr-mireg-implemented-miselect-note + normative: false + text: | + Ordinarily, mireg will access register state, access read-only 0 state, or raise an + illegal instruction exception. + - id: csr-mireg-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through mireg, + while the upper 32 bits are accessed through mireg4. +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml new file mode 100644 index 000000000..9a44d5516 --- /dev/null +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg2 +long_name: Machine Indirect Register Alias 2 +address: 0x352 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg2-purpose + normative: true + text: | + The `mireg2` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. + + - id: csr-mireg2-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + - id: csr-mireg2-unimplemented-miselect-typical + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + - id: csr-mireg2-implemented-miselect + normative: true + text: | + Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is + defined by the extension to which the `miselect` value is allocated. + + - id: csr-mireg2-behavior-typical + normative: false + text: | + Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + - id: csr-mireg2-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg2`, + while the upper 32 bits are accessed through `mireg5`. + +fields: + VALUE: + long_name: Indirect Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg2-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml new file mode 100644 index 000000000..dc0caf73b --- /dev/null +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg3 +long_name: Machine Indirect Register Alias 3 +address: 0x353 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg3-purpose + normative: true + text: | + The `mireg3` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. + + - id: csr-mireg3-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + - id: csr-mireg3-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + - id: csr-mireg3-implemented-miselect + normative: true + text: | + Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is + defined by the extension to which the `miselect` value is allocated. + + - id: csr-mireg3-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + - id: csr-mireg3-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg3`, + while the upper 32 bits are accessed through `mireg6`. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg3-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml new file mode 100644 index 000000000..1065dea5a --- /dev/null +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg4 +long_name: Machine Indirect Register Alias 4 +address: 0x355 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg4-purpose + normative: true + text: | + The `mireg4` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. + + - id: csr-mireg4-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + - id: csr-mireg4-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + - id: csr-mireg4-implemented-miselect + normative: true + text: | + Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is + defined by the extension to which the `miselect` value is allocated. + + - id: csr-mireg4-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + - id: csr-mireg4-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg4`, + while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg4-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml new file mode 100644 index 000000000..68971e7d8 --- /dev/null +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg5 +long_name: Machine Indirect Register Alias 5 +address: 0x356 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg5-purpose + normative: true + text: | + The `mireg5` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. + + - id: csr-mireg5-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + - id: csr-mireg5-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + - id: csr-mireg5-implemented-miselect + normative: true + text: | + Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is + defined by the extension to which the `miselect` value is allocated. + + - id: csr-mireg5-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + - id: csr-mireg5-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg5`, + while the lower 32 bits are accessed through `mireg2`. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg5-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml new file mode 100644 index 000000000..7a5b74e25 --- /dev/null +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg6 +long_name: Machine Indirect Register Alias 6 +address: 0x357 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-mireg6-purpose + normative: true + text: | + The `mireg6` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. + + - id: csr-mireg6-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + - id: csr-mireg6-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + - id: csr-mireg6-implemented-miselect + normative: true + text: | + Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is + defined by the extension to which the `miselect` value is allocated. + + - id: csr-mireg6-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + - id: csr-mireg6-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg6`, + while the lower 32 bits are accessed through `mireg3`. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-mireg6-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml new file mode 100644 index 000000000..443d3c4bd --- /dev/null +++ b/arch/csr/Smcsrind/miselect.yaml @@ -0,0 +1,58 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: miselect +long_name: Machine Indirect Register Select +address: 0x350 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: + - id: csr-miselect-purpose + normative: true + text: | + The CSRs listed in the table above provide a window for accessing register state indirectly. + The value of `miselect` determines which register is accessed upon read or write of each of + the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent + extensions, which specify the register state accessible via each `miregi` register, for each + `miselect` value. `miselect` is a WARL register. + + - id: csr-miselect-implemented-bits + normative: true + text: | + The `miselect` register implements at least enough bits to support all implemented `miselect` + values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to + indirectly access register state). The `miselect` register may be read-only zero if there are + no extensions implemented that utilize it. + + - id: csr-miselect-custom-standard-bit + normative: true + text: | + Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of + `miselect` with the most-significant bit clear are designated only for standard use and are + reserved until allocated to a standard architecture extension. + + - id: csr-miselect-msb-stability + normative: true + text: | + If XLEN is changed, the most-significant bit of `miselect` moves to the new position, + retaining its value from before. + + - id: csr-miselect-no-custom-support + normative: false + text: | + An implementation is not required to support any custom values for `miselect`. + +fields: + VALUE: + long_name: Indirect Register Selector + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-miselect-value-purpose + normative: true + text: Selects which indirect register is accessed via `mireg*`. + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml new file mode 100644 index 000000000..30e75063f --- /dev/null +++ b/arch/csr/Smcsrind/sireg.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg +long_name: Supervisor Indirect Register Alias +address: 0x151 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg-behavior-implemented + normative: true + text: | + Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg-unimplemented + normative: true + text: | + The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml new file mode 100644 index 000000000..7ae9e042e --- /dev/null +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg2 +long_name: Supervisor Indirect Register Alias 2 +address: 0x152 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg2-behavior-implemented + normative: true + text: | + Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg2-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg2-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg2-unimplemented + normative: true + text: | + The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg2-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg2-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg2-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml new file mode 100644 index 000000000..bee9ce84b --- /dev/null +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg3 +long_name: Supervisor Indirect Register Alias 3 +address: 0x153 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg3-behavior-implemented + normative: true + text: | + Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg3-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg3-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg3-unimplemented + normative: true + text: | + The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg3-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg3-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg3-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml new file mode 100644 index 000000000..3dbaba483 --- /dev/null +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg4 +long_name: Supervisor Indirect Register Alias 4 +address: 0x155 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg4-behavior-implemented + normative: true + text: | + Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg4-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg4-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg4-unimplemented + normative: true + text: | + The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg4-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg4-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg4-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml new file mode 100644 index 000000000..4a77067b6 --- /dev/null +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg5 +long_name: Supervisor Indirect Register Alias 5 +address: 0x156 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg5-behavior-implemented + normative: true + text: | + Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg5-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg5-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg5-unimplemented + normative: true + text: | + The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg5-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg5-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg5-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml new file mode 100644 index 000000000..8bf9f6678 --- /dev/null +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -0,0 +1,77 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg6 +long_name: Supervisor Indirect Register Alias 6 +address: 0x157 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-sireg6-behavior-implemented + normative: true + text: | + Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated. + + - id: csr-sireg6-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. + + - id: csr-sireg6-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + + - id: csr-sireg6-unimplemented + normative: true + text: | + The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + - id: csr-sireg6-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + - id: csr-sireg6-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-sireg6-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml new file mode 100644 index 000000000..46bd99678 --- /dev/null +++ b/arch/csr/Smcsrind/siselect.yaml @@ -0,0 +1,47 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: siselect +long_name: Supervisor Indirect Register Select +address: 0x150 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: + - id: csr-siselect-value-range + normative: true + text: | + The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may + define a value range outside of this minimum range. Only if such an extension is implemented will + `siselect` be required to support larger values. + + - id: csr-siselect-emulation + normative: false + text: | + Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or + inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, + including registers that may be standardized in the future. + + - id: csr-siselect-msb + normative: true + text: | + Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect` + with the most-significant bit clear are designated only for standard use and are reserved until + allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of + `siselect` moves to the new position, retaining its value from before. + +fields: + VALUE: + long_name: Indirect Register Select Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-siselect-value-desc + normative: true + text: | + Value ranges are allocated to dependent extensions, which specify the + register state accessible via each `sireg*` register, for each `siselect` value. + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml new file mode 100644 index 000000000..099f2a94b --- /dev/null +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -0,0 +1,81 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg +long_name: Virtual Supervisor Indirect Register Alias +address: 0x251 +virtual_address: 0x251 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg-purpose + normative: true + text: | + The `vsireg` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg-selection-mechanism + normative: true + text: | + The register addressed by `vsireg` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg`, or from VU-mode to access `siselect` or `sireg`. + + - id: csr-vsireg-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg`. + + - id: csr-vsireg-width + normative: true + text: | + The width of `vsireg` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg-value-indirect-data + normative: true + text: | + The data read from or written to the register selected by the current + value of the `vsiselect` CSR. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml new file mode 100644 index 000000000..1bc93a1e8 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -0,0 +1,80 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg2 +long_name: Virtual Supervisor Indirect Register Alias 2 +address: 0x252 +virtual_address: 0x252 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg2-purpose + normative: true + text: | + The `vsireg2` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg2-selection-mechanism + normative: true + text: | + The register addressed by `vsireg2` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg2-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg2-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg2`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg2-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg2-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg2`. + + - id: csr-vsireg2-width + normative: true + text: | + The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg2-value-indirect-data + normative: true + text: | + Data read or written based on the currently selected `vsiselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml new file mode 100644 index 000000000..141bd9d76 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -0,0 +1,80 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg3 +long_name: Virtual Supervisor Indirect Register Alias 3 +address: 0x253 +virtual_address: 0x253 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg3-purpose + normative: true + text: | + The `vsireg3` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg3-selection-mechanism + normative: true + text: | + The register addressed by `vsireg3` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg3-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg3-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg3`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg3-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg3-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg3`. + + - id: csr-vsireg3-width + normative: true + text: | + The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg3-value-indirect-data + normative: true + text: | + The data read or written based on the currently selected `vsiselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml new file mode 100644 index 000000000..95f8e6098 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -0,0 +1,80 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg4 +long_name: Virtual Supervisor Indirect Register Alias 4 +address: 0x255 +virtual_address: 0x255 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg4-purpose + normative: true + text: | + The `vsireg4` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg4-selection-mechanism + normative: true + text: | + The register addressed by `vsireg4` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg4-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg4-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg4`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg4-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg4-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg4`. + + - id: csr-vsireg4-width + normative: true + text: | + The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg4-value-indirect-data + normative: true + text: | + The data read or written based on the currently selected `vsiselect` value. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml new file mode 100644 index 000000000..224388afc --- /dev/null +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -0,0 +1,80 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg5 +long_name: Virtual Supervisor Indirect Register Alias 5 +address: 0x256 +virtual_address: 0x256 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg5-purpose + normative: true + text: | + The `vsireg5` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg5-selection + normative: true + text: | + The register addressed by `vsireg5` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg5-benefits + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg5-access-traps + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg5`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg5-unimplemented + normative: true + text: | + The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg5-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + such accesses to unimplemented targets. + + - id: csr-vsireg5-width + normative: true + text: | + The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg5-value + normative: true + text: | + The data read or written from the register selected by the value in `vsiselect`. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml new file mode 100644 index 000000000..ed4ce451c --- /dev/null +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -0,0 +1,80 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg6 +long_name: Virtual Supervisor Indirect Register Alias 6 +address: 0x257 +virtual_address: 0x257 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsireg6-purpose + normative: true + text: | + The `vsireg6` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg6-selection + normative: true + text: | + The register addressed by `vsireg6` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg6-benefits + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg6-access-traps + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg6`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg6-unimplemented + normative: true + text: | + The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg6-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + such accesses to unimplemented targets. + + - id: csr-vsireg6-width + normative: true + text: | + The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + +fields: + VALUE: + long_name: Indirectly Selected Register Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsireg6-value + normative: true + text: | + The data read or written from the register selected by the current value of `vsiselect`. + reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); +sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml new file mode 100644 index 000000000..6d712d97c --- /dev/null +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -0,0 +1,59 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsiselect +long_name: Virtual Supervisor Indirect Register Select +address: 0x250 +virtual_address: 0x250 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: + - id: csr-vsiselect-range-minimum + normative: true + text: | + The `vsiselect` register will support the value range 0..0xFFF at a minimum. + A future extension may define a value range outside of this minimum range. + Only if such an extension is implemented will `vsiselect` be required to support larger values. + + - id: csr-vsiselect-hypervisor-emulation + normative: true + text: | + Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved + or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented + range, including registers that may be standardized in the future. + + - id: csr-vsiselect-siselect-width-matching + normative: false + text: | + It is recommended that `vsiselect` and `siselect` be implemented with the same number of bits. + This avoids the creation of a virtualization hole due to observable differences between their widths. + + - id: csr-vsiselect-msb-custom-vs-standard + normative: true + text: | + Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. + Values with the most-significant bit clear are designated only for standard use and are reserved + until allocated to a standard architecture extension. + + - id: csr-vsiselect-msb-behavior-xlen-change + normative: true + text: | + If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position, + retaining its value from before. + +fields: + VALUE: + long_name: Indirect Register Select Value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: + - id: csr-vsiselect-value-indirect-access + normative: true + text: | + The index value selecting the register accessed through the `vsireg*` alias registers. + reset_value: UNDEFINED_LEGAL + +sw_read(): | diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml new file mode 100644 index 000000000..db3201edd --- /dev/null +++ b/arch/ext/Smcsrind.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smcsrind +type: privileged +long_name: Machine Indirect CSR Access (Smcsrind) +description: | + Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as + part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating + an unnecessary dependence on Smaia/Ssaia. + + This extension confers two benefits: + + It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of + the limited CSR address space. + + It enables software to access each of an array of registers by index, without requiring a switch statement + with a case for each register. + + CSRs are accessed indirectly via this extension using select values, in contrast to being accessed directly + using standard CSR numbers. A CSR accessible via one method may or may not be accessible via the other method. + Select values are a separate address space from CSR numbers, and from tselect values in the Sdtrig extension. + If a CSR is both directly and indirectly accessible, the CSR’s select value is unrelated to its CSR number. + + Further, Machine-level and Supervisor-level select values are separate address spaces from each other; + however, Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension + as partial or full aliases with respect to each other. + This typically would be done for CSRs that can be delegated from Machine-level to Supervisor-level. + + The machine-level extension Smcsrind encompasses all added CSRs and all behavior modifications for a hart, + over all privilege levels. For a supervisor-level environment, extension Sscsrind is essentially the same + as Smcsrind except excluding the machine-level CSRs and behavior not directly visible to supervisor level. + + +versions: + - version: "1.0.0" + state: ratified + ratification_date: "2024-11" + url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" + requires: { name: S, version: "~> 1.13" } diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml new file mode 100644 index 000000000..fba0681d9 --- /dev/null +++ b/arch/ext/Sscsrind.yaml @@ -0,0 +1,44 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Sscsrind +type: privileged +long_name: Supervisor Indirect CSR Access (Sscsrind) +description: | + Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as + part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating + an unnecessary dependence on Smaia/Ssaia. + + This extension confers two benefits: + + It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of + the limited CSR address space. + + It enables software to access each of an array of registers by index, without requiring a switch statement + with a case for each register. + + CSRs are accessed indirectly via this extension using select values, in contrast to being accessed directly + using standard CSR numbers. A CSR accessible via one method may or may not be accessible via the other method. + Select values are a separate address space from CSR numbers, and from tselect values in the Sdtrig extension. + If a CSR is both directly and indirectly accessible, the CSR’s select value is unrelated to its CSR number. + + Further, Machine-level and Supervisor-level select values are separate address spaces from each other; + however, Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension + as partial or full aliases with respect to each other. This typically would be done for CSRs that can be + delegated from Machine-level to Supervisor-level. + + For a supervisor-level environment, extension Sscsrind is essentially the same as Smcsrind except excluding + the machine-level CSRs and behavior not directly visible to supervisor level. + +versions: + - version: "1.0.0" + state: ratified + ratification_date: "2024-11" + url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" + requires: + allOf: + - name: S + version: ~> 1.13 + - name: Smcsrind + version: ~> 1.0