Skip to content

Commit 34157aa

Browse files
Add Smcsrind and Sscsrind CSR YAML Files (#590)
This PR adds: - Extension YAML files for `Smcsrind` and `Sscsrind` - CSR YAMLs for: - MISELECT, MIREG to MIREG6 - SISELECT, SIREG to SIREG6 - VSISELECT, VSIREG to VSIREG6 Closes #557 --------- Co-authored-by: Paul Clarke <[email protected]>
1 parent ffe1ea6 commit 34157aa

23 files changed

+1648
-0
lines changed

arch/csr/Smcsrind/mireg.yaml

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
$schema: csr_schema.json#
3+
kind: csr
4+
name: mireg
5+
long_name: Machine Indirect Register Alias
6+
address: 0x351
7+
priv_mode: M
8+
length: MXLEN
9+
definedBy: Smcsrind
10+
description:
11+
- id: csr-mireg-purpose
12+
normative: true
13+
text: |
14+
The mireg machine indirect alias CSR is used to access another CSR's state
15+
indirectly upon a read or write, as determined by the value of miselect.
16+
- id: csr-mireg-unimplemented-miselect
17+
normative: true
18+
text: |
19+
The behavior upon accessing mireg from M-mode, while miselect holds a value
20+
that is not implemented, is UNSPECIFIED.
21+
- id: csr-mireg-unimplemented-miselect-note
22+
normative: false
23+
text: |
24+
It is expected that implementations will typically raise an illegal instruction exception for
25+
such accesses, so that, for example, they can be identified as software bugs. Platform
26+
specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
27+
behavior for such accesses.
28+
- id: csr-mireg-implemented-miselect
29+
normative: true
30+
text: |
31+
Attempts to access mireg while miselect holds a number in an allocated and implemented range
32+
results in a specific behavior that, for each combination of miselect and mireg, is defined by the
33+
extension to which the miselect value is allocated.
34+
- id: csr-mireg-implemented-miselect-note
35+
normative: false
36+
text: |
37+
Ordinarily, mireg will access register state, access read-only 0 state, or raise an
38+
illegal instruction exception.
39+
- id: csr-mireg-rv32-64bit-access
40+
normative: false
41+
text: |
42+
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
43+
recommended that the lower 32 bits of the register are accessed through mireg,
44+
while the upper 32 bits are accessed through mireg4.
45+
fields:
46+
VALUE:
47+
long_name: Indirectly Selected Register Value
48+
location_rv32: 31-0
49+
location_rv64: 63-0
50+
type: RW
51+
description:
52+
- id: csr-mireg-value-purpose
53+
normative: true
54+
text: Register state of the CSR selected by the current `miselect` value
55+
reset_value: UNDEFINED_LEGAL
56+
sw_write(csr_value): |
57+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
58+
if (!handle.valid) {
59+
unimplemented_csr($encoding);
60+
}
61+
if (!handle.writable) {
62+
raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
63+
}
64+
csr_sw_write(handle, csr_value.VALUE);
65+
return csr_hw_read(handle);
66+
sw_read(): |
67+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
68+
if (!handle.valid) {
69+
unimplemented_csr($encoding);
70+
}
71+
return csr_sw_read(handle);

arch/csr/Smcsrind/mireg2.yaml

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
$schema: csr_schema.json#
3+
kind: csr
4+
name: mireg2
5+
long_name: Machine Indirect Register Alias 2
6+
address: 0x352
7+
priv_mode: M
8+
length: MXLEN
9+
definedBy: Smcsrind
10+
description:
11+
- id: csr-mireg2-purpose
12+
normative: true
13+
text: |
14+
The `mireg2` machine indirect alias CSR is used to access register state indirectly
15+
upon a read or write, as determined by the value of `miselect`.
16+
17+
- id: csr-mireg2-unimplemented-miselect
18+
normative: true
19+
text: |
20+
The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
21+
that is not implemented, is UNSPECIFIED.
22+
23+
- id: csr-mireg2-unimplemented-miselect-typical
24+
normative: false
25+
text: |
26+
It is expected that implementations will typically raise an illegal instruction exception for
27+
such accesses, so that, for example, they can be identified as software bugs. Platform
28+
specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
29+
behavior for such accesses.
30+
31+
- id: csr-mireg2-implemented-miselect
32+
normative: true
33+
text: |
34+
Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
35+
range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
36+
defined by the extension to which the `miselect` value is allocated.
37+
38+
- id: csr-mireg2-behavior-typical
39+
normative: false
40+
text: |
41+
Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
42+
illegal instruction exception.
43+
44+
- id: csr-mireg2-rv32-64bit-access
45+
normative: false
46+
text: |
47+
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
48+
recommended that the lower 32 bits of the register are accessed through `mireg2`,
49+
while the upper 32 bits are accessed through `mireg5`.
50+
51+
fields:
52+
VALUE:
53+
long_name: Indirect Register Value
54+
location_rv32: 31-0
55+
location_rv64: 63-0
56+
type: RW
57+
description:
58+
- id: csr-mireg2-value-purpose
59+
normative: true
60+
text: Register state of the CSR selected by the current `miselect` value
61+
reset_value: UNDEFINED_LEGAL
62+
sw_write(csr_value): |
63+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
64+
if (!handle.valid) {
65+
unimplemented_csr($encoding);
66+
}
67+
if (!handle.writable) {
68+
raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
69+
}
70+
csr_sw_write(handle, csr_value.VALUE);
71+
return csr_hw_read(handle);
72+
sw_read(): |
73+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
74+
if (!handle.valid) {
75+
unimplemented_csr($encoding);
76+
}
77+
return csr_sw_read(handle);

arch/csr/Smcsrind/mireg3.yaml

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
$schema: csr_schema.json#
3+
kind: csr
4+
name: mireg3
5+
long_name: Machine Indirect Register Alias 3
6+
address: 0x353
7+
priv_mode: M
8+
length: MXLEN
9+
definedBy: Smcsrind
10+
description:
11+
- id: csr-mireg3-purpose
12+
normative: true
13+
text: |
14+
The `mireg3` machine indirect alias CSR is used to access register state indirectly
15+
upon a read or write, as determined by the value of `miselect`.
16+
17+
- id: csr-mireg3-unimplemented-miselect
18+
normative: true
19+
text: |
20+
The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
21+
that is not implemented, is UNSPECIFIED.
22+
23+
- id: csr-mireg3-unimplemented-miselect-note
24+
normative: false
25+
text: |
26+
It is expected that implementations will typically raise an illegal instruction exception for
27+
such accesses, so that, for example, they can be identified as software bugs. Platform
28+
specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
29+
behavior for such accesses.
30+
31+
- id: csr-mireg3-implemented-miselect
32+
normative: true
33+
text: |
34+
Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
35+
range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
36+
defined by the extension to which the `miselect` value is allocated.
37+
38+
- id: csr-mireg3-implemented-miselect-note
39+
normative: false
40+
text: |
41+
Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
42+
illegal instruction exception.
43+
44+
- id: csr-mireg3-rv32-64bit-access
45+
normative: false
46+
text: |
47+
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
48+
recommended that the lower 32 bits of the register are accessed through `mireg3`,
49+
while the upper 32 bits are accessed through `mireg6`.
50+
51+
fields:
52+
VALUE:
53+
long_name: Indirectly Selected Register Value
54+
location_rv32: 31-0
55+
location_rv64: 63-0
56+
type: RW
57+
description:
58+
- id: csr-mireg3-value-purpose
59+
normative: true
60+
text: Register state of the CSR selected by the current `miselect` value
61+
reset_value: UNDEFINED_LEGAL
62+
sw_write(csr_value): |
63+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
64+
if (!handle.valid) {
65+
unimplemented_csr($encoding);
66+
}
67+
if (!handle.writable) {
68+
raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
69+
}
70+
csr_sw_write(handle, csr_value.VALUE);
71+
return csr_hw_read(handle);
72+
sw_read(): |
73+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
74+
if (!handle.valid) {
75+
unimplemented_csr($encoding);
76+
}
77+
return csr_sw_read(handle);

arch/csr/Smcsrind/mireg4.yaml

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
$schema: csr_schema.json#
3+
kind: csr
4+
name: mireg4
5+
long_name: Machine Indirect Register Alias 4
6+
address: 0x355
7+
priv_mode: M
8+
length: MXLEN
9+
definedBy: Smcsrind
10+
description:
11+
- id: csr-mireg4-purpose
12+
normative: true
13+
text: |
14+
The `mireg4` machine indirect alias CSR is used to access register state indirectly
15+
upon a read or write, as determined by the value of `miselect`.
16+
17+
- id: csr-mireg4-unimplemented-miselect
18+
normative: true
19+
text: |
20+
The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
21+
that is not implemented, is UNSPECIFIED.
22+
23+
- id: csr-mireg4-unimplemented-miselect-note
24+
normative: false
25+
text: |
26+
It is expected that implementations will typically raise an illegal instruction exception for
27+
such accesses, so that, for example, they can be identified as software bugs. Platform
28+
specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
29+
behavior for such accesses.
30+
31+
- id: csr-mireg4-implemented-miselect
32+
normative: true
33+
text: |
34+
Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
35+
range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
36+
defined by the extension to which the `miselect` value is allocated.
37+
38+
- id: csr-mireg4-implemented-miselect-note
39+
normative: false
40+
text: |
41+
Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
42+
illegal instruction exception.
43+
44+
- id: csr-mireg4-rv32-64bit-access
45+
normative: false
46+
text: |
47+
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
48+
recommended that the upper 32 bits of the register are accessed through `mireg4`,
49+
while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
50+
51+
fields:
52+
VALUE:
53+
long_name: Indirectly Selected Register Value
54+
location_rv32: 31-0
55+
location_rv64: 63-0
56+
type: RW
57+
description:
58+
- id: csr-mireg4-value-purpose
59+
normative: true
60+
text: Register state of the CSR selected by the current `miselect` value
61+
reset_value: UNDEFINED_LEGAL
62+
sw_write(csr_value): |
63+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
64+
if (!handle.valid) {
65+
unimplemented_csr($encoding);
66+
}
67+
if (!handle.writable) {
68+
raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
69+
}
70+
csr_sw_write(handle, csr_value.VALUE);
71+
return csr_hw_read(handle);
72+
sw_read(): |
73+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
74+
if (!handle.valid) {
75+
unimplemented_csr($encoding);
76+
}
77+
return csr_sw_read(handle);

arch/csr/Smcsrind/mireg5.yaml

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
$schema: csr_schema.json#
3+
kind: csr
4+
name: mireg5
5+
long_name: Machine Indirect Register Alias 5
6+
address: 0x356
7+
priv_mode: M
8+
length: MXLEN
9+
definedBy: Smcsrind
10+
description:
11+
- id: csr-mireg5-purpose
12+
normative: true
13+
text: |
14+
The `mireg5` machine indirect alias CSR is used to access register state indirectly
15+
upon a read or write, as determined by the value of `miselect`.
16+
17+
- id: csr-mireg5-unimplemented-miselect
18+
normative: true
19+
text: |
20+
The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
21+
that is not implemented, is UNSPECIFIED.
22+
23+
- id: csr-mireg5-unimplemented-miselect-note
24+
normative: false
25+
text: |
26+
It is expected that implementations will typically raise an illegal instruction exception for
27+
such accesses, so that, for example, they can be identified as software bugs. Platform
28+
specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
29+
behavior for such accesses.
30+
31+
- id: csr-mireg5-implemented-miselect
32+
normative: true
33+
text: |
34+
Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
35+
range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
36+
defined by the extension to which the `miselect` value is allocated.
37+
38+
- id: csr-mireg5-implemented-miselect-note
39+
normative: false
40+
text: |
41+
Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
42+
illegal instruction exception.
43+
44+
- id: csr-mireg5-rv32-64bit-access
45+
normative: false
46+
text: |
47+
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
48+
recommended that the upper 32 bits of the register are accessed through `mireg5`,
49+
while the lower 32 bits are accessed through `mireg2`.
50+
51+
fields:
52+
VALUE:
53+
long_name: Indirectly Selected Register Value
54+
location_rv32: 31-0
55+
location_rv64: 63-0
56+
type: RW
57+
description:
58+
- id: csr-mireg5-value-purpose
59+
normative: true
60+
text: Register state of the CSR selected by the current `miselect` value
61+
reset_value: UNDEFINED_LEGAL
62+
sw_write(csr_value): |
63+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
64+
if (!handle.valid) {
65+
unimplemented_csr($encoding);
66+
}
67+
if (!handle.writable) {
68+
raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
69+
}
70+
csr_sw_write(handle, csr_value.VALUE);
71+
return csr_hw_read(handle);
72+
sw_read(): |
73+
Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
74+
if (!handle.valid) {
75+
unimplemented_csr($encoding);
76+
}
77+
return csr_sw_read(handle);

0 commit comments

Comments
 (0)