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ThinkOpenly
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Add Smcsrind and Sscsrind CSR YAML Files (#590)
This PR adds: - Extension YAML files for `Smcsrind` and `Sscsrind` - CSR YAMLs for: - MISELECT, MIREG to MIREG6 - SISELECT, SIREG to SIREG6 - VSISELECT, VSIREG to VSIREG6 Closes #557 --------- Co-authored-by: Paul Clarke <[email protected]>
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‎arch/csr/Smcsrind/mireg.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mireg
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long_name: Machine Indirect Register Alias
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address: 0x351
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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg-purpose
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normative: true
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text: |
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The mireg machine indirect alias CSR is used to access another CSR's state
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indirectly upon a read or write, as determined by the value of miselect.
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- id: csr-mireg-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing mireg from M-mode, while miselect holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg-unimplemented-miselect-note
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg-implemented-miselect
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normative: true
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text: |
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Attempts to access mireg while miselect holds a number in an allocated and implemented range
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results in a specific behavior that, for each combination of miselect and mireg, is defined by the
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extension to which the miselect value is allocated.
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- id: csr-mireg-implemented-miselect-note
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normative: false
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text: |
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Ordinarily, mireg will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the lower 32 bits of the register are accessed through mireg,
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while the upper 32 bits are accessed through mireg4.
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fields:
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VALUE:
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long_name: Indirectly Selected Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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if (!handle.writable) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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csr_sw_write(handle, csr_value.VALUE);
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return csr_hw_read(handle);
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sw_read(): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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return csr_sw_read(handle);

‎arch/csr/Smcsrind/mireg2.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mireg2
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long_name: Machine Indirect Register Alias 2
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address: 0x352
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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg2-purpose
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normative: true
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text: |
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The `mireg2` machine indirect alias CSR is used to access register state indirectly
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upon a read or write, as determined by the value of `miselect`.
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- id: csr-mireg2-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg2-unimplemented-miselect-typical
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg2-implemented-miselect
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normative: true
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text: |
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Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
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range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
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defined by the extension to which the `miselect` value is allocated.
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- id: csr-mireg2-behavior-typical
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normative: false
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text: |
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Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg2-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the lower 32 bits of the register are accessed through `mireg2`,
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while the upper 32 bits are accessed through `mireg5`.
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fields:
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VALUE:
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long_name: Indirect Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg2-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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if (!handle.writable) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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csr_sw_write(handle, csr_value.VALUE);
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return csr_hw_read(handle);
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sw_read(): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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return csr_sw_read(handle);

‎arch/csr/Smcsrind/mireg3.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mireg3
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long_name: Machine Indirect Register Alias 3
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address: 0x353
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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg3-purpose
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normative: true
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text: |
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The `mireg3` machine indirect alias CSR is used to access register state indirectly
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upon a read or write, as determined by the value of `miselect`.
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- id: csr-mireg3-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg3-unimplemented-miselect-note
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg3-implemented-miselect
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normative: true
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text: |
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Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
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range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
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defined by the extension to which the `miselect` value is allocated.
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- id: csr-mireg3-implemented-miselect-note
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normative: false
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text: |
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Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg3-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the lower 32 bits of the register are accessed through `mireg3`,
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while the upper 32 bits are accessed through `mireg6`.
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fields:
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VALUE:
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long_name: Indirectly Selected Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg3-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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if (!handle.writable) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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csr_sw_write(handle, csr_value.VALUE);
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return csr_hw_read(handle);
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sw_read(): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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return csr_sw_read(handle);

‎arch/csr/Smcsrind/mireg4.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mireg4
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long_name: Machine Indirect Register Alias 4
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address: 0x355
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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg4-purpose
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normative: true
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text: |
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The `mireg4` machine indirect alias CSR is used to access register state indirectly
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upon a read or write, as determined by the value of `miselect`.
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- id: csr-mireg4-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg4-unimplemented-miselect-note
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg4-implemented-miselect
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normative: true
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text: |
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Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
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range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
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defined by the extension to which the `miselect` value is allocated.
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- id: csr-mireg4-implemented-miselect-note
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normative: false
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text: |
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Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg4-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the upper 32 bits of the register are accessed through `mireg4`,
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while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
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fields:
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VALUE:
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long_name: Indirectly Selected Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg4-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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if (!handle.writable) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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csr_sw_write(handle, csr_value.VALUE);
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return csr_hw_read(handle);
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sw_read(): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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return csr_sw_read(handle);

‎arch/csr/Smcsrind/mireg5.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mireg5
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long_name: Machine Indirect Register Alias 5
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address: 0x356
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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg5-purpose
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normative: true
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text: |
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The `mireg5` machine indirect alias CSR is used to access register state indirectly
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upon a read or write, as determined by the value of `miselect`.
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- id: csr-mireg5-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg5-unimplemented-miselect-note
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg5-implemented-miselect
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normative: true
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text: |
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Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
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range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
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defined by the extension to which the `miselect` value is allocated.
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- id: csr-mireg5-implemented-miselect-note
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normative: false
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text: |
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Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg5-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the upper 32 bits of the register are accessed through `mireg5`,
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while the lower 32 bits are accessed through `mireg2`.
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fields:
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VALUE:
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long_name: Indirectly Selected Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg5-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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if (!handle.writable) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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csr_sw_write(handle, csr_value.VALUE);
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return csr_hw_read(handle);
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sw_read(): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
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if (!handle.valid) {
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unimplemented_csr($encoding);
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}
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return csr_sw_read(handle);

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