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how to use debug tools during simulation stage? #523

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zhajio1988 opened this issue Dec 22, 2023 · 5 comments
Open

how to use debug tools during simulation stage? #523

zhajio1988 opened this issue Dec 22, 2023 · 5 comments

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@zhajio1988
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Such as i want to use debug feature of risc-tests during Synopsys VCS or Cadence XRUN simulation?

@timsifive
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It's possible to do this, but I should warn you that these tests take a very long time to run in simulation. E.g. CheckMisa, which is one of the smaller tests, scans over 13000 JTAG cycles.

Having said that, what I've seen done with a rocket core is that you implement https://github.com/fjullien/jtag_vpi in your simulation, and then write an OpenOCD config file that connects to that. You'll have to build an OpenOCD with --enable-jtag_vpi. Then make a python config file following the examples in the targets/ directory.

@zhajio1988
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zhajio1988 commented Mar 15, 2024

It's possible to do this, but I should warn you that these tests take a very long time to run in simulation. E.g. CheckMisa, which is one of the smaller tests, scans over 13000 JTAG cycles.

Having said that, what I've seen done with a rocket core is that you implement https://github.com/fjullien/jtag_vpi in your simulation, and then write an OpenOCD config file that connects to that. You'll have to build an OpenOCD with --enable-jtag_vpi. Then make a python config file following the examples in the targets/ directory.

Thanks for your replay. Could you give some tips about how to run these tests use Synopsys VCS or Cadence XRUN simulator?

@zhajio1988
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zhajio1988 commented Mar 15, 2024

Hi,
After a day of research I have found the problem, I modified my own target by referring to targets/SiFive/Freedom/U500Sim.py, but there is a problem in this script

def target(self):
      return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)

It should read

def create(self): 
      return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)

Otherwise the VCS simulation won't start

Translated with www.DeepL.com/Translator (free version)

@zhajio1988
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@timsifive
As previous comment, i have run some testcase successfully. But i also found a little issue. If I set the jtag's clk to 200 MHZ, CheckMisa is wrong, if I set it to 100 MHZ, CheckMisa passes! Could you help confirm the max clock of the jtag during debug testing?

@zhajio1988
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zhajio1988 commented Mar 18, 2024

In addition to these cases, how long does each case run, I currently run to DebugFunctionCall, this case has been running for more than ten hours, I'm not sure if I need to kill this case!

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