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In the current README.md, I found the following table of all existing TVMs. However, when checking the described riscv_test.h, I found a different set. This set is listed in the second table below. Is it correct that the table in README.md is outdated or did I misinterpret it and is there no 1-to-1 mapping with the macros in riscv_test.h?
TVM Name
Description
rv32ui
RV32 user-level, integer only
rv32si
RV32 supervisor-level, integer only
rv64ui
RV64 user-level, integer only
rv64uf
RV64 user-level, integer and floating-point
rv64uv
RV64 user-level, integer, floating-point, and vector
rv64si
RV64 supervisor-level, integer only
rv64sv
RV64 supervisor-level, integer and vector
TVM macro name
Supposed description
RVTEST_RV32M
machine-level, RV32I
RVTEST_RV32S
supervisor-level, RV32I
RVTEST_RV32U
user-level, RV32I
RVTEST_RV32UF
user-level, RV32IF
RVTEST_RV32UV
user-level, RV32IFV
RVTEST_RV64M
machine-level, RV64I
RVTEST_RV64S
supervisor-level, RV64I
RVTEST_RV64U
user-level, RV64I
RVTEST_RV64UF
user-level, RV64IF
RVTEST_RV64UV
user-level, RV64IFV
The text was updated successfully, but these errors were encountered:
In the current
README.md
, I found the following table of all existing TVMs. However, when checking the describedriscv_test.h
, I found a different set. This set is listed in the second table below. Is it correct that the table inREADME.md
is outdated or did I misinterpret it and is there no 1-to-1 mapping with the macros inriscv_test.h
?rv32ui
rv32si
rv64ui
rv64uf
rv64uv
rv64si
rv64sv
RVTEST_RV32M
RVTEST_RV32S
RVTEST_RV32U
RVTEST_RV32UF
RVTEST_RV32UV
RVTEST_RV64M
RVTEST_RV64S
RVTEST_RV64U
RVTEST_RV64UF
RVTEST_RV64UV
The text was updated successfully, but these errors were encountered: