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I'm trying to understand how Rocket-chip uses riscv-tests to test instruction sets and then uses it to my own processor.
how rocket-chip know the test result through these two macro. I'm confused about the execution details of these two macros. how to adapt this repo to my own processor? how can my own testbench know the test result?
Does anyone can help? Is there any tutorial? thanks.
related code below:
#define RVTEST_PASS
fence;
li TESTNUM, 1;
li a7, 93;
li a0, 0;
ecall
#define TESTNUM gp
#define RVTEST_FAIL
fence;
1: beqz TESTNUM, 1b;
sll TESTNUM, TESTNUM, 1;
or TESTNUM, TESTNUM, 1;
li a7, 93;
addi a0, TESTNUM, 0;
ecall
The text was updated successfully, but these errors were encountered:
ZhaoHaowenn
changed the title
Question about RVTEST_PASS and RVTEST——FAIL
Question about RVTEST_PASS and RVTEST_FAIL
May 11, 2023
The macros use the ecall instruction to execute an "exit" system call. The RISC-V calling convention defines registers a0-a7 (0x10-x17) as function arguments, so these registers may be read when executing a system call. Register a7 holds the system call code. For the exit system call, the return code is read from a0. A return code of 0 means that the test passed; any value other than zero means that the test failed. In this macro, the test number is returned if the test fails so you can tell which subtest caused the test to fail.
I'm trying to understand how Rocket-chip uses riscv-tests to test instruction sets and then uses it to my own processor.
how rocket-chip know the test result through these two macro. I'm confused about the execution details of these two macros. how to adapt this repo to my own processor? how can my own testbench know the test result?
Does anyone can help? Is there any tutorial? thanks.
related code below:
#define RVTEST_PASS
fence;
li TESTNUM, 1;
li a7, 93;
li a0, 0;
ecall
#define TESTNUM gp
#define RVTEST_FAIL
fence;
1: beqz TESTNUM, 1b;
sll TESTNUM, TESTNUM, 1;
or TESTNUM, TESTNUM, 1;
li a7, 93;
addi a0, TESTNUM, 0;
ecall
The text was updated successfully, but these errors were encountered: