From 2b3748ae4f77f23718f0c831d73a3158b5fa7eed Mon Sep 17 00:00:00 2001
From: Anand Kumar S <anku.anand@gmail.com>
Date: Mon, 28 Mar 2022 15:04:07 +0530
Subject: [PATCH 1/5] 1)  pack and zext.h have same opcode, func3, funct7 only
 diffrence is in rs2 value  for zext.h rs2 is always 0, if pack instruction is
 used with x0 as rs2  then cannot distinguish from each other, hence using
 cover label to differentiate.

2) updated coverage.py for xperm4, xperm8, zip, unzip instructions
---
 riscv_isac/coverage.py                |  7 ++++---
 riscv_isac/plugins/internaldecoder.py | 23 +++++++++++++++--------
 riscv_isac/plugins/specification.py   |  4 ++--
 3 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py
index bf27d9f6..e62c0574 100644
--- a/riscv_isac/coverage.py
+++ b/riscv_isac/coverage.py
@@ -36,14 +36,15 @@
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
-        'bclri','bexti','binvi','bseti']
+        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip']
 unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
         'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
         'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
         'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\
         'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
         'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
-        'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
+        'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw',\
+        'xperm4','xperm8','zip','unzip']
 
 class cross():
 
@@ -940,7 +941,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
     decoderclass = getattr(instructionObjectfile, "disassembler")
     decoder_pm.register(decoderclass())
     decoder = decoder_pm.hook
-    decoder.setup(arch="rv"+str(xlen))
+    decoder.setup(arch="rv"+str(xlen),labels=cov_labels)
 
     iterator = iter(parser.__iter__()[0])
     rcgf = cgf
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
index 7b2a43b6..01db0108 100644
--- a/riscv_isac/plugins/internaldecoder.py
+++ b/riscv_isac/plugins/internaldecoder.py
@@ -406,8 +406,9 @@ def init_rvp_dictionary(self):
         self.rvp_dict_11[0x00003077] = 'bpick'
 
     @plugins.decoderHookImpl
-    def setup(self, arch):
+    def setup(self, arch,labels):
         self.arch = arch
+        self.labels = labels
 
     FIRST2_MASK = 0x00000003
     OPCODE_MASK = 0x0000007f
@@ -598,10 +599,10 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b001:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
-                    instrObj.instr_name = 'zip'
-                    instrObj.rs1= rs1
-                    instrObj.rd = rd
+                if self.arch == 'rv32':
+                   instrObj.instr_name = 'zip'
+                   instrObj.rs1= rs1
+                   instrObj.rd = rd
             elif sbi == 0b0100100 or  sbi == 0b010010:
                 instrObj.rs1 = rs1
                 instrObj.rd = rd
@@ -720,7 +721,7 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b101:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
+                if self.arch == 'rv32':
                     instrObj.instr_name = 'unzip'
                     instrObj.rs1= rs1
                     instrObj.rd = rd
@@ -1210,7 +1211,10 @@ def arith_ops(self, instrObj):
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
             elif funct7 == 0b0000100:
-                if rs2[0] == 0b0:
+# pack and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
+# for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
+# then cannot distinguish from each other, hence using cover label to differentiate.
+                if rs2[0] == 0b0 and  "pack" not in self.labels:
                     instrObj.instr_name = 'zext.h'
                     instrObj.rs1 = rs1
                     instrObj.rd = rd
@@ -1499,7 +1503,10 @@ def rv64i_arith_ops(self, instrObj):
 
         if funct3 == 0b100:
             if funct7 == 0b0000100:
-                if rs2[0] == 0b0:
+# packw and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
+# for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
+# then cannot distinguish from each other, hence using cover label to differentiate.
+                if rs2[0] == 0b0 and  "packw" not in self.labels:
                     instrObj.instr_name = 'zext.h'
                     instrObj.rs1 = rs1
                     instrObj.rd = rd
diff --git a/riscv_isac/plugins/specification.py b/riscv_isac/plugins/specification.py
index 2dcd7659..636b5dce 100644
--- a/riscv_isac/plugins/specification.py
+++ b/riscv_isac/plugins/specification.py
@@ -5,7 +5,7 @@
 
 class DecoderSpec(object):
     @decoderHookSpec
-    def setup(self,arch):
+    def setup(self,arch,labels):
         pass
 
     @decoderHookSpec
@@ -19,4 +19,4 @@ def setup(self,trace,arch):
 
     @parserHookSpec
     def __iter__(self):
-        pass
\ No newline at end of file
+        pass

From aa98e426002062c2f9bc5dcae16f03a02d11943a Mon Sep 17 00:00:00 2001
From: Anand Kumar S <anku.anand@gmail.com>
Date: Tue, 12 Apr 2022 00:44:30 +0530
Subject: [PATCH 2/5] using isa to differentiate between zext.h and pack, packw
 instructions

---
 riscv_isac/coverage.py                |  2 +-
 riscv_isac/plugins/internaldecoder.py | 32 +++++++++++++--------------
 riscv_isac/plugins/specification.py   |  2 +-
 3 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py
index da8a5438..ebaddc3c 100644
--- a/riscv_isac/coverage.py
+++ b/riscv_isac/coverage.py
@@ -941,7 +941,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
     decoderclass = getattr(instructionObjectfile, "disassembler")
     decoder_pm.register(decoderclass())
     decoder = decoder_pm.hook
-    decoder.setup(arch="rv"+str(xlen),labels=cov_labels)
+    decoder.setup(arch="rv"+str(xlen),isa=cgf[cov_labels]['config'])
 
     iterator = iter(parser.__iter__()[0])
     rcgf = cgf
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
index 01db0108..76f1ca95 100644
--- a/riscv_isac/plugins/internaldecoder.py
+++ b/riscv_isac/plugins/internaldecoder.py
@@ -406,9 +406,9 @@ def init_rvp_dictionary(self):
         self.rvp_dict_11[0x00003077] = 'bpick'
 
     @plugins.decoderHookImpl
-    def setup(self, arch,labels):
+    def setup(self, arch,isa):
         self.arch = arch
-        self.labels = labels
+        self.isa = isa
 
     FIRST2_MASK = 0x00000003
     OPCODE_MASK = 0x0000007f
@@ -1213,16 +1213,15 @@ def arith_ops(self, instrObj):
             elif funct7 == 0b0000100:
 # pack and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
 # for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
-# then cannot distinguish from each other, hence using cover label to differentiate.
-                if rs2[0] == 0b0 and  "pack" not in self.labels:
+# then cannot distinguish from each other, hence using isa to differentiate.
+# zext.h is part of Zbb, pack is part of Zbkb
+                if (len(list (filter (lambda x: "Zbb" in x, self.isa)))==1):
                     instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
                 else:
                     instrObj.instr_name = 'pack'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0000101:
                 instrObj.instr_name = 'min'
                 instrObj.rs1 = rs1
@@ -1505,16 +1504,15 @@ def rv64i_arith_ops(self, instrObj):
             if funct7 == 0b0000100:
 # packw and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
 # for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
-# then cannot distinguish from each other, hence using cover label to differentiate.
-                if rs2[0] == 0b0 and  "packw" not in self.labels:
-                    instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
+# then cannot distinguish from each other, hence using isa to differentiate.
+# zext.h is part of Zbb, packw is part of Zbkb
+                if (len(list (filter (lambda x: "Zbb" in x, self.isa))) == 1):
+                        instrObj.instr_name = 'zext.h'
                 else:
                     instrObj.instr_name = 'packw'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0010000:
                 instrObj.instr_name = 'sh2add.uw'
                 instrObj.rs1 = rs1
diff --git a/riscv_isac/plugins/specification.py b/riscv_isac/plugins/specification.py
index 636b5dce..bb7577ec 100644
--- a/riscv_isac/plugins/specification.py
+++ b/riscv_isac/plugins/specification.py
@@ -5,7 +5,7 @@
 
 class DecoderSpec(object):
     @decoderHookSpec
-    def setup(self,arch,labels):
+    def setup(self,arch,isa):
         pass
 
     @decoderHookSpec

From c82d51f7bf2248a36f9103d28f82cb275a5346d0 Mon Sep 17 00:00:00 2001
From: Anand Kumar S <anku.anand@gmail.com>
Date: Tue, 24 May 2022 16:53:00 +0530
Subject: [PATCH 3/5] Added gorci to unsgn_rs1 in coverage.py Added conditions
 to extract bs and rnum fields in rvopcodesdecoder.py Removed zext.h from
 internaldecoder.py

---
 riscv_isac/coverage.py                |  3 +--
 riscv_isac/data/rvopcodesdecoder.py   |  4 ++++
 riscv_isac/plugins/internaldecoder.py | 10 ++--------
 3 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py
index 5abd18c0..8f9d588a 100644
--- a/riscv_isac/coverage.py
+++ b/riscv_isac/coverage.py
@@ -37,7 +37,7 @@
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
-        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip']
+        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci']
 unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
         'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
         'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
@@ -720,7 +720,6 @@ def compute_per_line(queue, event, cgf_queue, stats_queue, cgf, xlen, addr_pairs
                 local_dict[i] = int(csr_regfile[i],16)
 
             local_dict['xlen'] = xlen
-            
             if enable :
                 for cov_labels,value in cgf.items():
                     if cov_labels != 'datasets':
diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py
index 22bf061a..0c0d0d92 100644
--- a/riscv_isac/data/rvopcodesdecoder.py
+++ b/riscv_isac/data/rvopcodesdecoder.py
@@ -395,6 +395,10 @@ def decode(self, instrObj_temp):
                     temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2)
                 if arg == 'csr':
                     temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'bs':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'rnum':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
                 if arg.find('imm') != -1:
                     if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']:
                         imm = get_arg_val(arg)(mcode)
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
index 026f94bd..70851514 100644
--- a/riscv_isac/plugins/internaldecoder.py
+++ b/riscv_isac/plugins/internaldecoder.py
@@ -1215,10 +1215,7 @@ def arith_ops(self, instrObj):
 # for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
 # then cannot distinguish from each other, hence using isa to differentiate.
 # zext.h is part of Zbb, pack is part of Zbkb
-                if (len(list (filter (lambda x: "Zbb" in x, self.isa)))==1):
-                    instrObj.instr_name = 'zext.h'
-                else:
-                    instrObj.instr_name = 'pack'
+                instrObj.instr_name = 'pack'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
@@ -1506,10 +1503,7 @@ def rv64i_arith_ops(self, instrObj):
 # for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
 # then cannot distinguish from each other, hence using isa to differentiate.
 # zext.h is part of Zbb, packw is part of Zbkb
-                if (len(list (filter (lambda x: "Zbb" in x, self.isa))) == 1):
-                        instrObj.instr_name = 'zext.h'
-                else:
-                    instrObj.instr_name = 'packw'
+                instrObj.instr_name = 'packw'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
                 instrObj.rd = rd

From a0b076c21eb4e4eff94e43897a262b18f69d7a71 Mon Sep 17 00:00:00 2001
From: Anand Kumar S <anku.anand@gmail.com>
Date: Mon, 30 May 2022 01:33:49 +0530
Subject: [PATCH 4/5] removed isa argument from decoder plugin setup

---
 riscv_isac/coverage.py                | 2 +-
 riscv_isac/plugins/internaldecoder.py | 7 +------
 riscv_isac/plugins/specification.py   | 2 +-
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py
index 8f9d588a..63313e30 100644
--- a/riscv_isac/coverage.py
+++ b/riscv_isac/coverage.py
@@ -1059,7 +1059,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
     decoderclass = getattr(instructionObjectfile, "disassembler")
     decoder_pm.register(decoderclass())
     decoder = decoder_pm.hook
-    decoder.setup(arch="rv"+str(xlen),isa=cgf[cov_labels]['config'])
+    decoder.setup(arch="rv"+str(xlen))
 
     iterator = iter(parser.__iter__()[0])
     
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
index 70851514..38a2c1c3 100644
--- a/riscv_isac/plugins/internaldecoder.py
+++ b/riscv_isac/plugins/internaldecoder.py
@@ -406,9 +406,8 @@ def init_rvp_dictionary(self):
         self.rvp_dict_11[0x00003077] = 'bpick'
 
     @plugins.decoderHookImpl
-    def setup(self, arch,isa):
+    def setup(self, arch):
         self.arch = arch
-        self.isa = isa
 
     FIRST2_MASK = 0x00000003
     OPCODE_MASK = 0x0000007f
@@ -1211,10 +1210,6 @@ def arith_ops(self, instrObj):
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
             elif funct7 == 0b0000100:
-# pack and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
-# for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
-# then cannot distinguish from each other, hence using isa to differentiate.
-# zext.h is part of Zbb, pack is part of Zbkb
                 instrObj.instr_name = 'pack'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
diff --git a/riscv_isac/plugins/specification.py b/riscv_isac/plugins/specification.py
index bb7577ec..4c8b529a 100644
--- a/riscv_isac/plugins/specification.py
+++ b/riscv_isac/plugins/specification.py
@@ -5,7 +5,7 @@
 
 class DecoderSpec(object):
     @decoderHookSpec
-    def setup(self,arch,isa):
+    def setup(self,arch):
         pass
 
     @decoderHookSpec

From 5aaf74c61884339bff6c5efcea3eddb4d62530bd Mon Sep 17 00:00:00 2001
From: Anand Kumar S <anku.anand@gmail.com>
Date: Thu, 8 Sep 2022 12:43:42 +0530
Subject: [PATCH 5/5] update CHANGELOG.md

---
 CHANGELOG.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5ae6aa63..926cdae0 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,9 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.16.0] - 2022-08-25
+- Added instructions in updated crypto scalar spec.
+
 ## [0.15.0] - 2022-08-25
 - Added support for instruction aliases