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I have a test case which sets all software triggerable bits in MIP.
For Spike with H and Sscofpmf this should mean the MIP value 0x20aa.
It does however look like Spike doesn't prioritize the LCOF interrupt correctly since it is considered a custom interrupt.
Prior to LCOF and SGEI, MEI was the highest priority standard interrupt, but it looks like the following code hasn't been updated to deal with that.
I have a test case which sets all software triggerable bits in MIP.
For Spike with H and Sscofpmf this should mean the MIP value 0x20aa.
It does however look like Spike doesn't prioritize the LCOF interrupt correctly since it is considered a custom interrupt.
Prior to LCOF and SGEI, MEI was the highest priority standard interrupt, but it looks like the following code hasn't been updated to deal with that.
Tested the following and that seems to have been enough.
https://github.com/riscv-software-src/riscv-isa-sim/blob/f7d0dba6012d49cb75b2f175a31a85cf4b2db3b3/riscv/processor.cc#L697C32-L697C41
Reproducible:
hypervisor_tests.txt
spike -m0x80000000:0x10000000,0x20000000:0x1000,0x4000:0x1000,0xB000:0x1000 --isa rv64gvh_svinval_zba_zbb_zbc_zbs_zfh_zbkb_zicsr_zifencei_sscofpmf_smepmp_zicbom_zicntr_zihpm_svadu_sstc_zicond -p1 hypervisor_tests.txt
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