From 363fbf35a7322348d9644031aae3483838e2351e Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 15 Dec 2024 12:09:20 -0600 Subject: [PATCH 1/2] Address public review feedback --- src/server_soc_requirements.adoc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/server_soc_requirements.adoc b/src/server_soc_requirements.adoc index f449dec..d0b5bc2 100644 --- a/src/server_soc_requirements.adoc +++ b/src/server_soc_requirements.adoc @@ -1184,11 +1184,9 @@ and more. | QOS_030 | If CBQRI is supported, RISC-V harts within the application processors of the SoC MUST include support for the `srmcfg` CSR. Furthermore, this CSR MUST support a minimum of 16 RCIDs and at - least 32 MCIDs. -2+a| _The count of RCID and MCID that can be used in the SoC should scale with - the number of RISC-V harts in the SoC._ + - + - _The `srmcfg` CSR is provided by the Ssqosid extension cite:[PRIV]._ + least 32 MCIDs. The count of RCID and MCID that can be used in the + SoC SHOULD scale with the number of RISC-V harts in the SoC. +2+| _The `srmcfg` CSR is provided by the Ssqosid extension cite:[PRIV]._ | QOS_040 | If CBQRI is supported, the IOMMUs in the SoC SHOULD incorporate support for the CBQRI-defined extension, enabling the association @@ -1317,8 +1315,11 @@ data centers and enterprises. | SPM_010 a| Significant caches within the SoC SHOULD incorporate an HPM capable of counting: - * Cache lookup - * Cache miss + * Cache lookups for reads + * Cache misses on reads + * Cache lookups for writes + * Cache misses on writes + 2+| _It is recommended that a cache with a capacity that is approximately 16 KiB or larger be considered a significant cache._ From 20df4318a2903ba304a25528e69562f84ff881e6 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 21 Dec 2024 17:27:19 -0600 Subject: [PATCH 2/2] add reference to IOMMU performance monitoring rules --- src/server_soc_requirements.adoc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/server_soc_requirements.adoc b/src/server_soc_requirements.adoc index d0b5bc2..ae50628 100644 --- a/src/server_soc_requirements.adoc +++ b/src/server_soc_requirements.adoc @@ -102,6 +102,7 @@ deliver external interrupts to the RISC-V application processor harts. <<< +[[IOMMU]] === Input-Output Memory Management Unit (IOMMU) [width=100%] @@ -1351,6 +1352,8 @@ data centers and enterprises. PCIe specification 6.0. |=== +Please refer to <> for details on the IOMMU performance monitoring rules. + <<< === Security Requirements