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Andrei Warkentin
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Add RISC-V hart reqs and tests over from server soc spec.
As per mailing list discussion and agreement between Greg and Ved, these will move from the Server SoC spec. Signed-off-by: Andrei Warkentin <[email protected]>
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‎riscv-server-platform-ts.pdf

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‎riscv-server-platform.pdf

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‎server_platform.bib

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@electronic{ACPI,
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title = {Advanced Configuration and Power Interface (ACPI) Specification},
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url = {https://uefi.org/specifications}
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}
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@electronic{AHCI,
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title = {Advanced Host Controller Interface (AHCI)},
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url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf},
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year = {}
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}
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@electronic{BRS,
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title = {RISC-V Boot and Runtime Services Specification},
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url = {https://github.com/riscv-non-isa/riscv-brs},
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url = {https://github.com/riscv-non-isa/riscv-brs},
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year = {}
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}
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@electronic{NS16550,
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title = {National Semiconductor PC16550D UART Datasheet},
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url = {https://www.scs.stanford.edu/10wi-cs140/pintos/specs/pc16550d.pdf},
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year = {}
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}
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@electronic{PCI,
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title = {PCI Express® Base Specification Revision 6.0},
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url = {https://pcisig.com/pci-express-6.0-specification},
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year = {}
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}
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@electronic{RFC_2119,
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title = {Key words for use in RFCs to Indicate Requirement Levels},
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url = {https://datatracker.ietf.org/doc/html/rfc2119}
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}
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@electronic{RVA23,
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title = {RVA23 Profiles},
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url = {https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc},
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year = {}
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}
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@electronic{ServerSoC,
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title = {RISC-V Server SoC Specification},
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url = {https://github.com/riscv-non-isa/server-soc},
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url = {https://github.com/riscv-non-isa/server-soc},
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year = {}
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}
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@electronic{RFC_2119,
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title = {Key words for use in RFCs to Indicate Requirement Levels},
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url = {https://datatracker.ietf.org/doc/html/rfc2119}
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}
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@electronic{ACPI,
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title = {Advanced Configuration and Power Interface (ACPI) Specification},
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url = {https://uefi.org/specifications}
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}
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@electronic{UEFI,
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title = {Unified Extensible Firmware Interface},
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url = {https://uefi.org/specifications}
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}
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@electronic{PCI,
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title = {PCI Express® Base Specification Revision 6.0},
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url = {https://pcisig.com/pci-express-6.0-specification},
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year = {}
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}
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@electronic{NS16550,
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title = {National Semiconductor PC16550D UART Datasheet},
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url = {https://www.scs.stanford.edu/10wi-cs140/pintos/specs/pc16550d.pdf},
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year = {}
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}
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@electronic{XHCI,
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title = {eXtensible Host Controller Interface for Universal Serial Bus 1.2},
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url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf},
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year = {}
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}
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@electronic{AHCI,
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title = {Advanced Host Controller Interface (AHCI)},
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url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf},
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year = {}
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}

‎server_platform_intro.adoc

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.Components of a RISC-V Server Platform
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image::riscv-server-platform.png[width=800]
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The RISC-V server platform is defined as the collection of SoC hardware,
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peripherals, platform firmware, boot/runtime services, and platform security services.
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The platform provides hardware interfaces (e.g., harts, timers, interrupt
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controllers, PCIe root ports, etc.) to portable system software. It also offers a set of
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standardized boot and runtime services based on the UEFI and ACPI standards. To
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support provisioning and platform management, it interfaces with a baseboard
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management controller (BMC) through both in-band and out-of-band (OOB)
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management interfaces. The in-band management interfaces support the use of
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standard manageability specifications like MCTP, PLDM, IPMI, and Redfish for
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provisioning and management of the operating system executing on the platform.
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The OOB interface supports the use of standard manageability specifications like
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MCTP, PLDM, Redfish, and IPMI for functions such as power management, telemetry,
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debug, and provisioning. The platform security model includes guidelines and requirements
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for aspects such as debug authorization, secure/measured boot, firmware updates,
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firmware resilience, and confidential computing, among others.
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The RISC-V server platform is defined as the collection of RVA profile-compliant
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application processor harts, SoC hardware, peripherals, platform firmware,
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boot/runtime services, and platform security services. The platform provides
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hardware interfaces (e.g., harts, timers, interrupt controllers, PCIe root ports, etc.)
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to portable system software. It also offers a set of standardized boot and runtime
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services based on the UEFI and ACPI standards. To support provisioning and
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platform management, it interfaces with a baseboard management controller (BMC)
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through both in-band and out-of-band (OOB) management interfaces. The in-band
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management interfaces support the use of standard manageability specifications
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like MCTP, PLDM, IPMI, and Redfish for provisioning and management of the operating
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system executing on the platform. The OOB interface supports the use of standard
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manageability specifications like MCTP, PLDM, Redfish, and IPMI for functions such
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as power management, telemetry, debug, and provisioning. The platform security model
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includes guidelines and requirements for aspects such as debug authorization,
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secure/measured boot, firmware updates, firmware resilience, and confidential
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computing, among others.
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The platform firmware, typically operating at privilege level M, is
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considered part of the platform and is usually expected to be customized and
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This specification standardizes the requirements for hardware and software
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interfaces and capabilities by building on top of relevant RISC-V standards,
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such as the Server SoC, Boot and Runtime Services and Platform Security
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specifications for server software executing on the application processor harts
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at privilege levels below M. It enables OS and hypervisor vendors to support such
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platforms with a single binary OS image distribution model. The requirements posed by this
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specification represent a standard set of infrastructural capabilities,
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encompassing areas where divergence is typically unnecessary and where novelty
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is absent across implementations.
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such as the RISC-V Architecture Profiles, Server SoC, Boot and Runtime Services
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and Platform Security specifications for server software executing on the application
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processor harts at privilege levels below M. It enables OS and hypervisor vendors to
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support such platforms with a single binary OS image distribution model. The
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requirements posed by this specification represent a standard set of infrastructural
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capabilities, encompassing areas where divergence is typically unnecessary and
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where novelty is absent across implementations.
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To be compliant with this specification, the server platform MUST support all
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mandatory requirements and MUST support the listed versions of the specifications.

‎server_platform_requirements.adoc

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== Server Platform Hardware Requirements
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=== RISC-V SoC
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=== RISC-V Harts
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A RISC-V server platform includes a RISC-V application processor and may include
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one or more service processors. These service processors may provide services such
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as security and power management to software executing on the application
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processors, and they may themselves implement the RISC-V ISA. The requirements
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in this section apply solely to harts in the application processors of the SoC.
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[width=100%]
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[%header, cols="5,25"]
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|===
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| ID# ^| Requirement
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| RVA_010 | The RISC-V application processor harts in the SoC MUST support the
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RVA23 ISA profile cite:[RVA23].
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2+| _The next major release of the profiles is expected to be RVA24, which is
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still under construction. This specification should be updated to comply
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with the RVA24 profiles as the profile definition becomes more finalized._
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| RVA_020 a| The RISC-V application processor harts in the SoC MUST support the
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following extensions:
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* Sv48
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* Sv48x4
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* Svadu
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* Sdtrig
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* Sdext
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* H
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* Sscofpmf
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* Zkr
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* Ssecorrupt
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* Ssccfg
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* Ssctr
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* Sscrind
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2+| _Ssccfg, Sscind, and Ssctr are under construction._ +
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+
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_Many of these mandated extensions are optional in the RVA23 ISA profile.
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This requirement is placed here as a placeholder. These mandates may be
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moved into a new ISA profile specification._
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| RVA_030 | The ISA extensions and associated CSR field widths implemented by
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any of the RISC-V application processor harts in the SoC MUST be
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identical.
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2+| _The RVA23 profile supports a set of optional extensions. The set of
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optional extensions implemented by the harts must be identical. Where the
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extension supports optionality in the form of field widths (e.g.,
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ASIDLEN, VLEN, allowed vstart values, physical address width, debug
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triggers, cache-block size, etc.), the implementation of these must also be
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identical. Having an identical ISA on all harts allows system software to
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migrate tasks among the harts without constraints._
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| RVA_040 | The RISC-V application processor harts in the SoC MAY support
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different power and performance characteristics but MUST be
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otherwise indistinguishable from each other from a software
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execution viewpoint.
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2+| _All harts in the SoC being indistinguishable from a software execution
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viewpoint allows system software to migrate tasks among the harts without
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constraints._
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| RVA_050 a| The RISC-V application processor hart MUST support:
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* Single stepping using the step bit in `dcsr`
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* Debug scratch register 0 (`dscratch0`)
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| RVA_060 a| The RISC-V application processor hart MUST support:
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* At least 4 instruction address match triggers.
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* At least 4 load/store address match triggers.
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* At least one icount trigger to support single stepping.
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* At least one interrupt trigger.
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* At least one exception trigger.
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* Trigger filtering using `hcontext`.
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* Trigger filtering using all VMID encodings supported by the hart.
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* Trigger filtering using `scontext`.
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* Trigger filtering using all ASID encodings supported by the hart.
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| RVA_070 | The RISC-V application processor MUST support at least 6 hardware
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performance counters defined by the Zihpm extension in addition to
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the three counters defined by Zicntr extension.
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|===
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A RISC-V server platform is based on a RISC-V SoC with RISC-V application processors.
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=== RISC-V SoC
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[width=100%]
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[%header, cols="5,25"]

‎server_platform_tests.adoc

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22

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=== Server Platform Hardware Requirements
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==== RISC-V Harts
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[width=100%]
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[%header, cols="8,25"]
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|===
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| ID# ^| Algorithm
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| ME_RVA_010_010 a| For each application processor hart:
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. Determine the ISA node in ACPI RHCT table for that hart.
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. Parse the ISA string in the ISA node and verify that all
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mandatory extensions are supported.
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. Verify that the ISA string matches that of hart 0.
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. Report the ISA string of hart 0 into the test output log.
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| ME_RVA_020_010 | See T_RVA_010_010.
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| ME_RVA_030_010 a| . The T_RVA_010_010 verifies that all ISA strings are
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identical.
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. For each ISA extension reported in the ISA string, if
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there are CSRs associated with that extension, then probe
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the CSR to determine the width of the CSR fields and the
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legal encodings on each application processor hart. The
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CSR field widths and legal encodings supported by each
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hart must match that of hart 0.
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| ME_RVA_040_010 | See ME_RVA_030_010.
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| ME_RVA_050_010 a| No test.
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| MF_RVA_060_010 a| Install 4 instruction address match triggers using the debug
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triggers SBI and verify that each trigger fires.
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| MF_RVA_060_020 a| Install 4 load address match triggers using the debug
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triggers SBI and verify that each trigger fires.
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| MF_RVA_060_030 a| Install 4 store address match triggers using the debug
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triggers SBI and verify that each trigger fires.
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| MF_RVA_060_040 a| Install an `icount` trigger using the debug triggers SBI and
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verify single-step.
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| MF_RVA_060_050 a| . Install an interrupt trigger to match supervisor timer
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interrupt using the debug triggers SBI.
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. Program a timer deadline in `stimecmp`
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. Verify that the trigger fires on reaching the programmed
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deadline.
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| MF_RVA_060_060 a| . Install an exception trigger to match ECALL to S-mode
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exception using the debug triggers SBI.
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. Transition to U-mode and invoke an ECALL.
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. Verify that the trigger fires.
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| MF_RVA_060_070 a| . Verify `hcontext` exists.
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. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching
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and non-matching `hcontext` value.
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| ME_RVA_060_080 a| . Install and read-back triggers with VMID values between 0
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and `VMIDLEN`.
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| MF_RVA_060_090 a| . Verify `scontext` exists.
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. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching
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and non-matching `scontext` value.
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| ME_RVA_060_100 a| . Install and read-back triggers with ASID values between 0
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and `ASIDLEN`.
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| ME_RVA_070_010 a| . Request delegation of all HPM counters using the SBI.
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. Verify at least 6 programmable HPM counter are implemented.
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. Verify that the `scountovf` CSR is implemented
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. Verify `cycles` and `instret` are writeable.
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. Verify ability to toggle counter enable for each
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implemented HPM, `cycles`, and `instret` counters.
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|===
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<<<
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==== RISC-V SoC
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[width=100%]

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