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About SBI PMU extension reserved 16 bits in mhpmeventX CSR #157
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If we restrict SBI PMU raw events to 56-bits then it is not fair to RISC-V platforms without Sscofpmf where entire 64-bits of mhpmeventX CSR is programmable. |
Hi @avpatel, Thanks for the explanation. But it seems the SBI PMU spec[1] defines more restrictions for raw events that can program only 48-bits of mhpmeventX CSR.
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I think we should not change existing semantics In addition, to the discrepancy which you pointed, the Priv v1.13 specification makes I think it is better to define new @atishp04 Thoughts ?? |
Priv v1.12 had mhpmevent specified as MXLEN
Should we make this change after v1.13 is ratified only ? The SBI implementation can conform to raw events v2 (Type #3) and wider hpmevent for RV32 based on the priv version. |
Hi @atishp04 , Can I ask, will we define the new Thanks. [1] https://github.com/torvalds/linux/blob/master/drivers/perf/riscv_pmu_sbi.c#L531 |
@dslin1010 : Yes. But we are waiting for confirmation about how many bits are actually reserved now ? |
Currently, the SBI PMU spec[1] defines the raw event type as follows:
However, the current OpenSBI PMU implementation for Sscofpmf extension only reserved 8 bits[2] according to the Sscofpmf extension spec[3].
Should we change the SBI PMU raw event type definition as follows?
Thanks.
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-hardware-raw-events-type-2
[2] riscv-software-src/opensbi@df997c6
[3] https://github.com/riscvarchive/riscv-count-overflow
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