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I couldn't find any relevant information about pointer/selector registers to be used for exception handling, for any RISC-V variant. According to this 1 LLVM patch, the values that they rely on are based on GCC implementation but it is fuzzy to find the origin of those. Stumbling upon the same issue on D runtime 2.
Would be cool to have a clarification of those register numbers on the documentation.
The text was updated successfully, but these errors were encountered:
I couldn't find any relevant information about pointer/selector registers to be used for exception handling, for any RISC-V variant. According to this 1 LLVM patch, the values that they rely on are based on GCC implementation but it is fuzzy to find the origin of those. Stumbling upon the same issue on D runtime 2.
Would be cool to have a clarification of those register numbers on the documentation.
The text was updated successfully, but these errors were encountered: