diff --git a/README.md b/README.md index a17ac8e4f..fcc2a0803 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v4.5.0](https://github.com/renesas/fsp/releases/tag/v4.5.0) +[FSP v4.6.0](https://github.com/renesas/fsp/releases/tag/v4.6.0) ### Supported RA MCU Kits @@ -73,6 +73,7 @@ For a list of software modules packaged with FSP, see [Supported Software](SUPPO - FSP versions of 4.1.0 and later require a minimum e² studio version of 2022-10. - FSP versions of 4.3.0 and later require a minimum e² studio version of 2023-01. - FSP versions of 4.4.0 and later require a minimum e² studio version of 2023-04. +- FSP versions of 4.6.0 and later require a minimum e² studio version of 2023-07. If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\.exe, that will work on Windows. @@ -80,7 +81,7 @@ When using the zipped version of the packs the zip file should be extracted into #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.5.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.6.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index d5e5aa31a..a46bac744 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -110,6 +110,7 @@ * [Motor inertia estimation (rm_motor_inertia_estimate)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_e_r_t_i_a___e_s_t_i_m_a_t_e.html) * [Motor return origin function (rm_motor_return_origin)](https://renesas.github.io/fsp/group___m_o_t_o_r___r_e_t_u_r_n___o_r_i_g_i_n.html) * [Motor vector control with induction sensor (rm_motor_induction)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_d_u_c_t_i_o_n.html) + * [Shared ADC module (on rm_motor_driver)](https://renesas.github.io/fsp/group___m_o_t_o_r___d_r_i_v_e_r.html) * Networking * Bluetooth Low Energy Mesh Network modules * [BLE Mesh (rm_ble_mesh)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h.html) @@ -359,7 +360,7 @@ * [RYZ012 SPP Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___s_p_p.html) * [TinyCBOR](https://github.com/intel/tinycbor/) * [WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html) - * [WiFi Onchip DA16xxx Driver using r_sci_uart (rm_wifi_onchip_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___d_a16200.html) + * [WiFi Onchip DA16xxx Driver using r_sci_uart (rm_wifi_onchip_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___d_a16_x_x_x.html) * [WiFi Onchip Silex Driver using r_sci_uart (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) * Security * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) diff --git a/ra/fsp/inc/api/fsp_common_api.h b/ra/fsp/inc/api/fsp_common_api.h index 42a0133f9..0ab2ece3b 100644 --- a/ra/fsp/inc/api/fsp_common_api.h +++ b/ra/fsp/inc/api/fsp_common_api.h @@ -300,15 +300,14 @@ typedef enum e_fsp_err FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error - /* Start of SF_CELLULAR Specific */ FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. diff --git a/ra/fsp/inc/api/r_adc_api.h b/ra/fsp/inc/api/r_adc_api.h index a25f7122b..cd3c6ac68 100644 --- a/ra/fsp/inc/api/r_adc_api.h +++ b/ra/fsp/inc/api/r_adc_api.h @@ -183,9 +183,9 @@ typedef enum e_adc_group_mask /** ADC states. */ typedef enum e_adc_state { - ADC_STATE_IDLE = 0, ///< ADC is idle - ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress - ADC_STATE_CALIBRATION_IN_PROGRESS = 2, ///< ADC calibration in progress - Not used by all ADC instances + ADC_STATE_IDLE = 0, ///< ADC is idle + ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress + ADC_STATE_CALIBRATION_IN_PROGRESS = 2, ///< ADC calibration in progress - Not used by all ADC instances } adc_state_t; /** ADC status. */ diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h index c1a78fe58..cc019a5d4 100644 --- a/ra/fsp/inc/api/r_crc_api.h +++ b/ra/fsp/inc/api/r_crc_api.h @@ -148,11 +148,12 @@ typedef void crc_ctrl_t; /** User configuration structure, used in open function */ typedef struct st_crc_cfg { - crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS) - crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS) + crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS) + crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS) + /* crc_snoop_address_t is to be deprecated. */ - int32_t snoop_address; ///< Register Snoop Address (CRCSA) - void const * p_extend; ///< CRC Hardware Dependent Configuration + int32_t snoop_address; ///< Register Snoop Address (CRCSA) + void const * p_extend; ///< CRC Hardware Dependent Configuration } crc_cfg_t; /** CRC driver structure. General CRC functions implemented at the HAL layer will follow this API. */ diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h index 03f45b2f0..533d483a2 100644 --- a/ra/fsp/inc/api/r_ioport_api.h +++ b/ra/fsp/inc/api/r_ioport_api.h @@ -16,7 +16,8 @@ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ + **********************************************************************************************************************/ + /*******************************************************************************************************************//** * @ingroup RENESAS_INTERFACES * @defgroup IOPORT_API I/O Port Interface @@ -69,11 +70,11 @@ typedef enum e_ioport_peripheral /** Pin will function as an AGT peripheral pin */ IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ + + /** Pin will function as an AGT peripheral pin */ IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ + + /** Pin will function as an AGT peripheral pin */ IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), /** Pin will function as a GPT peripheral pin */ @@ -116,12 +117,14 @@ typedef enum e_ioport_peripheral IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED + /** Pin will function as an SCI peripheral DEn pin */ IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), /** Pin will function as an SCI DEn peripheral pin */ IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), #else + /** Pin will function as an SCI peripheral DEn pin */ IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), @@ -132,10 +135,9 @@ typedef enum e_ioport_peripheral /** Pin will function as a DALI peripheral pin */ IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - /** Pin will function as a CEU peripheral pin */ IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - + /** Pin will function as a CAN peripheral pin */ IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), @@ -193,11 +195,11 @@ typedef enum e_ioport_peripheral /** Pin will function as a PGAOUT peripheral pin */ IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - /** Pin will function as a MIPI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - /** Pin will function as a ULPT peripheral pin */ IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a MIPI DSI peripheral pin */ + IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), } ioport_peripheral_t; /** Options to configure pin functions */ diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h index f46377b15..0996d2793 100644 --- a/ra/fsp/inc/api/r_lpm_api.h +++ b/ra/fsp/inc/api/r_lpm_api.h @@ -94,7 +94,7 @@ typedef enum e_lpm_snooze_request LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request - LPM_SNOOZE_REQUEST_AGTW1_UNDERFLOW = 0x10000000ULL, ///< Enable AGTW1 underflow snooze request + LPM_SNOOZE_REQUEST_AGTW1_UNDERFLOW = 0x10000000ULL, ///< Enable AGTW1 underflow snooze request LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request LPM_SNOOZE_REQUEST_AGTW1_COMPARE_A = 0x20000000ULL, ///< Enable AGTW1 compare match A snooze request LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request @@ -157,60 +157,60 @@ typedef enum e_lpm_snooze_dtc /** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ typedef enum e_lpm_standby_wake_source { - LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 - LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 - LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 - LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 - LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 - LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 - LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 - LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 - LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 - LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 - LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 - LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 - LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 - LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 - LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 - LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 - LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt - LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt - LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt - LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt - LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt - LPM_STANDBY_WAKE_SOURCE_VRTC = 0x00200000ULL, ///< LVDVRTC interrupt - LPM_STANDBY_WAKE_SOURCE_EXLVD = 0x00400000ULL, ///< LVDEXLVD interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_RTCALM1 = 0x00800000ULL, ///< RTC Alarm interrupt 1 - LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt - LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt - LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt - LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt - LPM_STANDBY_WAKE_SOURCE_AGTW0UD = 0x08000000ULL, ///< AGTW0 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGTW1UD = 0x10000000ULL, ///< AGTW1 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGTW1CA = 0x20000000ULL, ///< AGTW1 Compare Match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGTW1CB = 0x40000000ULL, ///< AGTW1 Compare Match B interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt - LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt - LPM_STANDBY_WAKE_SOURCE_AGT0UD = 0x100000000ULL, ///< AGT0 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1UD_S = 0x200000000ULL, ///< AGT1 Underflow interrupt for specific board - LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 Compare Match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGT2UD = 0x400000000ULL, ///< AGT2 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 Compare Match B interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3UD_S = 0x800000000ULL, ///< AGT3 Underflow interrupt for specific board - LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt - LPM_STANDBY_WAKE_SOURCE_AGT4UD = 0x1000000000ULL, ///< AGT4 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT5UD = 0x2000000000ULL, ///< AGT5 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT6UD = 0x4000000000ULL, ///< AGT6 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT7UD = 0x8000000000ULL, ///< AGT7 Underflow interrupt - LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x10000000000ULL, ///< SOSTD interrupt - LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt - LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt - LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_VRTC = 0x00200000ULL, ///< LVDVRTC interrupt + LPM_STANDBY_WAKE_SOURCE_EXLVD = 0x00400000ULL, ///< LVDEXLVD interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM1 = 0x00800000ULL, ///< RTC Alarm interrupt 1 + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW0UD = 0x08000000ULL, ///< AGTW0 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1UD = 0x10000000ULL, ///< AGTW1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1CA = 0x20000000ULL, ///< AGTW1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1CB = 0x40000000ULL, ///< AGTW1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_AGT0UD = 0x100000000ULL, ///< AGT0 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD_S = 0x200000000ULL, ///< AGT1 Underflow interrupt for specific board + LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT2UD = 0x400000000ULL, ///< AGT2 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD_S = 0x800000000ULL, ///< AGT3 Underflow interrupt for specific board + LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt + LPM_STANDBY_WAKE_SOURCE_AGT4UD = 0x1000000000ULL, ///< AGT4 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT5UD = 0x2000000000ULL, ///< AGT5 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT6UD = 0x4000000000ULL, ///< AGT6 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT7UD = 0x8000000000ULL, ///< AGT7 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x10000000000ULL, ///< SOSTD interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x100000000000ULL, ///< ULPT1 Underflow Interrupt LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x200000000000ULL, ///< ULPT1 Compare Match A Interrupt @@ -396,20 +396,23 @@ typedef enum e_lpm_ldo_standby_operation } lpm_ldo_standby_operation_t; #if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + /** RAM Retention Configuration for deep sleep and standby modes. */ typedef struct s_lpm_ram_retention { -#if BSP_FEATURE_LPM_HAS_PDRAMSCR + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + /** Configure RAM retention in software standby mode. */ uint16_t ram_retention; /** Enable or disable TCM retention in deep sleep and software standby modes. */ bool tcm_retention; -#endif -#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + /** Enable Standby RAM retention in software standby and deep software standby modes. */ bool standby_ram_retention; -#endif + #endif } lpm_ram_retention_t; #endif diff --git a/ra/fsp/inc/api/r_lvd_api.h b/ra/fsp/inc/api/r_lvd_api.h index 0eaf66bea..0031ba2fc 100644 --- a/ra/fsp/inc/api/r_lvd_api.h +++ b/ra/fsp/inc/api/r_lvd_api.h @@ -85,18 +85,18 @@ typedef enum LVD_THRESHOLD_MONITOR_2_LEVEL_2_92V = 0x06UL, ///< 2.92V LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V = 0x07UL, ///< 2.85V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_3_1V = 0x06UL, ///< 3.1V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_9V = 0x05UL, ///< 2.9V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_8V = 0x04UL, ///< 2.8V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_7V = 0x03UL, ///< 2.7V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_6V = 0x02UL, ///< 2.6V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_4V = 0x01UL, ///< 2.4V - LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_2V = 0x00UL, ///< 2.2V - - LVD_THRESHOLD_LVDVRTC_LEVEL_2_8V = 0x03UL, ///< 2.8V - LVD_THRESHOLD_LVDVRTC_LEVEL_2_6V = 0x02UL, ///< 2.6V - LVD_THRESHOLD_LVDVRTC_LEVEL_2_4V = 0x01UL, ///< 2.4V - LVD_THRESHOLD_LVDVRTC_LEVEL_2_2V = 0x00UL ///< 2.2V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_3_1V = 0x06UL, ///< 3.1V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_9V = 0x05UL, ///< 2.9V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_8V = 0x04UL, ///< 2.8V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_7V = 0x03UL, ///< 2.7V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_6V = 0x02UL, ///< 2.6V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_4V = 0x01UL, ///< 2.4V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_2V = 0x00UL, ///< 2.2V + + LVD_THRESHOLD_LVDVRTC_LEVEL_2_8V = 0x03UL, ///< 2.8V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_6V = 0x02UL, ///< 2.6V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_4V = 0x01UL, ///< 2.4V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_2V = 0x00UL ///< 2.2V } lvd_threshold_t; /** Response types for handling threshold crossing event. */ diff --git a/ra/fsp/inc/api/r_sce_key_injection_api.h b/ra/fsp/inc/api/r_sce_key_injection_api.h index ebee6d919..c2c08c7c2 100644 --- a/ra/fsp/inc/api/r_sce_key_injection_api.h +++ b/ra/fsp/inc/api/r_sce_key_injection_api.h @@ -373,7 +373,7 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_rsa2048_private_wrapped_key_t * const wrapped_key); -/** This API outputs 2048-bit RSA public wrapped key. + /** This API outputs 2048-bit RSA public wrapped key. * @par Implemented as * - @ref R_SCE_RSA2048_EncryptedPublicKeyWrap "R_SCE_RSA2048_EncryptedPublicKeyWrap()" * @@ -531,7 +531,7 @@ typedef struct st_sce_key_injection_api const sce_key_update_key_t * const key_update_key, sce_ecc_public_wrapped_key_t * const wrapped_key); - /** This API outputs 384-bit ECC public wrapped key. + /** This API outputs 384-bit ECC public wrapped key. * @par Implemented as * - @ref R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap "R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap()" * @@ -637,7 +637,7 @@ typedef struct st_sce_key_injection_api const uint8_t * const initial_vector, const uint8_t * const encrypted_key, sce_ecc_public_wrapped_key_t * const wrapped_key); - + /** This API outputs 384-bit Brainpool ECC private wrapped key. * @par Implemented as * - @ref R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap "R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap()" @@ -710,7 +710,6 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, const sce_key_update_key_t * const key_update_key, sce_ecc_private_wrapped_key_t * const wrapped_key); - } sce_key_injection_api_t; /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_slcdc_api.h b/ra/fsp/inc/api/r_slcdc_api.h index 2c8057397..a57aa8430 100644 --- a/ra/fsp/inc/api/r_slcdc_api.h +++ b/ra/fsp/inc/api/r_slcdc_api.h @@ -131,7 +131,7 @@ typedef enum e_slcd_contrast SLCDC_CONTRAST_19, ///< Contrast level 19 SLCDC_CONTRAST_20, ///< Contrast level 20 SLCDC_CONTRAST_21, ///< Contrast level 21 - SLCDC_CONTRAST_22, ///< Contrast level 22 + SLCDC_CONTRAST_22, ///< Contrast level 22 } slcdc_contrast_t; /** LCD Display Enable/Disable*/ @@ -161,29 +161,29 @@ typedef enum e_slcd_display_clock /** LCD clock settings */ typedef enum e_slcdc_clk_div { - SLCDC_CLK_DIVISOR_LOCO_4 = 1, ///< LOCO Clock/4 - SLCDC_CLK_DIVISOR_LOCO_8, ///< LOCO Clock/8 - SLCDC_CLK_DIVISOR_LOCO_16, ///< LOCO Clock/16 - SLCDC_CLK_DIVISOR_LOCO_32, ///< LOCO Clock/32 - SLCDC_CLK_DIVISOR_LOCO_64, ///< LOCO Clock/64 - SLCDC_CLK_DIVISOR_LOCO_128, ///< LOCO Clock/128 - SLCDC_CLK_DIVISOR_LOCO_256, ///< LOCO Clock/256 - SLCDC_CLK_DIVISOR_LOCO_512, ///< LOCO Clock/512 - SLCDC_CLK_DIVISOR_LOCO_1024, ///< LOCO Clock/1024 - - SLCDC_CLK_DIVISOR_HOCO_256 = 0x11, ///< HOCO Clock/256 - SLCDC_CLK_DIVISOR_HOCO_512, ///< HOCO Clock/512 - SLCDC_CLK_DIVISOR_HOCO_1024, ///< HOCO Clock/1024 - SLCDC_CLK_DIVISOR_HOCO_2048, ///< HOCO Clock/2048 - SLCDC_CLK_DIVISOR_HOCO_4096, ///< HOCO Clock/4096 - SLCDC_CLK_DIVISOR_HOCO_8192, ///< HOCO Clock/8192 - SLCDC_CLK_DIVISOR_HOCO_16384, ///< HOCO Clock/16384 - SLCDC_CLK_DIVISOR_HOCO_32768, ///< HOCO Clock/32768 - SLCDC_CLK_DIVISOR_HOCO_65536, ///< HOCO Clock/65536 - SLCDC_CLK_DIVISOR_HOCO_131072, ///< HOCO Clock/131072 - SLCDC_CLK_DIVISOR_HOCO_262144, ///< HOCO Clock/262144 - - SLCDC_CLK_DIVISOR_HOCO_524288 = 0x2B, ///< HOCO Clock/524288 + SLCDC_CLK_DIVISOR_LOCO_4 = 1, ///< LOCO Clock/4 + SLCDC_CLK_DIVISOR_LOCO_8, ///< LOCO Clock/8 + SLCDC_CLK_DIVISOR_LOCO_16, ///< LOCO Clock/16 + SLCDC_CLK_DIVISOR_LOCO_32, ///< LOCO Clock/32 + SLCDC_CLK_DIVISOR_LOCO_64, ///< LOCO Clock/64 + SLCDC_CLK_DIVISOR_LOCO_128, ///< LOCO Clock/128 + SLCDC_CLK_DIVISOR_LOCO_256, ///< LOCO Clock/256 + SLCDC_CLK_DIVISOR_LOCO_512, ///< LOCO Clock/512 + SLCDC_CLK_DIVISOR_LOCO_1024, ///< LOCO Clock/1024 + + SLCDC_CLK_DIVISOR_HOCO_256 = 0x11, ///< HOCO Clock/256 + SLCDC_CLK_DIVISOR_HOCO_512, ///< HOCO Clock/512 + SLCDC_CLK_DIVISOR_HOCO_1024, ///< HOCO Clock/1024 + SLCDC_CLK_DIVISOR_HOCO_2048, ///< HOCO Clock/2048 + SLCDC_CLK_DIVISOR_HOCO_4096, ///< HOCO Clock/4096 + SLCDC_CLK_DIVISOR_HOCO_8192, ///< HOCO Clock/8192 + SLCDC_CLK_DIVISOR_HOCO_16384, ///< HOCO Clock/16384 + SLCDC_CLK_DIVISOR_HOCO_32768, ///< HOCO Clock/32768 + SLCDC_CLK_DIVISOR_HOCO_65536, ///< HOCO Clock/65536 + SLCDC_CLK_DIVISOR_HOCO_131072, ///< HOCO Clock/131072 + SLCDC_CLK_DIVISOR_HOCO_262144, ///< HOCO Clock/262144 + + SLCDC_CLK_DIVISOR_HOCO_524288 = 0x2B, ///< HOCO Clock/524288 SLCDC_CLK_DIVISOR_HOCO_1048576 = 0x3B, ///< HOCO Clock/1048576 } slcdc_clk_div_t; diff --git a/ra/fsp/inc/api/r_smci_api.h b/ra/fsp/inc/api/r_smci_api.h index 6e0df9e3f..f5b420670 100644 --- a/ra/fsp/inc/api/r_smci_api.h +++ b/ra/fsp/inc/api/r_smci_api.h @@ -73,9 +73,7 @@ typedef enum e_smci_event SMCI_EVENT_RX_CHAR = (1UL << 2), ///< Character transfer is completed SMCI_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event SMCI_EVENT_ERR_LOW_SIGNAL = (1UL << 4), ///< Low error signal response occurred event - SMCI_EVENT_ERR_OVERRUN = (1UL << 5), ///< Overrun error event - SMCI_EVENT_BREAK_DETECT = (1UL << 6), ///< Character received - SMCI_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data + SMCI_EVENT_ERR_OVERRUN = (1UL << 5) ///< Overrun error event } smci_event_t; typedef enum e_smci_convention_type @@ -84,7 +82,7 @@ typedef enum e_smci_convention_type SMCI_CONVENTION_TYPE_INVERSE = 1U, ///< Inverse convention type (MSB First, Low=1) } smci_convention_type_t; -/* This table matches Table 7 from ISO/IEC7816-3 Third edition 2006-11-01 */ +/* This table matches Table 8 from ISO/IEC7816-3 Third edition 2006-11-01 */ typedef enum e_smci_clock_conversion_integer { SMCI_CLOCK_CONVERSION_INTEGER_372_4 = 0U, ///< 372 base cycles for 1-bit period, max freq = 4Mhz diff --git a/ra/fsp/inc/api/r_usb_pmsc_api.h b/ra/fsp/inc/api/r_usb_pmsc_api.h index 0942ddd67..e95fd1f78 100644 --- a/ra/fsp/inc/api/r_usb_pmsc_api.h +++ b/ra/fsp/inc/api/r_usb_pmsc_api.h @@ -45,10 +45,11 @@ FSP_HEADER /* User specific options for USB PMSC API */ #include "r_usb_basic_cfg.h" #if defined(USB_CFG_OTG_USE) -#include "r_usb_otg_msc_cfg.h" -#else /* defined(USB_CFG_OTG_USE) */ -#include "r_usb_pmsc_cfg.h" + #include "r_usb_otg_msc_cfg.h" +#else /* defined(USB_CFG_OTG_USE) */ + #include "r_usb_pmsc_cfg.h" #endif /* defined(USB_CFG_OTG_USE) */ + /*********************************************************************************************************************** * Macro definitions ***********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_pprn_api.h b/ra/fsp/inc/api/r_usb_pprn_api.h index 0e991a6f7..705e0285d 100644 --- a/ra/fsp/inc/api/r_usb_pprn_api.h +++ b/ra/fsp/inc/api/r_usb_pprn_api.h @@ -51,7 +51,7 @@ FSP_HEADER #define USB_PPRN_SOFT_RESET (0x0200U) ///< Soft Reset #define USB_PPRN_PORT_STATUS_PAPER_EMPTY (1U << 5) ///< 1: Paper Empty, 0: Paper Not Empty -#define USB_PPRN_PORT STATUS_SELECT (1U << 4) ///< 1: Selected, 0: Not Selected +#define USB_PPRN_PORT_STATUS_SELECT (1U << 4) ///< 1: Selected, 0: Not Selected #define USB_PPRN_PORT_STATUS_NOT_ERROR (1U << 3) ///< 1: No Error, 0; Error /******************************************************************************* diff --git a/ra/fsp/inc/api/rm_adpcm_decoder_api.h b/ra/fsp/inc/api/rm_adpcm_decoder_api.h index 34073f62c..898be313b 100644 --- a/ra/fsp/inc/api/rm_adpcm_decoder_api.h +++ b/ra/fsp/inc/api/rm_adpcm_decoder_api.h @@ -56,7 +56,7 @@ FSP_HEADER /** Audio Decoder general configuration */ typedef struct st_adpcm_decoder_cfg { - void const * p_extend; // Placeholder for implementation specific configuration + void const * p_extend; // Placeholder for implementation specific configuration } adpcm_decoder_cfg_t; /** Audio Decoder control block. Allocate an instance specific control block to pass into the Audio Decoder API calls. @@ -89,8 +89,8 @@ typedef struct st_adpcm_decoder_api * @param[in] p_dest Number of bytes to be decoded. * */ - fsp_err_t (* decode)(adpcm_decoder_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, - uint32_t src_len_bytes); + fsp_err_t (* decode)(adpcm_decoder_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t src_len_bytes); /** Resets the ADPCM driver. * @par Implemented as @@ -108,7 +108,6 @@ typedef struct st_adpcm_decoder_api * @param[in] p_ctrl Pointer to control handle structure */ fsp_err_t (* close)(adpcm_decoder_ctrl_t * const p_ctrl); - } adpcm_decoder_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/api/rm_block_media_api.h b/ra/fsp/inc/api/rm_block_media_api.h index 921043c1a..677e3d821 100644 --- a/ra/fsp/inc/api/rm_block_media_api.h +++ b/ra/fsp/inc/api/rm_block_media_api.h @@ -109,6 +109,7 @@ typedef struct st_rm_block_media_status * - @ref rm_block_media_sdmmc_instance_ctrl_t * - @ref rm_block_media_spi_instance_ctrl_t * - @ref rm_block_media_usb_instance_ctrl_t + * - @ref rm_block_media_ram_instance_ctrl_t */ typedef void rm_block_media_ctrl_t; @@ -121,6 +122,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_Open * - @ref RM_BLOCK_MEDIA_SPI_Open * - @ref RM_BLOCK_MEDIA_USB_Open + * - @ref RM_BLOCK_MEDIA_RAM_Open * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -133,6 +135,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_MediaInit * - @ref RM_BLOCK_MEDIA_SPI_MediaInit * - @ref RM_BLOCK_MEDIA_USB_MediaInit + * - @ref RM_BLOCK_MEDIA_RAM_MediaInit * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. */ @@ -143,6 +146,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_Read * - @ref RM_BLOCK_MEDIA_SPI_Read * - @ref RM_BLOCK_MEDIA_USB_Read + * - @ref RM_BLOCK_MEDIA_RAM_Read * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_dest_address Destination to read the data into. @@ -157,6 +161,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_Write * - @ref RM_BLOCK_MEDIA_SPI_Write * - @ref RM_BLOCK_MEDIA_USB_Write + * - @ref RM_BLOCK_MEDIA_RAM_Write * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[in] p_src_address Address to read the data to be written. @@ -171,6 +176,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_Erase * - @ref RM_BLOCK_MEDIA_SPI_Erase * - @ref RM_BLOCK_MEDIA_USB_Erase + * - @ref RM_BLOCK_MEDIA_RAM_Erase * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[in] block_address Block address to start the erase process at. @@ -199,6 +205,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_StatusGet * - @ref RM_BLOCK_MEDIA_SPI_StatusGet * - @ref RM_BLOCK_MEDIA_USB_StatusGet + * - @ref RM_BLOCK_MEDIA_RAM_StatusGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_status Pointer to store current status. @@ -210,6 +217,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_InfoGet * - @ref RM_BLOCK_MEDIA_SPI_InfoGet * - @ref RM_BLOCK_MEDIA_USB_InfoGet + * - @ref RM_BLOCK_MEDIA_RAM_InfoGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_info Pointer to information structure. All elements of this structure will be set by the @@ -222,6 +230,7 @@ typedef struct st_rm_block_media_api * - @ref RM_BLOCK_MEDIA_SDMMC_Close * - @ref RM_BLOCK_MEDIA_SPI_Close * - @ref RM_BLOCK_MEDIA_USB_Close + * - @ref RM_BLOCK_MEDIA_RAM_Close * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. */ diff --git a/ra/fsp/inc/api/rm_comms_api.h b/ra/fsp/inc/api/rm_comms_api.h index 09004b2e3..1fbf718cc 100644 --- a/ra/fsp/inc/api/rm_comms_api.h +++ b/ra/fsp/inc/api/rm_comms_api.h @@ -171,7 +171,8 @@ typedef struct st_rm_comms_api * @param[in] p_callback Callback function * @param[in] p_context Pointer to send to callback function */ - fsp_err_t (* callbackSet)(rm_comms_ctrl_t * const p_api_ctrl, void (* p_callback)(rm_comms_callback_args_t *), void const * const p_context); + fsp_err_t (* callbackSet)(rm_comms_ctrl_t * const p_api_ctrl, void (* p_callback)(rm_comms_callback_args_t *), + void const * const p_context); } rm_comms_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/fsp_features.h b/ra/fsp/inc/fsp_features.h index 13aaec26e..0d1a6d27d 100644 --- a/ra/fsp/inc/fsp_features.h +++ b/ra/fsp/inc/fsp_features.h @@ -288,7 +288,7 @@ typedef enum e_fsp_signal FSP_SIGNAL_USB_INT, ///< USB INT FSP_SIGNAL_USB_RESUME, ///< USB RESUME FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B FSP_SIGNAL_ULPT_INT, ///< ULPT INT diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 4c5c0df0c..0850eb73d 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -45,7 +45,7 @@ extern "C" { #define FSP_VERSION_MAJOR (4U) /** FSP pack minor version. */ - #define FSP_VERSION_MINOR (5U) + #define FSP_VERSION_MINOR (6U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -54,10 +54,10 @@ extern "C" { #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("4.5.0") + #define FSP_VERSION_STRING ("4.6.0") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.5.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.6.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc_b.h b/ra/fsp/inc/instances/r_adc_b.h index 1976aac81..0b689629c 100644 --- a/ra/fsp/inc/instances/r_adc_b.h +++ b/ra/fsp/inc/instances/r_adc_b.h @@ -563,6 +563,22 @@ typedef __PACKED_STRUCT st_adc_b_extended_cfg }; /* Register Data */ + union + { + uint32_t bits; // Digital filter slection mask bits + __PACKED_STRUCT + { + adc_b_digital_filter_selection_t idx_0 : 2; // Digital filter selection 0 + uint32_t : 6; + adc_b_digital_filter_selection_t idx_1 : 2; // Digital filter selection 1 + uint32_t : 6; + adc_b_digital_filter_selection_t idx_2 : 2; // Digital filter selection 2 + uint32_t : 6; + adc_b_digital_filter_selection_t idx_3 : 2; // Digital filter selection 3 + uint32_t : 6; + } settings; + } adc_filter_selection[2]; + union { uint32_t clock_control_data; ///< Clock control register data diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h index 957db17f9..d53d78ab7 100644 --- a/ra/fsp/inc/instances/r_agt.h +++ b/ra/fsp/inc/instances/r_agt.h @@ -124,8 +124,8 @@ typedef enum e_agt_pin_cfg typedef enum e_agt_counter_bit_width { AGT_COUNTER_BIT_WIDTH_DEFAULT = 0, ///< Legacy - AGT_COUNTER_BIT_WIDTH_16 = 1, ///< AGT - AGT_COUNTER_BIT_WIDTH_32 = 2, ///< AGTW + AGT_COUNTER_BIT_WIDTH_16 = 1, ///< AGT + AGT_COUNTER_BIT_WIDTH_32 = 2, ///< AGTW } agt_counter_bit_width_t; /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ @@ -154,18 +154,18 @@ typedef struct st_agt_extended_cfg struct { - agt_pin_cfg_t agtoa : 3; ///< Configure AGTOA/AGTWOA pin + agt_pin_cfg_t agtoa : 3; ///< Configure AGTOA/AGTWOA pin uint8_t : 1; - agt_pin_cfg_t agtob : 3; ///< Configure AGTOB/AGTWOB pin + agt_pin_cfg_t agtob : 3; ///< Configure AGTOB/AGTWOB pin } agtoab_settings_b; }; - agt_pin_cfg_t agto : 3; ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO + agt_pin_cfg_t agto : 3; ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO /* Input pin settings. */ - agt_measure_t measurement_mode; ///< Measurement mode - agt_agtio_filter_t agtio_filter; ///< Input filter for AGTIO - agt_enable_pin_t enable_pin; ///< Enable pin (event counting only) - agt_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event + agt_measure_t measurement_mode; ///< Measurement mode + agt_agtio_filter_t agtio_filter; ///< Input filter for AGTIO + agt_enable_pin_t enable_pin; ///< Enable pin (event counting only) + agt_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event agt_counter_bit_width_t counter_bit_width; ///< Counter bit width } agt_extended_cfg_t; diff --git a/ra/fsp/inc/instances/r_canfd.h b/ra/fsp/inc/instances/r_canfd.h index 8f8d720aa..18da97b3a 100644 --- a/ra/fsp/inc/instances/r_canfd.h +++ b/ra/fsp/inc/instances/r_canfd.h @@ -40,6 +40,12 @@ FSP_HEADER * Macro definitions **********************************************************************************************************************/ +#if BSP_FEATURE_CANFD_LITE + #define R_CANFD_NUM_COMMON_FIFOS (1U) +#else + #define R_CANFD_NUM_COMMON_FIFOS (6U) +#endif + /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -87,6 +93,34 @@ typedef enum e_canfd_error CANFD_ERROR_GLOBAL_CH1_ECC = 0x20000000, ///< Channel 1 ECC Error } canfd_error_t; +/** CANFD Transmit Buffer (MB + CFIFO) */ +typedef enum e_canfd_tx_buffer +{ + CANFD_TX_BUFFER_0 = 0, + CANFD_TX_BUFFER_1 = 1, + CANFD_TX_BUFFER_2 = 2, + CANFD_TX_BUFFER_3 = 3, +#if !BSP_FEATURE_CANFD_LITE + CANFD_TX_BUFFER_4 = 4, + CANFD_TX_BUFFER_5 = 5, + CANFD_TX_BUFFER_6 = 6, + CANFD_TX_BUFFER_7 = 7, + CANFD_TX_BUFFER_32 = 32, + CANFD_TX_BUFFER_33 = 33, + CANFD_TX_BUFFER_34 = 34, + CANFD_TX_BUFFER_35 = 35, + CANFD_TX_BUFFER_36 = 36, + CANFD_TX_BUFFER_37 = 37, + CANFD_TX_BUFFER_38 = 38, + CANFD_TX_BUFFER_39 = 39, +#endif + CANFD_TX_BUFFER_FIFO_COMMON_0 = 40, +#if !BSP_FEATURE_CANFD_LITE + CANFD_TX_BUFFER_FIFO_COMMON_1 = 41, + CANFD_TX_BUFFER_FIFO_COMMON_2 = 42, +#endif +} canfd_tx_buffer_t; + /** CANFD Transmit Message Buffer (TX MB) */ typedef enum e_canfd_tx_mb { @@ -110,7 +144,7 @@ typedef enum e_canfd_tx_mb #endif } canfd_tx_mb_t; -/** CANFD Receive Buffer (MB + FIFO) */ +/** CANFD Receive Buffer (MB + FIFO + CFIFO) */ typedef enum e_canfd_rx_buffer { CANFD_RX_BUFFER_MB_0 = 0, @@ -154,6 +188,11 @@ typedef enum e_canfd_rx_buffer CANFD_RX_BUFFER_FIFO_5 = 37, CANFD_RX_BUFFER_FIFO_6 = 38, CANFD_RX_BUFFER_FIFO_7 = 39, +#endif + CANFD_RX_BUFFER_FIFO_COMMON_0 = 40, +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_BUFFER_FIFO_COMMON_1 = 41, + CANFD_RX_BUFFER_FIFO_COMMON_2 = 42, #endif } canfd_rx_buffer_t; @@ -207,6 +246,14 @@ typedef enum e_canfd_rx_fifo CANFD_RX_FIFO_5 = (1U << 5), CANFD_RX_FIFO_6 = (1U << 6), CANFD_RX_FIFO_7 = (1U << 7), +#endif + CANFD_RX_FIFO_COMMON_0 = (1U << 8), +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_FIFO_COMMON_1 = (1U << 9), + CANFD_RX_FIFO_COMMON_2 = (1U << 10), + CANFD_RX_FIFO_COMMON_3 = (1U << 11), + CANFD_RX_FIFO_COMMON_4 = (1U << 12), + CANFD_RX_FIFO_COMMON_5 = (1U << 13), #endif } canfd_rx_fifo_t; @@ -243,7 +290,7 @@ typedef enum e_canfd_frame_option /* CAN Instance Control Block */ typedef struct st_canfd_instance_ctrl { - R_CANFD_Type * p_reg; // Pointer to register base address + R_CANFD_Type * p_reg; // Pointer to register base address /* Parameters to control CAN peripheral device */ can_cfg_t const * p_cfg; // Pointer to the configuration structure @@ -305,16 +352,17 @@ typedef struct st_canfd_afl_entry_t /** CANFD Global Configuration */ typedef struct st_canfd_global_cfg { - uint32_t global_interrupts; ///< Global control options (CFDGCTR register setting) - uint32_t global_config; ///< Global configuration options (CFDGCFG register setting) + uint32_t global_interrupts; ///< Global control options (CFDGCTR register setting) + uint32_t global_config; ///< Global configuration options (CFDGCFG register setting) #if !BSP_FEATURE_CANFD_LITE - uint32_t rx_fifo_config[8]; ///< RX FIFO configuration (CFDRFCCn register settings) + uint32_t rx_fifo_config[8]; ///< RX FIFO configuration (CFDRFCCn register settings) #else - uint32_t rx_fifo_config[2]; ///< RX FIFO configuration (CFDRFCCn register settings) + uint32_t rx_fifo_config[2]; ///< RX FIFO configuration (CFDRFCCn register settings) #endif - uint32_t rx_mb_config; ///< Number and size of RX Message Buffers (CFDRMNB register setting) - uint8_t global_err_ipl; ///< Global Error interrupt priority - uint8_t rx_fifo_ipl; ///< RX FIFO interrupt priority + uint32_t rx_mb_config; ///< Number and size of RX Message Buffers (CFDRMNB register setting) + uint8_t global_err_ipl; ///< Global Error interrupt priority + uint8_t rx_fifo_ipl; ///< RX FIFO interrupt priority + uint32_t common_fifo_config[R_CANFD_NUM_COMMON_FIFOS]; ///< Common FIFO configurations } canfd_global_cfg_t; /** CANFD Extended Configuration */ diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h index 346a2066a..8f9f3202c 100644 --- a/ra/fsp/inc/instances/r_ctsu.h +++ b/ra/fsp/inc/instances/r_ctsu.h @@ -19,7 +19,7 @@ **********************************************************************************************************************/ /*******************************************************************************************************************//** - * @addtogroup CTSU + * @addtogroup CTSU * @{ **********************************************************************************************************************/ @@ -36,7 +36,6 @@ /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ FSP_HEADER - /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ @@ -270,54 +269,54 @@ typedef struct st_ctsu_diag_info /** CTSU private control block. DO NOT MODIFY. Initialization occurs when R_CTSU_Open() is called. */ typedef struct st_ctsu_instance_ctrl { - uint32_t open; ///< Whether or not driver is open. - volatile ctsu_state_t state; ///< CTSU run state. - ctsu_cap_t cap; ///< CTSU Scan Start Trigger Select - ctsu_md_t md; ///< CTSU Measurement Mode Select(copy to cfg) - ctsu_tuning_t tuning; ///< CTSU Initial offset tuning status. - uint16_t num_elements; ///< Number of elements to scan - uint16_t wr_index; ///< Word index into ctsuwr register array. - uint16_t rd_index; ///< Word index into scan data buffer. - uint8_t * p_element_complete_flag; ///< Pointer to complete flag of each element. g_ctsu_element_complete_flag[] is set by Open API. + uint32_t open; ///< Whether or not driver is open. + volatile ctsu_state_t state; ///< CTSU run state. + ctsu_cap_t cap; ///< CTSU Scan Start Trigger Select + ctsu_md_t md; ///< CTSU Measurement Mode Select(copy to cfg) + ctsu_tuning_t tuning; ///< CTSU Initial offset tuning status. + uint16_t num_elements; ///< Number of elements to scan + uint16_t wr_index; ///< Word index into ctsuwr register array. + uint16_t rd_index; ///< Word index into scan data buffer. + uint8_t * p_element_complete_flag; ///< Pointer to complete flag of each element. g_ctsu_element_complete_flag[] is set by Open API. #if (BSP_FEATURE_CTSU_VERSION == 2) - uint8_t * p_frequency_complete_flag; ///< Pointer to complete flag of each frequency. g_ctsu_frequency_complete_flag[] is set by Open API. + uint8_t * p_frequency_complete_flag; ///< Pointer to complete flag of each frequency. g_ctsu_frequency_complete_flag[] is set by Open API. #endif - int32_t * p_tuning_diff; ///< Pointer to difference from base value of each element. g_ctsu_tuning_diff[] is set by Open API. - uint16_t average; ///< CTSU Moving average counter. - uint16_t num_moving_average; ///< Copy from config by Open API. - uint8_t ctsucr1; ///< Copy from (atune1 << 3, md << 6) by Open API. CLK, ATUNE0, CSW, and PON is set by HAL driver. - ctsu_ctsuwr_t * p_ctsuwr; ///< CTSUWR write register value. g_ctsu_ctsuwr[] is set by Open API. - ctsu_self_buf_t * p_self_raw; ///< Pointer to Self raw data. g_ctsu_self_raw[] is set by Open API. - uint16_t * p_self_corr; ///< Pointer to Self correction data. g_ctsu_self_corr[] is set by Open API. - ctsu_data_t * p_self_data; ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API. - ctsu_mutual_buf_t * p_mutual_raw; ///< Pointer to Mutual raw data. g_ctsu_mutual_raw[] is set by Open API. - uint16_t * p_mutual_pri_corr; ///< Pointer to Mutual primary correction data. g_ctsu_self_corr[] is set by Open API. - uint16_t * p_mutual_snd_corr; ///< Pointer to Mutual secondary correction data. g_ctsu_self_corr[] is set by Open API. - ctsu_data_t * p_mutual_pri_data; ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API. - ctsu_data_t * p_mutual_snd_data; ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API. - ctsu_correction_info_t * p_correction_info; ///< Pointer to correction info - ctsu_txvsel_t txvsel; ///< CTSU Transmission Power Supply Select - ctsu_txvsel2_t txvsel2; ///< CTSU Transmission Power Supply Select 2 (CTSU2 Only) - uint8_t ctsuchac0; ///< TS00-TS07 enable mask - uint8_t ctsuchac1; ///< TS08-TS15 enable mask - uint8_t ctsuchac2; ///< TS16-TS23 enable mask - uint8_t ctsuchac3; ///< TS24-TS31 enable mask - uint8_t ctsuchac4; ///< TS32-TS39 enable mask - uint8_t ctsuchtrc0; ///< TS00-TS07 mutual-tx mask - uint8_t ctsuchtrc1; ///< TS08-TS15 mutual-tx mask - uint8_t ctsuchtrc2; ///< TS16-TS23 mutual-tx mask - uint8_t ctsuchtrc3; ///< TS24-TS31 mutual-tx mask - uint8_t ctsuchtrc4; ///< TS32-TS39 mutual-tx mask - uint16_t self_elem_index; ///< self element index number for Current instance. - uint16_t mutual_elem_index; ///< mutual element index number for Current instance. - uint16_t ctsu_elem_index; ///< CTSU element index number for Current instance. + int32_t * p_tuning_diff; ///< Pointer to difference from base value of each element. g_ctsu_tuning_diff[] is set by Open API. + uint16_t average; ///< CTSU Moving average counter. + uint16_t num_moving_average; ///< Copy from config by Open API. + uint8_t ctsucr1; ///< Copy from (atune1 << 3, md << 6) by Open API. CLK, ATUNE0, CSW, and PON is set by HAL driver. + ctsu_ctsuwr_t * p_ctsuwr; ///< CTSUWR write register value. g_ctsu_ctsuwr[] is set by Open API. + ctsu_self_buf_t * p_self_raw; ///< Pointer to Self raw data. g_ctsu_self_raw[] is set by Open API. + uint16_t * p_self_corr; ///< Pointer to Self correction data. g_ctsu_self_corr[] is set by Open API. + ctsu_data_t * p_self_data; ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API. + ctsu_mutual_buf_t * p_mutual_raw; ///< Pointer to Mutual raw data. g_ctsu_mutual_raw[] is set by Open API. + uint16_t * p_mutual_pri_corr; ///< Pointer to Mutual primary correction data. g_ctsu_self_corr[] is set by Open API. + uint16_t * p_mutual_snd_corr; ///< Pointer to Mutual secondary correction data. g_ctsu_self_corr[] is set by Open API. + ctsu_data_t * p_mutual_pri_data; ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API. + ctsu_data_t * p_mutual_snd_data; ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API. + ctsu_correction_info_t * p_correction_info; ///< Pointer to correction info + ctsu_txvsel_t txvsel; ///< CTSU Transmission Power Supply Select + ctsu_txvsel2_t txvsel2; ///< CTSU Transmission Power Supply Select 2 (CTSU2 Only) + uint8_t ctsuchac0; ///< TS00-TS07 enable mask + uint8_t ctsuchac1; ///< TS08-TS15 enable mask + uint8_t ctsuchac2; ///< TS16-TS23 enable mask + uint8_t ctsuchac3; ///< TS24-TS31 enable mask + uint8_t ctsuchac4; ///< TS32-TS39 enable mask + uint8_t ctsuchtrc0; ///< TS00-TS07 mutual-tx mask + uint8_t ctsuchtrc1; ///< TS08-TS15 mutual-tx mask + uint8_t ctsuchtrc2; ///< TS16-TS23 mutual-tx mask + uint8_t ctsuchtrc3; ///< TS24-TS31 mutual-tx mask + uint8_t ctsuchtrc4; ///< TS32-TS39 mutual-tx mask + uint16_t self_elem_index; ///< self element index number for Current instance. + uint16_t mutual_elem_index; ///< mutual element index number for Current instance. + uint16_t ctsu_elem_index; ///< CTSU element index number for Current instance. #if (BSP_FEATURE_CTSU_VERSION == 2) - uint8_t * p_selected_freq_self; ///< Frequency selected by self-capacity - uint8_t * p_selected_freq_mutual; ///< Frequency selected by mutual-capacity + uint8_t * p_selected_freq_self; ///< Frequency selected by self-capacity + uint8_t * p_selected_freq_mutual; ///< Frequency selected by mutual-capacity #endif #if (BSP_FEATURE_CTSU_VERSION == 1) #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) - ctsu_diag_info_t * p_diag_info; ///< pointer to diagnosis info + ctsu_diag_info_t * p_diag_info; ///< pointer to diagnosis info #endif #endif @@ -374,7 +373,7 @@ fsp_err_t R_CTSU_SpecificDataGet(ctsu_ctrl_t * const p_ctrl, uint16_t * p_specific_data, ctsu_specific_data_type_t specific_data_type); fsp_err_t R_CTSU_DataInsert(ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_data); -fsp_err_t R_CTSU_OffsetTuning (ctsu_ctrl_t * const p_ctrl); +fsp_err_t R_CTSU_OffsetTuning(ctsu_ctrl_t * const p_ctrl); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_sci_smci.h b/ra/fsp/inc/instances/r_sci_smci.h index 8edf2a734..4d54244d8 100644 --- a/ra/fsp/inc/instances/r_sci_smci.h +++ b/ra/fsp/inc/instances/r_sci_smci.h @@ -143,10 +143,6 @@ fsp_err_t R_SCI_SMCI_CallbackSet(smci_ctrl_t * const p_api_ctrl, smci_callback_args_t * const p_callback_memory); fsp_err_t R_SCI_SMCI_Close(smci_ctrl_t * const p_api_ctrl); -void sci_smci_rxi_isr(void); -void sci_smci_txi_isr(void); -void sci_smci_eri_isr(void); - /*******************************************************************************************************************//** * @} (end addtogroup SCI_SMCI) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_ulpt.h b/ra/fsp/inc/instances/r_ulpt.h index 9059578b0..89550212c 100644 --- a/ra/fsp/inc/instances/r_ulpt.h +++ b/ra/fsp/inc/instances/r_ulpt.h @@ -55,17 +55,16 @@ typedef enum e_ulpt_clock /** Counter mode for event enable. */ typedef enum e_ulpt_enable_function { - // R_ULPT0_ULPTIOC_TIOGT0_Msk 0X00 0000 0=Always count, 1 count external events (Not to be mized with nonzero TEECTL) - // R_ULPT0_ULPTISR_RCCPSEL2_Msk 0000 0X00 0=count low level, 1 count high level, only valid when TIOGT0=1 (Not to be mized with nonzero TEECTL) - // R_ULPT0_ULPTMR3_TEECTL_Msk 00XX 0000 - //0100 0000 Count external high, - //0100 0100 Count external low + // R_ULPT0_ULPTIOC_TIOGT0_Msk 0X00 0000 0=Always count, 1 count external events (Not to be mized with nonzero TEECTL) + // R_ULPT0_ULPTISR_RCCPSEL2_Msk 0000 0X00 0=count low level, 1 count high level, only valid when TIOGT0=1 (Not to be mized with nonzero TEECTL) + // R_ULPT0_ULPTMR3_TEECTL_Msk 00XX 0000 + // 0100 0000 Count external high, + // 0100 0100 Count external low ULPT_ENABLE_FUNCTION_IGNORED = 0x00U, ///< Always count external events, ignore ULPTEE. ULPT_ENABLE_FUNCTION_ENABLE_LOW = 0x40U, ///< Event counting is enabled while ULPTEE is low (event counting only). ULPT_ENABLE_FUNCTION_ENABLE_HIGH = 0x44U, ///< Event counting is enabled while ULPTEE is high (event counting only). ULPT_ENABLE_FUNCTION_START = 0x20U, ///< Counting is started after ULPTEE. ULPT_ENABLE_FUNCTION_RESTART = 0x30U, ///< Counting is restarted after ULPTEE. - } ulpt_enable_function_t; /** Enable signal trigger edge for start and restart functions. */ @@ -94,9 +93,9 @@ typedef enum e_ulpt_output_pin /** ULPTO pulse output pin. */ typedef enum e_ulpt_pulse_pin_cfg { - ULPT_PULSE_PIN_CFG_DISABLED = 0x00U, ///< Output pin disabled. + ULPT_PULSE_PIN_CFG_DISABLED = 0x00U, ///< Output pin disabled. ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_LOW = 0x01U, ///< Output pin Enabled Start Low - ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH = 0x02U, ///< Output pin enabled Start Hig + ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH = 0x02U, ///< Output pin enabled Start Hig } ulpt_pulse_pin_cfg_t; /** ULPT match output pin. */ diff --git a/ra/fsp/inc/instances/rm_adpcm_decoder.h b/ra/fsp/inc/instances/rm_adpcm_decoder.h index a2ff59ce7..9e2ab9a4e 100644 --- a/ra/fsp/inc/instances/rm_adpcm_decoder.h +++ b/ra/fsp/inc/instances/rm_adpcm_decoder.h @@ -56,9 +56,9 @@ FSP_HEADER * Initialized in @ref adpcm_decoder_api_t::open(). */ typedef struct st_adpcm_decoder_instance_ctrl { - int8_t id; // Step size - int16_t vp; // Variable to hold last PCM sample value - uint32_t opened; // Flag to determine if the device is open + int8_t id; // Step size + int16_t vp; // Variable to hold last PCM sample value + uint32_t opened; // Flag to determine if the device is open } adpcm_decoder_instance_ctrl_t; /********************************************************************************************************************** @@ -75,8 +75,10 @@ extern const adpcm_decoder_api_t g_adpcm_decoder_on_adpcm_decoder; * Public APIs **********************************************************************************************************************/ fsp_err_t RM_ADPCM_DECODER_Open(adpcm_decoder_ctrl_t * p_ctrl, adpcm_decoder_cfg_t const * const p_cfg); -fsp_err_t RM_ADPCM_DECODER_Decode(adpcm_decoder_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, - uint32_t src_len_bytes); +fsp_err_t RM_ADPCM_DECODER_Decode(adpcm_decoder_ctrl_t * const p_ctrl, + void const * p_src, + void * p_dest, + uint32_t src_len_bytes); fsp_err_t RM_ADPCM_DECODER_Reset(adpcm_decoder_ctrl_t * p_ctrl); fsp_err_t RM_ADPCM_DECODER_Close(adpcm_decoder_ctrl_t * p_ctrl); diff --git a/ra/fsp/inc/instances/rm_ble_abs.h b/ra/fsp/inc/instances/rm_ble_abs.h index e77080d2e..e209afe3b 100644 --- a/ra/fsp/inc/instances/rm_ble_abs.h +++ b/ra/fsp/inc/instances/rm_ble_abs.h @@ -29,9 +29,9 @@ #include "bsp_api.h" #include "r_ble_cfg.h" -#if defined (BLE_CFG_RYZ012_DEVICE) +#if defined(BLE_CFG_RYZ012_DEVICE) #include "rm_ble_abs_spp_cfg.h" -#elif defined (BLE_CFG_DA14xxx_DEVICE) +#elif defined(BLE_CFG_DA14xxx_DEVICE) #include "rm_ble_abs_gtl_cfg.h" #else #include "rm_ble_abs_cfg.h" diff --git a/ra/fsp/inc/instances/rm_block_media_ram.h b/ra/fsp/inc/instances/rm_block_media_ram.h index e7463261d..d9bb03673 100644 --- a/ra/fsp/inc/instances/rm_block_media_ram.h +++ b/ra/fsp/inc/instances/rm_block_media_ram.h @@ -72,18 +72,18 @@ extern const rm_block_media_api_t g_rm_block_media_on_ram_media; fsp_err_t RM_BLOCK_MEDIA_RAM_Open(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_cfg_t const * const p_cfg); fsp_err_t RM_BLOCK_MEDIA_RAM_MediaInit(rm_block_media_ctrl_t * const p_ctrl); fsp_err_t RM_BLOCK_MEDIA_RAM_Read(rm_block_media_ctrl_t * const p_ctrl, - uint8_t * const p_dest_address, - uint32_t const block_address, - uint32_t const num_blocks); + uint8_t * const p_dest_address, + uint32_t const block_address, + uint32_t const num_blocks); fsp_err_t RM_BLOCK_MEDIA_RAM_Write(rm_block_media_ctrl_t * const p_ctrl, - uint8_t const * const p_src_address, - uint32_t const block_address, - uint32_t const num_blocks); + uint8_t const * const p_src_address, + uint32_t const block_address, + uint32_t const num_blocks); fsp_err_t RM_BLOCK_MEDIA_RAM_Erase(rm_block_media_ctrl_t * const p_ctrl, - uint32_t const block_address, - uint32_t const num_blocks); + uint32_t const block_address, + uint32_t const num_blocks); fsp_err_t RM_BLOCK_MEDIA_RAM_StatusGet(rm_block_media_ctrl_t * const p_api_ctrl, - rm_block_media_status_t * const p_status); + rm_block_media_status_t * const p_status); fsp_err_t RM_BLOCK_MEDIA_RAM_InfoGet(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info); fsp_err_t RM_BLOCK_MEDIA_RAM_Close(rm_block_media_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/instances/rm_motor_driver.h b/ra/fsp/inc/instances/rm_motor_driver.h index 8adc2c2ac..b55f60f99 100644 --- a/ra/fsp/inc/instances/rm_motor_driver.h +++ b/ra/fsp/inc/instances/rm_motor_driver.h @@ -45,6 +45,13 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ +/** Support two ADC instance valid for adc */ +typedef enum e_motor_driver_select_adc_instance +{ + MOTOR_DRIVER_SELECT_ADC_INSTANCE_FIRST = 0, ///< Use first ADC instance + MOTOR_DRIVER_SELECT_ADC_INSTANCE_SECOND, ///< Use second ADC instanse +} motor_driver_select_adc_instance_t; + /* Modulation type selection */ typedef enum e_motor_driver_modulation_method { @@ -71,36 +78,67 @@ typedef struct st_motor_driver_modulation uint8_t u1_sat_flag; ///< Saturation flag } motor_driver_modulation_t; +/** For multiple motor */ +typedef struct st_motor_driver_shared_instance_ctrl +{ + uint32_t open; + uint8_t registered_motor_count; ///< Registered motor counts + void const * p_context[MOTOR_DRIVER_CFG_SUPPORT_MOTOR_NUM]; +} motor_driver_shared_instance_ctrl_t; + +/** For multiple motor */ +typedef struct st_motor_driver_extended_shared_cfg +{ + adc_instance_t const * p_adc_instance_first; ///< first ADC instance + adc_instance_t const * p_adc_instance_second; ///< second ADC instance + + motor_driver_shared_instance_ctrl_t * const p_shared_instance_ctrl; +} motor_driver_extended_shared_cfg_t; + typedef struct st_motor_driver_extended_cfg { - uint16_t u2_pwm_timer_freq; ///< PWM timer frequency [MHz] - uint16_t u2_pwm_carrier_freq; ///< PWM carrier frequency [kHz] - uint16_t u2_deadtime; ///< PWM deadtime [usec] + uint16_t u2_pwm_timer_freq; ///< PWM timer frequency [MHz] + uint16_t u2_pwm_carrier_freq; ///< PWM carrier frequency [kHz] + uint16_t u2_deadtime; ///< PWM deadtime [usec] - float f_current_range; ///< A/D current measure range (max current) [A] - float f_vdc_range; ///< A/D main line voltage measure range (max voltage) [V] - float f_ad_resolution; ///< A/D resolution - float f_ad_current_offset; ///< A/D offset (Center value) - float f_ad_voltage_conversion; ///< A/D conversion level + float f_current_range; ///< A/D current measure range (max current) [A] + float f_vdc_range; ///< A/D main line voltage measure range (max voltage) [V] + float f_ad_resolution; ///< A/D resolution + float f_ad_current_offset; ///< A/D offset (Center value) + float f_ad_voltage_conversion; ///< A/D conversion level - uint16_t u2_offset_calc_count; ///< Calculation counts for current offset + uint16_t u2_offset_calc_count; ///< Calculation counts for current offset - motor_driver_modulation_method_t modulation_method; ///< Modulation method + motor_driver_modulation_method_t modulation_method; ///< Modulation method /* PWM output port */ - bsp_io_port_pin_t port_up; ///< PWM output port UP - bsp_io_port_pin_t port_un; ///< PWM output port UN - bsp_io_port_pin_t port_vp; ///< PWM output port VP - bsp_io_port_pin_t port_vn; ///< PWM output port VN - bsp_io_port_pin_t port_wp; ///< PWM output port WP - bsp_io_port_pin_t port_wn; ///< PWM output port WN + bsp_io_port_pin_t port_up; ///< PWM output port UP + bsp_io_port_pin_t port_un; ///< PWM output port UN + bsp_io_port_pin_t port_vp; ///< PWM output port VP + bsp_io_port_pin_t port_vn; ///< PWM output port VN + bsp_io_port_pin_t port_wp; ///< PWM output port WP + bsp_io_port_pin_t port_wn; ///< PWM output port WN /* For 1shunt */ - float f_ad_current_adjust; ///< Adjustment value for 1shunt A/D current - int32_t s4_difference_minimum; ///< Minimum difference of PWM duty - int32_t s4_adjust_adc_delay; ///< Adjustment delay for A/D conversion + float f_ad_current_adjust; ///< Adjustment value for 1shunt A/D current + int32_t s4_difference_minimum; ///< Minimum difference of PWM duty + int32_t s4_adjust_adc_delay; ///< Adjustment delay for A/D conversion + + /* For multiple motor */ + adc_group_mask_t adc_group; ///< Used ADC scan group only valid for adc_b + + /* Channel assignment */ + uint8_t iu_ad_unit; ///< Used A/D unit number for U phase current + uint8_t iv_ad_unit; ///< Used A/D unit number for V phase current + uint8_t iw_ad_unit; ///< Used A/D unit number for W phase current + uint8_t vdc_ad_unit; ///< Used A/D unit number for main line voltage + uint8_t sin_ad_unit; ///< Used A/D unit number for sin signal of induction sensor + uint8_t cos_ad_unit; ///< Used A/D unit number for cos signal of induction sensor motor_driver_modulation_t mod_param; + + motor_driver_select_adc_instance_t interrupt_adc; ///< Select which interrupt to use + motor_driver_extended_shared_cfg_t const * p_shared_cfg; ///< Shared extended config } motor_driver_extended_cfg_t; typedef struct st_motor_driver_instance_ctrl @@ -148,6 +186,9 @@ typedef struct st_motor_driver_instance_ctrl /* For GPT(Timer) callback */ timer_callback_args_t timer_callback_args; ///< For call GPT(Timer) callbackSet function + + /* Shared ADC */ + motor_driver_shared_instance_ctrl_t * p_shared_instance_ctrl; } motor_driver_instance_ctrl_t; /********************************************************************************************************************** diff --git a/ra/fsp/inc/instances/rm_motor_sense_hall.h b/ra/fsp/inc/instances/rm_motor_sense_hall.h index ac9809054..ddfe51beb 100644 --- a/ra/fsp/inc/instances/rm_motor_sense_hall.h +++ b/ra/fsp/inc/instances/rm_motor_sense_hall.h @@ -49,6 +49,19 @@ typedef enum e_motor_sense_hall_direction MOTOR_SENSE_HALL_DIRECTION_CCW = 0, ///< Rotation direction counter clockwise } motor_sense_hall_direction_t; +typedef enum e_motor_sense_hall_signal_status +{ + MOTOR_SENSE_HALL_SIGNAL_STATUS_INITIAL = 1, ///< Hall signal isn't captured. (Initial) + MOTOR_SENSE_HALL_SIGNAL_STATUS_CAPTURED = 0, ///< Hall signal is captured. +} motor_sense_hall_signal_status_t; + +/** This stucture is provided to receive speed information. */ +typedef struct st_motor_sense_hall_input +{ + float f4_ref_speed_rad_ctrl; ///< Speed Reference [rad/sec] +} motor_sense_hall_input_t; + +/** Optional Motor sense hall extension data structure. */ typedef struct st_motor_sense_hall_extended_cfg { bsp_io_port_pin_t port_hall_sensor_u; ///< Hall U-signal input port BSP_IO_PORT_12_PIN_04 @@ -60,12 +73,18 @@ typedef struct st_motor_sense_hall_extended_cfg float f_pwm_carrier_freq; ///< PWM carrier frequency 20.0kHz float f_angle_correct; ///< Coefficent to correct angle 0.4 + uint8_t u1_trigger_hall_signal_count; ///< Rotation counts to wait the stability + float f4_target_pseudo_speed_rad; ///< Target value for pseudo speed estimates [radian/second] + float f4_reach_time_msec; ///< Time until the pseudo speed estimate reaches the target value [msec] + uint16_t u2_trigger_carrier_count; ///< Estimated speed 0 until this trigger + uint16_t u2_default_counts; ///< Default counts for period of hall signal to reset uint16_t u2_maximum_period; ///< Maximum counts of hall signal period uint8_t u1_hall_polepairs; ///< Hall pole pairs } motor_sense_hall_extended_cfg_t; +/** SENSE_HALL control block. DO NOT INITIALIZE. Initialization occurs when @ref motor_angle_api_t::open is called. */ typedef struct st_motor_sense_hall_instance_ctrl { uint32_t open; @@ -81,6 +100,15 @@ typedef struct st_motor_sense_hall_instance_ctrl float f_angle_per_count; ///< Angle per 1 count float f_calculated_speed; ///< Calculated speed [radian/second] + /* For startup */ + uint8_t u1_hall_signal_memory; ///< Memorized hall signal at startup + motor_sense_hall_signal_status_t hall_signal_status; ///< Hall signal status + uint8_t u1_hall_signal_count; ///< Rotation counter + float f4_pseudo_speed_rad; ///< Pseudo speed used for startup [radian/second] + float f4_add_pseudo_speed_rad; ///< Step of pseudo speed to update [radian/second] + uint16_t u2_startup_carrier_count; ///< Counter of carrier interrupt for startup + motor_sense_hall_input_t st_input; ///< Input parameter structure + motor_angle_cfg_t const * p_cfg; } motor_sense_hall_instance_ctrl_t; diff --git a/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h b/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h index f8bdab319..7e2c7fe8b 100644 --- a/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h +++ b/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h @@ -41,9 +41,6 @@ #define MQTT_ONCHIP_DA16XXX_MAX_PUBTOPICMSG_LEN (2063) ///< Maximum total length for message + topic supported by DA16XXX. #define MQTT_ONCHIP_DA16XXX_SUBTOPIC_MAX_CNT (32) ///< Maximum number of subscription topics allowed. -#define MQTT_ONCHIP_DA16XXX_CFG_CMD_TX_BUF_SIZE (2048) ///< Size of the transmit buffer for the MQTT client. -#define MQTT_ONCHIP_DA16XXX_CFG_CMD_RX_BUF_SIZE (3000) ///< Size of the receive buffer for the MQTT client. - /** MQTT Quality-of-service (QoS) levels */ typedef enum e_mqtt_onchip_da16xxx_qos { diff --git a/ra/fsp/inc/instances/rm_rai_data_shipper.h b/ra/fsp/inc/instances/rm_rai_data_shipper.h index 1a395a606..6c49d45f2 100644 --- a/ra/fsp/inc/instances/rm_rai_data_shipper.h +++ b/ra/fsp/inc/instances/rm_rai_data_shipper.h @@ -33,6 +33,7 @@ #include #include "bsp_api.h" +#include "rm_rai_data_collector_cfg.h" #include "rm_rai_data_shipper_cfg.h" #include "rm_rai_data_shipper_api.h" @@ -49,11 +50,7 @@ FSP_HEADER **********************************************************************************************************************/ /* Max number of data channels (including CRC) to be sent */ -#ifdef RM_RAI_DATA_COLLECTOR_CFG_MAX_CHANNELS - #define RM_RAI_DATA_SHIPPER_CFG_MAX_CHANNELS (RM_RAI_DATA_COLLECTOR_CFG_MAX_CHANNELS + 1) // Sensor data from Data collector + 1 channel for CRC -#else - #define RM_RAI_DATA_SHIPPER_CFG_MAX_CHANNELS (16) -#endif +#define RM_RAI_DATA_SHIPPER_CFG_MAX_CHANNELS (RM_RAI_DATA_COLLECTOR_CFG_MAX_CHANNELS + 1) // Sensor data from Data collector + 1 channel for CRC /* Header buffer structure */ typedef __PACKED_STRUCT st_rai_data_shipper_header_buffer_type diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h index e6c05a8e3..f95845729 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -4627,17 +4627,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 22; } CFDGFDCFG_b; }; - - union - { - __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */ - - struct - { - __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */ - uint32_t : 31; - } CFDGCRCCFG_b; - }; + __IM uint32_t RESERVED34; union { @@ -4691,7 +4681,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 16; } CFDGAFLIGNCTR_b; }; - __IM uint32_t RESERVED34; + __IM uint32_t RESERVED35; union { @@ -4734,7 +4724,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 22; } CFDCDTSTS_b; }; - __IM uint32_t RESERVED35[2]; + __IM uint32_t RESERVED36[2]; union { @@ -4775,7 +4765,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 14; } CFDCDTTSTS_b; }; - __IM uint32_t RESERVED36[2]; + __IM uint32_t RESERVED37[2]; union { @@ -4795,7 +4785,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 1; } CFDGRINTSTS_b[2]; }; - __IM uint32_t RESERVED37[10]; + __IM uint32_t RESERVED38[10]; union { @@ -4809,18 +4799,18 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure uint32_t : 16; } CFDGRSTC_b; }; - __IM uint32_t RESERVED38[31]; + __IM uint32_t RESERVED39[31]; __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED39[240]; + __IM uint32_t RESERVED40[240]; __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED40[448]; + __IM uint32_t RESERVED41[448]; __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED41[3072]; + __IM uint32_t RESERVED42[3072]; __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED42[1600]; + __IM uint32_t RESERVED43[1600]; __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED43[252]; + __IM uint32_t RESERVED44[252]; union { @@ -4831,7 +4821,7 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ } CFDRPGACC_b[64]; }; - __IM uint32_t RESERVED44[7872]; + __IM uint32_t RESERVED45[7872]; __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ } R_CANFD_Type; /*!< Size = 81920 (0x14000) */ @@ -21504,9 +21494,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ====================================================== CFDGCRCCFG ======================================================= */ - #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */ - #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */ /* ======================================================= CFDGLOCKK ======================================================= */ #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index b8081ff9f..e1dfa0bc0 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -280,16 +280,6 @@ void SystemInit (void) #endif #endif -#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN - - /* Turn on graphics power domain. - * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ - R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); - R_SYSTEM->PDCTRGD = 0; - (void) R_SYSTEM->PDCTRGD; - R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); -#endif - /* Call post clock initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); @@ -434,6 +424,18 @@ void SystemInit (void) R_BSP_SecurityInit(); #endif +#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN + + /* Turn on graphics power domain. + * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + R_SYSTEM_PDCTRGD_PDPGSF_Msk); + R_SYSTEM->PDCTRGD = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +#endif + /* Call Post C runtime initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_POST_C); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index 279a1b6fb..bcc2d98ec 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -79,7 +79,7 @@ /* Stop interval of at least 5 SOSC clock cycles between stop and restart of SOSC. * Calculated based on 8Mhz of MOCO clock. */ -#define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (1220U) +#define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (200U) /* Locations of bitfields used to configure Peripheral Clocks. */ #define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS (6U) @@ -248,8 +248,8 @@ #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1) - #define BSP_PRV_PLLCCR (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ - (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT) + #define BSP_PRV_PLLCCR ((BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ + (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)) #endif #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE @@ -527,12 +527,15 @@ static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_ro #if defined(__ICCARM__) void R_BSP_SubClockStabilizeWait(uint32_t delay_ms); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms); #pragma weak R_BSP_SubClockStabilizeWait + #pragma weak R_BSP_SubClockStabilizeWaitAfterReset #elif defined(__GNUC__) || defined(__ARMCC_VERSION) void R_BSP_SubClockStabilizeWait(uint32_t delay_ms) __attribute__((weak)); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms) __attribute__((weak)); #endif #endif @@ -553,6 +556,9 @@ static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode); #if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET static void bsp_prv_clock_set_hard_reset(void); +#else +void bsp_soft_reset_prepare(void); + #endif void prv_clock_dividers_set(uint32_t sckdivcr, uint8_t sckdivcr2); @@ -1189,6 +1195,147 @@ static void bsp_clock_freq_var_init (void) SystemCoreClockUpdate(); } +#if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + +/* + * If the clock registers are not guaranteed to be set to their value after reset (Ie. the application is executing after a bootloader), + * then the current state of the registers must be taken into consideration before writing the clock configuration. + * + * The HOCO must be stopped in the following situations: + * - The application configures the HOCO to be stopped. + * - The application enables the FLL, but the HOCO is already running. In order to enable the FLL, the HOCO must be stopped. + * The PLL must be stopped in the following situations: + * - The application configures the PLL to be stopped. + * - The application configures settings that are different than the current settings, but the PLL is already running. In order to + * write new PLL settings, the PLL must be stopped. + * - The HOCO is the PLL source clock and the HOCO is being stopped. + * The PLL2 must be stopped in the following situations: + * - The application configures the PLL2 to be stopped. + * - The application configures settings that are different than the current settings, but the PLL2 is already running. In order to + * write new PLL2 settings, the PLL2 must be stopped. + * - The HOCO is the PLL2 source clock and the HOCO is being stopped. + * + * If the HOCO or PLL are being used as the system clock source and they need to be stopped, then the system clock source needs to be switched + * to the default system clock source before the current system clock source is disabled. + */ +void bsp_soft_reset_prepare (void) +{ + bool stop_hoco = false; + #if BSP_PRV_PLL_SUPPORTED + bool stop_pll = false; + #endif + #if BSP_PRV_PLL2_SUPPORTED + bool stop_pll2 = false; + #endif + + #if BSP_PRV_HOCO_USE_FLL || !BSP_PRV_HOCO_USED + #if BSP_PRV_HOCO_USE_FLL + + /* Determine if the FLL needs to be enabled. */ + bool enable_fll = (0 == R_SYSTEM->FLLCR1 && BSP_PRV_HOCO_USE_FLL); + #else + bool enable_fll = false; + #endif + + /* If the HOCO is already enabled and either the FLL needs to be enabled or the HOCO is not used, then stop the HOCO. */ + if ((0 == R_SYSTEM->HOCOCR) && (enable_fll || !BSP_PRV_HOCO_USED)) + { + stop_hoco = true; + } + #endif + + #if BSP_PRV_PLL_SUPPORTED + if (0 == R_SYSTEM->PLLCR) + { + /* + * If any of the following conditions are true, then the PLL needs to be stopped: + * - The PLL is not used + * - The PLL settings need to be changed + * - The HOCO is selected as the PLL clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL_USED + #if 3 == BSP_FEATURE_CGC_PLLCCR_TYPE + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (BSP_PRV_PLLCCR2 != R_SYSTEM->PLLCCR2) || + (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #elif 2 == BSP_FEATURE_CGC_PLLCCR_TYPE + if (BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR2) + #else + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #endif + #endif + { + stop_pll = true; + } + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (0 == R_SYSTEM->PLL2CR) + { + /* + * If any of the following conditions are true, then the PLL2 needs to be stopped: + * - The PLL2 is not used + * - The PLL2 settings need to be changed + * - The HOCO is selected as the PLL2 clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL2_USED + #if 3 == BSP_FEATURE_CGC_PLLCCR_TYPE + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (BSP_PRV_PLL2CCR2 != R_SYSTEM->PLL2CCR2) || + (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #else + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #endif + #endif + { + stop_pll2 = true; + } + } + #endif + + uint8_t sckscr = R_SYSTEM->SCKSCR; + + /* If the System Clock source needs to be stopped, then switch to the MOCO. */ + #if BSP_PRV_PLL_SUPPORTED + if ((stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) || + (stop_pll && (BSP_CLOCKS_SOURCE_CLOCK_PLL == sckscr))) + #else + if (stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) + #endif + { + bsp_prv_clock_set(BSP_FEATURE_CGC_STARTUP_SCKSCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR2); + } + + /* Disable the oscillators so that the application can write the new clock configuration. */ + + #if BSP_PRV_PLL_SUPPORTED + if (stop_pll) + { + R_SYSTEM->PLLCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0); + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (stop_pll2) + { + R_SYSTEM->PLL2CR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0); + } + #endif + + if (stop_hoco) + { + R_SYSTEM->HOCOCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 0); + } +} + +#endif + /*******************************************************************************************************************//** * Initializes system clocks. Makes no assumptions about current register settings. **********************************************************************************************************************/ @@ -1218,6 +1365,12 @@ void bsp_clock_init (void) bsp_clock_freq_var_init(); +#if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Transition to an intermediate clock configuration in order to prepare for writing the new clock configuraiton. */ + bsp_soft_reset_prepare(); +#endif + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET @@ -1247,28 +1400,50 @@ void bsp_clock_init (void) #if BSP_FEATURE_CGC_HAS_SOSC #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED - - /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ - if (0U == R_SYSTEM->SOSCCR) + if (R_SYSTEM->SOSCCR || (BSP_CLOCK_CFG_SUBCLOCK_DRIVE != R_SYSTEM->SOMCR_b.SODRV)) { - /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ - R_SYSTEM->SOSCCR = 1U; + /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity + * and restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* + * r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: + * When changing the value of the SOSTP bit, execute subsequent instructions + * only after reading the bit to check that the value is updated. + */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } - /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity - * and restarting Sub-Clock Oscillator. */ - R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); - } + /* Configure the subclock drive as subclock is not running. */ + R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); - /* Configure the subclock drive as subclock is not running. */ - R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); + R_SYSTEM->SOSCCR = 0U; - /* Restart the Sub-Clock Oscillator. */ - R_SYSTEM->SOSCCR = 0U; + /* r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: + * After setting the SOSTP bit to 0, use the sub-clock only after the sub-clock + * oscillation stabilization time has elapsed. + */ #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) - - /* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */ - R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); #endif + } + else + { + /* + * RA MCUs like RA6M5 requires to use sub-clock after oscillation stabilization time + * has elapsed on Power-On-Reset. But, POR is not well supported on EK boards, so BSP + * has to wait on any reset. Please override this function in application if waiting + * for stabilization is not required. + */ + R_BSP_SubClockStabilizeWaitAfterReset(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + } + #else R_SYSTEM->SOSCCR = 1U; #endif @@ -1378,59 +1553,71 @@ void bsp_clock_init (void) #endif #endif #if BSP_PRV_MAIN_OSC_USED - R_SYSTEM->MOSCCR = 0U; + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->MOSCCR) + #endif + { + R_SYSTEM->MOSCCR = 0U; #if BSP_PRV_STABILIZE_MAIN_OSC - /* Wait for main oscillator to stabilize. */ - FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); + /* Wait for main oscillator to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); #endif + } #endif /* Start clocks that require other clocks. At this point, all dependent clocks are running and stable if needed. */ #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED - R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLL2CR) + #endif + { + R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) - R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2; + R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2; #endif - /* Start PLL2. */ - R_SYSTEM->PLL2CR = 0U; + /* Start PLL2. */ + R_SYSTEM->PLL2CR = 0U; + } #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */ #endif #if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED - - /* Configure the PLL registers. */ + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLLCR) + #endif + { #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE - R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; + R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE - R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; - R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2; + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2; #endif #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0 - /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some - * MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100). - * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of - * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running - * while setting PLLCCR. */ - bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); + /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some + * MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100). + * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of + * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running + * while setting PLLCCR. */ + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); #endif - /* Start the PLL. */ - R_SYSTEM->PLLCR = 0U; + R_SYSTEM->PLLCR = 0U; #if BSP_PRV_STABILIZE_PLL - /* Wait for PLL to stabilize. */ - FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U); + /* Wait for PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U); #endif + } #endif /* Set source clock and dividers. */ @@ -1453,27 +1640,6 @@ void bsp_clock_init (void) /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */ #if !BSP_CFG_USE_LOW_VOLTAGE_MODE #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED - #if BSP_PRV_PLL_SUPPORTED - #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET - if (BSP_PRV_OPERATING_MODE_LOW_SPEED == BSP_PRV_STARTUP_OPERATING_MODE) - { - /* If the MCU has a PLL, ensure PLL is stopped and stable before entering low speed mode. */ - R_SYSTEM->PLLCR = 1U; - - /* Wait for PLL to stabilize. */ - FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0U); - - #if BSP_FEATURE_CGC_HAS_PLL2 - - /* If the MCU has a PLL2, ensure PLL2 is stopped and stable before entering low speed mode. */ - R_SYSTEM->PLL2CR = 1U; - - /* Wait for PLL to stabilize. */ - FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0U); - #endif - } - #endif - #endif bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE); #endif #endif @@ -1522,7 +1688,7 @@ void bsp_clock_init (void) R_SYSTEM->SCKDIVCR2 = BSP_PRV_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV && !BSP_FEATURE_BSP_HAS_USBCKDIVCR */ - /* If there is a REQ bit in USBCKCR than follow sequence from section 8.2.29 in RA6M4 hardware manual R01UH0890EJ0050. */ + /* If there is a REQ bit in USBCKCR, then follow sequence from section 8.2.29 in RA6M4 hardware manual R01UH0890EJ0050. */ #if BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ /* Request to change the USB Clock. */ @@ -1670,6 +1836,25 @@ void R_BSP_SubClockStabilizeWait (uint32_t delay_ms) R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); } +/*******************************************************************************************************************//** + * This function is called during SOSC registers initialization when Sub-Clock oscillator is populated. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to skip waiting for stabilization time after reset. + * To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] delay_ms Stabilization Time for the clock. + **********************************************************************************************************************/ +void R_BSP_SubClockStabilizeWaitAfterReset (uint32_t delay_ms) +{ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + + /* Wait for clock to stabilize after reset. */ + R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); + #else + FSP_PARAMETER_NOT_USED(delay_ms); + #endif +} + #endif #if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U) @@ -2017,6 +2202,10 @@ void R_BSP_Init_RTC (void) /* Disable RTC interrupts */ R_RTC->RCR1 = 0; + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see section 26.2.17 "RTC Control Register 1 (RCR1)" of the RA6M3 manual R01UH0886EJ0100)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1, 0); + #if BSP_FEATURE_RTC_HAS_TCEN for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++) { diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index 8e0d65449..2ac5d8c9d 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -281,7 +281,7 @@ FSP_HEADER * X=Integer portion of the multiplier. * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((X) -BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) + #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) #elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index 296340106..bb601f3fc 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -49,11 +49,11 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} /*******************************************************************************************************************//** * Enables the module stop state. @@ -61,151 +61,153 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} /** @} (end addtogroup BSP_MCU) */ #if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); #ifndef BSP_MSTP_REG_FSP_IP_AGT - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD #endif #ifndef BSP_MSTP_BIT_FSP_IP_AGT - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); #endif - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); #else #if (2U == BSP_FEATURE_ELC_VERSION) #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); #endif #endif -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); -#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) - #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); #else - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); #endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c index 1e0ff6d48..32595e626 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -212,8 +212,11 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3 BSP_CFG_ROM_REG_OFS3_SEL; #endif + #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel = - 0xFFFFFFFF; + BSP_CFG_ROM_REG_BANKSEL_SEL; + + #endif BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 = BSP_CFG_ROM_REG_BPS_SEL0; BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel1") g_bsp_rom_bps_sel1 = diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 421ac6bfa..7cb9297ff 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -215,6 +215,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44000404) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -359,7 +362,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index 6dd346b6a..e40e26174 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -213,6 +213,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // @@ -357,7 +360,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h index c91ee607b..08b187118 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h @@ -213,6 +213,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) // #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // @@ -357,7 +360,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index 9b421477b..feae0d656 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -213,6 +213,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -357,7 +360,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h index c14e4a0d2..9c8a900a8 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h index 3f0d861ba..3d38b28d0 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h @@ -216,6 +216,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -359,7 +362,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index 45bd4b979..750c55493 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -215,6 +215,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -359,7 +362,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index 060da0a09..bf7d107c9 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -217,7 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) // Feature not available on this MCU - +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) @@ -361,7 +363,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index 3c290d875..67d70f802 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h index 752283ea2..67590e1ed 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index c544dbce2..88183539f 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -215,6 +215,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -359,7 +362,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h index 4a2f2be8f..4e5585ebd 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h index e263417dd..da00169a6 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h @@ -216,6 +216,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -359,7 +362,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index fad000009..f176a7206 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -219,6 +219,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -363,7 +366,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index 1b025deff..eaf6c6d3d 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -219,6 +219,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -363,7 +366,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index d569170e5..f5b1b0072 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -219,6 +219,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -363,7 +366,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index 176c7719d..118f48f18 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h index dbd810c3d..0d8b4dfbc 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index f92f2a529..f8e2e6e99 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -219,6 +219,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -363,7 +366,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h index e0439a9e5..6efbe1a14 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h index 5020afa84..d336f7314 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h @@ -217,6 +217,9 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) @@ -361,7 +364,8 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) diff --git a/ra/fsp/src/r_adc_b/r_adc_b.c b/ra/fsp/src/r_adc_b/r_adc_b.c index 2ee01c3ec..df60ad094 100644 --- a/ra/fsp/src/r_adc_b/r_adc_b.c +++ b/ra/fsp/src/r_adc_b/r_adc_b.c @@ -210,10 +210,9 @@ fsp_err_t R_ADC_B_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) R_ADC_B->ADSHSTR0 = p_extend->sample_and_hold_config_012; R_ADC_B->ADSHSTR1 = p_extend->sample_and_hold_config_456; - /* Configure Digital filters - DFSEL1 is Sync3 and DFSEL2 is 'Phase', for both ADC 0 and 1. These settings are - * configured once and groups are updated to use the desired filter. */ - R_ADC_B->ADDFSR0 = ADC_B_DIGITAL_FILTER_SELECTION; - R_ADC_B->ADDFSR1 = ADC_B_DIGITAL_FILTER_SELECTION; + /* Configure Digital filters */ + R_ADC_B->ADDFSR0 = p_extend->adc_filter_selection[0].bits; + R_ADC_B->ADDFSR1 = p_extend->adc_filter_selection[1].bits; adc_b_open_pga(p_extend); diff --git a/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.5.0.xml.j2 b/ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 similarity index 79% rename from ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.5.0.xml.j2 rename to ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 index eb70f9da8..d36530594 100644 --- a/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.5.0.xml.j2 +++ b/ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 @@ -1,3 +1,10 @@ +{% if 'r_canfd' == module_variant %} + {% set num_rx_fifos=8 %} + {% set num_common_fifos=6 %} +{% else %} + {% set num_rx_fifos=2 %} + {% set num_common_fifos=1 %} +{% endif %} {% macro deref_id(id_prefix,name) %}${{ '{' + id_prefix + '.driver.' + id_name() + '.' + name + '}' }}{% endmacro %} {% macro id_name() %}{%- if 'r_canfd' == module_variant %}canfd{%- else %}canfdlite{%- endif %}{% endmacro %} {% macro rx_fifo_properties(id_prefix, index) %} @@ -19,16 +26,138 @@ + + + + + + - - + @@ -496,7 +449,7 @@ This file was generated using: ra/fsp/src/r_canfd/.util/canfd_gen.py testSymbol("${module.driver.{{ id_name() }}.afl_array}") -{%- if 'r_canfdlite' == module_variant %}{{ global_config('module',2) }}{%- endif %} +{%- if 'r_canfdlite' == module_variant %}{{ global_config('module', num_rx_fifos, num_common_fifos) }}{%- endif %} @@ -572,10 +525,23 @@ canfd_global_cfg_t g_canfd_global_cfg = ((CANFD_CFG_RXFIFO7_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO7_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO7_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO7_INT_MODE) | (CANFD_CFG_RXFIFO7_ENABLE)), #endif }, + .common_fifo_config = + { + CANFD_CFG_COMMONFIFO0, +#if !BSP_FEATURE_CANFD_LITE + CANFD_CFG_COMMONFIFO1, + CANFD_CFG_COMMONFIFO2, + CANFD_CFG_COMMONFIFO3, + CANFD_CFG_COMMONFIFO4, + CANFD_CFG_COMMONFIFO5, +#endif + } }; #endif {%- else %} +{{ common_fifo_config('module', num_common_fifos) }} + /* Buffer RAM used: ${module.driver.{{ id_name() }}.buffer_ram_used} bytes */ canfd_global_cfg_t ${module.driver.{{ id_name() }}.name}_global_cfg = { @@ -584,10 +550,14 @@ canfd_global_cfg_t ${module.driver.{{ id_name() }}.name}_global_cfg = .rx_mb_config = (${module.driver.{{ id_name() }}.rxmb.number} | (${module.driver.{{ id_name() }}.rxmb.size} << R_CANFD_CFDRMNB_RMPLS_Pos)), .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, - .rx_fifo_config = + .rx_fifo_config = { (${module.driver.{{ id_name() }}.rxfifo.0.int_threshold} << R_CANFD_CFDRFCC_RFIGCV_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.depth} << R_CANFD_CFDRFCC_RFDC_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.payload} << R_CANFD_CFDRFCC_RFPLS_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.int_mode}) | (${module.driver.{{ id_name() }}.rxfifo.0.enable}), (${module.driver.{{ id_name() }}.rxfifo.1.int_threshold} << R_CANFD_CFDRFCC_RFIGCV_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.depth} << R_CANFD_CFDRFCC_RFDC_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.payload} << R_CANFD_CFDRFCC_RFPLS_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.int_mode}) | (${module.driver.{{ id_name() }}.rxfifo.1.enable}) + }, + .common_fifo_config = + { + CANFD_CFG_COMMONFIFO0 } }; {%- endif %} @@ -620,6 +590,11 @@ const can_cfg_t ${module.driver.{{ id_name() }}.name}_cfg = .p_extend = &${module.driver.{{ id_name() }}.name}_extended_cfg, .p_context = NULL, .ipl = ${module.driver.{{ id_name() }}.ipl}, +#if defined(VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_COMFRX) + .rx_irq = VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_COMFRX, +#else + .rx_irq = FSP_INVALID_VECTOR, +#endif #if defined(VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_TX) .tx_irq = VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_TX, #else @@ -812,9 +787,9 @@ const can_instance_t ${module.driver.{{ id_name() }}.name} = -