diff --git a/LICENSE.txt b/LICENSE.txt index 633742c90..a08352dc2 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -1,17 +1,17 @@ -Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - -This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products -of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are -sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use -of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property -right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas -reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION -IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT -PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES -OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR -DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM -EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION -(OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, -WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, -OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY -OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. +Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + +This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products +of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are +sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use +of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property +right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas +reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION +IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT +PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES +OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR +DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM +EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION +(OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, +WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, +OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY +OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. diff --git a/README.md b/README.md index dbf7f3e5f..ce2f6bb11 100644 --- a/README.md +++ b/README.md @@ -1,73 +1,80 @@ -## Overview - -Flexible Software Package (FSP) for Renesas RA MCU Family - -FSP is the next generation Arm® MCU software package from Renesas, that enables secure devices and IoT connectivity through production ready peripheral drivers, FreeRTOS, and portable middleware stacks. -FSP includes best-in-class HAL drivers with high performance and low memory footprint. Middleware stacks with FreeRTOS integration are included to ease implementation of complex modules like communication and security. -The e² studio ISDE provides support with intuitive configurators and intelligent code generation to make programming and debugging easier and faster. - -FSP uses an open software ecosystem and provides flexibility in using your preferred RTOS, legacy code, and third-party ecosystem solutions. - -### Current Release - -[FSP v2.3.0](https://github.com/renesas/fsp/releases/tag/v2.3.0) - -### Supported RA MCU Kits - -- EK-RA2A1 -- EK-RA2E1 -- EK-RA2L1 -- EK-RA4M1 -- EK-RA4M2 -- EK-RA4M3 -- EK-RA4W1 -- EK-RA6M1 -- EK-RA6M2 -- EK-RA6M3 -- EK-RA6M3G -- EK-RA6M4 -- RSSK-RA2L1 -- RSSK-RA6T1 - -### Setup Instructions - -#### For existing users that are using FSP with e² studio - -- FSP versions of 2.0.0 and later require a minimum e² studio version of 2020-10. -- FSP versions of 2.3.0 and later require a minimum e² studio version of 2021-01. - -If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, and an installer version, FSP_Packs_\.exe. - -#### For new users that are using FSP with e² studio - -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v2.3.0). -2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. - -#### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### - -1. See [RA SC User Guide for MDK and IAR](https://renesas.github.io/fsp/_s_t_a_r_t__d_e_v.html#RASC-MDK-IAR-user-guide). - -### Starting Development - -1. Open e² studio and click File > New > C/C++ Project. -2. In the window that pops up, choose Renesas RA in the left pane. - -### Related Links - -FSP Releases : https://github.com/renesas/fsp/releases - -FSP Documentation : https://renesas.github.io/fsp - -FSP Webpage: www.renesas.com/ra/fsp - -RA Product Information: www.renesas.com/ra - -RA Product Support Forum: www.renesas.com/ra/forum - -e² studio : www.renesas.com/e2studio - -Example Projects : www.renesas.com/ra/example-projects - -Knowledge Base: https://en-support.renesas.com/knowledgeBase/category/31087 - -Support: www.renesas.com/support +## Overview + +Flexible Software Package (FSP) for Renesas RA MCU Family + +FSP is the next generation Arm® MCU software package from Renesas, that enables secure devices and IoT connectivity through production ready peripheral drivers, FreeRTOS, and portable middleware stacks. +FSP includes best-in-class HAL drivers with high performance and low memory footprint. Middleware stacks with FreeRTOS integration are included to ease implementation of complex modules like communication and security. +The e² studio ISDE provides support with intuitive configurators and intelligent code generation to make programming and debugging easier and faster. + +FSP uses an open software ecosystem and provides flexibility in using your preferred RTOS, legacy code, and third-party ecosystem solutions. + +### Current Release + +[FSP v2.4.0](https://github.com/renesas/fsp/releases/tag/v2.4.0) + +### Supported RA MCU Kits + +- EK-RA2A1 +- EK-RA2E1 +- EK-RA2L1 +- EK-RA4M1 +- EK-RA4M2 +- EK-RA4M3 +- EK-RA4W1 +- EK-RA6M1 +- EK-RA6M2 +- EK-RA6M3 +- EK-RA6M3G +- EK-RA6M4 +- EK-RA6M5 +- RSSK-RA2L1 +- RSSK-RA6T1 + +### Known Issues + +[Visit GitHub Issues for this project.](https://github.com/renesas/fsp/issues) + +[Critical issues](https://github.com/renesas/fsp/issues?q=label%3Acritical+is%3Aclosed) that cause an MCU to operate out of the hardware manual documented specifications are tagged with the 'critical' label. Please check critical issues before going to production for a fix, workaround, or recommended patch upgrade. + +### Setup Instructions + +#### For existing users that are using FSP with e² studio + +- FSP versions of 2.0.0 and later require a minimum e² studio version of 2020-10. +- FSP versions of 2.3.0 and later require a minimum e² studio version of 2021-01. + +If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, and an installer version, FSP_Packs_\.exe. + +#### For new users that are using FSP with e² studio + +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v2.4.0). +2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. + +#### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### + +1. See [RA SC User Guide for MDK and IAR](https://renesas.github.io/fsp/_s_t_a_r_t__d_e_v.html#RASC-MDK-IAR-user-guide). + +### Starting Development + +1. Open e² studio and click File > New > C/C++ Project. +2. In the window that pops up, choose Renesas RA in the left pane. + +### Related Links + +FSP Releases : https://github.com/renesas/fsp/releases + +FSP Documentation : https://renesas.github.io/fsp + +FSP Webpage: www.renesas.com/ra/fsp + +RA Product Information: www.renesas.com/ra + +RA Product Support Forum: www.renesas.com/ra/forum + +e² studio : www.renesas.com/e2studio + +Example Projects : www.renesas.com/ra/example-projects + +Knowledge Base: https://en-support.renesas.com/knowledgeBase/category/31087 + +Support: www.renesas.com/support diff --git a/ra/board/ra6m5_ek/board.h b/ra/board/ra6m5_ek/board.h new file mode 100644 index 000000000..f616d5aba --- /dev/null +++ b/ra/board/ra6m5_ek/board.h @@ -0,0 +1,70 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA6M5_EK for the RA6M5-EK board + * @brief BSP for the RA6M5-EK Board + * + * The RA6M5_EK is a development kit for the Renesas R7FA6M5BH3CFC microcontroller in a LQFP176 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA6M5_EK + +/* Except for BSP_CLOCK_CFG_SUBCLOCK_POPULATED and _MAIN_OSC_POPULATED, these are just default settings, not based on the board design. */ +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS (1000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA6M5_EK) */ + +#endif diff --git a/ra/board/ra6m5_ek/board_ethernet_phy.h b/ra/board/ra6m5_ek/board_ethernet_phy.h new file mode 100644 index 000000000..1972fa46d --- /dev/null +++ b/ra/board/ra6m5_ek/board_ethernet_phy.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6M5_EK + * @defgroup BOARD_RA6M5_EK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RA6M5_EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_PHY_TYPE (1) +#define BOARD_PHY_REF_CLK (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M5_EK_ETHERNET_PHY) */ diff --git a/ra/board/ra6m5_ek/board_init.c b/ra/board/ra6m5_ek/board_init.c new file mode 100644 index 000000000..e4c09d6b8 --- /dev/null +++ b/ra/board/ra6m5_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_EK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA6M5_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA6M5_EK) */ diff --git a/ra/board/ra6m5_ek/board_init.h b/ra/board/ra6m5_ek/board_init.h new file mode 100644 index 000000000..0c0c1153b --- /dev/null +++ b/ra/board/ra6m5_ek/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_EK + * @brief Board specific code for the RA6M5-EK Board + * + * This include file is specific to the RA6M5-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA6M5_EK) */ diff --git a/ra/board/ra6m5_ek/board_leds.c b/ra/board/ra6m5_ek/board_leds.c new file mode 100644 index 000000000..cdbdaa202 --- /dev/null +++ b/ra/board/ra6m5_ek/board_leds.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_EK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA6M5_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_00_PIN_06, ///< LED1 + (uint16_t) BSP_IO_PORT_00_PIN_07, ///< LED2 + (uint16_t) BSP_IO_PORT_00_PIN_08, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA6M5_EK_LEDS) */ diff --git a/ra/board/ra6m5_ek/board_leds.h b/ra/board/ra6m5_ek/board_leds.h new file mode 100644 index 000000000..f471d4bc0 --- /dev/null +++ b/ra/board/ra6m5_ek/board_leds.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6M5_EK + * @defgroup BOARD_RA6M5_EK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M5_EK_LEDS) */ diff --git a/ra/fsp/inc/api/r_can_api.h b/ra/fsp/inc/api/r_can_api.h index e1e1add3a..a2149a5fa 100644 --- a/ra/fsp/inc/api/r_can_api.h +++ b/ra/fsp/inc/api/r_can_api.h @@ -34,7 +34,10 @@ * - Callback function support with returning event code * - Hardware resource locking during a transaction * - * Implemented by: @ref CAN + * Implemented by: + * - @ref CAN + * - @ref CANFD + * * @{ **********************************************************************************************************************/ @@ -51,8 +54,14 @@ FSP_HEADER /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define CAN_API_VERSION_MAJOR (1U) // DEPRECATED -#define CAN_API_VERSION_MINOR (1U) // DEPRECATED +#define CAN_API_VERSION_MAJOR (1U) // DEPRECATED +#define CAN_API_VERSION_MINOR (1U) // DEPRECATED + +#if BSP_FEATURE_CANFD_NUM_CHANNELS + #define CAN_DATA_BUFFER_LENGTH (64) +#else + #define CAN_DATA_BUFFER_LENGTH (8) +#endif /********************************************************************************************************************** * Typedef definitions @@ -66,65 +75,45 @@ typedef enum e_can_event CAN_EVENT_ERR_BUS_OFF = 8, ///< Bus Off event. CAN_EVENT_BUS_RECOVERY = 16, ///< Bus Off Recovery event. CAN_EVENT_MAILBOX_MESSAGE_LOST = 32, ///< Mailbox has been overrun. + CAN_EVENT_ERR_BUS_LOCK = 128, ///< Bus lock detected (32 consecutive dominant bits). + CAN_EVENT_ERR_CHANNEL = 256, ///< Channel error has occurred. + CAN_EVENT_TX_ABORTED = 512, ///< Transmit abort event. CAN_EVENT_RX_COMPLETE = 1024, ///< Receive complete event. - CAN_EVENT_TX_COMPLETE = 2048 ///< Transmit complete event. + CAN_EVENT_TX_COMPLETE = 2048, ///< Transmit complete event. + CAN_EVENT_ERR_GLOBAL = 4096, ///< Global error has occurred. } can_event_t; -/** CAN Status */ -typedef enum e_can_status -{ - CAN_STATUS_NEW_DATA = 1, ///< New Data status flag - CAN_STATUS_SENT_DATA = 2, ///< Sent Data status flag - CAN_STATUS_RECEIVE_FIFO = 4, ///< Receive FIFO status flag (Not supported) - CAN_STATUS_TRANSMIT_FIFO = 8, ///< Transmit FIFO status flag (Not supported) - CAN_STATUS_NORMAL_MBOX_MESSAGE_LOST = 16, ///< Normal mailbox message lost status flag - CAN_STATUS_FIFO_MBOX_MESSAGE_LOST = 32, ///< FIFO mailbox message lost status flag (Not Supported) - CAN_STATUS_TRANSMISSION_ABORT = 64, ///< Transmission abort status flag - CAN_STATUS_ERROR = 128, ///< Error status flag - CAN_STATUS_RESET_MODE = 256, ///< Reset mode status flag - CAN_STATUS_HALT_MODE = 512, ///< Halt mode status flag - CAN_STATUS_SLEEP_MODE = 1024, ///< Sleep mode status flag - CAN_STATUS_ERROR_PASSIVE = 2048, ///< Error-passive status flag - CAN_STATUS_BUS_OFF = 4096, ///< Bus-off status flag -} can_status_t; - -/** CAN Error Code */ -typedef enum e_can_error -{ - CAN_ERROR_STUFF = 1, ///< Stuff Error - CAN_ERROR_FORM = 2, ///< Form Error - CAN_ERROR_ACK = 4, ///< ACK Error - CAN_ERROR_CRC = 8, ///< CRC Error - CAN_ERROR_BIT_RECESSIVE = 16, ///< Bit Error (recessive) Error - CAN_ERROR_BIT_DOMINANT = 32, ///< Bit Error (dominant) Error - CAN_ERROR_ACK_DELIMITER = 64, ///< ACK Delimiter Error - CAN_ERROR_ERROR_DISPLAY_MODE = 128, ///< Error Display mode -} can_error_t; - /** CAN Operation modes */ typedef enum e_can_operation_mode { - CAN_OPERATION_MODE_NORMAL = 0, ///< CAN Normal Operation Mode. - CAN_OPERATION_MODE_RESET, ///< CAN Reset Operation Mode. - CAN_OPERATION_MODE_HALT, ///< CAN Halt Operation Mode. - CAN_OPERATION_MODE_SLEEP ///< CAN SLEEP Operation Mode. + CAN_OPERATION_MODE_NORMAL = 0, ///< CAN Normal Operation Mode + CAN_OPERATION_MODE_RESET, ///< CAN Reset Operation Mode + CAN_OPERATION_MODE_HALT, ///< CAN Halt Operation Mode + CAN_OPERATION_MODE_SLEEP = 5, ///< CAN Sleep Operation Mode + CAN_OPERATION_MODE_GLOBAL_OPERATION = 0x80, // CANFD Global Operation Mode + CAN_OPERATION_MODE_GLOBAL_RESET, // CANFD Global Reset Mode + CAN_OPERATION_MODE_GLOBAL_HALT, // CANFD Global Halt Mode + CAN_OPERATION_MODE_GLOBAL_SLEEP = 0x85 // CANFD Global Sleep Mode } can_operation_mode_t; /** CAN Test modes */ typedef enum e_can_test_mode { - CAN_TEST_MODE_DISABLED = 0, ///< CAN Test Mode Disabled. - CAN_TEST_MODE_LISTEN = 3, ///< CAN Test Listen Mode. - CAN_TEST_MODE_LOOPBACK_EXTERNAL = 5, ///< CAN Test External Loopback Mode. - CAN_TEST_MODE_LOOPBACK_INTERNAL = 7 ///< CAN Test Internal Loopback Mode. + CAN_TEST_MODE_DISABLED = 0, ///< CAN Test Mode Disabled. + CAN_TEST_MODE_LISTEN = 3, ///< CAN Test Listen Mode. + CAN_TEST_MODE_LOOPBACK_EXTERNAL = 5, ///< CAN Test External Loopback Mode. + CAN_TEST_MODE_LOOPBACK_INTERNAL = 7, ///< CAN Test Internal Loopback Mode. + CAN_TEST_MODE_INTERNAL_BUS = 0x80 ///< CANFD Internal CAN Bus Communication Test Mode. } can_test_mode_t; typedef struct st_can_info { - can_status_t status; ///< Useful information from the CAN status register. - uint8_t error_count_transmit; ///< Transmit error count. - uint8_t error_count_receive; ///< Receive error count. - can_error_t error_code; ///< Error code, cleared after reading. + uint32_t status; ///< Useful information from the CAN status register. + uint32_t rx_mb_status; ///< CANFD RX Message Buffer New Data flags. + uint32_t rx_fifo_status; ///< CANFD RX FIFO Empty flags. + uint8_t error_count_transmit; ///< Transmit error count. + uint8_t error_count_receive; ///< Receive error count. + uint32_t error_code; ///< Error code, cleared after reading. } can_info_t; /** CAN ID modes */ @@ -134,11 +123,19 @@ typedef enum e_can_id_mode CAN_ID_MODE_EXTENDED, ///< Extended IDs of 29 bits used. } can_id_mode_t; +/** Global CAN ID mode settings */ +typedef enum e_can_global_id_mode +{ + CAN_GLOBAL_ID_MODE_STANDARD, ///< Standard IDs of 11 bits used. + CAN_GLOBAL_ID_MODE_EXTENDED, ///< Extended IDs of 29 bits used. + CAN_GLOBAL_ID_MODE_MIXED, ///< Both Standard and Extended IDs used. +} can_global_id_mode_t; + /** CAN frame types */ typedef enum e_can_frame_type { - CAN_FRAME_TYPE_DATA, ///< Data frame type. - CAN_FRAME_TYPE_REMOTE, ///< Remote frame type. + CAN_FRAME_TYPE_DATA, ///< Data frame. + CAN_FRAME_TYPE_REMOTE, ///< Remote frame. } can_frame_type_t; /** CAN Message Modes */ @@ -155,119 +152,88 @@ typedef enum e_can_clock_source CAN_CLOCK_SOURCE_CANMCLK, ///< CANMCLK is the source of the CAN Clock } can_clock_source_t; -/** CAN Time Segment 1 Time Quanta */ -typedef enum e_can_time_segment1 -{ - CAN_TIME_SEGMENT1_TQ4 = 3, ///< Time Segment 1 setting for 4 Time Quanta - CAN_TIME_SEGMENT1_TQ5, ///< Time Segment 1 setting for 5 Time Quanta - CAN_TIME_SEGMENT1_TQ6, ///< Time Segment 1 setting for 6 Time Quanta - CAN_TIME_SEGMENT1_TQ7, ///< Time Segment 1 setting for 7 Time Quanta - CAN_TIME_SEGMENT1_TQ8, ///< Time Segment 1 setting for 8 Time Quanta - CAN_TIME_SEGMENT1_TQ9, ///< Time Segment 1 setting for 9 Time Quanta - CAN_TIME_SEGMENT1_TQ10, ///< Time Segment 1 setting for 10 Time Quanta - CAN_TIME_SEGMENT1_TQ11, ///< Time Segment 1 setting for 11 Time Quanta - CAN_TIME_SEGMENT1_TQ12, ///< Time Segment 1 setting for 12 Time Quanta - CAN_TIME_SEGMENT1_TQ13, ///< Time Segment 1 setting for 13 Time Quanta - CAN_TIME_SEGMENT1_TQ14, ///< Time Segment 1 setting for 14 Time Quanta - CAN_TIME_SEGMENT1_TQ15, ///< Time Segment 1 setting for 15 Time Quanta - CAN_TIME_SEGMENT1_TQ16, ///< Time Segment 1 setting for 16 Time Quanta -} can_time_segment1_t; - -/** CAN Time Segment 2 Time Quanta */ -typedef enum e_can_time_segment2 -{ - CAN_TIME_SEGMENT2_TQ2 = 1, ///< Time Segment 2 setting for 2 Time Quanta - CAN_TIME_SEGMENT2_TQ3, ///< Time Segment 2 setting for 3 Time Quanta - CAN_TIME_SEGMENT2_TQ4, ///< Time Segment 2 setting for 4 Time Quanta - CAN_TIME_SEGMENT2_TQ5, ///< Time Segment 2 setting for 5 Time Quanta - CAN_TIME_SEGMENT2_TQ6, ///< Time Segment 2 setting for 6 Time Quanta - CAN_TIME_SEGMENT2_TQ7, ///< Time Segment 2 setting for 7 Time Quanta - CAN_TIME_SEGMENT2_TQ8, ///< Time Segment 2 setting for 8 Time Quanta -} can_time_segment2_t; - -/** CAN Synchronization Jump Width Time Quanta */ -typedef enum e_can_sync_jump_width +/** CAN Mailbox type */ +typedef enum e_can_mailbox_send_receive { - CAN_SYNC_JUMP_WIDTH_TQ1 = 1, ///< Synchronization Jump Width setting for 1 Time Quanta - CAN_SYNC_JUMP_WIDTH_TQ2, ///< Synchronization Jump Width setting for 2 Time Quanta - CAN_SYNC_JUMP_WIDTH_TQ3, ///< Synchronization Jump Width setting for 3 Time Quanta - CAN_SYNC_JUMP_WIDTH_TQ4, ///< Synchronization Jump Width setting for 4 Time Quanta -} can_sync_jump_width_t; + CAN_MAILBOX_RECEIVE, ///< Mailbox is for receiving. + CAN_MAILBOX_TRANSMIT, ///< Mailbox is for sending. +} can_mailbox_send_receive_t; /** CAN bit rate configuration. */ typedef struct st_can_bit_timing_cfg { - uint32_t baud_rate_prescaler; ///< Baud rate prescaler. Valid values: 1 - 1024. - can_time_segment1_t time_segment_1; ///< Time segment 1 control. - can_time_segment2_t time_segment_2; ///< Time segment 2 control. - can_sync_jump_width_t synchronization_jump_width; ///< Synchronization jump width. + uint32_t baud_rate_prescaler; ///< Baud rate prescaler. Valid values: 1 - 1024. + uint32_t time_segment_1; ///< Time segment 1 control. + uint32_t time_segment_2; ///< Time segment 2 control. + uint32_t synchronization_jump_width; ///< Synchronization jump width. } can_bit_timing_cfg_t; -/** CAN Id */ +/* DEPRECATED CAN Id */ typedef uint32_t can_id_t; /** CAN data Frame */ typedef struct st_can_frame { - can_id_t id; ///< CAN id. - uint8_t data_length_code; ///< CAN Data Length code, number of bytes in the message. - uint8_t data[8]; ///< CAN data, up to 8 bytes. - can_frame_type_t type; ///< Frame type, data or remote frame. + uint32_t id; ///< CAN ID. + can_id_mode_t id_mode; ///< Standard or Extended ID (IDE). + uint8_t data_length_code; ///< CAN Data Length Code (DLC). + can_frame_type_t type; ///< Frame type (RTR). + uint32_t options; ///< Implementation-specific options. + uint8_t data[CAN_DATA_BUFFER_LENGTH]; ///< CAN data. } can_frame_t; -/** CAN Mailbox type */ -typedef enum e_can_mailbox_send_receive +/** CAN callback parameter definition */ +typedef struct st_can_callback_args { - CAN_MAILBOX_RECEIVE, ///< Mailbox is for receiving. - CAN_MAILBOX_TRANSMIT, ///< Mailbox is for sending. -} can_mailbox_send_receive_t; + uint32_t channel; ///< Device channel number. + can_event_t event; ///< Event code. + uint32_t error; ///< Error code. + union + { + uint32_t mailbox; ///< Mailbox number of interrupt source. + uint32_t buffer; ///< Buffer number of interrupt source. + }; + can_frame_t * p_frame; // DEPRECATED Pointer to the received frame. + void const * p_context; ///< Context provided to user during callback. + can_frame_t frame; ///< Received frame data. +} can_callback_args_t; /** CAN Mailbox */ typedef struct st_can_mailbox { - can_id_t mailbox_id; ///< Mailbox ID. + uint32_t mailbox_id; ///< Mailbox ID. + can_id_mode_t id_mode; ///< Standard or Extended ID. Only used in Mixed ID mode. can_mailbox_send_receive_t mailbox_type; ///< Receive or Transmit mailbox type. can_frame_type_t frame_type; ///< Frame type for receive mailbox. } can_mailbox_t; -/** CAN callback parameter definition */ -typedef struct st_can_callback_arg -{ - uint32_t channel; ///< Device channel number. - can_event_t event; ///< Event code. - uint32_t mailbox; ///< Mailbox number of interrupt source. - can_frame_t * p_frame; ///< Pointer to the received frame. - void const * p_context; ///< Context provided to user during callback. -} can_callback_args_t; - /** CAN Configuration */ typedef struct st_can_cfg { /* CAN generic configuration */ uint32_t channel; ///< CAN channel. can_bit_timing_cfg_t * p_bit_timing; ///< CAN bit timing. - can_id_mode_t id_mode; ///< Standard or Extended ID mode. - uint32_t mailbox_count; ///< Number of mailboxes. - can_mailbox_t * p_mailbox; ///< Pointer to mailboxes. - can_message_mode_t message_mode; ///< Overwrite message or overrun. - can_operation_mode_t operation_mode; ///< CAN operation mode. - can_test_mode_t test_mode; ///< CAN operation mode. /* Configuration for CAN Event processing */ void (* p_callback)(can_callback_args_t * p_args); ///< Pointer to callback function void const * p_context; ///< User defined callback context. /* Pointer to CAN peripheral specific configuration */ - void const * p_extend; ///< CAN hardware dependent configuration - uint8_t ipl; ///< Error/Transmit/Receive interrupt priority - IRQn_Type error_irq; ///< Error IRQ number - IRQn_Type mailbox_rx_irq; ///< Receive mailbox IRQ number - IRQn_Type mailbox_tx_irq; ///< Transmit mailbox IRQ number + void const * p_extend; ///< CAN hardware dependent configuration + uint8_t ipl; ///< Error/Transmit/Receive interrupt priority + IRQn_Type error_irq; ///< Error IRQ number + IRQn_Type mailbox_rx_irq; ///< Receive IRQ number + IRQn_Type mailbox_tx_irq; ///< Transmit IRQ number + can_mailbox_t * p_mailbox; ///< Pointer to mailboxes. + can_global_id_mode_t id_mode; ///< Standard or Extended ID mode. + uint32_t mailbox_count; ///< Number of mailboxes. + can_message_mode_t message_mode; ///< Overwrite message or overrun. } can_cfg_t; /** CAN control block. Allocate an instance specific control block to pass into the CAN API calls. * @par Implemented as * - can_instance_ctrl_t + * - canfd_instance_ctrl_t */ typedef void can_ctrl_t; @@ -277,6 +243,7 @@ typedef struct st_can_api /** Open function for CAN device * @par Implemented as * - R_CAN_Open() + * - R_CANFD_Open() * * @param[in,out] p_ctrl Pointer to the CAN control block. Must be declared by user. Value set here. * @param[in] can_cfg_t Pointer to CAN configuration structure. All elements of this structure must be set by @@ -287,11 +254,21 @@ typedef struct st_can_api /** Write function for CAN device * @par Implemented as * - R_CAN_Write() + * - R_CANFD_Write() * @param[in] p_ctrl Pointer to the CAN control block. - * @param[in] mailbox Mailbox (number) to write to. + * @param[in] buffer Buffer number (mailbox or message buffer) to write to. * @param[in] p_frame Pointer for frame of CAN ID, DLC, data and frame type to write. */ - fsp_err_t (* write)(can_ctrl_t * const p_ctrl, uint32_t mailbox, can_frame_t * const p_frame); + fsp_err_t (* write)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); + + /** Read function for CAN device + * @par Implemented as + * - R_CANFD_Read() + * @param[in] p_ctrl Pointer to the CAN control block. + * @param[in] buffer Message buffer (number) to read from. + * @param[in] p_frame Pointer to store the CAN ID, DLC, data and frame type. + */ + fsp_err_t (* read)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); /** Close function for CAN device * @par Implemented as @@ -303,6 +280,7 @@ typedef struct st_can_api /** Mode Transition function for CAN device * @par Implemented as * - R_CAN_ModeTransition() + * - R_CANFD_ModeTransition() * @param[in] p_ctrl Pointer to the CAN control block. * @param[in] operation_mode Destination CAN operation state. * @param[in] test_mode Destination CAN test state. @@ -313,6 +291,7 @@ typedef struct st_can_api /** Get CAN channel info. * @par Implemented as * - R_CAN_InfoGet() + * - R_CANFD_InfoGet() * * @param[in] p_ctrl Handle for channel (pointer to channel control block) * @param[out] p_info Memory address to return channel specific data to. @@ -321,7 +300,8 @@ typedef struct st_can_api /** Specify callback function and optional context pointer and working memory pointer. * @par Implemented as - * - @ref R_CAN_CallbackSet() + * - R_CAN_CallbackSet() + * - R_CANFD_CallbackSet() * * @param[in] p_ctrl Control block set in @ref can_api_t::open call. * @param[in] p_callback Callback function to register @@ -335,6 +315,7 @@ typedef struct st_can_api /* DEPRECATED Version get function for CAN device * @par Implemented as * - R_CAN_VersionGet() + * - R_CANFD_VersionGet() * @param[in] p_version Pointer to the memory to store the version information */ fsp_err_t (* versionGet)(fsp_version_t * const p_version); diff --git a/ra/fsp/inc/api/r_ctsu_api.h b/ra/fsp/inc/api/r_ctsu_api.h index edacb94c2..7e8b90685 100644 --- a/ra/fsp/inc/api/r_ctsu_api.h +++ b/ra/fsp/inc/api/r_ctsu_api.h @@ -50,8 +50,10 @@ FSP_HEADER /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define CTSU_API_VERSION_MAJOR (1U) // DEPRECATED -#define CTSU_API_VERSION_MINOR (2U) // DEPRECATED +#define CTSU_API_VERSION_MAJOR (1U) // DEPRECATED +#define CTSU_API_VERSION_MINOR (2U) // DEPRECATED + +#define CTSU_COUNT_MAX (0xFFFF) ///< Value of Maximum count /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/api/r_ether_api.h b/ra/fsp/inc/api/r_ether_api.h index 687568b89..87127baca 100644 --- a/ra/fsp/inc/api/r_ether_api.h +++ b/ra/fsp/inc/api/r_ether_api.h @@ -103,7 +103,7 @@ typedef enum e_ether_padding ETHER_PADDING_DISABLE = 0, ETHER_PADDING_1BYTE = 1, ETHER_PADDING_2BYTE = 2, - ETEHR_PADDING_3BYTE = 3, + ETHER_PADDING_3BYTE = 3, } ether_padding_t; /** EDMAC descriptor as defined in the hardware manual. diff --git a/ra/fsp/inc/api/r_spi_flash_api.h b/ra/fsp/inc/api/r_spi_flash_api.h index 7d4674103..f364409e2 100644 --- a/ra/fsp/inc/api/r_spi_flash_api.h +++ b/ra/fsp/inc/api/r_spi_flash_api.h @@ -180,6 +180,7 @@ typedef struct st_spi_flash_cfg /** SPI flash control block. Allocate an instance specific control block to pass into the SPI flash API calls. * @par Implemented as * - qspi_instance_ctrl_t + * - ospi_instance_ctrl_t */ typedef void spi_flash_ctrl_t; @@ -196,6 +197,7 @@ typedef struct st_spi_flash_api { /** Open the SPI flash driver module. * @par Implemented as + * - @ref R_OSPI_Open() * - @ref R_QSPI_Open() * * @param[in] p_ctrl Pointer to a driver handle @@ -205,6 +207,7 @@ typedef struct st_spi_flash_api /** Write raw data to the SPI flash. * @par Implemented as + * - @ref R_OSPI_DirectWrite() * - @ref R_QSPI_DirectWrite() * * @param[in] p_ctrl Pointer to a driver handle @@ -220,6 +223,7 @@ typedef struct st_spi_flash_api /** Read raw data from the SPI flash. Must follow a call to @ref spi_flash_api_t::directWrite. * @par Implemented as + * - @ref R_OSPI_DirectRead() * - @ref R_QSPI_DirectRead() * * @param[in] p_ctrl Pointer to a driver handle @@ -241,6 +245,7 @@ typedef struct st_spi_flash_api /** Change the SPI protocol in the driver. The application must change the SPI protocol on the device. * @par Implemented as + * - @ref R_OSPI_SpiProtocolSet() * - @ref R_QSPI_SpiProtocolSet() * * @param[in] p_ctrl Pointer to a driver handle @@ -250,6 +255,7 @@ typedef struct st_spi_flash_api /** Program a page of data to the flash. * @par Implemented as + * - @ref R_OSPI_Write() * - @ref R_QSPI_Write() * * @param[in] p_ctrl Pointer to a driver handle @@ -262,6 +268,7 @@ typedef struct st_spi_flash_api /** Erase a certain number of bytes of the flash. * @par Implemented as + * - @ref R_OSPI_Erase() * - @ref R_QSPI_Erase() * * @param[in] p_ctrl Pointer to a driver handle @@ -273,6 +280,7 @@ typedef struct st_spi_flash_api /** Get the write or erase status of the flash. * @par Implemented as + * - @ref R_OSPI_StatusGet() * - @ref R_QSPI_StatusGet() * * @param[in] p_ctrl Pointer to a driver handle @@ -282,6 +290,7 @@ typedef struct st_spi_flash_api /** Enter XIP mode. * @par Implemented as + * - @ref R_OSPI_XipEnter() * - @ref R_QSPI_XipEnter() * * @param[in] p_ctrl Pointer to a driver handle @@ -290,6 +299,7 @@ typedef struct st_spi_flash_api /** Exit XIP mode. * @par Implemented as + * - @ref R_OSPI_XipExit() * - @ref R_QSPI_XipExit() * * @param[in] p_ctrl Pointer to a driver handle @@ -298,6 +308,7 @@ typedef struct st_spi_flash_api /** Select the bank to access. See implementation for details. * @par Implemented as + * - @ref R_OSPI_BankSet() * - @ref R_QSPI_BankSet() * * @param[in] p_ctrl Pointer to a driver handle @@ -307,6 +318,7 @@ typedef struct st_spi_flash_api /** Close the SPI flash driver module. * @par Implemented as + * - @ref R_OSPI_Close() * - @ref R_QSPI_Close() * * @param[in] p_ctrl Pointer to a driver handle @@ -315,6 +327,7 @@ typedef struct st_spi_flash_api /* DEPRECATED Get the driver version based on compile time macros. * @par Implemented as + * - @ref R_OSPI_VersionGet() * - @ref R_QSPI_VersionGet() * * @param[out] p_version Code and API version stored here. diff --git a/ra/fsp/inc/api/r_transfer_api.h b/ra/fsp/inc/api/r_transfer_api.h index 608e63cf5..3fddac510 100644 --- a/ra/fsp/inc/api/r_transfer_api.h +++ b/ra/fsp/inc/api/r_transfer_api.h @@ -93,7 +93,11 @@ typedef enum e_transfer_mode * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any * further transfers. */ - TRANSFER_MODE_BLOCK = 2 + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 } transfer_mode_t; /** Transfer size specifies the size of each individual transfer. @@ -123,14 +127,14 @@ typedef enum e_transfer_addr_mode } transfer_addr_mode_t; /** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its - * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK, the selected pointer - * returns to its original value after each transfer. */ + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ typedef enum e_transfer_repeat_area { - /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ TRANSFER_REPEAT_AREA_DESTINATION = 0, - /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */ + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ TRANSFER_REPEAT_AREA_SOURCE = 1 } transfer_repeat_area_t; @@ -218,11 +222,13 @@ typedef struct st_transfer_info void const * volatile p_src; ///< Source pointer void * volatile p_dest; ///< Destination pointer - /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) and - * @ref TRANSFER_MODE_REPEAT (DMAC only), unused in other modes. */ + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ volatile uint16_t num_blocks; - /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT, + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK * see HAL driver for details. */ volatile uint16_t length; } transfer_info_t; diff --git a/ra/fsp/inc/api/rm_block_media_api.h b/ra/fsp/inc/api/rm_block_media_api.h index a2d7e1537..17c75da64 100644 --- a/ra/fsp/inc/api/rm_block_media_api.h +++ b/ra/fsp/inc/api/rm_block_media_api.h @@ -32,6 +32,7 @@ * * Implemented by: * - @ref RM_BLOCK_MEDIA_SDMMC + * - @ref RM_BLOCK_MEDIA_SPI * - @ref RM_BLOCK_MEDIA_USB * * @{ @@ -88,7 +89,7 @@ typedef struct st_rm_block_media_callback_args /** User configuration structure, used in open function */ typedef struct st_rm_block_media_cfg { - uint32_t block_size; ///< Block size, must be a power of 2 multiple of sector_size_bytes + uint32_t block_size; /// DEPRECATED - Block size, must be a power of 2 multiple of sector_size_bytes void (* p_callback)(rm_block_media_callback_args_t * p_args); ///< Pointer to callback function void const * p_context; ///< User defined context passed into callback function void const * p_extend; ///< Extension parameter for hardware specific settings @@ -106,6 +107,7 @@ typedef struct st_rm_block_media_status /** Block media API control block. Allocate an instance specific control block to pass into the block media API calls. * @par Implemented as * - @ref rm_block_media_sdmmc_instance_ctrl_t + * - @ref rm_block_media_spi_instance_ctrl_t * - @ref rm_block_media_usb_instance_ctrl_t */ typedef void rm_block_media_ctrl_t; @@ -117,6 +119,7 @@ typedef struct st_rm_block_media_api * intitialization procedure. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_Open + * - @ref RM_BLOCK_MEDIA_SPI_Open * - @ref RM_BLOCK_MEDIA_USB_Open * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. @@ -128,6 +131,7 @@ typedef struct st_rm_block_media_api * This function blocks until media initialization is complete. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_MediaInit + * - @ref RM_BLOCK_MEDIA_SPI_MediaInit * - @ref RM_BLOCK_MEDIA_USB_MediaInit * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -137,6 +141,7 @@ typedef struct st_rm_block_media_api /** Reads blocks of data from the specified memory device address to the location specified by the caller. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_Read + * - @ref RM_BLOCK_MEDIA_SPI_Read * - @ref RM_BLOCK_MEDIA_USB_Read * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -150,6 +155,7 @@ typedef struct st_rm_block_media_api /** Writes blocks of data to the specified device memory address. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_Write + * - @ref RM_BLOCK_MEDIA_SPI_Write * - @ref RM_BLOCK_MEDIA_USB_Write * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -163,6 +169,7 @@ typedef struct st_rm_block_media_api /** Erases blocks of data from the memory device. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_Erase + * - @ref RM_BLOCK_MEDIA_SPI_Erase * - @ref RM_BLOCK_MEDIA_USB_Erase * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -190,6 +197,7 @@ typedef struct st_rm_block_media_api * * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_StatusGet + * - @ref RM_BLOCK_MEDIA_SPI_StatusGet * - @ref RM_BLOCK_MEDIA_USB_StatusGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -200,6 +208,7 @@ typedef struct st_rm_block_media_api /** Returns information about the block media device. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_InfoGet + * - @ref RM_BLOCK_MEDIA_SPI_InfoGet * - @ref RM_BLOCK_MEDIA_USB_InfoGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -211,6 +220,7 @@ typedef struct st_rm_block_media_api /** Closes the module. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_Close + * - @ref RM_BLOCK_MEDIA_SPI_Close * - @ref RM_BLOCK_MEDIA_USB_Close * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. @@ -220,6 +230,7 @@ typedef struct st_rm_block_media_api /* DEPRECATED Gets version and stores it in provided pointer p_version. * @par Implemented as * - @ref RM_BLOCK_MEDIA_SDMMC_VersionGet + * - @ref RM_BLOCK_MEDIA_SPI_VersionGet * - @ref RM_BLOCK_MEDIA_USB_VersionGet * * @param[out] p_version Code and API version used. diff --git a/ra/fsp/inc/api/rm_touch_api.h b/ra/fsp/inc/api/rm_touch_api.h index bd26cdb68..bcdf3ab31 100644 --- a/ra/fsp/inc/api/rm_touch_api.h +++ b/ra/fsp/inc/api/rm_touch_api.h @@ -50,8 +50,11 @@ FSP_HEADER /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define TOUCH_API_VERSION_MAJOR (1U) // DEPRECATED -#define TOUCH_API_VERSION_MINOR (0U) // DEPRECATED +#define TOUCH_API_VERSION_MAJOR (1U) // DEPRECATED +#define TOUCH_API_VERSION_MINOR (0U) // DEPRECATED + +#define TOUCH_COUNT_MAX CTSU_COUNT_MAX ///< Value of Maximum count +#define TOUCH_OFF_VALUE (0xFFFF) ///< Value of Non-touch /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/fsp_common_api.h b/ra/fsp/inc/fsp_common_api.h index 18b2a9ba8..a83e39203 100644 --- a/ra/fsp/inc/fsp_common_api.h +++ b/ra/fsp/inc/fsp_common_api.h @@ -107,6 +107,7 @@ typedef enum e_fsp_err FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer /* Start of RTOS only error codes */ FSP_ERR_INTERNAL = 100, ///< Internal error diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 533a6a00a..a8a4753ac 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -41,7 +41,7 @@ #define FSP_VERSION_MAJOR (2U) /** FSP pack minor version. */ -#define FSP_VERSION_MINOR (3U) +#define FSP_VERSION_MINOR (4U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -50,10 +50,10 @@ #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ -#define FSP_VERSION_STRING ("2.3.0") +#define FSP_VERSION_STRING ("2.4.0") /** Unique FSP version ID. */ -#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.3.0") +#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.4.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc.h b/ra/fsp/inc/instances/r_adc.h index cb9d62f35..bf6d52e5b 100644 --- a/ra/fsp/inc/instances/r_adc.h +++ b/ra/fsp/inc/instances/r_adc.h @@ -192,6 +192,7 @@ typedef struct st_adc_extended_cfg adc_trigger_t trigger_group_b; ///< Group B trigger source; valid only for group mode adc_double_trigger_t double_trigger_mode; ///< Double-trigger mode setting adc_vref_control_t adc_vref_control; ///< VREFADC output voltage control + uint8_t enable_adbuf; ///< Enable ADC Ring Buffer, Valid only to use along with DMAC transfer } adc_extended_cfg_t; /** ADC channel(s) configuration */ diff --git a/ra/fsp/inc/instances/r_can.h b/ra/fsp/inc/instances/r_can.h index d05591cc7..147f510c1 100644 --- a/ra/fsp/inc/instances/r_can.h +++ b/ra/fsp/inc/instances/r_can.h @@ -46,6 +46,113 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ +/** CAN Status */ +typedef enum e_can_status +{ + CAN_STATUS_NEW_DATA = 1, ///< New Data status flag + CAN_STATUS_SENT_DATA = 2, ///< Sent Data status flag + CAN_STATUS_RECEIVE_FIFO = 4, ///< Receive FIFO status flag (Not supported) + CAN_STATUS_TRANSMIT_FIFO = 8, ///< Transmit FIFO status flag (Not supported) + CAN_STATUS_NORMAL_MBOX_MESSAGE_LOST = 16, ///< Normal mailbox message lost status flag + CAN_STATUS_FIFO_MBOX_MESSAGE_LOST = 32, ///< FIFO mailbox message lost status flag (Not Supported) + CAN_STATUS_TRANSMISSION_ABORT = 64, ///< Transmission abort status flag + CAN_STATUS_ERROR = 128, ///< Error status flag + CAN_STATUS_RESET_MODE = 256, ///< Reset mode status flag + CAN_STATUS_HALT_MODE = 512, ///< Halt mode status flag + CAN_STATUS_SLEEP_MODE = 1024, ///< Sleep mode status flag + CAN_STATUS_ERROR_PASSIVE = 2048, ///< Error-passive status flag + CAN_STATUS_BUS_OFF = 4096, ///< Bus-off status flag +} can_status_t; + +/** CAN Error Code */ +typedef enum e_can_error +{ + CAN_ERROR_STUFF = 1, ///< Stuff Error + CAN_ERROR_FORM = 2, ///< Form Error + CAN_ERROR_ACK = 4, ///< ACK Error + CAN_ERROR_CRC = 8, ///< CRC Error + CAN_ERROR_BIT_RECESSIVE = 16, ///< Bit Error (recessive) Error + CAN_ERROR_BIT_DOMINANT = 32, ///< Bit Error (dominant) Error + CAN_ERROR_ACK_DELIMITER = 64, ///< ACK Delimiter Error +} can_error_t; + +/* CAN Time Segment 1 Time Quanta (DEPRECATED) */ +typedef enum e_can_time_segment1 +{ + CAN_TIME_SEGMENT1_TQ2 = 2, + CAN_TIME_SEGMENT1_TQ3, + CAN_TIME_SEGMENT1_TQ4, + CAN_TIME_SEGMENT1_TQ5, + CAN_TIME_SEGMENT1_TQ6, + CAN_TIME_SEGMENT1_TQ7, + CAN_TIME_SEGMENT1_TQ8, + CAN_TIME_SEGMENT1_TQ9, + CAN_TIME_SEGMENT1_TQ10, + CAN_TIME_SEGMENT1_TQ11, + CAN_TIME_SEGMENT1_TQ12, + CAN_TIME_SEGMENT1_TQ13, + CAN_TIME_SEGMENT1_TQ14, + CAN_TIME_SEGMENT1_TQ15, + CAN_TIME_SEGMENT1_TQ16, + CAN_TIME_SEGMENT1_TQ17, + CAN_TIME_SEGMENT1_TQ18, + CAN_TIME_SEGMENT1_TQ19, + CAN_TIME_SEGMENT1_TQ20, + CAN_TIME_SEGMENT1_TQ21, + CAN_TIME_SEGMENT1_TQ22, + CAN_TIME_SEGMENT1_TQ23, + CAN_TIME_SEGMENT1_TQ24, + CAN_TIME_SEGMENT1_TQ25, + CAN_TIME_SEGMENT1_TQ26, + CAN_TIME_SEGMENT1_TQ27, + CAN_TIME_SEGMENT1_TQ28, + CAN_TIME_SEGMENT1_TQ29, + CAN_TIME_SEGMENT1_TQ30, + CAN_TIME_SEGMENT1_TQ31, + CAN_TIME_SEGMENT1_TQ32, +} can_time_segment1_t; + +/* CAN Time Segment 2 Time Quanta (DEPRECATED) */ +typedef enum e_can_time_segment2 +{ + CAN_TIME_SEGMENT2_TQ2 = 2, + CAN_TIME_SEGMENT2_TQ3, + CAN_TIME_SEGMENT2_TQ4, + CAN_TIME_SEGMENT2_TQ5, + CAN_TIME_SEGMENT2_TQ6, + CAN_TIME_SEGMENT2_TQ7, + CAN_TIME_SEGMENT2_TQ8, + CAN_TIME_SEGMENT2_TQ9, + CAN_TIME_SEGMENT2_TQ10, + CAN_TIME_SEGMENT2_TQ11, + CAN_TIME_SEGMENT2_TQ12, + CAN_TIME_SEGMENT2_TQ13, + CAN_TIME_SEGMENT2_TQ14, + CAN_TIME_SEGMENT2_TQ15, + CAN_TIME_SEGMENT2_TQ16, +} can_time_segment2_t; + +/* CAN Synchronization Jump Width Time Quanta (DEPRECATED) */ +typedef enum e_can_sync_jump_width +{ + CAN_SYNC_JUMP_WIDTH_TQ1 = 1, + CAN_SYNC_JUMP_WIDTH_TQ2, + CAN_SYNC_JUMP_WIDTH_TQ3, + CAN_SYNC_JUMP_WIDTH_TQ4, + CAN_SYNC_JUMP_WIDTH_TQ5, + CAN_SYNC_JUMP_WIDTH_TQ6, + CAN_SYNC_JUMP_WIDTH_TQ7, + CAN_SYNC_JUMP_WIDTH_TQ8, + CAN_SYNC_JUMP_WIDTH_TQ9, + CAN_SYNC_JUMP_WIDTH_TQ10, + CAN_SYNC_JUMP_WIDTH_TQ11, + CAN_SYNC_JUMP_WIDTH_TQ12, + CAN_SYNC_JUMP_WIDTH_TQ13, + CAN_SYNC_JUMP_WIDTH_TQ14, + CAN_SYNC_JUMP_WIDTH_TQ15, + CAN_SYNC_JUMP_WIDTH_TQ16, +} can_sync_jump_width_t; + /* CAN Instance Control Block */ typedef struct st_can_instance_ctrl { @@ -89,6 +196,7 @@ extern const can_api_t g_can_on_can; fsp_err_t R_CAN_Open(can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg); fsp_err_t R_CAN_Close(can_ctrl_t * const p_api_ctrl); fsp_err_t R_CAN_Write(can_ctrl_t * const p_api_ctrl, uint32_t const mailbox, can_frame_t * const p_frame); +fsp_err_t R_CAN_Read(can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_frame_t * const p_frame); fsp_err_t R_CAN_ModeTransition(can_ctrl_t * const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode); diff --git a/ra/fsp/inc/instances/r_canfd.h b/ra/fsp/inc/instances/r_canfd.h new file mode 100644 index 000000000..184c69f76 --- /dev/null +++ b/ra/fsp/inc/instances/r_canfd.h @@ -0,0 +1,355 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CANFD_H +#define R_CANFD_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_canfd_cfg.h" +#include "r_can_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup CANFD + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define CANFD_CODE_VERSION_MAJOR (1U) // DEPRECATED +#define CANFD_CODE_VERSION_MINOR (1U) // DEPRECATED + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CANFD Status */ +typedef enum e_canfd_status +{ + CANFD_STATUS_RESET_MODE = 0x001, ///< Channel in Reset mode + CANFD_STATUS_HALT_MODE = 0x002, ///< Channel in Halt mode + CANFD_STATUS_SLEEP_MODE = 0x004, ///< Channel in Sleep mode + CANFD_STATUS_ERROR_PASSIVE = 0x008, ///< Channel in error-passive state + CANFD_STATUS_BUS_OFF = 0x010, ///< Channel in bus-off state + CANFD_STATUS_TRANSMITTING = 0x020, ///< Channel is transmitting + CANFD_STATUS_RECEIVING = 0x040, ///< Channel is receiving + CANFD_STATUS_READY = 0x080, ///< Channel is ready for communication + CANFD_STATUS_ESI = 0x100, ///< At least one CAN-FD message was received with the ESI flag set +} canfd_status_t; + +/** CANFD Error Code */ +typedef enum e_canfd_error +{ + CANFD_ERROR_CHANNEL_BUS = 0x00000001, ///< Bus Error + CANFD_ERROR_CHANNEL_WARNING = 0x00000002, ///< Error Warning (TX/RX error count over 0x5F) + CANFD_ERROR_CHANNEL_PASSIVE = 0x00000004, ///< Error Passive (TX/RX error count over 0x7F) + CANFD_ERROR_CHANNEL_BUS_OFF_ENTRY = 0x00000008, ///< Bus-Off State Entry + CANFD_ERROR_CHANNEL_BUS_OFF_RECOVERY = 0x00000010, ///< Recovery from Bus-Off State + CANFD_ERROR_CHANNEL_OVERLOAD = 0x00000020, ///< Overload + CANFD_ERROR_CHANNEL_BUS_LOCK = 0x00000040, ///< Bus Locked + CANFD_ERROR_CHANNEL_ARBITRATION_LOSS = 0x00000080, ///< Arbitration Lost + CANFD_ERROR_CHANNEL_STUFF = 0x00000100, ///< Stuff Error + CANFD_ERROR_CHANNEL_FORM = 0x00000200, ///< Form Error + CANFD_ERROR_CHANNEL_ACK = 0x00000400, ///< ACK Error + CANFD_ERROR_CHANNEL_CRC = 0x00000800, ///< CRC Error + CANFD_ERROR_CHANNEL_BIT_RECESSIVE = 0x00001000, ///< Bit Error (recessive) Error + CANFD_ERROR_CHANNEL_BIT_DOMINANT = 0x00002000, ///< Bit Error (dominant) Error + CANFD_ERROR_CHANNEL_ACK_DELIMITER = 0x00004000, ///< ACK Delimiter Error + CANFD_ERROR_GLOBAL_DLC = 0x00010000, ///< DLC Error + CANFD_ERROR_GLOBAL_MESSAGE_LOST = 0x00020000, ///< Message Lost + CANFD_ERROR_GLOBAL_PAYLOAD_OVERFLOW = 0x00080000, ///< FD Payload Overflow + CANFD_ERROR_GLOBAL_TXQ_OVERWRITE = 0x00100000, ///< TX Queue Message Overwrite + CANFD_ERROR_GLOBAL_TXQ_MESSAGE_LOST = 0x00400000, ///< TX Queue Message Lost + CANFD_ERROR_GLOBAL_CH0_SCAN_FAIL = 0x01000000, ///< Channel 0 RX Scan Failure + CANFD_ERROR_GLOBAL_CH1_SCAN_FAIL = 0x02000000, ///< Channel 1 RX Scan Failure + CANFD_ERROR_GLOBAL_CH0_ECC = 0x10000000, ///< Channel 0 ECC Error + CANFD_ERROR_GLOBAL_CH1_ECC = 0x20000000, ///< Channel 1 ECC Error +} canfd_error_t; + +/** CANFD Transmit Message Buffer (TX MB) */ +typedef enum e_canfd_tx_mb +{ + CANFD_TX_MB_0 = 0, + CANFD_TX_MB_1 = 1, + CANFD_TX_MB_2 = 2, + CANFD_TX_MB_3 = 3, + CANFD_TX_MB_4 = 4, + CANFD_TX_MB_5 = 5, + CANFD_TX_MB_6 = 6, + CANFD_TX_MB_7 = 7, + CANFD_TX_MB_32 = 32, + CANFD_TX_MB_33 = 33, + CANFD_TX_MB_34 = 34, + CANFD_TX_MB_35 = 35, + CANFD_TX_MB_36 = 36, + CANFD_TX_MB_37 = 37, + CANFD_TX_MB_38 = 38, + CANFD_TX_MB_39 = 39, +} canfd_tx_mb_t; + +/** CANFD Receive Buffer (MB + FIFO) */ +typedef enum e_canfd_rx_buffer +{ + CANFD_RX_BUFFER_MB_0 = 0, + CANFD_RX_BUFFER_MB_1 = 1, + CANFD_RX_BUFFER_MB_2 = 2, + CANFD_RX_BUFFER_MB_3 = 3, + CANFD_RX_BUFFER_MB_4 = 4, + CANFD_RX_BUFFER_MB_5 = 5, + CANFD_RX_BUFFER_MB_6 = 6, + CANFD_RX_BUFFER_MB_7 = 7, + CANFD_RX_BUFFER_MB_8 = 8, + CANFD_RX_BUFFER_MB_9 = 9, + CANFD_RX_BUFFER_MB_10 = 10, + CANFD_RX_BUFFER_MB_11 = 11, + CANFD_RX_BUFFER_MB_12 = 12, + CANFD_RX_BUFFER_MB_13 = 13, + CANFD_RX_BUFFER_MB_14 = 14, + CANFD_RX_BUFFER_MB_15 = 15, + CANFD_RX_BUFFER_MB_16 = 16, + CANFD_RX_BUFFER_MB_17 = 17, + CANFD_RX_BUFFER_MB_18 = 18, + CANFD_RX_BUFFER_MB_19 = 19, + CANFD_RX_BUFFER_MB_20 = 20, + CANFD_RX_BUFFER_MB_21 = 21, + CANFD_RX_BUFFER_MB_22 = 22, + CANFD_RX_BUFFER_MB_23 = 23, + CANFD_RX_BUFFER_MB_24 = 24, + CANFD_RX_BUFFER_MB_25 = 25, + CANFD_RX_BUFFER_MB_26 = 26, + CANFD_RX_BUFFER_MB_27 = 27, + CANFD_RX_BUFFER_MB_28 = 28, + CANFD_RX_BUFFER_MB_29 = 29, + CANFD_RX_BUFFER_MB_30 = 30, + CANFD_RX_BUFFER_MB_31 = 31, + CANFD_RX_BUFFER_FIFO_0 = 32, + CANFD_RX_BUFFER_FIFO_1 = 33, + CANFD_RX_BUFFER_FIFO_2 = 34, + CANFD_RX_BUFFER_FIFO_3 = 35, + CANFD_RX_BUFFER_FIFO_4 = 36, + CANFD_RX_BUFFER_FIFO_5 = 37, + CANFD_RX_BUFFER_FIFO_6 = 38, + CANFD_RX_BUFFER_FIFO_7 = 39, +} canfd_rx_buffer_t; + +/** CANFD Receive Message Buffer (RX MB) */ +typedef enum e_canfd_rx_mb +{ + CANFD_RX_MB_NONE = 0, + CANFD_RX_MB_0 = 0x80, + CANFD_RX_MB_1 = 0x80 + 1, + CANFD_RX_MB_2 = 0x80 + 2, + CANFD_RX_MB_3 = 0x80 + 3, + CANFD_RX_MB_4 = 0x80 + 4, + CANFD_RX_MB_5 = 0x80 + 5, + CANFD_RX_MB_6 = 0x80 + 6, + CANFD_RX_MB_7 = 0x80 + 7, + CANFD_RX_MB_8 = 0x80 + 8, + CANFD_RX_MB_9 = 0x80 + 9, + CANFD_RX_MB_10 = 0x80 + 10, + CANFD_RX_MB_11 = 0x80 + 11, + CANFD_RX_MB_12 = 0x80 + 12, + CANFD_RX_MB_13 = 0x80 + 13, + CANFD_RX_MB_14 = 0x80 + 14, + CANFD_RX_MB_15 = 0x80 + 15, + CANFD_RX_MB_16 = 0x80 + 16, + CANFD_RX_MB_17 = 0x80 + 17, + CANFD_RX_MB_18 = 0x80 + 18, + CANFD_RX_MB_19 = 0x80 + 19, + CANFD_RX_MB_20 = 0x80 + 20, + CANFD_RX_MB_21 = 0x80 + 21, + CANFD_RX_MB_22 = 0x80 + 22, + CANFD_RX_MB_23 = 0x80 + 23, + CANFD_RX_MB_24 = 0x80 + 24, + CANFD_RX_MB_25 = 0x80 + 25, + CANFD_RX_MB_26 = 0x80 + 26, + CANFD_RX_MB_27 = 0x80 + 27, + CANFD_RX_MB_28 = 0x80 + 28, + CANFD_RX_MB_29 = 0x80 + 29, + CANFD_RX_MB_30 = 0x80 + 30, + CANFD_RX_MB_31 = 0x80 + 31, +} canfd_rx_mb_t; + +/** CANFD Receive FIFO (RX FIFO) */ +typedef enum e_canfd_rx_fifo +{ + CANFD_RX_FIFO_0 = (1U), + CANFD_RX_FIFO_1 = (1U << 1), + CANFD_RX_FIFO_2 = (1U << 2), + CANFD_RX_FIFO_3 = (1U << 3), + CANFD_RX_FIFO_4 = (1U << 4), + CANFD_RX_FIFO_5 = (1U << 5), + CANFD_RX_FIFO_6 = (1U << 6), + CANFD_RX_FIFO_7 = (1U << 7), +} canfd_rx_fifo_t; + +/** CANFD AFL Minimum DLC settings */ +typedef enum e_canfd_minimum_dlc +{ + CANFD_MINIMUM_DLC_0 = 0, + CANFD_MINIMUM_DLC_1, + CANFD_MINIMUM_DLC_2, + CANFD_MINIMUM_DLC_3, + CANFD_MINIMUM_DLC_4, + CANFD_MINIMUM_DLC_5, + CANFD_MINIMUM_DLC_6, + CANFD_MINIMUM_DLC_7, + CANFD_MINIMUM_DLC_8, + CANFD_MINIMUM_DLC_12, + CANFD_MINIMUM_DLC_16, + CANFD_MINIMUM_DLC_20, + CANFD_MINIMUM_DLC_24, + CANFD_MINIMUM_DLC_32, + CANFD_MINIMUM_DLC_48, + CANFD_MINIMUM_DLC_64, +} canfd_minimum_dlc_t; + +/** CANFD Frame Options */ +typedef enum e_canfd_frame_option +{ + CANFD_FRAME_OPTION_ERROR = 0x01, ///< Error state set (ESI). + CANFD_FRAME_OPTION_BRS = 0x02, ///< Bit Rate Switching (BRS) enabled. + CANFD_FRAME_OPTION_FD = 0x04, ///< Flexible Data frame (FDF). + // CANFD_FRAME_OPTION_ONESHOT = 0x80, ///< One-shot mode (no retries). +} canfd_frame_options_t; + +/* CAN Instance Control Block */ +typedef struct st_canfd_instance_ctrl +{ + /* Parameters to control CAN peripheral device */ + can_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Open status of channel. + can_operation_mode_t operation_mode; // Can operation mode. + can_test_mode_t test_mode; // Can operation mode. +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(can_callback_args_t *); // Pointer to callback + can_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function +} canfd_instance_ctrl_t; + +/** AFL Entry (based on R_CANFD_CFDGAFL_Type in renesas.h) */ +typedef struct st_canfd_afl_entry_t +{ + union + { + uint32_t id_u32; + + struct + { + uint32_t id : 29; ///< ID to match against + uint32_t : 1; + can_frame_type_t frame_type : 1; ///< Frame type (Data or Remote) + can_id_mode_t id_mode : 1; ///< ID mode (Standard or Extended) + } id; + }; + + union + { + uint32_t mask_u32; + + struct + { + uint32_t mask_id : 29; ///< ID Mask + uint32_t : 1; + uint32_t mask_frame_type : 1; ///< Only accept frames with the configured frame type + uint32_t mask_id_mode : 1; ///< Only accept frames with the configured ID mode + } mask; + }; + + union + { + uint32_t destination_u32[2]; + + struct + { + canfd_minimum_dlc_t minimum_dlc : 4; ///< Minimum DLC value to accept (valid when DLC Check is enabled) + uint32_t : 4; + canfd_rx_mb_t rx_buffer : 8; ///< RX Message Buffer to receive messages accepted by this rule + uint32_t : 16; + canfd_rx_fifo_t fifo_select_flags; ///< RX FIFO(s) to receive messages accepted by this rule + } destination; + }; +} canfd_afl_entry_t; + +/** CANFD Global Configuration */ +typedef struct st_canfd_global_cfg +{ + uint32_t global_interrupts; ///< Global control options (CFDGCTR register setting) + uint32_t global_config; ///< Global configuration options (CFDGCFG register setting) + uint32_t rx_fifo_config[8]; ///< RX FIFO configuration (CFDRFCCn register settings) + uint32_t rx_mb_config; ///< Number and size of RX Message Buffers (CFDRMNB register setting) + uint8_t global_err_ipl; ///< Global Error interrupt priority + uint8_t rx_fifo_ipl; ///< RX FIFO interrupt priority +} canfd_global_cfg_t; + +/** CANFD Extended Configuration */ +typedef struct st_canfd_extended_cfg +{ + canfd_afl_entry_t const * p_afl; ///< AFL rules list + uint64_t txmb_txi_enable; ///< Array of TX Message Buffer enable bits + uint32_t error_interrupts; ///< Error interrupt enable bits + can_bit_timing_cfg_t * p_data_timing; ///< FD Data Rate (when bitrate switching is used) + uint8_t delay_compensation; ///< FD Transceiver Delay Compensation (enable or disable) + canfd_global_cfg_t * p_global_cfg; ///< Global configuration (global error callback channel only) +} canfd_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const can_api_t g_canfd_on_canfd; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CANFD_Open(can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg); +fsp_err_t R_CANFD_Close(can_ctrl_t * const p_api_ctrl); +fsp_err_t R_CANFD_Write(can_ctrl_t * const p_api_ctrl, uint32_t const buffer, can_frame_t * const p_frame); +fsp_err_t R_CANFD_Read(can_ctrl_t * const p_api_ctrl, uint32_t const buffer, can_frame_t * const p_frame); +fsp_err_t R_CANFD_ModeTransition(can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode); +fsp_err_t R_CANFD_InfoGet(can_ctrl_t * const p_api_ctrl, can_info_t * const p_info); +fsp_err_t R_CANFD_CallbackSet(can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void const * const p_context, + can_callback_args_t * const p_callback_memory); +fsp_err_t R_CANFD_VersionGet(fsp_version_t * const version); + +/*******************************************************************************************************************//** + * @} (end defgroup CAN) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h index e389f9d21..7d90f426a 100644 --- a/ra/fsp/inc/instances/r_ctsu.h +++ b/ra/fsp/inc/instances/r_ctsu.h @@ -125,31 +125,27 @@ typedef struct st_ctsu_mutual_buf /** Correction information */ typedef struct st_ctsu_correction_info { - ctsu_correction_status_t status; ///< Correction status - ctsu_ctsuwr_t ctsuwr; ///< Correction scan parameter - volatile ctsu_self_buf_t scanbuf; ///< Correction scan buffer + ctsu_correction_status_t status; ///< Correction status + ctsu_ctsuwr_t ctsuwr; ///< Correction scan parameter + volatile ctsu_self_buf_t scanbuf; ///< Correction scan buffer #if (BSP_FEATURE_CTSU_VERSION == 2) #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - uint16_t tscap_voltage; ///< TSCAP Voltage by ADC - #endif - uint16_t scan_index; ///< Scan point index - uint16_t update_counter; ///< Coefficient update counter - uint16_t ex_base_value; ///< Value of external registance measurement - uint8_t suadj0; ///< Stored SUADJ0 value + uint16_t scan_index; ///< Scan point index + uint16_t update_counter; ///< Coefficient update counter + uint16_t ex_base_value; ///< Value of external registance measurement + uint8_t suadj0; ///< Stored SUADJ0 value #endif - uint16_t base_value[CTSU_RANGE_NUM]; ///< Value of internal registance measurement - uint16_t error_rate[CTSU_RANGE_NUM]; ///< Error rate of base vs DAC - uint16_t range_ratio[CTSU_RANGE_NUM - 1]; ///< Ratio between 160uA range and other ranges - uint16_t real_value[CTSU_CORRECTION_POINT_NUM]; ///< Value calculated by error rate for dac value - uint16_t dac_value[CTSU_CORRECTION_POINT_NUM]; ///< Value of internal DAC measurement - uint16_t coefficient[CTSU_RANGE_NUM][CTSU_CORRECTION_POINT_NUM]; ///< Coefficient table + uint16_t base_value[CTSU_RANGE_NUM]; ///< Value of internal registance measurement + uint16_t error_rate[CTSU_RANGE_NUM]; ///< Error rate of base vs DAC + uint16_t range_ratio[CTSU_RANGE_NUM - 1]; ///< Ratio between 160uA range and other ranges + uint16_t dac_value[CTSU_CORRECTION_POINT_NUM]; ///< Value of internal DAC measurement + uint16_t ref_value[CTSU_RANGE_NUM][CTSU_CORRECTION_POINT_NUM]; ///< Value of reference #else - uint16_t first_val; ///< 1st correction value - uint16_t second_val; ///< 2nd correction value - uint32_t first_coefficient; ///< 1st correction coefficient - uint32_t second_coefficient; ///< 2nd correction coefficient - uint32_t ctsu_clock; ///< CTSU clock [MHz] + uint16_t first_val; ///< 1st correction value + uint16_t second_val; ///< 2nd correction value + uint32_t first_coefficient; ///< 1st correction coefficient + uint32_t second_coefficient; ///< 2nd correction coefficient + uint32_t ctsu_clock; ///< CTSU clock [MHz] #endif } ctsu_correction_info_t; @@ -159,17 +155,17 @@ typedef struct st_ctsu_correction_info /** CFC correction information */ typedef struct st_ctsu_corrcfc_info { - ctsu_correction_status_t status; ///< Correction status - ctsu_ctsuwr_t ctsuwr; ///< Correction scan parameter - volatile ctsu_self_buf_t scanbuf[CTSU_CFG_NUM_CFC]; ///< Correction scan buffer - uint16_t base_value[CTSU_CFG_NUM_CFC]; ///< Value of CFC circuit measurement - uint16_t error_rate[CTSU_CFG_NUM_CFC]; ///< Error rate of base vs DAC - uint16_t value[CTSU_CFG_NUM_CFC][CTSU_CORRCFC_POINT_NUM]; ///< Value of internal DAC measurement - uint16_t coefficient[CTSU_CFG_NUM_CFC][CTSU_CORRCFC_POINT_NUM]; ///< Coefficient table - uint8_t ts_table[CTSU_CFG_NUM_CFC]; ///< Number of TS terminal - uint8_t index; ///< Index of ts_table - uint8_t num_ts; ///< Number of CFC-TS for instance - uint64_t stored_rx_bitmap; ///< Bitmap of registered CFC terminal + ctsu_correction_status_t status; ///< Correction status + ctsu_ctsuwr_t ctsuwr; ///< Correction scan parameter + volatile ctsu_self_buf_t scanbuf[CTSU_CFG_NUM_CFC]; ///< Correction scan buffer + uint16_t base_value[CTSU_CFG_NUM_CFC]; ///< Value of CFC circuit measurement + uint16_t error_rate[CTSU_CFG_NUM_CFC]; ///< Error rate of base vs DAC + uint16_t dac_value[CTSU_CFG_NUM_CFC][CTSU_CORRCFC_POINT_NUM]; ///< Value of internal DAC measurement + uint16_t ref_value[CTSU_CFG_NUM_CFC][CTSU_CORRCFC_POINT_NUM]; ///< Value of reference + uint8_t ts_table[CTSU_CFG_NUM_CFC]; ///< Number of TS terminal + uint8_t index; ///< Index of ts_table + uint8_t num_ts; ///< Number of CFC-TS for instance + uint64_t stored_rx_bitmap; ///< Bitmap of registered CFC terminal } ctsu_corrcfc_info_t; #endif #endif diff --git a/ra/fsp/inc/instances/r_dmac.h b/ra/fsp/inc/instances/r_dmac.h index cd44b1c8f..a8373034b 100644 --- a/ra/fsp/inc/instances/r_dmac.h +++ b/ra/fsp/inc/instances/r_dmac.h @@ -85,6 +85,9 @@ typedef struct st_dmac_extended_cfg uint8_t ipl; ///< DMAC interrupt priority int32_t offset; ///< Offset value used with transfer_addr_mode_t::TRANSFER_ADDR_MODE_OFFSET. + /** Source ring buffer size for @ref TRANSFER_MODE_REPEAT_BLOCK. */ + uint16_t src_buffer_size; + /** Select which event will trigger the transfer. * @note Select ELC_EVENT_NONE for software activation in order to use softwareStart and softwareStart to trigger * transfers. */ diff --git a/ra/fsp/inc/instances/rm_block_media_spi.h b/ra/fsp/inc/instances/rm_block_media_spi.h new file mode 100644 index 000000000..7c2ec5600 --- /dev/null +++ b/ra/fsp/inc/instances/rm_block_media_spi.h @@ -0,0 +1,114 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RM_BLOCK_MEDIA_SPI_H +#define RM_BLOCK_MEDIA_SPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_spi_flash_api.h" +#include "rm_block_media_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup RM_BLOCK_MEDIA_SPI + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define RM_BLOCK_MEDIA_SPI_CODE_VERSION_MAJOR (1U) +#define RM_BLOCK_MEDIA_SPI_CODE_VERSION_MINOR (6U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Extended configuration structure. */ +typedef struct st_rm_block_media_spi_extended_cfg +{ + spi_flash_instance_t const * p_spi; + + uint32_t block_size_bytes; ///< Block size, must be a power of 2 multiple of sector_size_bytes + uint32_t block_count_total; ///< Total number of blocks registered for use + uint32_t base_address; ///< Base address of memory mapped region. Can be offset to use subset of available flash size if desired. +} rm_block_media_spi_extended_cfg_t; + +/** SPI block media instance control block. */ +typedef struct st_rm_block_media_spi_instance_ctrl +{ + spi_flash_instance_t * p_spi_flash; ///< Pointer to SPI Flash instance structure + rm_block_media_cfg_t const * p_cfg; ///< Low level SPI configuration structure + uint32_t open; ///< Used to determine if framework is initialized. + bool initialized; ///< Initialized flag + + /* Busy flags */ + bool erase_in_progress; ///< Block Media SPI erase in progress + bool read_in_progress; ///< Block Media SPI read in progress + bool write_in_progress; ///< Block Media SPI write in progress +} rm_block_media_spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const rm_block_media_api_t g_rm_block_media_on_spi; + +/** @endcond */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Open(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_cfg_t const * const p_cfg); +fsp_err_t RM_BLOCK_MEDIA_SPI_MediaInit(rm_block_media_ctrl_t * const p_ctrl); +fsp_err_t RM_BLOCK_MEDIA_SPI_Read(rm_block_media_ctrl_t * const p_ctrl, + uint8_t * const p_dest, + uint32_t const start_block, + uint32_t const num_blocks); +fsp_err_t RM_BLOCK_MEDIA_SPI_Write(rm_block_media_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const start_block, + uint32_t const num_blocks); +fsp_err_t RM_BLOCK_MEDIA_SPI_Erase(rm_block_media_ctrl_t * const p_ctrl, + uint32_t const start_block, + uint32_t const num_blocks); +fsp_err_t RM_BLOCK_MEDIA_SPI_CallbackSet(rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory); +fsp_err_t RM_BLOCK_MEDIA_SPI_StatusGet(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_status_t * const p_status); +fsp_err_t RM_BLOCK_MEDIA_SPI_InfoGet(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info); +fsp_err_t RM_BLOCK_MEDIA_SPI_Close(rm_block_media_ctrl_t * const p_ctrl); +fsp_err_t RM_BLOCK_MEDIA_SPI_VersionGet(fsp_version_t * const p_version); + +#endif /* FSP_INC_FRAMEWORK_INSTANCES_RM_BLOCK_MEDIA_SPI_H_ */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_BLOCK_MEDIA_SPI) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h index 0f4d9656e..3373248b6 100644 --- a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h +++ b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h @@ -32,25 +32,22 @@ /* Register definitions, common services and error codes. */ #include "bsp_api.h" +#include "time.h" -#include "iot_wifi.h" - +#include "r_ioport_api.h" #include "r_uart_api.h" #include "r_sci_uart.h" -#include "rm_wifi_onchip_silex_cfg.h" - #include "FreeRTOS.h" #include "semphr.h" #include "stream_buffer.h" +#include "iot_wifi.h" + +#include "rm_wifi_onchip_silex_cfg.h" #include "aws_secure_sockets_config.h" #include "aws_wifi_config.h" -#include "r_ioport_api.h" - -extern const ioport_instance_t g_ioport; - /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ FSP_HEADER @@ -66,7 +63,7 @@ FSP_HEADER **********************************************************************************************************************/ /** Silex ULPGN Wifi security types */ -typedef enum +typedef enum e_sx_ulpgn_security { WIFI_ONCHIP_SILEX_SECURITY_OPEN = 0, WIFI_ONCHIP_SILEX_SECURITY_WPA, @@ -76,7 +73,7 @@ typedef enum } sx_ulpgn_security_t; /** Silex ULPGN Wifi socket status types */ -typedef enum +typedef enum e_sx_ulpgn_socket_status { WIFI_ONCHIP_SILEX_SOCKET_STATUS_CLOSED = 0, WIFI_ONCHIP_SILEX_SOCKET_STATUS_SOCKET, @@ -86,21 +83,40 @@ typedef enum } sx_ulpgn_socket_status_t; /** Silex socket shutdown channels */ -typedef enum +typedef enum e_sx_ulpgn_socket_rw { WIFI_ONCHIP_SILEX_SOCKET_READ = 1, WIFI_ONCHIP_SILEX_SOCKET_WRITE = 2, } sx_ulpgn_socket_rw; +/** Silex WiFi module enable/disable for SNTP */ +typedef enum e_wifi_onchip_silex_sntp_enable +{ + WIFI_ONCHIP_SILEX_SNTP_DISABLE = 0, + WIFI_ONCHIP_SILEX_SNTP_ENABLE = 1, +} wifi_onchip_silex_sntp_enable_t; + +/** Silex WiFi module enable/disable for SNTP */ +typedef enum e_wifi_onchip_silex_sntp_daylight_savings_enable +{ + WIFI_ONCHIP_SILEX_SNTP_DAYLIGHT_SAVINGS_DISABLE = 0, + WIFI_ONCHIP_SILEX_SNTP_DAYLIGHT_SAVINGS_ENABLE = 1, +} wifi_onchip_silex_sntp_daylight_savings_enable_t; + /** User configuration structure, used in open function */ typedef struct st_wifi_onchip_cfg { - const uint32_t num_uarts; ///< Number of UART interfaces to use - const uint32_t num_sockets; ///< Number of sockets to initialize - const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module - const uart_instance_t * uart_instances[WIFI_ONCHIP_SILEX_CFG_MAX_NUMBER_UART_PORTS]; ///< SCI UART instances - void const * p_context; ///< User defined context passed into callback function. - void const * p_extend; ///< Pointer to extended configuration by instance of interface. + const uint32_t num_uarts; ///< Number of UART interfaces to use + const uint32_t num_sockets; ///< Number of sockets to initialize + const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module + const uart_instance_t * uart_instances[WIFI_ONCHIP_SILEX_CFG_MAX_NUMBER_UART_PORTS]; ///< SCI UART instances + const wifi_onchip_silex_sntp_enable_t sntp_enabled; ///< Enable/Disable the SNTP Client + const uint8_t * sntp_server_ip; ///< The SNTP server IP address string + const int32_t sntp_timezone_offset_from_utc_hours; ///< Timezone offset from UTC in (+/-) hours + const uint32_t sntp_timezone_offset_from_utc_minutes; ///< Timezone offset from UTC in minutes + const wifi_onchip_silex_sntp_daylight_savings_enable_t sntp_timezone_use_daylight_savings; ///< Enable/Disable use of daylight saving time. + void const * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< Pointer to extended configuration by instance of interface. } wifi_onchip_silex_cfg_t; /** Silex ULPGN Wifi internal socket instance structure */ @@ -115,12 +131,6 @@ typedef struct uint32_t socket_read_write_flag; ///< flag to determine if read and/or write channels are active. } ulpgn_socket_t; -/** Silex ULPGN Wifi SCI UART state information */ -typedef struct -{ - SemaphoreHandle_t uart_tei_sem; ///< UART transmission end binary semaphore -} uart_state_t; - /** WIFI_ONCHIP_SILEX private control block. DO NOT MODIFY. */ typedef struct { @@ -146,10 +156,14 @@ typedef struct SemaphoreHandle_t rx_sem; ///< Receive binary semaphore handle uint8_t last_data[WIFI_ONCHIP_SILEX_RETURN_TEXT_LENGTH]; ///< Tailing buffer used for command parser uart_instance_t * uart_instance_objects[WIFI_ONCHIP_SILEX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART instance objects - uart_state_t uart_state_info[WIFI_ONCHIP_SILEX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART instance state information + SemaphoreHandle_t uart_tei_sem[WIFI_ONCHIP_SILEX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART transmission end binary semaphore ulpgn_socket_t sockets[WIFI_ONCHIP_SILEX_CFG_NUM_CREATEABLE_SOCKETS]; ///< Internal socket instances } wifi_onchip_silex_instance_ctrl_t; +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_ONCHIP_SILEX) + **********************************************************************************************************************/ + /********************************************************************************************************************** * Public Function Prototypes **********************************************************************************************************************/ @@ -173,14 +187,44 @@ fsp_err_t rm_wifi_onchip_silex_socket_disconnect(uint32_t socket_no); fsp_err_t rm_wifi_onchip_silex_disconnect(); fsp_err_t rm_wifi_onchip_silex_dns_query(const char * p_textstring, uint8_t * p_ip_addr); fsp_err_t rm_wifi_onchip_silex_socket_connected(fsp_err_t * p_status); +void rm_wifi_onchip_silex_uart_callback(uart_callback_args_t * p_args); + +/*******************************************************************************************************************//** + * @addtogroup WIFI_ONCHIP_SILEX WIFI_ONCHIP_SILEX + * @{ + **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Callback function for first UART port in command mode. Used specifically for the SCI UART driver. + * Get the current system time as the number of seconds since epoch 1970-01-01 00:00:00 UTC * - * @param[in] p_args Pointer to callback arguments structure. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_EpochTimeGet(time_t * p_utc_time); + +/*******************************************************************************************************************//** + * Get the current local time based on current timezone in a string format + * + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_LocalTimeGet(uint8_t * p_local_time, uint32_t size_string); + +/*******************************************************************************************************************//** + * Enable or Disable the SNTP Client Service + * + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpEnableSet(wifi_onchip_silex_sntp_enable_t enable); + +/*******************************************************************************************************************//** + * Update the SNTP Server IP Address + * + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpServerIpAddressSet(uint8_t * p_ip_address); + +/*******************************************************************************************************************//** + * Update the SNTP Timezone * **********************************************************************************************************************/ -void rm_wifi_onchip_silex_uart_callback(uart_callback_args_t * p_args); +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpTimeZoneSet(int32_t hours, + uint32_t minutes, + wifi_onchip_silex_sntp_daylight_savings_enable_t daylightSavingsEnable); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h index cefbf4687..30f845a90 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h @@ -53,6 +53,7 @@ #define R_OSPI_BASE 0x400A6000 #define R_CAN0_BASE 0x400A8000 #define R_CAN1_BASE 0x400A9000 + #define R_CANFD_BASE 0x400B0000 #define R_CTSU_BASE 0x400D0000 #define R_PSCU_BASE 0x400E0000 #define R_AGT0_BASE 0x400E8000 @@ -170,6 +171,7 @@ #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) @@ -317,6 +319,7 @@ #define R_GPT_POEG1_BASE 0x40042100 #define R_GPT_POEG2_BASE 0x40042200 #define R_GPT_POEG3_BASE 0x40042300 + #define R_I3C_BASE 0x40083000 #define R_ICU_BASE 0x40006000 #define R_IIC0_BASE 0x40053000 #define R_IIC1_BASE 0x40053100 @@ -457,6 +460,7 @@ #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_I3C ((R_I3C_Type *) R_I3C_BASE) #define R_ICU ((R_ICU_Type *) R_ICU_BASE) #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h index 259fee3e2..072198376 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -555,12102 +555,14816 @@ typedef struct } R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ typedef struct { union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ + __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ + __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers) - */ -typedef struct -{ union { - __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */ + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ struct { - __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the start time of the pulse output timer in nanoseconds. */ - } STTRU_b; + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; }; union { - __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */ + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ struct { - __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the start time of the pulse output timer in nanoseconds. */ - } STTRL_b; + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ union { - __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */ + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ struct { - __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in - * nanoseconds. Set a value that is equivalent to at least - * four cycles of the STCA clock. */ - uint32_t : 2; - } CYCR_b; + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; }; union { - __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */ + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ struct { - __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse - * signal from the timer in nanoseconds. Set a value that - * is equivalent to at least two cycles of the STCA clock. */ - uint32_t : 3; - } PLSR_b; + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ + } FDCFG_b; }; -} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers) - */ -typedef struct -{ union { - __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ struct { - __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the local MAC address for Ethernet port 0. */ - uint32_t : 8; - } MACRU_b; + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; }; union { - __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */ + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ struct { - __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the local MAC address for Ethernet port 0. */ - uint32_t : 8; - } MACRL_b; + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; }; -} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */ -/** - * @brief R_GLCDC_BG [BG] (Background Registers) - */ -typedef struct -{ union { - __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ struct { - __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ - uint32_t : 7; - __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to - * internal operations */ - uint32_t : 7; - __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ - uint32_t : 15; - } EN_b; + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period - * Register */ + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ struct { - __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period - * on the basis of pixel clock (PXCLK). */ - uint32_t : 5; - __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period - * on the basis of line. */ - uint32_t : 5; - } PERI_b; + __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ + uint32_t : 23; + } BLCT_b; }; union { - __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position - * Register */ + __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ struct { - __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion - * position on the basis of pixel clock (PXCLK). */ - uint32_t : 12; - __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion - * position on the basis of line. */ - uint32_t : 12; - } SYNC_b; + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ + } BLSTS_b; }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ union { - __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical - * Size Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ struct { - __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis - * of line */ - uint32_t : 5; - __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position - * on the basis of line */ - uint32_t : 5; - } VSIZE_b; + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; }; union { - __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal - * Size Register */ + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ struct { - __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the - * basis of pixel clock (PXCLK) Note: When serial RGB is selected - * as the output format for the output control block, add - * two to the horizontal enable signal width and set the resulting - * value to this field. */ - uint32_t : 5; - __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position - * on the basis of pixel clock (PXCLK). */ - uint32_t : 5; - } HSIZE_b; + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; }; union { - __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; - * 8-bit integer */ - __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; - * 8-bit integer */ - __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; - * 8-bit integer. */ - uint32_t : 8; - } BGC_b; + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; }; union { - __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ - uint32_t : 7; - __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal - * monitor. The signal state for controlling reflection of - * the register values to the internal operations upon assertion - * of the vertical synchronization signal. */ - uint32_t : 7; - __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ - uint32_t : 15; - } MON_b; + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; }; -} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_GLCDC_GR [GR] (Layer Registers) + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) */ typedef struct { union { - __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ struct { - __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection - * to internal operations. Reflection of the register values - * to the internal operation at the assertion of the vertical - * synchronization signal (VS). */ - uint32_t : 31; - } VEN_b; + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; }; union { - __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ struct { - __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ - uint32_t : 31; - } FLMRD_b; + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ union { - __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ struct { - __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer - * data) access */ - uint32_t : 30; - } FLM1_b; + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer - * data) Set the head address in the frame buffer where graphics - * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed - * to 0 during 64-byte burst transfer. */ - } FLM2_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ struct { - uint32_t : 16; - __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data - * (frame buffer data) Signed; 16-bit integer */ - } FLM3_b; + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing - * graphics data (frame buffer data), where one transfer is - * defined as 16-beat burst access (64-byte boundary) */ - __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data - * (frame buffer data). */ - uint32_t : 5; - } FLM5_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ union { - __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ struct { - uint32_t : 28; - __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer - * data). */ - uint32_t : 1; - } FLM6_b; + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ struct { - __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ - uint32_t : 2; - __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ - uint32_t : 3; - __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area - * alpha blending. */ - uint32_t : 3; - __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ - uint32_t : 19; - } AB1_b; + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ struct { - __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ - uint32_t : 5; - __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ - uint32_t : 5; - } AB2_b; + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ struct { - __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ - uint32_t : 5; - __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ - uint32_t : 5; - } AB3_b; + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ union { - __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + __IM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ struct { - __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image - * area. */ - uint32_t : 5; - __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending - * image area */ - uint32_t : 5; - } AB4_b; + __IM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + __IM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ struct { - __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending - * image area. */ - uint32_t : 5; - __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha - * blending image area. */ - uint32_t : 5; - } AB5_b; + __IM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ struct { - __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ - uint32_t : 8; - __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular - * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) - * [7:0]: Variation (absolute value) */ - uint32_t : 7; - } AB6_b; + __IM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ struct { - __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ - uint32_t : 15; - __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular - * area. */ - uint32_t : 8; - } AB7_b; + __IM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ union { - __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ struct { - __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; - * 8 bits. */ - __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; - * 8 bits. */ - __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; - * 8 bits. */ - uint32_t : 8; - } AB8_b; + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ struct { - __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement - * Unsigned; 8 bits. */ - __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement - * Unsigned; 8 bits. */ - __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement - * Unsigned; 8 bits. */ - __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ - } AB9_b; + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ struct { - __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ - __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ - __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ - uint32_t : 8; - } BASE_b; + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; }; union { - __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ struct { - __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ - uint32_t : 5; - __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ - uint32_t : 15; - } CLUTINT_b; + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ - uint32_t : 15; - __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ - uint32_t : 15; - } MON_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; - __IM uint32_t RESERVED2[42]; -} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) */ typedef struct { union { - __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection - * to internal operations. The register values to be reflected - * to the internal operations at the assertion of the vertical - * synchronization signal (VS). */ - uint32_t : 31; - } LATCH_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers) + */ +typedef struct +{ union { - __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */ struct { - __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ - uint32_t : 31; - } GAM_SW_b; + __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the start time of the pulse output timer in nanoseconds. */ + } STTRU_b; }; union { - __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */ struct { - __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ - uint32_t : 5; - __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ - uint32_t : 5; - } LUT_b[8]; + __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the start time of the pulse output timer in nanoseconds. */ + } STTRL_b; }; union { - __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */ struct { - __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ - __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ - __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ - uint32_t : 2; - } AREA_b[5]; + __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in + * nanoseconds. Set a value that is equivalent to at least + * four cycles of the STCA clock. */ + uint32_t : 2; + } CYCR_b; }; - __IM uint32_t RESERVED; -} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_GLCDC_OUT [OUT] (Output Control Registers) - */ -typedef struct -{ union { - __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control - * Register */ + __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */ struct { - __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection - * to internal operations. The register values to be reflected - * to the internal operations at the assertion of the vertical - * synchronization signal (VS). */ - uint32_t : 31; - } VLATCH_b; + __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse + * signal from the timer in nanoseconds. Set a value that + * is equivalent to at least two cycles of the STCA clock. */ + uint32_t : 3; + } PLSR_b; }; +} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers) + */ +typedef struct +{ union { - __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */ struct { - __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ - uint32_t : 2; - __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ - uint32_t : 3; - __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ - uint32_t : 2; - __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ - uint32_t : 10; - __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ - uint32_t : 3; - __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ - uint32_t : 3; - } SET_b; + __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRU_b; }; union { - __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register - * 1 */ + __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */ struct { - __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; - +512 with offset; integer */ - uint32_t : 22; - } BRIGHT1_b; + __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRL_b; }; +} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ union { - __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register - * 2 */ + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ struct { - __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; - +512 with offset; integer */ - uint32_t : 6; - __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 - * bits; +512 with offset; integer */ - uint32_t : 6; - } BRIGHT2_b; + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; }; union { - __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ struct { - __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits - * fixed point */ - __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits - * fixed point */ - __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 - * bits fixed point. */ - uint32_t : 8; - } CONTRAST_b; + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; }; union { - __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position * Register */ struct { - __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit - * integer */ - uint32_t : 2; - __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit - * integer */ - uint32_t : 2; - __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit - * integer */ - uint32_t : 2; - __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned - * 2-bit integer */ - uint32_t : 2; - __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ - uint32_t : 2; - __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ - uint32_t : 10; - } PDTHA_b; + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ struct { - uint32_t : 3; - __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ - __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ - __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ - __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ - uint32_t : 1; - __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ - uint32_t : 3; - __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ - uint32_t : 19; - } CLKPHASE_b; + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; }; -} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ - -/** - * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED; union { - __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ struct { - __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference - * timing Sets the offset from the assertion of the internal - * horizontal synchronization signal in terms of pixels. */ - uint32_t : 5; - __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing - * Sets the delay from the assertion of the internal horizontal - * synchronization signal in terms of pixels. */ + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ uint32_t : 5; - } TIM_b; + } HSIZE_b; }; union { - __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ struct { - __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion - * width. */ - uint32_t : 5; - __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ - uint32_t : 5; - } STVA1_b; + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; }; union { - __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ struct { - __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by - * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 - * register) pin */ - uint32_t : 1; - __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ - uint32_t : 27; - } STVA2_b; + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ union { - __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ struct { - __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion - * width. */ - uint32_t : 5; - __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ - uint32_t : 5; - } STVB1_b; + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; }; union { - __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ struct { - __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by - * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 - * register) pin */ - uint32_t : 1; - __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ - uint32_t : 27; - } STVB2_b; + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; }; union { - __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ struct { - __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion - * width. */ - uint32_t : 5; - __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ - uint32_t : 5; - } STHA1_b; + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; }; union { - __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ struct { - __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled - * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 - * register) pin. */ - uint32_t : 1; - __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ - uint32_t : 3; - __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ - uint32_t : 23; - } STHA2_b; + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; }; union { - __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ struct { - __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion - * width. */ - uint32_t : 5; - __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ - uint32_t : 5; - } STHB1_b; + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ struct { - __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled - * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 - * register) pin. */ - uint32_t : 1; - __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ - uint32_t : 3; - __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ - uint32_t : 23; - } STHB2_b; + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; }; union { - __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ struct { - __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ - uint32_t : 31; - } DE_b; + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; }; -} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ -/** - * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) - */ -typedef struct -{ union { - __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control - * Register */ + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ struct { - __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ - __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ - __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ - uint32_t : 29; - } DTCTEN_b; + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; }; union { - __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable - * Control Register */ + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ struct { - __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ - __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ - __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ - uint32_t : 29; - } INTEN_b; + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; }; union { - __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ struct { - __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ - __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ - __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ - uint32_t : 29; - } STCLR_b; + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; }; union { - __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ struct { - __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ - __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ - __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ - uint32_t : 29; - } STMON_b; + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; }; union { - __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock - * Control Register */ + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ struct { - __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 - * for details about setting value. Note: Settings that are - * not listed in table 2.7.1 are prohibited. */ - __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing - * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to - * 0. */ - uint32_t : 1; - __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ - uint32_t : 3; - __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same - * value as OUT_SET.FRQSEL[1]. */ - uint32_t : 3; - __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ - } PANEL_CLK_b; + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; }; -} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ -/** - * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) - */ -typedef struct -{ union { - __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } A_b; + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; }; union { - __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } B_b; + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; }; -} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; }; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED1[2]; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; }; - __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ /** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) */ typedef struct { union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control * Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; }; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; }; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; }; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) - */ -typedef struct -{ - __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ - __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ - __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ -} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ -/** - * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) - */ -typedef struct -{ union { - __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ struct { - __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ - uint8_t : 3; - } P_b; + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; }; + __IM uint32_t RESERVED[3]; union { - __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ struct { - __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ - uint8_t : 3; - } N_b; + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; }; -} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) */ typedef struct { + __IM uint32_t RESERVED; + union { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_PFS_PORT [PORT] (Port [0..11]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 2; - } RTCCR_b; + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; }; - __IM uint8_t RESERVED1; union { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; }; - __IM uint8_t RESERVED3[3]; union { - union + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; }; - __IM uint8_t RESERVED4; union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; }; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - } E_b; + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; }; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ -/* =========================================================================================================================== */ -/* ================ R_ACMPHS0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ /** - * @brief High-Speed Analog Comparator (R_ACMPHS0) + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) */ - -typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +typedef struct { union { - __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ struct { - __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ - __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ - __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ - __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ - __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ - __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ - } CMPCTL_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; }; - __IM uint8_t RESERVED[3]; union { - __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ struct { - __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ - uint8_t : 4; - } CMPSEL0_b; - }; - __IM uint8_t RESERVED1[3]; - - union - { - __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ - - struct - { - __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ - uint8_t : 2; - } CMPSEL1_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; }; - __IM uint8_t RESERVED2[3]; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ - uint8_t : 7; - } CMPMON_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; - __IM uint8_t RESERVED3[3]; union { - __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ - uint8_t : 6; - __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ - } CPIOC_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ - -/* =========================================================================================================================== */ -/* ================ R_ACMPLP ================ */ -/* =========================================================================================================================== */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief Low-Power Analog Comparator (R_ACMPLP) + * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) */ - -typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +typedef struct { union { - __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ - __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ - __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ - __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ - __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ - __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ - __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ - __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ - } COMPMDR_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + uint16_t : 13; + } C_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ - __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ - __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ - __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ - __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ - __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ - } COMPFIR_b; + __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: + * The low-order 2 bits are fixed to 0. */ + } S_b; }; union { - __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - uint8_t : 1; - __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ - __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ - uint8_t : 2; - __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ - __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ - __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ - } COMPOCR_b; + __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination.NOTE: The low-order + * 2 bits are fixed to 1. */ + } E_b; }; - __IM uint8_t RESERVED; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + */ +typedef struct +{ union { - __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ struct { - __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ - uint8_t : 1; - __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ - uint8_t : 1; - } COMPSEL0_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } CTL_b; }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[63]; + __IM uint16_t RESERVED2; union { - __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ struct { - __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ - uint8_t : 1; - __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ - __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ - } COMPSEL1_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; -} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ + __IM uint32_t RESERVED3[63]; + __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ +} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) */ - -typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +typedef struct { union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ struct { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + uint16_t : 2; + __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ + __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ + __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ + __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ + __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ + __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ + uint16_t : 4; + __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ + __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit + * is read as 1. The write value should be 1.) */ + __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ + __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ + } R_b; }; + __IM uint16_t RESERVED; +} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * "1" while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; - __IM uint8_t RESERVED; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) + */ +typedef struct +{ + __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ + __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ + __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ +} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ +/** + * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) + */ +typedef struct +{ union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ + uint8_t : 3; + } P_b; }; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ + uint8_t : 3; + } N_b; }; +} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct + union { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; + union + { + struct + { + __IM uint16_t RESERVED; - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..11]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; union { union { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ struct { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; }; }; + __IM uint8_t RESERVED1; union { - __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - struct + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[28]; + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; }; - __IM uint16_t RESERVED1[5]; + __IM uint8_t RESERVED2; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - struct + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - struct + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; }; + __IM uint8_t RESERVED4; union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; }; union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + } E_b; }; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ union { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ struct { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; }; + __IM uint8_t RESERVED[3]; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; }; + __IM uint8_t RESERVED1[3]; union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; }; + __IM uint8_t RESERVED2[3]; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; }; - __IM uint16_t RESERVED2; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; }; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * "1" while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; - __IM uint8_t RESERVED4; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; - __IM uint8_t RESERVED5; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select * Register */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; + __IM uint8_t RESERVED; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct + union { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; - struct + union { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; - __IM uint8_t RESERVED8; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; }; - __IM uint8_t RESERVED9; + __IM uint16_t RESERVED1[5]; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED2; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; + __IM uint16_t RESERVED3; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; - __IM uint8_t RESERVED12; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14[4]; - __IM uint8_t RESERVED15; + __IM uint8_t RESERVED4; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; - __IM uint8_t RESERVED16; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; - __IM uint8_t RESERVED17; - __IM uint16_t RESERVED18; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[82]; union { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; union { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; - __IM uint16_t RESERVED21[6]; + __IM uint8_t RESERVED8; union { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; - __IM uint16_t RESERVED22; + __IM uint8_t RESERVED9; union { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; union { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; - __IM uint16_t RESERVED23[21]; union { - __IOM uint8_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint8_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint8_t : 1; - __IOM uint8_t MONSEL : 4; /*!< [7..4] Monitor output selection bit. */ - } ADREFMON_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; - __IM uint8_t RESERVED24; - __IM uint16_t RESERVED25; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - uint32_t : 1; - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 12; - __IOM uint32_t PSARC26 : 1; /*!< [26..26] CANFD1 and the MSTPCRC.MSTPC26 bit security attribution */ - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC12 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 9; - } PSARD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; union { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; - } MSSAR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; union { - __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - uint32_t : 15; - __IM uint32_t CFS1 : 9; /*!< [23..15] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; union { - __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - uint32_t : 10; - __IM uint32_t CFS2 : 14; /*!< [23..10] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; union { - __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - uint32_t : 10; - __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; union { - __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ struct { - uint32_t : 13; - __IM uint32_t SS1 : 8; /*!< [20..13] SRAM Secure area 1 */ - uint32_t : 11; - } SSAMONA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; }; union { - __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - uint32_t : 10; - __IM uint32_t SS2 : 11; /*!< [20..10] SRAM secure area 2 */ - uint32_t : 11; - } SSAMONB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; union { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_AGT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGT0) - */ -typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ -{ union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written - * to the TSTOP bit in the AGTCRn register, the 16-bit counter - * is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; - __IM uint8_t RESERVED1; + __IM uint8_t RESERVED12; union { - __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[4]; + __IM uint8_t RESERVED15; union { - __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; -} R_AGT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40044600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; }; + __IM uint8_t RESERVED16; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; + __IM uint8_t RESERVED17; + __IM uint16_t RESERVED18; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; - __IM uint8_t RESERVED; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[82]; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; }; + __IM uint16_t RESERVED21[6]; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ + __IM uint16_t RESERVED22; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED23[21]; + + union + { + __IOM uint8_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint8_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint8_t : 1; + __IOM uint8_t MONSEL : 4; /*!< [7..4] Monitor output selection bit. */ + } ADREFMON_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ /* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ +/* ================ R_PSCU ================ */ /* =========================================================================================================================== */ /** - * @brief Controller Area Network (CAN) Module (R_CAN0) + * @brief Peripheral Security Control Unit (R_PSCU) */ -typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ { - __IM uint32_t RESERVED[128]; - __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + __IM uint32_t RESERVED; union { - __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 3; - } MKR_b[8]; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; union { - __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } FIDCR_b[2]; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 13; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; union { - __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ - } MKIVLR_b; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC12 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 9; + } PSARD_b; }; union { - union + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct { - __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ - } MIER_b; - }; + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - union + struct { - __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox - * Mode */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - } MIER_FIFO_b; - }; + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; }; - __IM uint32_t RESERVED1[252]; union { - union - { - __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - - struct - { - __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ - __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox - * setting enabled) */ - __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting - * enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_TX_b[32]; - }; + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ - union + struct { - __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ - - struct - { - __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ - __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting - * enabled) */ - __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_RX_b[32]; - }; + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; }; union { - __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ - __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ - __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ - __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ - __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ - __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ - __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ - __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ - __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ - __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ - uint16_t : 2; - } CTLR_b; + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; }; union { - __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ - __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ - __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ - __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ - __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ - __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ - __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ - __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ - __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ - __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ - __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ - __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ - __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ - __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ - __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ - uint16_t : 1; - } STR_b; + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ - uint32_t : 7; - __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ - uint32_t : 1; - __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ - uint32_t : 2; - __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the - * frequency of the CAN communication clock (fCANCLK). */ - uint32_t : 2; - __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ - } BCR_b; + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ - __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ - __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ - __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ - __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ - __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ - } RFCR_b; + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; }; union { - __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented - * by writing FFh to RFPCR. */ - } RFPCR_b; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ union { - __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ - __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ - uint8_t : 2; - __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ - __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ - } TFCR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented - * by writing FFh to TFPCR. */ - } TFPCR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ - __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ - __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ - __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ - __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ - __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ - __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ - __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ - } EIER_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ struct { - __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ - __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ - __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ - __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ - __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ - __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ - __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ - __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ - } EIFR_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ struct { - __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements - * the counter value according to the error status of the - * CAN module during reception. */ - } RECR_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ struct { - __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements - * the counter value according to the error status of the - * CAN module during transmission. */ - } TECR_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; + __IM uint8_t RESERVED1; union { - __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ struct { - __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ - __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ - __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ - __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ - __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ - __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ - __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ - __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ - } ECSR_b; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ struct { - __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel - * number is output to MSSR. */ - } CSSR_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ struct { - __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output - * the smallest mailbox number that is searched in each mode - * of MSMR. */ - uint8_t : 2; - __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ - } MSSR_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ struct { - __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ - uint8_t : 6; - } MSMR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ - union - { - __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ - - struct - { - __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ - } TSR_b; - }; +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ +/** + * @brief Bus Interface (R_BUS) + */ - struct - { - __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, - * the value converted for data table search can be read. */ - } AFSR_b; - }; +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ - __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ - uint8_t : 5; - } TCR_b; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ /* =========================================================================================================================== */ -/* ================ R_CRC ================ */ +/* ================ R_CAC ================ */ /* =========================================================================================================================== */ /** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) */ -typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ { union { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; union { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; - __IM uint16_t RESERVED; union { - union + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - union + struct { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - union + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - union + struct { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - union + struct { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; union { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ +} R_CAC_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ +/* ================ R_CAN0 ================ */ /* =========================================================================================================================== */ /** - * @brief Capacitive Touch Sensing Unit (R_CTSU) + * @brief Controller Area Network (CAN) Module (R_CAN0) */ -typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ { + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + union { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ struct { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; }; union { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ struct { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; }; union { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ struct { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; }; union { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct + union { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; - struct + union { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; }; + __IM uint32_t RESERVED1[252]; union { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - struct + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; }; union { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; }; union { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; }; union { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ struct { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; }; union { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ struct { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; }; union { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ struct { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; }; union { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ struct { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; }; union { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ struct { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; }; union { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ struct { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; }; union { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ struct { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; }; union { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ struct { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 3; - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ -/* =========================================================================================================================== */ -/* ================ R_CTSU2 ================ */ -/* =========================================================================================================================== */ + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU2) - */ + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; -typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ -{ union { - union + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct { - __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; - struct - { - __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ - __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ - __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ - __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */ - __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */ - __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ - __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ - __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ - __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ - __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ - __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ - __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ - __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */ - __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ - __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ - __IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */ - __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ - __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ - __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ - } CTSUCRA_b; - }; + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ struct { - union - { - __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ - - struct - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ - }; - }; + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; - union - { - __IOM uint16_t CTSUCRAH; /*!< (@ 0x00000002) CTSU Control Register A */ + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ - struct - { - __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ - __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ - }; - }; - }; + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; }; union { - union + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct { - __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; - struct - { - __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */ - __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */ - __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */ - uint32_t : 8; - __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */ - uint32_t : 1; - __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */ - uint32_t : 2; - } CTSUCRB_b; - }; + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ struct { - union - { - __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; - struct - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ - __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ - }; - }; + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ - union - { - __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ - - struct - { - __IM uint8_t RESERVED; - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ - }; - }; - }; + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; }; union { - union - { - __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - - struct - { - __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ - uint32_t : 2; - __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ - uint32_t : 2; - __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ - uint32_t : 12; - } CTSUMCH_b; - }; + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ struct { - union - { - __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ - struct - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ - }; - }; +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ - __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ - }; - }; - }; +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED[25]; union { - union + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct { - __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; - struct - { - __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ - uint32_t : 1; - __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ - uint32_t : 1; - __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ - uint32_t : 2; - __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ - } CTSUCHACA_b; - }; + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ struct { - union - { - __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - - struct - { - __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ - }; - }; + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 2; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ + uint32_t : 14; + } CFDGCTR_b; + }; - union - { - __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - struct - { - __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ - __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ - }; - }; - }; + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; }; union { - union - { - __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - struct - { - __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ - uint32_t : 28; - } CTSUCHACB_b; - }; - __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ - __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ + __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + uint32_t : 1; + __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ + __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ + uint32_t : 6; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; }; union { - union + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct { - __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; - struct - { - __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; - __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; - __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ - uint32_t : 2; - __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ - } CTSUCHTRCA_b; - }; + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ struct { - union - { - __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ - - struct - { - __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ - __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register - * A */ - }; - }; + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; - union - { - __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register - * A */ + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ - struct - { - __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register - * A */ - __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register - * A */ - }; - }; - }; + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; }; + __IM uint32_t RESERVED1[3]; union { - union - { - __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - struct - { - __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ - uint32_t : 28; - } CTSUCHTRCB_b; - }; - __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ - __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; }; union { - union + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct { - __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; - struct - { - __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ - uint32_t : 3; - __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ - __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ - __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ - __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ - uint32_t : 1; - __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ - __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ - uint32_t : 1; - __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ - __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ - uint32_t : 10; - } CTSUSR_b; - }; + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ struct { - union - { - __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; - struct - { - __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ - __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ - }; - }; + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - union - { - __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ - __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ - }; - }; + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; }; union { - union + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + + struct { - __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; - struct - { - __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ - __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ - uint32_t : 2; - __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */ - __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ - } CTSUSO_b; - }; + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ struct { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ - }; + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; }; + __IM uint32_t RESERVED3[18]; union { - union - { - __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement + * Registers */ - struct - { - __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ - __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter */ - } CTSUSCNT_b; - }; - __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; }; + __IM uint32_t RESERVED4[18]; union { - union + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + + struct { - __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; - struct - { - uint32_t : 2; - __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */ - __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Power Supply Forced Start */ - __IOM uint32_t CLKSEL : 2; /*!< [5..4] CTSU Observation Clock Select */ - __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */ - __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Switched Capacitor Operation Stop */ - __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] CTSU Read Count Select of Sensor Counter */ - __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */ - __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */ - __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */ - uint32_t : 4; - __IOM uint32_t CFCSEL : 6; /*!< [21..16] CTSU Observation CFC Clock Select */ - __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */ - uint32_t : 2; - __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */ - uint32_t : 1; - __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */ - __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */ - __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */ - __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */ - __IOM uint32_t TXREV : 1; /*!< [31..31] CTSU Transmit Pin Inverted Output */ - } CTSUCALIB_b; - }; + union + { + __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ struct { - __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ - __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ - }; + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; }; + __IM uint32_t RESERVED6[18]; union { - union + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct { - __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; - struct - { - __IOM uint32_t SUADJ0 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ - __IOM uint32_t SUADJ1 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ - } CTSUSUCLKA_b; - }; + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ struct { - __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ - __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ - }; + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ + uint32_t : 18; + } CFDFFSTS_b; }; union { - union + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct { - __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; - struct - { - __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ - __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ - } CTSUSUCLKB_b; - }; + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ struct { - __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ - __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ - }; + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; }; union { - union + __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct { - __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; - struct - { - __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ - uint32_t : 16; - } CTSUCFCCNT_b; - }; - __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + union + { + __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; }; -} R_CTSU2_Type; /*!< Size = 56 (0x38) */ -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ -/** - * @brief D/A Converter (R_DAC) - */ + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; -typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ -{ union { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ struct { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; }; union { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ struct { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ + uint32_t : 26; + } CFDCFMOWSTS_b; }; union { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ struct { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ + uint32_t : 18; + } CFDFFFSTS_b; }; + __IM uint32_t RESERVED7[2]; union { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ struct { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; }; + __IM uint32_t RESERVED8[288]; union { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ struct { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; }; + __IM uint32_t RESERVED9[288]; union { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register */ struct { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; + __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ + uint32_t : 24; + } CFDTMTRSTS_b[4]; }; + __IM uint32_t RESERVED10[36]; union { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; + __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 24; + } CFDTMTARSTS_b[4]; }; - __IM uint16_t RESERVED[9]; + __IM uint32_t RESERVED11[36]; union { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register */ struct { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; + __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 24; + } CFDTMTCSTS_b[4]; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; + __IM uint32_t RESERVED12[36]; union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 1; - } DAADUSR_b; + __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ + uint32_t : 24; + } CFDTMTASTS_b[4]; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC8 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief 8-Bit D/A Converter (R_DAC8) - */ + __IM uint32_t RESERVED13[36]; -typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ -{ union { - __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration + * Register */ struct { - __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ - } DACS_b[2]; + __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ + uint32_t : 24; + } CFDTMIEC_b[4]; }; - __IM uint8_t RESERVED; + __IM uint32_t RESERVED14[40]; union { - __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ struct { - __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ - __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ - uint8_t : 2; - __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ - __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ - uint8_t : 2; - } DAM_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; }; - __IM uint8_t RESERVED1[2]; + __IM uint32_t RESERVED15[6]; union { - __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ struct { - __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ - uint8_t : 7; - } DACADSCR_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS0_b[2]; }; + __IM uint32_t RESERVED16[6]; union { - __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ - uint8_t : 7; - } DACPC_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; }; -} R_DAC8_Type; /*!< Size = 8 (0x8) */ - -/* =========================================================================================================================== */ -/* ================ R_DALI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Digital Addressable Lighting Interface (R_DALI0) - */ + __IM uint32_t RESERVED17[6]; -typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */ -{ union { - __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register - * 1 */ + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ struct { - __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing - * violation threshold value 1.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 1; - __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing - * violation threshold value 2.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - } BTVTHR1_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; }; + __IM uint32_t RESERVED18[6]; union { - __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register - * 2 */ + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ struct { - __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing - * violation threshold value 3.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing - * violation threshold value 4.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - } BTVTHR2_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS1_b[2]; }; + __IM uint32_t RESERVED19[6]; union { - __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register - * 3 */ + __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ struct { - __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing - * violation threshold value 5.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 8; - } BTVTHR3_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; }; + __IM uint32_t RESERVED20[6]; union { - __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register - * 4 */ + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ struct { - __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing - * violation threshold value 6.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 7; - } BTVTHR4_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; }; + __IM uint32_t RESERVED21[6]; union { - __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */ + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ struct { - __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold - * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 2; - __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold - * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 2; - } COLTHR1_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS2_b[2]; }; + __IM uint32_t RESERVED22[6]; union { - __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */ + __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ struct { - __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold - * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold - * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - } COLTHR2_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; }; + __IM uint32_t RESERVED23[6]; union { - __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */ + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ struct { - __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold - * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold - * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - } COLTHR3_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; }; + __IM uint32_t RESERVED24[6]; union { - __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */ + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ struct { - __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold - * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold - * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - } COLTHR4_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 13; + } CFDTXQSTS3_b[2]; }; + __IM uint32_t RESERVED25[6]; union { - __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */ + __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ struct { - __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold - * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 8; - } COLTHR5_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; }; + __IM uint32_t RESERVED26[6]; union { - __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */ + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ struct { - __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */ - __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */ - uint16_t : 2; - __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */ - uint16_t : 1; - } CNFR1_b; + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; }; union { - __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */ + __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ struct { - __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only - * when the DALI0.STR1.BBF bit is 0. */ - uint16_t : 10; - } CNFR2_b; + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; }; union { - __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */ + __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ struct { - __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */ - uint16_t : 9; - } TXWR1_b; + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; }; - __IM uint16_t RESERVED[3]; + __IM uint32_t RESERVED27; union { - __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */ + __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ struct { - __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */ - } TDR1H_b; + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; }; union { - __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */ + __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ struct { - __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */ - } TDR1L_b; + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; }; union { - __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */ + __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ struct { - __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */ - uint16_t : 15; - } TRSTR1_b; + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 25; + } CFDTXQOFRISTS_b; }; - __IM uint16_t RESERVED1; union { - __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */ + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ struct { - __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */ - __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */ - uint16_t : 6; - __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */ - __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */ - __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */ - __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */ - __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */ - uint16_t : 3; - } CTR1_b; + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; }; + __IM uint32_t RESERVED28[24]; union { - __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */ + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ struct { - __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only - * when the DALI0.CTR1.TE bit is 0. */ - __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only - * when the DALI0.CTR1.TE bit is 0. */ - uint16_t : 14; - } TXDCTR1_b; + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; }; - __IM uint16_t RESERVED2[2]; + __IM uint32_t RESERVED29[6]; union { - __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */ + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ struct { - __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */ - } RDR1H_b; + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; }; + __IM uint32_t RESERVED30[6]; union { - __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */ + __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ struct { - __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */ - } RDR1L_b; + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; }; + __IM uint32_t RESERVED31[46]; union { - __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */ + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ struct { - __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */ - __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */ - __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */ - __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */ - __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */ - __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */ - __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */ - __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */ - __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */ - __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */ - __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length - * for data received successfully */ - } STR1_b; + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; }; - __IM uint16_t RESERVED3; + __IM uint32_t RESERVED32; union { - __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */ + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ struct { - __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */ - __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */ - uint16_t : 5; - __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */ - __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after - * the DRX0 pin is synchronized */ - __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */ - __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */ - uint16_t : 2; - } COLR1_b; + __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; }; - __IM uint16_t RESERVED4; union { - __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */ + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ struct { - __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */ - __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */ - __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */ - __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */ - __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */ - __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF - * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */ - __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */ - __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */ - __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */ - __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */ - uint16_t : 6; - } FECR1_b; + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; }; + __IM uint32_t RESERVED33; union { - __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */ + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ struct { - __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software - * reset. */ - uint16_t : 15; - } SWRR1_b; + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; }; -} R_DALI0_Type; /*!< Size = 62 (0x3e) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ union { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */ struct { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; + __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */ + uint32_t : 31; + } CFDGCRCCFG_b; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ struct { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 14; - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ union { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ struct { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; + __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ + uint32_t : 7; + __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ + __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ + __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ + __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ + uint32_t : 16; + } CFDGLOTB_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; union { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; + __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ + uint32_t : 7; + __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ + uint32_t : 13; + } CFDGAFLIGNENT_b; }; -} R_DMA_Type; /*!< Size = 68 (0x44) */ -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ union { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ struct { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; }; + __IM uint32_t RESERVED34; union { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ struct { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; }; union { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ struct { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; }; + __IM uint32_t RESERVED35[2]; union { - __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ struct { - __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ struct { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; }; - __IM uint8_t RESERVED1; + __IM uint32_t RESERVED36[2]; union { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ struct { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; }; + __IM uint32_t RESERVED37[10]; union { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ struct { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ - } DMAMD_b; + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; }; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED38[31]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED39[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED40[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED41[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IM uint32_t RESERVED42[8]; + __IOM R_CANFD_CFDCF_Type CFDCF[5]; /*!< (@ 0x00006420) Common FIFO Access Registers */ + __IM uint32_t RESERVED43[1624]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED44[252]; union { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ struct { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address update mode for transfer source or destination. */ - } DMOFR_b; + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; }; + __IM uint32_t RESERVED45[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[32]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ +} R_CANFD_Type; /*!< Size = 69632 (0x11000) */ - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ union { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ struct { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; }; union { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ struct { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; }; - __IM uint8_t RESERVED3; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + __IM uint16_t RESERVED; union { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct + union { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; - struct + union { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; }; union { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct + union { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ -typedef struct /*!< (@ 0x40054100) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; - struct + union { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; - struct + union { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; }; union { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ struct { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ -/* ================ R_DRW ================ */ +/* ================ R_CTSU ================ */ /* =========================================================================================================================== */ /** - * @brief 2D Drawing Engine (R_DRW) + * @brief Capacitive Touch Sensing Unit (R_CTSU) */ -typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ { union { - union - { - __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ - - struct - { - __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ - __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ - __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ - __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ - __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ - __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ - __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ - __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ - __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ - __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ - __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ - __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ - __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ - __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ - __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ - __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ - __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ - __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ - __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ - __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ - __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ - __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ - __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per - * scanline */ - __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line - * span start */ - uint32_t : 8; - } CONTROL_b; - }; + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - union + struct { - __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ - - struct - { - __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ - __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ - __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ - __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ - __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ - __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ - __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ - uint32_t : 1; - __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ - __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ - __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ - uint32_t : 21; - } STATUS_b; - }; + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; }; union { - union - { - __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ - - struct - { - __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and - * COLOR2 depending on PATTERN and pattern index) */ - __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha - * to blend between COLOR1 and COLOR2 */ - __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default - * U limiter.Limiter 5 can be combined with limiter 6 to form - * a quadratic limiter which can be used to make quadratic - * pattern functions to draw radial patterns. */ - __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ - __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT - * above for description */ - __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel - * blending mode (USEACB = 1) */ - __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel - * blending mode (USEACB = 1) */ - __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above - * description. */ - __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per - * default) */ - __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor - * is 1 per default) */ - __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted - * (meaning 1-a or 1-1 depending on BSF) */ - __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will - * be inverted (meaning 1-a or 1-1 depending on BDF) */ - __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ - __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes - * what happens if the U limiter (x direction in texture space) - * calculates a U value outside of the used texture */ - __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes - * what happens if the V limiter (y direction in texture space) - * calculates a V value outside of the used texture */ - __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ - __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ - __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: - * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: - * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) - * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), - * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), - * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), - * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), - * 1 bit indexed color/luminance */ - __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ - __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha - * source' for the framebuffer(USEACB = 0)Blend alpha in color - * 2 instead of framebuffer alpha((USEACB = 1))In not alpha - * channel blending mode (USEACB = 0):Set the 'alpha source' - * for the framebuffer.In alpha channel blending mode (USEACB - * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: - * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: - * BC2A = 0: use alpha in color 2 as destination (DST_A) */ - __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ - __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ - __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ - __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ - __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB - * = 1) */ - __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel - * (USEACB = 1) */ - __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ - } CONTROL2_b; - }; + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - union + struct { - __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ - - struct - { - __IM uint32_t REV : 12; /*!< [11..0] Revision number */ - uint32_t : 5; - __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ - __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ - __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ - __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ - __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ - uint32_t : 1; - __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ - __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ - __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ - uint32_t : 1; - __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ - uint32_t : 4; - } HWREVISION_b; - }; + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; }; - __IM uint32_t RESERVED[2]; union { - __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L1START_b; + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; }; union { - __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L2START_b; - }; - - union - { - __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ - - struct - { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L3START_b; + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; }; union { - __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L4START_b; + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; }; union { - __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L5START_b; + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; }; union { - __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L6START_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; }; union { - __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L1XADD_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; }; union { - __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L2XADD_b; + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; }; union { - __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L3XADD_b; + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; }; union { - __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L4XADD_b; + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; }; union { - __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L5XADD_b; + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; }; union { - __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L6XADD_b; + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; }; union { - __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L1YADD_b; + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; }; union { - __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L2YADD_b; + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; }; union { - __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L3YADD_b; + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 3; + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ - union - { - __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L4YADD_b; - }; +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU2) + */ +typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ +{ union { - __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ - - struct + union { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L5YADD_b; - }; + __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ - union - { - __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + struct + { + __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ + __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ + __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ + __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */ + __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */ + __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ + __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ + __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ + __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ + __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ + __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ + __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ + __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */ + __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ + __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ + __IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */ + __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ + __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ + __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ + } CTSUCRA_b; + }; struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L6YADD_b; - }; + union + { + __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ - union - { - __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + struct + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ + }; + }; - struct - { - __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ - } L1BAND_b; + union + { + __IOM uint16_t CTSUCRAH; /*!< (@ 0x00000002) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ + __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ + }; + }; + }; }; union { - __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ - - struct + union { - __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ - } L2BAND_b; - }; - __IM uint32_t RESERVED1; + __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ - union - { - __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + struct + { + __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */ + __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */ + __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */ + uint32_t : 8; + __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */ + uint32_t : 1; + __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */ + uint32_t : 2; + } CTSUCRB_b; + }; struct { - __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ - __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ - __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ - __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: - * opaque) */ - } COLOR1_b; - }; - - union - { - __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + union + { + __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ - struct - { - __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ - __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ - __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ - __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: - * opaque) */ - } COLOR2_b; - }; - __IM uint32_t RESERVED2[2]; + struct + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ + }; + }; - union - { - __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + union + { + __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ - struct - { - __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ - uint32_t : 24; - } PATTERN_b; + struct + { + __IM uint8_t RESERVED; + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ + }; + }; + }; }; union { - __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ - - struct + union { - __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to - * 1024 */ - __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 - * to 1024 */ - } SIZE_b; - }; + __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - union - { - __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + struct + { + __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ + uint32_t : 2; + __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ + uint32_t : 2; + __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ + uint32_t : 12; + } CTSUMCH_b; + }; struct { - __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used - * to render bottom-up instead of top-down */ - __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ - } PITCH_b; - }; + union + { + __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - union - { - __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + struct + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ + }; + }; - struct - { - __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ - } ORIGIN_b; + union + { + __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + }; + }; }; - __IM uint32_t RESERVED3[3]; union { - __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ - - struct + union { - __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ - } LUSTART_b; - }; + __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - union - { - __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + struct + { + __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ + uint32_t : 2; + __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ + } CTSUCHACA_b; + }; struct { - __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ - } LUXADD_b; - }; - - union - { - __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + union + { + __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - struct - { - __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ - } LUYADD_b; - }; + struct + { + __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ + }; + }; - union - { - __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + union + { + __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ - struct - { - __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ - } LVSTARTI_b; + struct + { + __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ + }; + }; + }; }; union { - __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ - - struct + union { - __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ - uint32_t : 16; - } LVSTARTF_b; - }; - - union - { - __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ - struct - { - __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ - } LVXADDI_b; + struct + { + __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ + uint32_t : 28; + } CTSUCHACB_b; + }; + __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ }; union { - __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ - - struct + union { - __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ - } LVYADDI_b; - }; + __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ - union - { - __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + struct + { + __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ + uint32_t : 2; + __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ + } CTSUCHTRCA_b; + }; struct { - __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ - __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ - } LVYXADDF_b; - }; - __IM uint32_t RESERVED4; + union + { + __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ - union - { - __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + struct + { + __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; - struct - { - __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ - } TEXPITCH_b; + union + { + __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + }; }; union { - __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ - - struct + union { - __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture - * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width - * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX - * = 1):all widths up to 2048 are allowed. */ - __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = - * 0): texture_height must be a power of 2In texture clamping - * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 - * are allowed. */ - } TEXMASK_b; + __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + + struct + { + __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ + uint32_t : 28; + } CTSUCHTRCB_b; + }; + __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ }; union { - __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ - - struct + union { - __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ - } TEXORIGIN_b; - }; + __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ - union - { - __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + struct + { + __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ + uint32_t : 3; + __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ + __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ + __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ + __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ + uint32_t : 1; + __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ + __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ + uint32_t : 1; + __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ + __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ + uint32_t : 10; + } CTSUSR_b; + }; struct { - __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ - __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ - __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ - __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ - __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ - __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ - uint32_t : 26; - } IRQCTL_b; - }; + union + { + __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ - union - { - __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + struct + { + __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ + }; + }; - struct - { - __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ - __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ - __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ - __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ - uint32_t : 28; - } CACHECTL_b; + union + { + __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ + __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ + }; + }; }; union { - __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ - - struct + union { - __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ - } DLISTSTART_b; - }; + __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ - union - { - __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ + __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ + uint32_t : 2; + __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */ + __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ + } CTSUSO_b; + }; struct { - __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT - * = 0000 0000H. */ - } PERFCOUNT1_b; + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + }; }; union { - __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ - - struct + union { - __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT - * = 0000 0000H. */ - } PERFCOUNT2_b; + __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + + struct + { + __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ + __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter */ + } CTSUSCNT_b; + }; + __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ }; union { - __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + union + { + __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */ + __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Power Supply Forced Start */ + __IOM uint32_t CLKSEL : 2; /*!< [5..4] CTSU Observation Clock Select */ + __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */ + __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Switched Capacitor Operation Stop */ + __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] CTSU Read Count Select of Sensor Counter */ + __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */ + __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */ + __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */ + uint32_t : 4; + __IOM uint32_t CFCSEL : 6; /*!< [21..16] CTSU Observation CFC Clock Select */ + __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */ + uint32_t : 2; + __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */ + uint32_t : 1; + __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */ + __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */ + __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */ + __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */ + __IOM uint32_t TXREV : 1; /*!< [31..31] CTSU Transmit Pin Inverted Output */ + } CTSUCALIB_b; + }; struct { - __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 - * register. */ - __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 - * register */ - } PERFTRIGGER_b; + __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + }; }; - __IM uint32_t RESERVED5; union { - __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + union + { + __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + + struct + { + __IOM uint32_t SUADJ0 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ1 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKA_b; + }; struct { - __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ - uint32_t : 24; - } TEXCLADDR_b; + __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ + }; }; union { - __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + union + { + __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + + struct + { + __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKB_b; + }; struct { - __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ - } TEXCLDATA_b; + __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ + }; }; union { - __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ - - struct + union { - __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] - * is or'ed with the original index */ - uint32_t : 24; - } TEXCLOFFSET_b; - }; - - union - { - __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ - struct - { - __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ - __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ - __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ - uint32_t : 8; - } COLKEY_b; + struct + { + __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ + uint32_t : 16; + } CTSUCFCCNT_b; + }; + __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ }; -} R_DRW_Type; /*!< Size = 236 (0xec) */ +} R_CTSU2_Type; /*!< Size = 56 (0x38) */ /* =========================================================================================================================== */ -/* ================ R_DTC ================ */ +/* ================ R_DAC ================ */ /* =========================================================================================================================== */ /** - * @brief Data Transfer Controller (R_DTC) + * @brief D/A Converter (R_DAC) */ -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ { union { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ struct { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ - } DTCVBR_b; + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ struct { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ uint8_t : 7; - } DTCST_b; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; }; - __IM uint8_t RESERVED3; union { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ struct { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; }; union { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; - } DTCCR_SEC_b; + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ struct { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ -typedef struct /*!< (@ 0x40041000) R_ELC Structure */ -{ union { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ struct { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; + __IM uint16_t RESERVED[9]; union { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ struct { - __IOM uint16_t ELSEGR0 : 1; /*!< [0..0] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [1..1] Event Link Software Event Generation Register 1Security - * Attribution */ - __IOM uint16_t ELCR : 1; /*!< [2..2] Event Link Controller RegisterSecurity Attribution */ - uint16_t : 13; - } ELCSARA_b; + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; }; - __IM uint16_t RESERVED3; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; union { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; }; + __IM uint8_t RESERVED3; __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ +/* ================ R_DAC8 ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet MAC Controller (R_ETHERC0) + * @brief 8-Bit D/A Converter (R_DAC8) */ -typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ { union { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ struct { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; }; - __IM uint32_t RESERVED; + __IM uint8_t RESERVED; union { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ struct { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; }; - __IM uint32_t RESERVED1; + __IM uint8_t RESERVED1[2]; union { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ struct { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ struct { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; }; - __IM uint32_t RESERVED3; +} R_DAC8_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_DALI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Digital Addressable Lighting Interface (R_DALI0) + */ +typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */ +{ union { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register + * 1 */ struct { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; + __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing + * violation threshold value 1.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 1; + __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing + * violation threshold value 2.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR1_b; }; - __IM uint32_t RESERVED4; union { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register + * 2 */ struct { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; + __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing + * violation threshold value 3.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing + * violation threshold value 4.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR2_b; }; - __IM uint32_t RESERVED5[5]; union { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ + __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register + * 3 */ struct { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; + __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing + * violation threshold value 5.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 8; + } BTVTHR3_b; }; - __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register + * 4 */ struct { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" */ - uint32_t : 27; - } IPGR_b; + __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing + * violation threshold value 6.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 7; + } BTVTHR4_b; }; union { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */ struct { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; + __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold + * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold + * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + } COLTHR1_b; }; union { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */ struct { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; + __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold + * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold + * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR2_b; }; - __IM uint32_t RESERVED7; union { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */ struct { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; + __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold + * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold + * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR3_b; }; union { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */ struct { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; + __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold + * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold + * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + } COLTHR4_b; }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ union { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */ struct { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; + __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold + * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 8; + } COLTHR5_b; }; - __IM uint32_t RESERVED8[20]; union { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */ struct { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; + __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */ + __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */ + uint16_t : 2; + __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */ + uint16_t : 1; + } CNFR1_b; }; - __IM uint32_t RESERVED9; union { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */ struct { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; + __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only + * when the DALI0.STR1.BBF bit is 0. */ + uint16_t : 10; + } CNFR2_b; }; - __IM uint32_t RESERVED10; union { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */ struct { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; + __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */ + uint16_t : 9; + } TXWR1_b; }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + __IM uint16_t RESERVED[3]; union { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */ struct { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; + __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */ + } TDR1H_b; }; union { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */ struct { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; + __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */ + } TDR1L_b; }; - __IM uint32_t RESERVED11; union { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */ struct { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; + __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */ + uint16_t : 15; + } TRSTR1_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */ struct { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union + __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */ + __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */ + uint16_t : 6; + __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */ + __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */ + __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */ + __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */ + __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */ + uint16_t : 3; + } CTR1_b; + }; + + union { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */ struct { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; + __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + uint16_t : 14; + } TXDCTR1_b; }; + __IM uint16_t RESERVED2[2]; union { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */ struct { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; + __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */ + } RDR1H_b; }; union { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */ struct { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; + __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */ + } RDR1L_b; }; union { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */ struct { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; + __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */ + __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */ + __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */ + __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */ + __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */ + __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */ + __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */ + __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */ + __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */ + __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */ + __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length + * for data received successfully */ + } STR1_b; }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + __IM uint16_t RESERVED3; + + union + { + __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */ + + struct + { + __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */ + __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */ + uint16_t : 5; + __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */ + __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after + * the DRX0 pin is synchronized */ + __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */ + __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */ + uint16_t : 2; + } COLR1_b; + }; + __IM uint16_t RESERVED4; + + union + { + __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */ + + struct + { + __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */ + __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */ + __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */ + __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */ + __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */ + __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF + * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */ + __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */ + __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */ + __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */ + __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */ + uint16_t : 6; + } FECR1_b; + }; + + union + { + __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */ + + struct + { + __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software + * reset. */ + uint16_t : 15; + } SWRR1_b; + }; +} R_DALI0_Type; /*!< Size = 62 (0x3e) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ +/* ================ R_DEBUG ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + * @brief Debug Function (R_DEBUG) */ -typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ { union { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ struct { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; }; - __IM uint32_t RESERVED; + __IM uint32_t RESERVED[3]; union { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ struct { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; }; - __IM uint32_t RESERVED1; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ union { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ struct { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; }; - __IM uint32_t RESERVED2; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; union { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ struct { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; }; - __IM uint32_t RESERVED3; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ union { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ struct { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; }; - __IM uint32_t RESERVED4; union { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ struct { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; }; - __IM uint32_t RESERVED5; union { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ struct { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; }; - __IM uint32_t RESERVED6; union { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ + __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ struct { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; + __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; }; - __IM uint32_t RESERVED7; + __IM uint16_t RESERVED; union { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ struct { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; }; - __IM uint32_t RESERVED8; + __IM uint8_t RESERVED1; union { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ struct { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; }; - __IM uint32_t RESERVED9; union { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ struct { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; }; - __IM uint32_t RESERVED10; + __IM uint16_t RESERVED2; union { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ struct { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; }; - __IM uint32_t RESERVED11[2]; union { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ struct { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; }; union { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ struct { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; }; union { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ struct { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; }; + __IM uint8_t RESERVED3; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ struct { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; }; - __IM uint32_t RESERVED12; union { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ struct { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; }; union { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ struct { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; }; - __IM uint32_t RESERVED13[18]; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ union { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ struct { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ struct { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; }; - __IM uint32_t RESERVED14; union { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ struct { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC ================ */ -/* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ /** - * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + * @brief 2D Drawing Engine (R_DRW) */ -typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ { union { - __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ - struct + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union { - __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ - __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ - __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ - uint32_t : 1; - __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ - __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ - __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ - uint32_t : 5; - __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ - uint32_t : 1; - __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ - uint32_t : 1; - __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ - __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ - uint32_t : 14; - } SYSR_b; + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; }; union { - __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ - struct + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union { - __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ - __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ - __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ - __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ - __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ - uint32_t : 5; - __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ - __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ - uint32_t : 14; - } SYIPR_b; + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; }; __IM uint32_t RESERVED[2]; union { - __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ struct { - __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the local MAC address. */ - uint32_t : 8; - } SYMACRU_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; }; union { - __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ struct { - __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the local MAC address. */ - uint32_t : 8; - } SYMACRL_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; }; union { - __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ struct { - __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the - * control field in the LLC sublayer when generating IEEE802.3 - * frames. */ - uint32_t : 24; - } SYLLCCTLR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; }; union { - __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ struct { - __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ - } SYIPADDRR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; }; - __IM uint32_t RESERVED1[8]; union { - __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ struct { - __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the - * versionPTP field value of the PTP v2 header.When a message - * is received, this value is compared with the versionPTP - * field of the received frame.In generating messages, the - * value is used for the versionPTP field of the frame for - * transmission.Set these bits to 0010b (PTP v2). */ - __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set - * the transportSpecific field value of the PTP v2 header.When - * a message is received, this value is compared with the - * transportSpecific field of the received frame.In generating - * messages, the value is used for the transportSpecific field - * of the frame for transmission.Set these bits to 0000b (IEEE - * 1588). */ - uint32_t : 24; - } SYSPVRR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; }; union { - __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ struct { - __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to - * set the domainNumber field value of the PTP v2 header.When - * a message is received, this value is compared with the - * domainNumber field of the received frame as a condition - * for PTP reception processing.In generating messages, the - * value is used for the domainNumber field of the frame for - * transmission. */ - uint32_t : 24; - } SYDOMR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; }; - __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ struct { - __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the - * leap61 member of timePropertiesDS. */ - __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the - * leap59 member of timePropertiesDS. */ - __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical - * value of the currentUtcOffsetValid member of timePropertiesDS. */ - __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value - * of the ptpTimescale member of timePropertiesDS. */ - __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value - * of the timeTraceable member of timePropertiesDS. */ - __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical - * value of the frequencyTraceable member of timePropertiesDS. */ - uint32_t : 2; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - uint32_t : 1; - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } ANFR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; }; union { - __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ struct { - uint32_t : 8; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } SYNFR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; }; union { - __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ struct { - uint32_t : 10; - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } DYRQFR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; }; union { - __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ struct { - uint32_t : 8; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } DYRPFR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; }; union { - __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ struct { - __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the clock-ID of your port. */ - } SYCIDRU_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; }; union { - __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ struct { - __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the clock-ID of your port. */ - } SYCIDRL_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; }; union { - __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ struct { - __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting - * for the port number of the local port. */ - uint32_t : 16; - } SYPNUMR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; }; - __IM uint32_t RESERVED3[5]; union { - __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ struct { - __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ - __OM uint32_t STUP : 1; /*!< [1..1] State Update */ - __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ - uint32_t : 29; - } SYRVLDR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ struct { - __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ - __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ - uint32_t : 2; - __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ - __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ - __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ - uint32_t : 1; - __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ - __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ - __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ - uint32_t : 1; - __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ - __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ - __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ - uint32_t : 1; - __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ - __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ - __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ - uint32_t : 1; - __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ - __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ - __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ - uint32_t : 1; - __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ - __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ - __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ - uint32_t : 1; - __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ - __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ - __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ - uint32_t : 1; - } SYRFL1R_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; }; union { - __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ struct { - __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ - __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ - uint32_t : 2; - __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ - __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ - uint32_t : 22; - __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ - __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ - uint32_t : 2; - } SYRFL2R_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; }; union { - __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ struct { - __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ - uint32_t : 19; - } SYTRENR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; }; - __IM uint32_t RESERVED5; union { - __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ struct { - __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the clock-ID of the master clock. */ - } MTCIDU_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; }; union { - __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ struct { - __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the clock-ID of the master clock. */ - } MTCIDL_b; + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; }; union { - __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ struct { - __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the - * setting for the port number of the master clock. */ - uint32_t : 16; - } MTPID_b; + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; }; - __IM uint32_t RESERVED6[5]; + __IM uint32_t RESERVED1; union { - __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ struct { - __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits - * set the interval for the transmission of Announce messages. */ - __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits - * set the interval for the transmission of Sync messages. - * The setting is also placed in the logMessageInterval field - * of transmitted Sync messages. */ - __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req - * Transmission Interval SettingThe bits set the average interval - * for the transmission of Delay_Req messages and the interval - * for the transmission of Pdelay_Req messages.The setting - * is also placed in the logMessageInterval field of Delay_Resp - * messages. */ - uint32_t : 8; - } SYTLIR_b; + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; }; union { - __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication - * Register */ + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ struct { - __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Announce message. */ - __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Sync message. */ - __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Delay_Resp message. */ - uint32_t : 8; - } SYRLIR_b; + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; }; + __IM uint32_t RESERVED2[2]; union { - __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ struct { - __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the - * calculated offsetFromMaster value. */ - } OFMRU_b; + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; }; union { - __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ struct { - __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated - * offsetFromMaster value. */ - } OFMRL_b; + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; }; union { - __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ struct { - __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the - * calculated meanPathDelay value. */ - } MPDRU_b; + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; }; union { - __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ struct { - __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated - * meanPathDelay value. */ - } MPDRL_b; + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; }; - __IM uint32_t RESERVED7[2]; + __IM uint32_t RESERVED3[3]; union { - __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ struct { - __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are - * used to set the value of the grandmasterPriority2 fields - * of Announce messages. */ - uint32_t : 8; - __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits - * are used to set the value of the grandmasterPriority1 fields - * of Announce messages. */ - uint32_t : 8; - } GMPR_b; + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; }; union { - __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ struct { - __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality - * fields of Announce messages. The correspondence between - * bits and the grandmasterClockQuality fields is as listed - * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 - * to b0: offsetScaledLogVariance */ - } GMCQR_b; + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; }; union { - __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ struct { - __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the value of the grandmasterIdentity fields of - * Announce messages. */ - } GMIDRU_b; + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; }; union { - __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ struct { - __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the value of the grandmasterIdentity fields of Announce - * messages. */ - } GMIDRL_b; + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; }; union { - __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ struct { - __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the - * timeSource fields of Announce messages. */ - uint32_t : 8; - __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value - * of the currentUtcOffset fields of Announce messages. */ - } CUOTSR_b; + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; }; union { - __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ struct { - __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value - * of the stepsRemoved fields of Announce messages. */ - uint32_t : 16; - } SRR_b; + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; }; - __IM uint32_t RESERVED8[2]; union { - __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting - * Registers */ + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ struct { - __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the destination MAC address for PTP-primary messages. */ - uint32_t : 8; - } PPMACRU_b; + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; }; union { - __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting - * Registers */ + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ struct { - __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the destination MAC address for PTP-primary messages. */ - uint32_t : 8; - } PPMACRL_b; + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ struct { - __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the destination MAC address for PTP-pdelay messages. */ - uint32_t : 8; - } PDMACRU_b; + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; }; union { - __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ struct { - __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the destination MAC address for PTP-pdelay messages. */ - uint32_t : 8; - } PDMACRL_b; + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; }; union { - __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ struct { - __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the - * setting for the EtherType field value for frames in the - * Ethernet II format. */ - uint32_t : 16; - } PETYPER_b; + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; }; - __IM uint32_t RESERVED9[3]; union { - __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting - * Register */ + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ struct { - __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address - * for PTPprimary messages. */ - } PPIPR_b; + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; }; union { - __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting - * Register */ + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ struct { - __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address - * for PTPpdelay messages. */ - } PDIPR_b; + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; }; union { - __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ struct { - __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold - * the setting for the value of the TOS field within the IPv4 - * headers of PTP event messages. */ - uint32_t : 24; - } PETOSR_b; + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; }; union { - __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ struct { - __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits - * hold the setting for the value of the TOS field within - * the IPv4 headers of PTP general messages. */ - uint32_t : 24; - } PGTOSR_b; + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; }; union { - __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ struct { - __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits - * hold the setting for the value of the TTL field within - * the IPv4 headers of PTP-primary messages. */ - uint32_t : 24; - } PPTTLR_b; + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; }; union { - __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ struct { - __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the - * setting for the value of the TTL field within the IPv4 - * headers of PTP-pdelay messages. */ - uint32_t : 24; - } PDTTLR_b; + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number - * Setting Register */ + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ struct { - __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese - * bits hold the setting for the value of the destination - * port number field within the UDP headers of PTP event messages. */ - uint32_t : 16; - } PEUDPR_b; + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; }; union { - __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number - * Setting Register */ + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ struct { - __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits - * hold the setting for the value of the destination port - * number field within the UDP headers of PTP general messages. */ - uint32_t : 16; - } PGUDPR_b; + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; }; union { - __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ struct { - __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these - * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ - __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits - * is only effective when EXTPRM=0 and ENB=1. */ - __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits - * is only effective when EXTPRM=0. */ - uint32_t : 13; - __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ - uint32_t : 15; - } FFLTR_b; + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; }; - __IM uint32_t RESERVED10[31]; union { - __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ struct { - __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 - * bits of the asymmetric delay value. */ - uint32_t : 16; - } DASYMRU_b; + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; }; +} R_DRW_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ union { - __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ struct { - __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the asymmetric delay value. */ - } DASYMRL_b; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; union { - __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ struct { - __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold - * the setting for the time stamp latency (ns) for the input - * ports. */ - __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold - * the setting for the time stamp latency (ns) for the output - * ports. */ - } TSLATR_b; + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ struct { - __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are - * used to set the time from the completion of one transmission - * to the start of the next in cycles of the transmission - * clock. A value n in these bits means that a transmission - * interval of n cycles will be secured.No interval is secured - * if the setting is 00h.We recommend the setting 28h (40 - * cycles). */ - uint32_t : 4; - __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ - uint32_t : 3; - __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ - uint32_t : 3; - __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ - uint32_t : 11; - } SYCONFR_b; + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; }; + __IM uint8_t RESERVED3; union { - __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ struct { - __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ - __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ - uint32_t : 30; - } SYFORMR_b; + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; }; union { - __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ struct { - __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response - * message not being received within n x 1024 (ns), where - * n is the setting, is judged to represent a timeout. */ - } RSTOUTR_b; + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; }; -} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* ================ R_ELC ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) + * @brief Event Link Controller (R_ELC) */ -typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ { union { - __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ struct { - __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ - uint32_t : 31; - } PTRSTR_b; + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; union { - __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ struct { - __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ - uint32_t : 5; - __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ - uint32_t : 21; - } STCSELR_b; + __IOM uint16_t ELSEGR0 : 1; /*!< [0..0] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [1..1] Event Link Software Event Generation Register 1Security + * Attribution */ + __IOM uint16_t ELCR : 1; /*!< [2..2] Event Link Controller RegisterSecurity Attribution */ + uint16_t : 13; + } ELCSARA_b; }; + __IM uint16_t RESERVED3; union { - __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ struct { - __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ - uint32_t : 15; - __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ - uint32_t : 15; - } BYPASS_b; + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; }; -} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* ================ R_ETHERC0 ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + * @brief Ethernet MAC Controller (R_ETHERC0) */ -typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ { union { - __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ struct { - __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ - __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ - __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ - __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ - uint32_t : 12; - __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ - __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ - __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ - __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ - __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ - __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ - uint32_t : 10; - } MIESR_b; + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ struct { - __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ - __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ - __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ - __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ - uint32_t : 12; - __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt - * Request Permission */ - uint32_t : 10; - } MIEIPR_b; + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; }; - __IM uint32_t RESERVED[2]; + __IM uint32_t RESERVED1; union { - __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission - * Register */ + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ struct { - __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output - * Enable */ - uint32_t : 2; - __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output - * Enable */ - uint32_t : 2; - __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt - * Request Permission */ - uint32_t : 7; - __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt - * Request Permission */ - uint32_t : 7; - } ELIPPR_b; + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic - * Clearing Register */ + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ struct { - __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ - __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ - __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ - __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ - __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ - __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ - uint32_t : 2; - __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ - __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ - __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ - __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ - __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ - __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ - uint32_t : 2; - __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ - uint32_t : 7; - __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ - uint32_t : 7; - } ELIPACR_b; + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; }; - __IM uint32_t RESERVED1[10]; + __IM uint32_t RESERVED3; union { - __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ struct { - __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ - __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ - uint32_t : 1; - __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ - __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ - uint32_t : 27; - } STSR_b; + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ struct { - __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ - __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ - uint32_t : 1; - __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ - __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ - uint32_t : 27; - } STIPR_b; + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; }; - __IM uint32_t RESERVED2[2]; + __IM uint32_t RESERVED5[5]; union { - __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ struct { - __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ - uint32_t : 30; - } STCFR_b; + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ struct { - __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ - uint32_t : 5; - __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ - uint32_t : 1; - __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ - __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ - __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ - uint32_t : 4; - __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ - __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ - uint32_t : 2; - } STMR_b; + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" */ + uint32_t : 27; + } IPGR_b; }; union { - __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ struct { - __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), - * where n is the setting, leads to a timeout for reception - * of Sync messages, leading to the STSR.SYNTOUT flag being - * set to 1. */ - } SYNTOR_b; + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; }; - __IM uint32_t RESERVED3; union { - __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ struct { - __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ - __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ - __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ - __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ - __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ - __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ - uint32_t : 26; - } IPTSELR_b; + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ struct { - __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ - uint32_t : 26; - } MITSELR_b; + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; }; union { - __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ struct { - __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ - __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ - __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ - __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ - __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ - __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ - uint32_t : 26; - } ELTSELR_b; + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ union { - __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ struct { - __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the - * value of this bit while the SYNSTARTR.STR bit is 1. */ - uint32_t : 31; - } STCHSELR_b; + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; }; - __IM uint32_t RESERVED4[4]; + __IM uint32_t RESERVED8[20]; union { - __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ struct { - __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ - uint32_t : 31; - } SYNSTARTR_b; + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; }; + __IM uint32_t RESERVED9; union { - __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive - * Register */ + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ struct { - __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ - uint32_t : 31; - } LCIVLDR_b; + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; }; - __IM uint32_t RESERVED5[2]; + __IM uint32_t RESERVED10; union { - __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ struct { - __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the threshold for detection of loss of synchronization. */ - } SYNTDARU_b; + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ union { - __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ struct { - __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the threshold for detection of loss of synchronization. */ - } SYNTDARL_b; + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; }; union { - __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ struct { - __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the threshold for detection of synchronization. */ - } SYNTDBRU_b; + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; }; + __IM uint32_t RESERVED11; union { - __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ struct { - __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the threshold for detection of synchronization. */ - } SYNTDBRL_b; + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ struct { - __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 - * bits of the integer portion of the initial value for the - * local timer counter. */ - uint32_t : 16; - } LCIVRU_b; + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; }; union { - __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ struct { - __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the integer portion of the initial value for the local - * timer counter. */ - } LCIVRM_b; + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; }; union { - __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ struct { - __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion - * of the initial value of the local timer counter in nanoseconds. */ - } LCIVRL_b; + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; }; - __IM uint32_t RESERVED7[26]; union { - __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ struct { - __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ - uint32_t : 31; - } GETW10R_b; + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; }; union { - __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ struct { - __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 - * bits of the limit for the positive gradient. */ - uint32_t : 1; - } PLIMITRU_b; + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ union { - __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ struct { - __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 - * bits of the limit for the positive gradient. */ - } PLIMITRM_b; + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ struct { - __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the limit for the positive gradient. */ - } PLIMITRL_b; + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ struct { - __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 - * bits of the limit for the negative gradient. */ - uint32_t : 1; - } MLIMITRU_b; + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ struct { - __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 - * bits of the limit for the negative gradient. */ - } MLIMITRM_b; + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ struct { - __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the limit for the negative gradient. */ - } MLIMITRL_b; + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ struct { - __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching - * is directed, values of various statistical information - * read before completion of information fetching are not - * guaranteed. */ - uint32_t : 31; - } GETINFOR_b; + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; }; - __IM uint32_t RESERVED8[11]; + __IM uint32_t RESERVED5; union { - __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ struct { - __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits - * of the integer portion of the local timer counter's value. */ - uint32_t : 16; - } LCCVRU_b; + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; }; + __IM uint32_t RESERVED6; union { - __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ struct { - __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the integer portion of the local timer counter's value. */ - } LCCVRM_b; + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; }; + __IM uint32_t RESERVED7; union { - __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ struct { - __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of - * the local timer counter's value (in nanoseconds). */ - } LCCVRL_b; + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; }; - __IM uint32_t RESERVED9[37]; + __IM uint32_t RESERVED8; union { - __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ struct { - __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits - * of the positive gradient value. */ - } PW10VRU_b; + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; }; + __IM uint32_t RESERVED9; union { - __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ struct { - __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits - * of the positive gradient value. */ - } PW10VRM_b; + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; }; + __IM uint32_t RESERVED10; union { - __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ struct { - __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the positive gradient value. */ - } PW10VRL_b; + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; }; - __IM uint32_t RESERVED10[45]; + __IM uint32_t RESERVED11[2]; union { - __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ struct { - __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits - * of the negative gradient value. */ - } MW10RU_b; + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; }; union { - __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ struct { - __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits - * of the negative gradient value. */ - } MW10RM_b; + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; }; union { - __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ struct { - __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the negative gradient value. */ - } MW10RL_b; + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; }; - __IM uint32_t RESERVED11[9]; - __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ - __IM uint32_t RESERVED12[7]; union { - __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ struct { - __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ - __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ - __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ - __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ - __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ - __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ - uint32_t : 26; - } TMSTARTR_b; + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; }; - __IM uint32_t RESERVED13[32]; + __IM uint32_t RESERVED12; union { - __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ struct { - __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ - __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ - __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ - __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ - uint32_t : 4; - __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ - uint32_t : 19; - __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ - __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ - uint32_t : 2; - } PRSR_b; + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; }; union { - __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ struct { - __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ - __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ - __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ - __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ - uint32_t : 4; - __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ - uint32_t : 19; - __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ - __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ - uint32_t : 2; - } PRIPR_b; + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; }; - __IM uint32_t RESERVED14[2]; - __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ + __IM uint32_t RESERVED13[18]; union { - __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ struct { - __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ - uint32_t : 30; - } TRNDISR_b; + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; }; - __IM uint32_t RESERVED15[3]; union { - __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ struct { - __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ - uint32_t : 7; - __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ - __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ - uint32_t : 22; - } TRNMR_b; + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; }; + __IM uint32_t RESERVED14; union { - __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ struct { - __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read - * data from the relay FIFO in cut-through mode (specified - * as the number of bytes)NOTE1: A value cannot be set in - * the lower-order 2 bits. These bits are fixed to 0.NOTE2: - * A value of less than 96 bytes cannot be set. */ - uint32_t : 21; - } TRNCTTDR_b; + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; }; -} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ union { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ /* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ +/* ================ R_ETHERC_EPTPC ================ */ /* =========================================================================================================================== */ /** - * @brief Flash Application Command Interface (R_FACI_HP) + * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) */ -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ { - __IM uint32_t RESERVED[4]; - union { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ struct { - __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ - uint8_t : 2; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; + __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ + __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ + uint32_t : 14; + } SYSR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; union { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ struct { - __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; + __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ + __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ + uint32_t : 14; + } SYIPR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; + __IM uint32_t RESERVED[2]; union { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ struct { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; + __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address. */ + uint32_t : 8; + } SYMACRU_b; }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ struct { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is "1". Writing to these bits in FRDY = "0" is ignored. */ - } FSADDR_b; + __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the local MAC address. */ + uint32_t : 8; + } SYMACRL_b; }; union { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ struct { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in "Blank Check" command. These - * bits can be written when FRDY bit of FSTATR register is - * "1". Writing to these bits in FRDY = "0" is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union + __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the + * control field in the LLC sublayer when generating IEEE802.3 + * frames. */ + uint32_t : 24; + } SYLLCCTLR_b; + }; + + union + { + __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + + struct + { + __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ + } SYIPADDRR_b; + }; + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + + struct + { + __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the + * versionPTP field value of the PTP v2 header.When a message + * is received, this value is compared with the versionPTP + * field of the received frame.In generating messages, the + * value is used for the versionPTP field of the frame for + * transmission.Set these bits to 0010b (PTP v2). */ + __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set + * the transportSpecific field value of the PTP v2 header.When + * a message is received, this value is compared with the + * transportSpecific field of the received frame.In generating + * messages, the value is used for the transportSpecific field + * of the frame for transmission.Set these bits to 0000b (IEEE + * 1588). */ + uint32_t : 24; + } SYSPVRR_b; + }; + + union + { + __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + + struct + { + __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to + * set the domainNumber field value of the PTP v2 header.When + * a message is received, this value is compared with the + * domainNumber field of the received frame as a condition + * for PTP reception processing.In generating messages, the + * value is used for the domainNumber field of the frame for + * transmission. */ + uint32_t : 24; + } SYDOMR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + + struct + { + __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the + * leap61 member of timePropertiesDS. */ + __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the + * leap59 member of timePropertiesDS. */ + __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical + * value of the currentUtcOffsetValid member of timePropertiesDS. */ + __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value + * of the ptpTimescale member of timePropertiesDS. */ + __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value + * of the timeTraceable member of timePropertiesDS. */ + __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical + * value of the frequencyTraceable member of timePropertiesDS. */ + uint32_t : 2; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + uint32_t : 1; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } ANFR_b; + }; + + union + { + __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } SYNFR_b; + }; + + union + { + __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRQFR_b; + }; + + union + { + __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRPFR_b; + }; + + union + { + __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of your port. */ + } SYCIDRU_b; + }; + + union + { + __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of your port. */ + } SYCIDRL_b; + }; + + union + { + __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting + * for the port number of the local port. */ + uint32_t : 16; + } SYPNUMR_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + + struct + { + __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ + __OM uint32_t STUP : 1; /*!< [1..1] State Update */ + __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ + uint32_t : 29; + } SYRVLDR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + + struct + { + __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ + __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ + uint32_t : 2; + __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ + __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ + __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ + uint32_t : 1; + __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ + __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ + __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ + uint32_t : 1; + __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ + __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ + __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ + __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ + __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ + uint32_t : 1; + } SYRFL1R_b; + }; + + union + { + __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + + struct + { + __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ + __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ + uint32_t : 2; + __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ + __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ + uint32_t : 22; + __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ + __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ + uint32_t : 2; + } SYRFL2R_b; + }; + + union + { + __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + + struct + { + __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ + uint32_t : 19; + } SYTRENR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of the master clock. */ + } MTCIDU_b; + }; + + union + { + __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of the master clock. */ + } MTCIDL_b; + }; + + union + { + __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the + * setting for the port number of the master clock. */ + uint32_t : 16; + } MTPID_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + + struct + { + __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits + * set the interval for the transmission of Announce messages. */ + __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits + * set the interval for the transmission of Sync messages. + * The setting is also placed in the logMessageInterval field + * of transmitted Sync messages. */ + __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req + * Transmission Interval SettingThe bits set the average interval + * for the transmission of Delay_Req messages and the interval + * for the transmission of Pdelay_Req messages.The setting + * is also placed in the logMessageInterval field of Delay_Resp + * messages. */ + uint32_t : 8; + } SYTLIR_b; + }; + + union + { + __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication + * Register */ + + struct + { + __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Announce message. */ + __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Sync message. */ + __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Delay_Resp message. */ + uint32_t : 8; + } SYRLIR_b; + }; + + union + { + __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated offsetFromMaster value. */ + } OFMRU_b; + }; + + union + { + __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * offsetFromMaster value. */ + } OFMRL_b; + }; + + union + { + __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated meanPathDelay value. */ + } MPDRU_b; + }; + + union + { + __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * meanPathDelay value. */ + } MPDRL_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + + struct + { + __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are + * used to set the value of the grandmasterPriority2 fields + * of Announce messages. */ + uint32_t : 8; + __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits + * are used to set the value of the grandmasterPriority1 fields + * of Announce messages. */ + uint32_t : 8; + } GMPR_b; + }; + + union + { + __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + + struct + { + __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality + * fields of Announce messages. The correspondence between + * bits and the grandmasterClockQuality fields is as listed + * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 + * to b0: offsetScaledLogVariance */ + } GMCQR_b; + }; + + union + { + __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the value of the grandmasterIdentity fields of + * Announce messages. */ + } GMIDRU_b; + }; + + union + { + __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the value of the grandmasterIdentity fields of Announce + * messages. */ + } GMIDRL_b; + }; + + union + { + __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + + struct + { + __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the + * timeSource fields of Announce messages. */ + uint32_t : 8; + __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value + * of the currentUtcOffset fields of Announce messages. */ + } CUOTSR_b; + }; + + union + { + __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + + struct + { + __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value + * of the stepsRemoved fields of Announce messages. */ + uint32_t : 16; + } SRR_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRU_b; + }; + + union + { + __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRL_b; + }; + + union + { + __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRU_b; + }; + + union + { + __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRL_b; + }; + + union + { + __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + + struct + { + __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the + * setting for the EtherType field value for frames in the + * Ethernet II format. */ + uint32_t : 16; + } PETYPER_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPprimary messages. */ + } PPIPR_b; + }; + + union + { + __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPpdelay messages. */ + } PDIPR_b; + }; + + union + { + __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + + struct + { + __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold + * the setting for the value of the TOS field within the IPv4 + * headers of PTP event messages. */ + uint32_t : 24; + } PETOSR_b; + }; + + union + { + __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + + struct + { + __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits + * hold the setting for the value of the TOS field within + * the IPv4 headers of PTP general messages. */ + uint32_t : 24; + } PGTOSR_b; + }; + + union + { + __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + + struct + { + __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits + * hold the setting for the value of the TTL field within + * the IPv4 headers of PTP-primary messages. */ + uint32_t : 24; + } PPTTLR_b; + }; + + union + { + __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + + struct + { + __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the + * setting for the value of the TTL field within the IPv4 + * headers of PTP-pdelay messages. */ + uint32_t : 24; + } PDTTLR_b; + }; + + union + { + __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese + * bits hold the setting for the value of the destination + * port number field within the UDP headers of PTP event messages. */ + uint32_t : 16; + } PEUDPR_b; + }; + + union + { + __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits + * hold the setting for the value of the destination port + * number field within the UDP headers of PTP general messages. */ + uint32_t : 16; + } PGUDPR_b; + }; + + union + { + __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these + * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ + __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0 and ENB=1. */ + __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0. */ + uint32_t : 13; + __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ + uint32_t : 15; + } FFLTR_b; + }; + __IM uint32_t RESERVED10[31]; + + union + { + __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the asymmetric delay value. */ + uint32_t : 16; + } DASYMRU_b; + }; + + union + { + __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the asymmetric delay value. */ + } DASYMRL_b; + }; + + union + { + __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + + struct + { + __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the input + * ports. */ + __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the output + * ports. */ + } TSLATR_b; + }; + + union + { + __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + + struct + { + __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are + * used to set the time from the completion of one transmission + * to the start of the next in cycles of the transmission + * clock. A value n in these bits means that a transmission + * interval of n cycles will be secured.No interval is secured + * if the setting is 00h.We recommend the setting 28h (40 + * cycles). */ + uint32_t : 4; + __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ + uint32_t : 3; + __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ + uint32_t : 3; + __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ + uint32_t : 11; + } SYCONFR_b; + }; + + union + { + __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + + struct + { + __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ + __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ + uint32_t : 30; + } SYFORMR_b; + }; + + union + { + __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + + struct + { + __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response + * message not being received within n x 1024 (ns), where + * n is the setting, is judged to represent a timeout. */ + } RSTOUTR_b; + }; +} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) + */ + +typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ +{ + union + { + __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + + struct + { + __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ + uint32_t : 31; + } PTRSTR_b; + }; + + union + { + __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + + struct + { + __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ + uint32_t : 5; + __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ + uint32_t : 21; + } STCSELR_b; + }; + + union + { + __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + + struct + { + __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ + uint32_t : 15; + __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ + uint32_t : 15; + } BYPASS_b; + }; +} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + */ + +typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +{ + union + { + __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + + struct + { + __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ + __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ + __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ + __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ + uint32_t : 10; + } MIESR_b; + }; + + union + { + __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + + struct + { + __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ + __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ + __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ + __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt + * Request Permission */ + uint32_t : 10; + } MIEIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission + * Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + } ELIPPR_b; + }; + + union + { + __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic + * Clearing Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ + uint32_t : 7; + } ELIPACR_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ + __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ + uint32_t : 27; + } STSR_b; + }; + + union + { + __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ + __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ + uint32_t : 27; + } STIPR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + + struct + { + __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ + uint32_t : 30; + } STCFR_b; + }; + + union + { + __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + + struct + { + __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ + uint32_t : 5; + __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ + uint32_t : 1; + __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ + __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ + __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ + uint32_t : 4; + __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ + __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ + uint32_t : 2; + } STMR_b; + }; + + union + { + __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + + struct + { + __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), + * where n is the setting, leads to a timeout for reception + * of Sync messages, leading to the STSR.SYNTOUT flag being + * set to 1. */ + } SYNTOR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ + __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ + __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ + __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ + __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ + __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ + uint32_t : 26; + } IPTSELR_b; + }; + + union + { + __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ + uint32_t : 26; + } MITSELR_b; + }; + + union + { + __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + + struct + { + __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ + __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ + __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ + __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ + __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ + __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ + uint32_t : 26; + } ELTSELR_b; + }; + + union + { + __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + + struct + { + __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the + * value of this bit while the SYNSTARTR.STR bit is 1. */ + uint32_t : 31; + } STCHSELR_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + + struct + { + __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ + uint32_t : 31; + } SYNSTARTR_b; + }; + + union + { + __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive + * Register */ + + struct + { + __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ + uint32_t : 31; + } LCIVLDR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of loss of synchronization. */ + } SYNTDARU_b; + }; + + union + { + __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of loss of synchronization. */ + } SYNTDARL_b; + }; + + union + { + __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of synchronization. */ + } SYNTDBRU_b; + }; + + union + { + __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of synchronization. */ + } SYNTDBRL_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the integer portion of the initial value for the + * local timer counter. */ + uint32_t : 16; + } LCIVRU_b; + }; + + union + { + __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the integer portion of the initial value for the local + * timer counter. */ + } LCIVRM_b; + }; + + union + { + __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion + * of the initial value of the local timer counter in nanoseconds. */ + } LCIVRL_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + + struct + { + __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ + uint32_t : 31; + } GETW10R_b; + }; + + union + { + __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the positive gradient. */ + uint32_t : 1; + } PLIMITRU_b; + }; + + union + { + __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the positive gradient. */ + } PLIMITRM_b; + }; + + union + { + __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the positive gradient. */ + } PLIMITRL_b; + }; + + union + { + __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the negative gradient. */ + uint32_t : 1; + } MLIMITRU_b; + }; + + union + { + __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the negative gradient. */ + } MLIMITRM_b; + }; + + union + { + __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the negative gradient. */ + } MLIMITRL_b; + }; + + union + { + __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + + struct + { + __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching + * is directed, values of various statistical information + * read before completion of information fetching are not + * guaranteed. */ + uint32_t : 31; + } GETINFOR_b; + }; + __IM uint32_t RESERVED8[11]; + + union + { + __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits + * of the integer portion of the local timer counter's value. */ + uint32_t : 16; + } LCCVRU_b; + }; + + union + { + __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the integer portion of the local timer counter's value. */ + } LCCVRM_b; + }; + + union + { + __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of + * the local timer counter's value (in nanoseconds). */ + } LCCVRL_b; + }; + __IM uint32_t RESERVED9[37]; + + union + { + __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the positive gradient value. */ + } PW10VRU_b; + }; + + union + { + __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the positive gradient value. */ + } PW10VRM_b; + }; + + union + { + __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the positive gradient value. */ + } PW10VRL_b; + }; + __IM uint32_t RESERVED10[45]; + + union + { + __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the negative gradient value. */ + } MW10RU_b; + }; + + union + { + __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the negative gradient value. */ + } MW10RM_b; + }; + + union + { + __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the negative gradient value. */ + } MW10RL_b; + }; + __IM uint32_t RESERVED11[9]; + __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ + __IM uint32_t RESERVED12[7]; + + union + { + __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + + struct + { + __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ + __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ + __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ + __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ + __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ + __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ + uint32_t : 26; + } TMSTARTR_b; + }; + __IM uint32_t RESERVED13[32]; + + union + { + __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ + __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ + uint32_t : 2; + } PRSR_b; + }; + + union + { + __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ + __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ + uint32_t : 2; + } PRIPR_b; + }; + __IM uint32_t RESERVED14[2]; + __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ + + union + { + __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + + struct + { + __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ + uint32_t : 30; + } TRNDISR_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + + struct + { + __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ + uint32_t : 7; + __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ + __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ + uint32_t : 22; + } TRNMR_b; + }; + + union + { + __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + + struct + { + __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read + * data from the relay FIFO in cut-through mode (specified + * as the number of bytes)NOTE1: A value cannot be set in + * the lower-order 2 bits. These bits are fixed to 0.NOTE2: + * A value of less than 96 bytes cannot be set. */ + uint32_t : 21; + } TRNCTTDR_b; + }; +} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is "1". Writing to these bits in FRDY = "0" is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in "Blank Check" command. These + * bits can be written when FRDY bit of FSTATR register is + * "1". Writing to these bits in FRDY = "0" is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in "Blank Check" + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and "Config Clear" + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is "1". + * Writing to this bit in FRDY = "0" is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSUTRIM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CTSU Trimming Registers (R_CTSUTRIM) + */ + +typedef struct /*!< (@ 0x407EC000) R_CTSUTRIM Structure */ +{ + __IM uint32_t RESERVED[233]; + + union + { + __IOM uint32_t CTSUTRIMA; /*!< (@ 0x000003A4) CTSU Trimming Register A */ + + struct + { + __IOM uint32_t RTRIM : 8; /*!< [7..0] CTSU Reference Resistance Adjustment */ + __IOM uint32_t DACTRIM : 8; /*!< [15..8] Linearity Adjustment of Offset Current */ + __IOM uint32_t SUADJD : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (120k) */ + } CTSUTRIMA_b; + }; + + union + { + __IOM uint32_t CTSUTRIMB; /*!< (@ 0x000003A8) CTSU Trimming Register B */ + + struct + { + __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance + * (7.5k) */ + __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance + * (15k) */ + __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance + * (30k) */ + __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (60k) */ + } CTSUTRIMB_b; + }; +} R_CTSUTRIM_Type; /*!< Size = 940 (0x3ac) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ struct { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10[12]; union { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ struct { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + uint32_t : 8; + } GTUPSR_b; }; - __IM uint16_t RESERVED11; union { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ struct { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + uint32_t : 8; + } GTDNSR_b; }; - __IM uint16_t RESERVED12; union { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ struct { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; }; union { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ struct { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is "1". Writing to this bit - * in FRDY = "0" is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is "1". Writing to this bit - * in FRDY = "0" is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; union { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ struct { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is "1". Writing to this bit in FRDY - * = "0" is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[4]; union { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[7]; union { - __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ struct { - __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ - uint16_t : 8; - } FPESTAT_b; + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[3]; union { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; union { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ struct { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; union { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ struct { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in "Blank Check" - * command execution. */ - uint32_t : 13; - } FPSADDR_b; + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; }; union { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ struct { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and "Config Clear" - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; }; union { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ struct { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; }; - __IM uint16_t RESERVED25; union { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ struct { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is "1". - * Writing to this bit in FRDY = "0" is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; }; - __IM uint16_t RESERVED26; union { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ struct { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is "1". Writing to this bit in FRDY - * = "0" is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_LP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_LP) - */ - -typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ -{ - __IM uint32_t RESERVED[36]; - __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[27]; union { - __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ struct { - uint8_t : 1; - __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode - * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash - * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ - uint8_t : 1; - __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ - __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to - * the description of the FMS0 bit. */ - uint8_t : 1; - __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ - __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description - * of the FMS0 bit. */ - } FPMCR_b; + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; union { - __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ struct { - __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ - uint8_t : 7; - } FASR_b; + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; union { - __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ struct { - __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ - } FSARL_b; + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9; union { - __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ struct { - __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ - uint16_t : 4; - __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ - } FSARH_b; + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ struct { - __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ - __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ - uint8_t : 1; - __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ - __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ - } FCR_b; + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; union { - __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ struct { - __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ - } FEARL_b; + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; union { - __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ - - struct - { - __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ - uint32_t : 4; - __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ - uint32_t : 16; - } FEARH_b; + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; }; union { - __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ struct { - __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ - uint32_t : 31; - } FRESETR_b; + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; }; union { - __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ struct { - __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ - __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ - __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ - __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ - __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ - __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ - uint32_t : 26; - } FSTATR00_b; + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; }; union { - __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ struct { - uint32_t : 1; - __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ - uint32_t : 4; - __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ - __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ - uint32_t : 24; - } FSTATR1_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; }; union { - __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ struct { - __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBL0_b; + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; }; - __IM uint32_t RESERVED15; union { - __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ struct { - __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBH0_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; }; union { - __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ struct { - __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ - __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ - uint32_t : 1; - __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ - uint32_t : 28; - } FSTATR01_b; + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; }; union { - __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ struct { - __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBL1_b; + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; }; union { - __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ struct { - __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBH1_b; + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; }; + __IM uint32_t RESERVED[5]; union { - __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ struct { - __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBL1_b; + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; }; union { - __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ struct { - __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBH1_b; + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; }; - __IM uint32_t RESERVED16[12]; + __IM uint32_t RESERVED1[4]; union { - __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ struct { - __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ - uint32_t : 24; - } FPR_b; + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; }; union { - __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ struct { - __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ - uint32_t : 31; - } FPSR_b; + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ union { - __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ struct { - __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBL0_b; + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */ + uint16_t : 7; + } GTDLYCR1_b; }; - __IM uint32_t RESERVED17; union { - __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ struct { - __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBH0_b; + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + uint16_t : 3; + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; }; - __IM uint32_t RESERVED18[11]; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ union { - __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ struct { - uint32_t : 8; - __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ - uint32_t : 5; - __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ - uint32_t : 17; - } FSCMR_b; + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; }; - __IM uint32_t RESERVED19; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - union - { - __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ - uint32_t : 20; - } FAWSMR_b; - }; - __IM uint32_t RESERVED20; +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ union { - __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ - uint32_t : 20; - } FAWEMR_b; + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; }; - __IM uint32_t RESERVED21; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ - union - { - __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ - __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ - uint32_t : 24; - } FISR_b; - }; +/** + * @brief Interrupt Controller Unit (R_ICU) + */ +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ union { - __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ struct { - __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ - uint32_t : 4; - __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ - uint32_t : 24; - } FEXCR_b; + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; }; + __IM uint32_t RESERVED[60]; union { - __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ struct { - __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ - uint32_t : 16; - } FEAML_b; + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; }; - __IM uint32_t RESERVED22; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; union { - __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ struct { - __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ - uint32_t : 16; - } FEAMH_b; + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; }; - __IM uint32_t RESERVED23; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; union { - __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ struct { - __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ - __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ - __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ - __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ - __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ - __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ - uint32_t : 26; - } FSTATR2_b; + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; }; - __IM uint32_t RESERVED24[3951]; - __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ - __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; - __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSUTRIM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CTSU Trimming Registers (R_CTSUTRIM) - */ - -typedef struct /*!< (@ 0x407EC000) R_CTSUTRIM Structure */ -{ - __IM uint32_t RESERVED[233]; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; union { - __IOM uint32_t CTSUTRIMA; /*!< (@ 0x000003A4) CTSU Trimming Register A */ + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ struct { - __IOM uint32_t RTRIM : 8; /*!< [7..0] CTSU Reference Resistance Adjustment */ - __IOM uint32_t DACTRIM : 8; /*!< [15..8] Linearity Adjustment of Offset Current */ - __IOM uint32_t SUADJD : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance - * (120k) */ - } CTSUTRIMA_b; + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t CTSUTRIMB; /*!< (@ 0x000003A8) CTSU Trimming Register B */ + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ struct { - __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance - * (7.5k) */ - __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance - * (15k) */ - __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance - * (30k) */ - __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance - * (60k) */ - } CTSUTRIMB_b; + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; }; -} R_CTSUTRIM_Type; /*!< Size = 940 (0x3ac) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; union { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ struct { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; }; - __IM uint16_t RESERVED1; + __IM uint32_t RESERVED10[22]; union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ - uint16_t : 15; - } FCACHEIV_b; + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; }; - __IM uint16_t RESERVED2[11]; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[31]; union { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ struct { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; + __IM uint32_t RESERVED13[24]; union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; - } FSAR_b; + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_ICU_Type; /*!< Size = 1152 (0x480) */ /* =========================================================================================================================== */ -/* ================ R_GLCDC ================ */ +/* ================ R_IIC0 ================ */ /* =========================================================================================================================== */ /** - * @brief Graphics LCD Controller (R_GLCDC) + * @brief I2C Bus Interface (R_IIC0) */ -typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ { union { - __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR1_CLUT0_b[256]; + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; }; union { - __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR1_CLUT1_b[256]; + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; }; union { - __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR2_CLUT0_b[256]; + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; }; union { - __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR2_CLUT1_b[256]; + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; }; - __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ - __IM uint32_t RESERVED[57]; - __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ - __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ - __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ - __IM uint32_t RESERVED1[6]; - __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ - __IM uint32_t RESERVED2[5]; - __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ -} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ -/** - * @brief General PWM Timer (R_GPT0) - */ + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; -typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ -{ union { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ struct { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; }; union { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ struct { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - uint32_t : 18; - } GTSTR_b; + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; }; union { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ struct { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - uint32_t : 18; - } GTSTP_b; + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; }; union { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ struct { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - uint32_t : 18; - } GTCLR_b; + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; }; union { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ struct { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ struct { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; }; union { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ struct { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - uint32_t : 7; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; }; union { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ struct { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - uint32_t : 8; - } GTUPSR_b; + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; }; + __IM uint8_t RESERVED[2]; union { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ struct { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - uint32_t : 8; - } GTDNSR_b; + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; }; union { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ struct { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; - } GTICASR_b; + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ union { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ struct { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; - } GTICBSR_b; + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ union { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ struct { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 15; - __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ - uint32_t : 4; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - uint32_t : 5; - } GTCR_b; + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - } GTUDDTYC_b; + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief JPEG Codec (R_JPEG) + */ +typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +{ union { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ struct { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - uint32_t : 2; - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - uint32_t : 2; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; + __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ + __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between + * processing for compression and for decompression, be sure + * to reset this module in advance by setting the JCUSRST + * bit in the software reset control register 2 (SWRSTCR2) + * of the power-downmodes. */ + uint8_t : 4; + } JCMOD_b; }; union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ struct { - uint32_t : 24; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; + __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, + * set this bit to 1. Do not write this bit to 1 again while + * this module is in operation. */ + __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped + * state caused by requests to read the image size and pixel + * format (enabled by the INT3 bit in JINTE0), set this bit + * to 1. */ + __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only + * for the interrupt sources corresponding to bits INS6, INS5, + * and INS3 in JINTS0. To clear an interrupt request, set + * this bit to 1 */ + uint8_t : 4; + __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the + * bus reset command should not be issued. */ + } JCCMD_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ struct { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; + __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component + * NOTE: Read-only in Decompression. */ + uint8_t : 2; + } JCQTN_b; }; union { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ struct { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 12; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; + __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: + * Read-only in Decompression. */ + uint8_t : 2; + } JCHTN_b; }; union { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ + __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ struct { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; + __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRIU_b; }; union { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ struct { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; + __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRID_b; }; union { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ struct { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; + __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZU_b; }; union { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ struct { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; + __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZD_b; }; union { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ struct { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; + __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZU_b; }; union { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ + __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ struct { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; + __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZD_b; }; union { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ struct { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; + __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed + * The values of this register are reset before compression + * starts.NOTE: Read-only in Decompression. */ + } JCDTCU_b; }; union { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ + __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ struct { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; + __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts. + * NOTE: Read-only in Decompression. */ + } JCDTCM_b; }; union { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ + __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ struct { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; + __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts.NOTE: + * Read-only in Decompression. */ + } JCDTCD_b; }; union { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ struct { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; + uint8_t : 3; + __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it + * has been determined that the image size and the subsampling + * setting of the compressed data can be read through analyzing + * the data. */ + uint8_t : 1; + __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the + * final number of MCU data in the Huffman-coding segment + * is not correct in decompression. When this bit is not set + * to enable interrupt generation, an error code is not returned. */ + __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the + * total number of data in the Huffman-coding segment is not + * correct in decompression. When this bit is not set to enable + * interrupt generation, an error code is not returned. */ + __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the + * number of data in the restart interval of the Huffman-coding + * segment is not correct in decompression.When this bit is + * not set to enable interrupt generation, an error code is + * not returned. */ + } JINTE0_b; }; union { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ + __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ struct { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; + uint8_t : 3; + __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format + * can be read. When an interrupt occurs, this module stops + * processing and the state is indicated by the JCRST register. + * To make this module resume processing, set the JPEG core + * process stop clear command bit (JRST) in JCCMD. */ + uint8_t : 1; + __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ + __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression + * process normally. */ + uint8_t : 1; + } JINTS0_b; }; union { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ + __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ struct { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; + __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error + * which has occurred in the compressed data analysis for + * decompression. */ + uint8_t : 4; + } JCDERR_b; }; union { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ struct { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; + __IM uint8_t RST : 1; /*!< [0..0] Operating State */ + uint8_t : 7; + } JCRST_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[11]; union { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; + __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ + uint32_t : 1; + __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ + __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the input of image + * data lines is on. Setting this bit to 1 resumes reading + * input image data. This bit is always read as 0. */ + __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data + * Lines This bit is only valid when the count mode for stopping + * the input of image data lines is on. Set this bit before + * writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression + * is swapped. */ + uint32_t : 21; + } JIFECNT_b; }; union { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ struct { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; + __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFESA_b; }; union { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; + __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower + * three bits should be set to 0. */ + uint32_t : 17; + } JIFESOFST_b; }; union { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address + * Register */ struct { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; + __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFEDA_b; }; union { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ + __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count + * Register */ struct { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line + * units) The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFESLC_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ + __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ struct { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; + __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is + * swapped. */ + uint32_t : 1; + __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ + __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the output of image + * data lines is on. Setting this bit to 1 resumes writing + * image data. This bit is always read as 0. */ + __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image + * Data Lines This bit is only valid when the count mode for + * stopping the output of image data lines is on. Set this + * bit before writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression + * is swapped. */ + uint32_t : 1; + __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ + __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only + * when the count mode for stopping the input of coded data + * is on. Setting this bit to 1 resumes reading input coded + * data. This bit is always read as 0. */ + __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed + * This bit is only valid when the count mode for stopping + * the input of coded data is on. Set this bit before writing + * 1 to the data resume command bit. */ + uint32_t : 9; + __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ + __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output + * image data. */ + __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image + * data. */ + uint32_t : 2; + } JIFDCNT_b; }; - __IM uint32_t RESERVED[5]; union { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ + __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ struct { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; + __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source + * Address (in 8-byte units) The lower three bits should be + * set to 0. */ + } JIFDSA_b; }; union { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ struct { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; + __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + uint32_t : 17; + } JIFDDOFST_b; }; - __IM uint32_t RESERVED1[4]; union { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ + __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address + * Register */ struct { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; + __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) + * The lower three bits should be set to 0. */ + } JIFDDA_b; }; union { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ + __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count + * Register */ struct { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - uint32_t : 6; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - uint32_t : 7; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - uint32_t : 7; - } GTSECR_b; + __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) + * The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFDSDC_b; }; -} R_GPT0_Type; /*!< Size = 216 (0xd8) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_ODC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief PWM Delay Generation Circuit (R_GPT_ODC) - */ -typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ -{ union { - __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line + * Count Register */ struct { - __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ - __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ - uint16_t : 6; - __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */ - uint16_t : 7; - } GTDLYCR1_b; + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three + * bits should be set to 0. These bits are read as0.Number + * of input image data lines to be read, in 8-line units. */ + uint32_t : 16; + } JIFDDLC_b; }; union { - __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ struct { - __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ - uint16_t : 4; - __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ - uint16_t : 3; - __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ - uint16_t : 3; - } GTDLYCR2_b; + __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + uint32_t : 24; + } JIFDADT_b; }; - __IM uint16_t RESERVED[10]; - __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ - __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ -} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ + __IM uint32_t RESERVED4[6]; -typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ -{ union { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ struct { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DOUTLF bit in JINTS1 is set to + * 1 */ + __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt + * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ + __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ + uint32_t : 2; + __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ + __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt + * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ + uint32_t : 25; + } JINTE1_b; + }; + + union + { + __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number + * of lines of output image data indicated by JIFDDLC have + * been written. This bit is only valid when the DOUTLC bit + * in JIFDCNT is set to 1. */ + __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data + * indicated by JIFDSDC is read in decompression. This bit + * is valid only when the JINC bit in JIFDCNT is set to 1. */ + __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data + * is written in decompression. */ uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; + __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data + * lines indicated by JIFESLC is read in compression. This + * bit is valid only when the DINLC bit in JIFECNT is set + * to 1. */ + __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data + * is written in compression. */ + uint32_t : 25; + } JINTS1_b; }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED5[27]; + __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ + __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ + __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ + __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ + __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ + __IM uint32_t RESERVED6; + __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[11]; + __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ + __IM uint32_t RESERVED9; + __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ + __IM uint16_t RESERVED10; +} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ /* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ +/* ================ R_KINT ================ */ /* =========================================================================================================================== */ /** - * @brief Port Output Enable for GPT (R_GPT_POEG0) + * @brief Key Interrupt Function (R_KINT) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ + __IM uint8_t RESERVED[3]; -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ union { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ struct { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; }; - __IM uint32_t RESERVED[60]; + __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ struct { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ I3C ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (I3C) + */ +typedef struct /*!< (@ 0x40083000) I3C Structure */ +{ union { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ struct { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; + __IM uint32_t RESERVED[4]; union { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ struct { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ struct { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; + __IM uint32_t RESERVED1; union { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; }; union { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ struct { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; }; - __IM uint32_t RESERVED10[22]; + __IM uint32_t RESERVED2[2]; union { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ struct { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[31]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; }; - __IM uint32_t RESERVED13[24]; union { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ struct { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ -/** - * @brief I2C Bus Interface (R_IIC0) - */ + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; -typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ -{ union { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ struct { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; }; + __IM uint32_t RESERVED4[4]; union { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ struct { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ struct { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; }; union { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ struct { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; }; + __IM uint32_t RESERVED6[2]; union { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ struct { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; }; union { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ struct { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; }; union { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ struct { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; }; union { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ struct { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; }; union { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ struct { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; }; union { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ struct { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ struct { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; }; union { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ struct { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; }; union { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ struct { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; }; + __IM uint32_t RESERVED7[3]; union { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ struct { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ struct { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; }; + __IM uint32_t RESERVED8[2]; union { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ + __IM uint32_t RESERVED9[3]; -/* =========================================================================================================================== */ -/* ================ R_IRDA ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ -/** - * @brief IrDA Interface (R_IRDA) - */ + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED10[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED11[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED12[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED14[10]; -typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ -{ union { - __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ struct { - uint8_t : 2; - __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ - __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ - uint8_t : 3; - __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ - } IRCR_b; + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; }; -} R_IRDA_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ + __IM uint32_t RESERVED15[3]; -typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ -{ union { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ struct { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; union { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ struct { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; }; -} R_IWDT_Type; /*!< Size = 6 (0x6) */ -/* =========================================================================================================================== */ -/* ================ R_JPEG ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ -/** - * @brief JPEG Codec (R_JPEG) - */ + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; -typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ -{ union { - __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ - __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between - * processing for compression and for decompression, be sure - * to reset this module in advance by setting the JCUSRST - * bit in the software reset control register 2 (SWRSTCR2) - * of the power-downmodes. */ - uint8_t : 4; - } JCMOD_b; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; }; union { - __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ struct { - __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, - * set this bit to 1. Do not write this bit to 1 again while - * this module is in operation. */ - __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped - * state caused by requests to read the image size and pixel - * format (enabled by the INT3 bit in JINTE0), set this bit - * to 1. */ - __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only - * for the interrupt sources corresponding to bits INS6, INS5, - * and INS3 in JINTS0. To clear an interrupt request, set - * this bit to 1 */ - uint8_t : 4; - __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the - * bus reset command should not be issued. */ - } JCCMD_b; + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; }; - __IM uint8_t RESERVED; union { - __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ struct { - __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component - * NOTE: Read-only in Decompression. */ - uint8_t : 2; - } JCQTN_b; + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; }; union { - __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ struct { - __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: - * Read-only in Decompression. */ - uint8_t : 2; - } JCHTN_b; + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; }; union { - __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ struct { - __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper - * and lower bytes are set to 00h, neither a DRI nor an RST - * marker is placed.NOTE: Read-only in Decompression. */ - } JCDRIU_b; + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; }; + __IM uint32_t RESERVED16[9]; union { - __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ struct { - __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper - * and lower bytes are set to 00h, neither a DRI nor an RST - * marker is placed.NOTE: Read-only in Decompression. */ - } JCDRID_b; + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; }; + __IM uint32_t RESERVED17[3]; union { - __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ struct { - __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, - * a downloaded value from the JPEG coded data is set. NOTE: - * Read-only in Decompression. */ - } JCVSZU_b; + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; }; + __IM uint32_t RESERVED18; union { - __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ struct { - __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, - * a downloaded value from the JPEG coded data is set. NOTE: - * Read-only in Decompression. */ - } JCVSZD_b; + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; }; + __IM uint32_t RESERVED19; union { - __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ struct { - __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression - * process, a downloaded value from the JPEG coded data is - * set. NOTE: Read-only in Decompression. */ - } JCHSZU_b; + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; }; + __IM uint32_t RESERVED20; union { - __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ struct { - __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression - * process, a downloaded value from the JPEG coded data is - * set. NOTE: Read-only in Decompression. */ - } JCHSZD_b; + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; }; + __IM uint32_t RESERVED21[24]; union { - __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ struct { - __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed - * The values of this register are reset before compression - * starts.NOTE: Read-only in Decompression. */ - } JCDTCU_b; + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; }; + __IM uint32_t RESERVED22[3]; union { - __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 (n + * = 0) */ struct { - __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe - * values of this register are reset before compression starts. - * NOTE: Read-only in Decompression. */ - } JCDTCM_b; + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; }; + __IM uint32_t RESERVED23[7]; union { - __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ struct { - __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe - * values of this register are reset before compression starts.NOTE: - * Read-only in Decompression. */ - } JCDTCD_b; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; }; union { - __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ struct { - uint8_t : 3; - __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it - * has been determined that the image size and the subsampling - * setting of the compressed data can be read through analyzing - * the data. */ - uint8_t : 1; - __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the - * final number of MCU data in the Huffman-coding segment - * is not correct in decompression. When this bit is not set - * to enable interrupt generation, an error code is not returned. */ - __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the - * total number of data in the Huffman-coding segment is not - * correct in decompression. When this bit is not set to enable - * interrupt generation, an error code is not returned. */ - __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the - * number of data in the restart interval of the Huffman-coding - * segment is not correct in decompression.When this bit is - * not set to enable interrupt generation, an error code is - * not returned. */ - } JINTE0_b; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; }; union { - __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ struct { - uint8_t : 3; - __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format - * can be read. When an interrupt occurs, this module stops - * processing and the state is indicated by the JCRST register. - * To make this module resume processing, set the JPEG core - * process stop clear command bit (JRST) in JCCMD. */ - uint8_t : 1; - __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ - __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression - * process normally. */ - uint8_t : 1; - } JINTS0_b; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; }; union { - __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ struct { - __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error - * which has occurred in the compressed data analysis for - * decompression. */ - uint8_t : 4; - } JCDERR_b; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; }; + __IM uint32_t RESERVED24[16]; union { - __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ struct { - __IM uint8_t RST : 1; /*!< [0..0] Operating State */ - uint8_t : 7; - } JCRST_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[11]; + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED25; union { - __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ struct { - __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ - uint32_t : 1; - __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ - __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid - * only when the count mode for stopping the input of image - * data lines is on. Setting this bit to 1 resumes reading - * input image data. This bit is always read as 0. */ - __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data - * Lines This bit is only valid when the count mode for stopping - * the input of image data lines is on. Set this bit before - * writing 1 to the data-line resume command bit. */ - uint32_t : 1; - __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression - * is swapped. */ - uint32_t : 21; - } JIFECNT_b; + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; }; + __IM uint32_t RESERVED26[7]; union { - __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ struct { - __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The - * lower three bits should be set to 0. */ - } JIFESA_b; + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; }; union { - __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ struct { - __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower - * three bits should be set to 0. */ - uint32_t : 17; - } JIFESOFST_b; + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; }; union { - __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address - * Register */ + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ struct { - __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The - * lower three bits should be set to 0. */ - } JIFEDA_b; + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; }; union { - __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count - * Register */ + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ struct { - __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line - * units) The lower three bits should be set to 0. */ - uint32_t : 16; - } JIFESLC_b; + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; }; - __IM uint32_t RESERVED3; union { - __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ struct { - __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is - * swapped. */ - uint32_t : 1; - __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ - __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid - * only when the count mode for stopping the output of image - * data lines is on. Setting this bit to 1 resumes writing - * image data. This bit is always read as 0. */ - __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image - * Data Lines This bit is only valid when the count mode for - * stopping the output of image data lines is on. Set this - * bit before writing 1 to the data-line resume command bit. */ - uint32_t : 1; - __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression - * is swapped. */ - uint32_t : 1; - __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ - __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only - * when the count mode for stopping the input of coded data - * is on. Setting this bit to 1 resumes reading input coded - * data. This bit is always read as 0. */ - __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed - * This bit is only valid when the count mode for stopping - * the input of coded data is on. Set this bit before writing - * 1 to the data resume command bit. */ - uint32_t : 9; - __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ - __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output - * image data. */ - __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image - * data. */ - uint32_t : 2; - } JIFDCNT_b; + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; }; union { - __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ struct { - __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source - * Address (in 8-byte units) The lower three bits should be - * set to 0. */ - } JIFDSA_b; + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device’s current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; }; union { - __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ struct { - __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The - * lower three bits should be set to 0. */ - uint32_t : 17; - } JIFDDOFST_b; + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; }; union { - __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address - * Register */ + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ struct { - __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) - * The lower three bits should be set to 0. */ - } JIFDDA_b; + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + uint32_t : 29; + } CMDSPR_b; }; union { - __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count - * Register */ + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ struct { - __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) - * The lower three bits should be set to 0. */ - uint32_t : 16; - } JIFDSDC_b; + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; }; union { - __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line - * Count Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three - * bits should be set to 0. These bits are read as0.Number - * of input image data lines to be read, in 8-line units. */ - uint32_t : 16; - } JIFDDLC_b; + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; }; + __IM uint32_t RESERVED27[2]; union { - __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ struct { - __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ uint32_t : 24; - } JIFDADT_b; + } BITCNT_b; }; - __IM uint32_t RESERVED4[6]; + __IM uint32_t RESERVED28[4]; union { - __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ struct { - __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DOUTLF bit in JINTS1 is set to - * 1 */ - __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt - * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ - __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ - uint32_t : 2; - __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ - __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt - * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ - uint32_t : 25; - } JINTE1_b; + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; }; union { - __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ struct { - __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number - * of lines of output image data indicated by JIFDDLC have - * been written. This bit is only valid when the DOUTLC bit - * in JIFDCNT is set to 1. */ - __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data - * indicated by JIFDSDC is read in decompression. This bit - * is valid only when the JINC bit in JIFDCNT is set to 1. */ - __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data - * is written in decompression. */ - uint32_t : 2; - __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data - * lines indicated by JIFESLC is read in compression. This - * bit is valid only when the DINLC bit in JIFECNT is set - * to 1. */ - __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data - * is written in compression. */ - uint32_t : 25; - } JINTS1_b; + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; }; - __IM uint32_t RESERVED5[27]; - __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ - __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ - __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ - __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ - __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ - __IM uint32_t RESERVED6; - __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ - __IM uint16_t RESERVED7; - __IM uint32_t RESERVED8[11]; - __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ - __IM uint32_t RESERVED9; - __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ - __IM uint16_t RESERVED10; -} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ - -/* =========================================================================================================================== */ -/* ================ R_KINT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Key Interrupt Function (R_KINT) - */ + __IM uint32_t RESERVED29[9]; -typedef struct /*!< (@ 0x40080000) R_KINT Structure */ -{ union { - __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ struct { - __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ - uint8_t : 6; - __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ - } KRCTL_b; + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED30[2]; union { - __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ struct { - __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ - __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ - __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ - __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ - __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ - __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ - __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ - __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ - } KRF_b; + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; }; - __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ struct { - __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ - __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ - __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ - __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ - __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ - __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ - __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ - __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ - } KRM_b; + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; }; -} R_KINT_Type; /*!< Size = 9 (0x9) */ +} I3C_Type; /*!< Size = 980 (0x3d4) */ /* =========================================================================================================================== */ /* ================ R_MMF ================ */ @@ -12767,7 +15481,7 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] I2C Bus Interface 0 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ uint32_t : 1; __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ @@ -12812,7 +15526,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 13; + uint32_t : 12; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ uint32_t : 2; __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ @@ -13465,13 +16180,13 @@ typedef struct /*!< (@ 0x40040D00) R_PMISC Structure struct { uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ } PWPRS_b; }; __IM uint16_t RESERVED2[5]; - __IOM R_PMISC_PMSAR_Type PMSAR[9]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 34 (0x22) */ + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 34 (0x22) */ /* =========================================================================================================================== */ /* ================ R_QSPI ================ */ @@ -16785,7 +19500,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } OCTACKDIVCR_b; }; - __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + __IM uint8_t RESERVED19; __IM uint32_t RESERVED20; union @@ -16813,7 +19539,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ } OCTACKCR_b; }; - __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + __IM uint8_t RESERVED21; __IM uint32_t RESERVED22[4]; union @@ -21133,6 +23872,381 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ + #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ + #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ + #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + /* =========================================================================================================================== */ /* ================ ELSEGR ================ */ /* =========================================================================================================================== */ @@ -22506,20 +25620,20 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ /* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS1_Pos (15UL) /*!< CFS1 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS1_Msk (0xff8000UL) /*!< CFS1 (Bitfield-Mask: 0x1ff) */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ /* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS2_Pos (10UL) /*!< CFS2 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS2_Msk (0xfffc00UL) /*!< CFS2 (Bitfield-Mask: 0x3fff) */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ /* ======================================================== DFSAMON ======================================================== */ #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ /* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS1_Pos (13UL) /*!< SS1 (Bit 13) */ - #define R_PSCU_SSAMONA_SS1_Msk (0x1fe000UL) /*!< SS1 (Bitfield-Mask: 0xff) */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ /* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS2_Pos (10UL) /*!< SS2 (Bit 10) */ - #define R_PSCU_SSAMONB_SS2_Msk (0x1ffc00UL) /*!< SS2 (Bitfield-Mask: 0x7ff) */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ /* ======================================================== DLMMON ========================================================= */ #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ @@ -23062,6 +26176,620 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ + #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDGCRCCFG ======================================================= */ + #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */ + #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDGLOTB ======================================================== */ + #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ + #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ + #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + /* =========================================================================================================================== */ /* ================ R_CRC ================ */ /* =========================================================================================================================== */ @@ -26796,6 +30524,595 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ +/* =========================================================================================================================== */ +/* ================ I3C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define I3C_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define I3C_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define I3C_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define I3C_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define I3C_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define I3C_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define I3C_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define I3C_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define I3C_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define I3C_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define I3C_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define I3C_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define I3C_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define I3C_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define I3C_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define I3C_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define I3C_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define I3C_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define I3C_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define I3C_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define I3C_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define I3C_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define I3C_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define I3C_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define I3C_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define I3C_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define I3C_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define I3C_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define I3C_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define I3C_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define I3C_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define I3C_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define I3C_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define I3C_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define I3C_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define I3C_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define I3C_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define I3C_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define I3C_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define I3C_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define I3C_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define I3C_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define I3C_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define I3C_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define I3C_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define I3C_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define I3C_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define I3C_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define I3C_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define I3C_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define I3C_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define I3C_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define I3C_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define I3C_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define I3C_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define I3C_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define I3C_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define I3C_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define I3C_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define I3C_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define I3C_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define I3C_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define I3C_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define I3C_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define I3C_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define I3C_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define I3C_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define I3C_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define I3C_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define I3C_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define I3C_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define I3C_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define I3C_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define I3C_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define I3C_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define I3C_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define I3C_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define I3C_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define I3C_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define I3C_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define I3C_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define I3C_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define I3C_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define I3C_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define I3C_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define I3C_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define I3C_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define I3C_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define I3C_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define I3C_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define I3C_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define I3C_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define I3C_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define I3C_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define I3C_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define I3C_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define I3C_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define I3C_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define I3C_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define I3C_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define I3C_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define I3C_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define I3C_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define I3C_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define I3C_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define I3C_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define I3C_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define I3C_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define I3C_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define I3C_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define I3C_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define I3C_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define I3C_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define I3C_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define I3C_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define I3C_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define I3C_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define I3C_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define I3C_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ======================================================== ACKCTL ========================================================= */ + #define I3C_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define I3C_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define I3C_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define I3C_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define I3C_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define I3C_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define I3C_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define I3C_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define I3C_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define I3C_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define I3C_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define I3C_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define I3C_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define I3C_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define I3C_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define I3C_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define I3C_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define I3C_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define I3C_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define I3C_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define I3C_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define I3C_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define I3C_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define I3C_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define I3C_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define I3C_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define I3C_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define I3C_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define I3C_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define I3C_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define I3C_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define I3C_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define I3C_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define I3C_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define I3C_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define I3C_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define I3C_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define I3C_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define I3C_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define I3C_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define I3C_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define I3C_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define I3C_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define I3C_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define I3C_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define I3C_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define I3C_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define I3C_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define I3C_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define I3C_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define I3C_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define I3C_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define I3C_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define I3C_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define I3C_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define I3C_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define I3C_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define I3C_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define I3C_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define I3C_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define I3C_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define I3C_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define I3C_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define I3C_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define I3C_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define I3C_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define I3C_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define I3C_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define I3C_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define I3C_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define I3C_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define I3C_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define I3C_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define I3C_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define I3C_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define I3C_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define I3C_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define I3C_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define I3C_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define I3C_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define I3C_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define I3C_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define I3C_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define I3C_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define I3C_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define I3C_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define I3C_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define I3C_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define I3C_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define I3C_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define I3C_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define I3C_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define I3C_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define I3C_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define I3C_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define I3C_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define I3C_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define I3C_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define I3C_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define I3C_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define I3C_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define I3C_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define I3C_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define I3C_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define I3C_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define I3C_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define I3C_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define I3C_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define I3C_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define I3C_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define I3C_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define I3C_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define I3C_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define I3C_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define I3C_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define I3C_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define I3C_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define I3C_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define I3C_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define I3C_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define I3C_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define I3C_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define I3C_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define I3C_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define I3C_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define I3C_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define I3C_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define I3C_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define I3C_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define I3C_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define I3C_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define I3C_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define I3C_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define I3C_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define I3C_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define I3C_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define I3C_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define I3C_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define I3C_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define I3C_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define I3C_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define I3C_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define I3C_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define I3C_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define I3C_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define I3C_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define I3C_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define I3C_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define I3C_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define I3C_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define I3C_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define I3C_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define I3C_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define I3C_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define I3C_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define I3C_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define I3C_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define I3C_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define I3C_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define I3C_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define I3C_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define I3C_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define I3C_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define I3C_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define I3C_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define I3C_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define I3C_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define I3C_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define I3C_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define I3C_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define I3C_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define I3C_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define I3C_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define I3C_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define I3C_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define I3C_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define I3C_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define I3C_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define I3C_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define I3C_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define I3C_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define I3C_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define I3C_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define I3C_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define I3C_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define I3C_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define I3C_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define I3C_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define I3C_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define I3C_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define I3C_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define I3C_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define I3C_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define I3C_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define I3C_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define I3C_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define I3C_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define I3C_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define I3C_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define I3C_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define I3C_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define I3C_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define I3C_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define I3C_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define I3C_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define I3C_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define I3C_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define I3C_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define I3C_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define I3C_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define I3C_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define I3C_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define I3C_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define I3C_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define I3C_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define I3C_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define I3C_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define I3C_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define I3C_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define I3C_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define I3C_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define I3C_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define I3C_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define I3C_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define I3C_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define I3C_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define I3C_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define I3C_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define I3C_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define I3C_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define I3C_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define I3C_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define I3C_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define I3C_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define I3C_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define I3C_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define I3C_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define I3C_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define I3C_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define I3C_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define I3C_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define I3C_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define I3C_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define I3C_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define I3C_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define I3C_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define I3C_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define I3C_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define I3C_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define I3C_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define I3C_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define I3C_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define I3C_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define I3C_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define I3C_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define I3C_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define I3C_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define I3C_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define I3C_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define I3C_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define I3C_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define I3C_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define I3C_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define I3C_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define I3C_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define I3C_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define I3C_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define I3C_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define I3C_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define I3C_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define I3C_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define I3C_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define I3C_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define I3C_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define I3C_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define I3C_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define I3C_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define I3C_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define I3C_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define I3C_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define I3C_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define I3C_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define I3C_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define I3C_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define I3C_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define I3C_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define I3C_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define I3C_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define I3C_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define I3C_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define I3C_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define I3C_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define I3C_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define I3C_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define I3C_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define I3C_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define I3C_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define I3C_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define I3C_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define I3C_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define I3C_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define I3C_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define I3C_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define I3C_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define I3C_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define I3C_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define I3C_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define I3C_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define I3C_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define I3C_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define I3C_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define I3C_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define I3C_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define I3C_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define I3C_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define I3C_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define I3C_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + /* =========================================================================================================================== */ /* ================ R_MMF ================ */ /* =========================================================================================================================== */ @@ -28624,722 +32941,732 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure /* =========================================================================================================================== */ /* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ /* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ - #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ - #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ - #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ - #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ - #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ /* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ /* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ /* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ /* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ /* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ /* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ /* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ /* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ /* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ /* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ /* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ /* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ /* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ /* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ /* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ /* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ /* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ /* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ /* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ /* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ /* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ /* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ /* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ /* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ /* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ /* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ /* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ /* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ /* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ /* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ /* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ /* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ /* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ /* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ /* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ /* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ /* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ /* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ /* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ /* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ /* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ /* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ /* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ /* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ /* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ /* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ /* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ /* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ /* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ /* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ /* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ /* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ /* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ /* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ /* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ /* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ /* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ /* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ /* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ /* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ /* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ /* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ /* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ /* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ /* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ /* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ /* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ /* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ /* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ /* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ /* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ /* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ /* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ /* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ /* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ /* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ /* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ /* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ /* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ /* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ /* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ - #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ - #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ - #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ - #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ - #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ - #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ - #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ - #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ - #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ - #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ /* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ /* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ /* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ /* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ /* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ /* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ /* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ /* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ /* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_TSN ================ */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd index a7aa2c0b8..2a34b81e6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd @@ -6105,25 +6105,6 @@ - - PSARC26 - CANFD1 and the MSTPCRC.MSTPC26 bit security attribution - 26 - 26 - read-write - - - 0 - Secure - #0 - - - 1 - Non-secure - #1 - - - PSARC27 CANFD0 and the MSTPCRC.MSTPC27 bit security attribution @@ -6794,8 +6775,8 @@ read-only - CFS1 - Code Flash Secure area 1 + CFS2 + Code Flash Secure area 2 15 23 read-only @@ -6810,8 +6791,8 @@ read-only - CFS2 - Code Flash Secure area 2 + CFS1 + Code Flash Secure area 1 10 23 read-only @@ -6842,8 +6823,8 @@ read-only - SS1 - SRAM Secure area 1 + SS2 + SRAM Secure area 2 13 20 read-only @@ -6858,8 +6839,8 @@ read-only - SS2 - SRAM secure area 2 + SS1 + SRAM secure area 1 10 20 read-only @@ -14081,496 +14062,9098 @@ 0x40051000 - R_CRC - Cyclic Redundancy Check (CRC) Calculator - 0x40074000 + R_CANFD + Controller Area Network - Flexible Data (CAN-FD) Module + 0x400B0000 - 0x00000000 - 0x002 + 0x00 + 44 registers - 0x00000004 - 0x00A + 0x84 + 28 registers - - - CRCCR0 - CRC Control Register0 - 0x00 - 8 - read-write - 0x00 - 0xFF - - - DORCLR - CRCDOR Register Clear - 7 - 7 - write-only - - - 0 - No effect. - #0 - - - 1 - Clears the CRCDOR register. - #1 - - - - - LMS - CRC Calculation Switching - 6 - 6 - read-write - - - 0 - Generates CRC for LSB first communication. - #0 - - - 1 - Generates CRC for MSB first communication. - #1 - - - - - GPS - CRC Generating Polynomial Switching - 0 - 2 - read-write - - - 000 - No calculation is executed. - #000 - - - 001 - 8-bit CRC-8 (X8 + X2 + X + 1) - #001 - - - 010 - 16-bit CRC-16 (X16 + X15 + X2 + 1) - #010 - - - 011 - 16-bit CRC-CCITT (X16 + X12 + X5 + 1) - #011 - - - 100 - 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) - #100 - - - 101 - 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) - #101 - - - others - No calculation is executed. - true - - - - - - - CRCCR1 - CRC Control Register1 - 0x01 - 8 - read-write - 0x00 - 0xFF - - - CRCSEN - Snoop enable bit - 7 - 7 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - CRCSWR - Snoop-on-write/read switch bit - 6 - 6 - read-write - - - 0 - Snoop-on-read - #0 - - - 1 - Snoop-on-write - #1 - - - - - - - CRCDIR - CRC Data Input Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRCDIR - Calculation input Data (Case of CRC-32, CRC-32C ) - 0 - 31 - read-write - - - - - CRCDIR_BY - CRC Data Input Register (byte access) - CRCDIR - 0x04 - 8 - read-write - 0x00 - 0xFF - - - CRCDIR_BY - Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) - 0 - 7 - read-write - - - - - CRCDOR - CRC Data Output Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRCDOR - Calculation output Data (Case of CRC-32, CRC-32C ) - 0 - 31 - read-write - - - - - CRCDOR_HA - CRC Data Output Register (halfword access) - CRCDOR - 0x08 - 16 - read-write - 0x0000 - 0xFFFF - - - CRCDOR_HA - Calculation output Data (Case of CRC-16 or CRC-CCITT ) - 0 - 15 - read-write - - - - - CRCDOR_BY - CRC Data Output Register(byte access) - CRCDOR - 0x08 - 8 - read-write - 0x00 - 0xFF - - - CRCDOR_BY - Calculation output Data (Case of CRC-8 ) - 0 - 7 - read-write - - - - - CRCSAR - Snoop Address Register - 0x0C - 16 - read-write - 0x0000 - 0xFFFF - - - CRCSA - snoop address bitSet the I/O register address to snoop - 0 - 13 - read-write - - - 0x0003 - SCI0.TDR - 0x0003 - - - 0x0005 - SCI0.RDR - 0x0005 - - - 0x0023 - SCI1.TDR - 0x0023 - - - 0x0025 - SCI1.RDR - 0x0025 - - - 0x0043 - SCI2.TDR - 0x0043 - - - 0x0045 - SCI2.RDR - 0x0045 - - - 0x0063 - SCI3.TDR - 0x0063 - - - 0x0065 - SCI3.RDR - 0x0065 - - - 0x0083 - SCI4.TDR - 0x0083 - - - 0x0085 - SCI4.RDR - 0x0085 - - - 0x00A3 - SCI5.TDR - 0x00A3 - - - 0x00A5 - SCI5.RDR - 0x00A5 - - - 0x00C3 - SCI6.TDR - 0x00C3 - - - 0x00C5 - SCI6.RDR - 0x00C5 - - - 0x00E3 - SCI7.TDR - 0x00E3 - - - 0x00E5 - SCI7.RDR - 0x00E5 - - - 0x0103 - SCI8.TDR - 0x0103 - - - 0x0105 - SCI8.RDR - 0x0105 - - - 0x0123 - SCI9.TDR - 0x0123 - - - 0x0125 - SCI9.RDR - 0x0125 - - - others - Settings other than above are prohibited. - true - - - - - - - - - R_CTSU - Capacitive Touch Sensing Unit - 0x40081000 - 0x00000000 - 0x01E + 0xAC + 8 registers - - - CTSUCR0 - CTSU Control Register 0 - 0x00 - 8 - read-write - 0x00 - 0xFF - - - CTSUTXVSEL - CTSU Transmission power supply selection - 7 - 7 - read-write - - - 0 - Select Vcc - #0 - - - 1 - Select internal logic power supply - #1 - - - - - CTSUINIT - CTSU Control Block Initialization - 4 - 4 - read-write - - - 0 - Writing a 0 has no effect, this bit is read as 0. - #0 - - - 1 - initializes the CTSU control block and registers. - #1 - - - - - CTSUIOC - CTSU Transmit Pin Control - 3 - 3 - read-write - - - 0 - Low-level output from transmit channel non-measurement pin. - #0 - - - 1 - High-level output from transmit channel non-measurement pin. - #1 - - - - - CTSUSNZ - CTSU Wait State Power-Saving Enable - 2 - 2 - read-write - - - 0 - Power-saving function during wait state is disabled. - #0 - - - 1 - Power-saving function during wait state is enabled. - #1 - - - - - CTSUCAP - CTSU Measurement Operation Start Trigger Select - 1 - 1 - read-write - - - 0 - Software trigger. - #0 - - - 1 - External trigger. - #1 - - - + + 0xC0 + 120 + registers + + + 0x180 + 24 + registers + + + 0x1E0 + 24 + registers + + + 0x240 + 24 + registers + + + 0x2A0 + 40 + registers + + + 0x2D0 + 128 + registers + + + 0x7D0 + 128 + registers + + + 0xCD0 + 16 + registers + + + 0xD70 + 16 + registers + + + 0xE10 + 16 + registers + + + 0xEB0 + 16 + registers + + + 0xF50 + 16 + registers + + + 0x1000 + 8 + registers + + + 0x1020 + 8 + registers + + + 0x1040 + 8 + registers + + + 0x1060 + 8 + registers + + + 0x1080 + 8 + registers + + + 0x10A0 + 8 + registers + + + 0x10C0 + 8 + registers + + + 0x10E0 + 8 + registers + + + 0x1100 + 8 + registers + + + 0x1120 + 8 + registers + + + 0x1140 + 8 + registers + + + 0x1160 + 8 + registers + + + 0x1180 + 12 + registers + + + 0x1190 + 16 + registers + + + 0x1200 + 8 + registers + + + 0x1220 + 8 + registers + + + 0x1240 + 8 + registers + + + 0x1300 + 4 + registers + + + 0x1308 + 8 + registers + + + 0x1314 + 24 + registers + + + 0x1330 + 8 + registers + + + 0x1340 + 8 + registers + + + 0x1350 + 8 + registers + + + 0x1380 + 4 + registers + + + 0x1400 + 92 + registers + + + 0x1800 + 268 + registers + + + 0x8000 + 20 + registers + + + 0x8400 + 256 + registers + + + 0x2000 + 4096 + registers + + + 0x6000 + 1024 + registers + + + 0x6420 + 768 + registers + + + 0x10000 + 8192 + registers + + + + 2 + 0x10 + CFDC[%s] + Channel Control/Status + 0x0000 + + NCFG + Channel Nominal Bitrate Configuration Register + 0x0000 + 32 + read-write + 0x00000000 + 0xffffffff + + + NBRP + Channel Nominal Baud Rate Prescaler + 0 + 9 + read-write + + + NSJW + Resynchronization Jump Width + 10 + 16 + read-write + + + NTSEG1 + Timing Segment 1 + 17 + 24 + read-write + + + NTSEG2 + Timing Segment 2 + 25 + 31 + read-write + + + + + CTR + Channel Control Registers + 0x0004 + 32 + read-write + 0x00000005 + 0xffffffff + + + CHMDC + Channel Mode Control + 0 + 1 + read-write + + + 00 + Channel Operation Mode request + #00 + + + 01 + Channel Reset request + #01 + + + 10 + Channel Halt request + #10 + + + 11 + Keep current value + #11 + + + + + CSLPR + Channel Sleep Request + 2 + 2 + read-write + + + 0 + Channel Sleep Request disabled + #0 + + + 1 + Channel Sleep Request enabled + #1 + + + + + RTBO + Return from Bus-Off + 3 + 3 + read-write + + + 0 + Channel is not forced to return from Bus-Off + #0 + + + 1 + Channel is forced to return from Bus-Off + #1 + + + + + BEIE + Bus Error Interrupt Enable + 8 + 8 + read-write + + + 0 + Bus Error Interrupt disabled + #0 + + + 1 + Bus Error Interrupt enabled + #1 + + + + + EWIE + Error Warning Interrupt Enable + 9 + 9 + read-write + + + 0 + Error Warning Interrupt disabled + #0 + + + 1 + Error Warning Interrupt enabled + #1 + + + + + EPIE + Error Passive Interrupt Enable + 10 + 10 + read-write + + + 0 + Error Passive Interrupt disabled + #0 + + + 1 + Error Passive Interrupt enabled + #1 + + + + + BOEIE + Bus-Off Entry Interrupt Enable + 11 + 11 + read-write + + + 0 + Bus-Off Entry Interrupt disabled + #0 + + + 1 + Bus-Off Entry Interrupt enabled + #1 + + + + + BORIE + Bus-Off Recovery Interrupt Enable + 12 + 12 + read-write + + + 0 + Bus-Off Recovery Interrupt disabled + #0 + + + 1 + Bus-Off Recovery Interrupt enabled + #1 + + + + + OLIE + Overload Interrupt Enable + 13 + 13 + read-write + + + 0 + Overload Interrupt disabled + #0 + + + 1 + Overload Interrupt enabled + #1 + + + + + BLIE + Bus Lock Interrupt Enable + 14 + 14 + read-write + + + 0 + Bus Lock Interrupt disabled + #0 + + + 1 + Bus Lock Interrupt enabled + #1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 15 + 15 + read-write + + + 0 + Arbitration Lost Interrupt disabled + #0 + + + 1 + Arbitration Lost Interrupt enabled + #1 + + + + + TAIE + Transmission abort Interrupt Enable + 16 + 16 + read-write + + + 0 + TX abort Interrupt disabled + #0 + + + 1 + TX abort Interrupt enabled + #1 + + + + + EOCOIE + Error occurrence counter overflow Interrupt enable + 17 + 17 + read-write + + + 0 + Error occurrence counter overflow Interrupt disabled + #0 + + + 1 + Error occurrence counter overflow Interrupt enabled + #1 + + + + + SOCOIE + Successful Occurrence Counter Overflow Interrupt enable + 18 + 18 + read-write + + + 0 + Successful occurrence counter overflow interrupt disabled + #0 + + + 1 + Successful occurrence counter overflow interrupt enabled + #1 + + + + + TDCVFIE + Transceiver Delay Compensation Violation Interrupt enable + 19 + 19 + read-write + + + 0 + Transceiver Delay Compensation Violation Interrupt disabled + #0 + + + 1 + Transceiver Delay Compensation Violation Interrupt enabled + #1 + + + + + BOM + Channel Bus-Off Mode + 21 + 22 + read-write + + + 00 + Normal mode (comply with ISO 11898-1) + #00 + + + 01 + Entry to Halt Mode automatically at Bus-Off start + #01 + + + 10 + Entry to Halt Mode automatically at Bus-Off end + #10 + + + 11 + Entry to Halt Mode (during Bus-Off Recovery Period) by S/W + #11 + + + + + ERRD + Channel Error Display + 23 + 23 + read-write + + + 0 + Only the 1st set of error codes displayed + #0 + + + 1 + Accumulated error codes displayed + #1 + + + + + CTME + Channel Test Mode Enable + 24 + 24 + read-write + + + 0 + Channel Test Mode disabled + #0 + + + 1 + Channel Test Mode enabled + #1 + + + + + CTMS + Channel Test Mode Select + 25 + 26 + read-write + + + 00 + Basic test mode + #00 + + + 01 + Listen-Only mode + #01 + + + 10 + Self test mode 0 (External Loop back mode) + #10 + + + 11 + Self test mode 1 (Internal Loop back mode) + #11 + + + + + TRWE + TEC/REC Write Enable + 27 + 27 + read-write + + + 0 + Error Counter write disabled + #0 + + + 1 + Error Counter write enabled + #1 + + + + + TRH + TEC/REC Hold + 28 + 28 + read-write + + + 0 + Error counter normal operation + #0 + + + 1 + Error counter frozen + #1 + + + + + TRR + TEC/REC Reset + 29 + 29 + read-write + + + 0 + Error counter normal operation + #0 + + + 1 + Error counter reset + #1 + + + + + CRCT + CRC Error Test + 30 + 30 + read-write + + + 0 + First data bit of reception stream not inverted + #0 + + + 1 + First data bit of reception stream inverted + #1 + + + + + ROM + Restricted Operation Mode + 31 + 31 + read-write + + + 0 + Restricted Operation Mode disabled + #0 + + + 1 + Restricted Operation Mode enabled + #1 + + + + + + + STS + Channel Status Registers + 0x0008 + 32 + read-write + 0x00000005 + 0xffffffff + + + CRSTSTS + Channel RESET Status + 0 + 0 + read-only + + + 0 + Channel not in Reset Mode + #0 + + + 1 + Channel in Reset Mode + #1 + + + + + CHLTSTS + Channel HALT Status + 1 + 1 + read-only + + + 0 + Channel not in Halt Mode + #0 + + + 1 + Channel in Halt Mode + #1 + + + + + CSLPSTS + Channel SLEEP Status + 2 + 2 + read-only + + + 0 + Channel not in Sleep Mode + #0 + + + 1 + Channel in Sleep Mode + #1 + + + + + EPSTS + Channel Error Passive Status + 3 + 3 + read-only + + + 0 + Channel not in Error Passive state + #0 + + + 1 + Channel in Error Passive state + #1 + + + + + BOSTS + Channel Bus-Off Status + 4 + 4 + read-only + + + 0 + Channel not in Bus-Off state + #0 + + + 1 + Channel in Bus-Off state + #1 + + + + + TRMSTS + Channel Transmit Status + 5 + 5 + read-only + + + 0 + Channel is not transmitting + #0 + + + 1 + Channel is transmitting + #1 + + + + + RECSTS + Channel Receive Status + 6 + 6 + read-only + + + 0 + Channel is not receiving + #0 + + + 1 + Channel is receiving + #1 + + + + + COMSTS + Channel Communication Status + 7 + 7 + read-only + + + 0 + Channel is not ready for communication + #0 + + + 1 + Channel is ready for communication + #1 + + + + + ESIF + Error State Indication Flag + 8 + 8 + read-write + + + 0 + No CAN-FD message has been received with the ESI flag was set + #0 + + + 1 + At least 1 CAN-FD message was received where the ESI flag was set + #1 + + + + + REC + Reception Error Count + 16 + 23 + read-only + + + TEC + Transmission Error Count + 24 + 31 + read-write + + + + + ERFL + Channel Error Flag Registers + 0x000C + 32 + read-write + 0x00000000 + 0xffffffff + + + BEF + Bus Error Flag + 0 + 0 + read-write + + + 0 + Channel Bus Error not detected + #0 + + + 1 + Channel Bus Error detected + #1 + + + + + EWF + Error Warning Flag + 1 + 1 + read-write + + + 0 + Channel Error Warning not detected + #0 + + + 1 + Channel Error Warning detected + #1 + + + + + EPF + Error Passive Flag + 2 + 2 + read-write + + + 0 + Channel Error Passive not detected + #0 + + + 1 + Channel Error Passive detected + #1 + + + + + BOEF + Bus-Off Entry Flag + 3 + 3 + read-write + + + 0 + Channel Bus-Off Entry not detected + #0 + + + 1 + Channel Bus-Off Entry detected + #1 + + + + + BORF + Bus-Off Recovery Flag + 4 + 4 + read-write + + + 0 + Channel Bus-Off Recovery not detected + #0 + + + 1 + Channel Bus-Off Recovery detected + #1 + + + + + OVLF + Overload Flag + 5 + 5 + read-write + + + 0 + Channel Overload not detected + #0 + + + 1 + Channel Overload detected + #1 + + + + + BLF + Bus Lock Flag + 6 + 6 + read-write + + + 0 + Channel Bus Lock not detected + #0 + + + 1 + Channel Bus Lock detected + #1 + + + + + ALF + Arbitration Lost Flag + 7 + 7 + read-write + + + 0 + Channel Arbitration Lost not detected + #0 + + + 1 + Channel Arbitration Lost detected + #1 + + + + + SERR + Stuff Error + 8 + 8 + read-write + + + 0 + Channel stuff Error not detected + #0 + + + 1 + Channel stuff Error detected + #1 + + + + + FERR + Form Error + 9 + 9 + read-write + + + 0 + Channel Form Error not detected + #0 + + + 1 + Channel Form Error detected + #1 + + + + + AERR + Acknowledge Error + 10 + 10 + read-write + + + 0 + Channel Ack Error not detected + #0 + + + 1 + Channel Ack Error detected + #1 + + + + + CERR + CRC Error + 11 + 11 + read-write + + + 0 + Channel CRC Error not detected + #0 + + + 1 + Channel CRC Error detected + #1 + + + + + B1ERR + Bit 1 Error + 12 + 12 + read-write + + + 0 + Channel Bit 1 Error not detected + #0 + + + 1 + Channel Bit 1 Error detected + #1 + + + + + B0ERR + Bit 0 Error + 13 + 13 + read-write + + + 0 + Channel Bit 0 Error not detected + #0 + + + 1 + Channel Bit 0 Error detected + #1 + + + + + ADERR + Acknowledge Delimiter Error + 14 + 14 + read-write + + + 0 + Channel Ack Del Error not detected + #0 + + + 1 + Channel Ack Del Error detected + #1 + + + + + CRCREG + CRC Register value + 16 + 30 + read-only + + + + + + CFDGCFG + Global Configuration Register + 0x0084 + 32 + read-write + 0x00000000 + 0xffffffff + + + TPRI + Transmission Priority + 0 + 0 + read-write + + + 0 + ID Priority + #0 + + + 1 + Message Buffer Number Priority + #1 + + + + + DCE + DLC Check Enable + 1 + 1 + read-write + + + 0 + DLC check disabled + #0 + + + 1 + DLC check enabled + #1 + + + + + DRE + DLC Replacement Enable + 2 + 2 + read-write + + + 0 + DLC replacement disabled + #0 + + + 1 + DLC replacement enabled + #1 + + + + + MME + Mirror Mode Enable + 3 + 3 + read-write + + + 0 + Mirror Mode disabled + #0 + + + 1 + Mirror Mode enabled + #1 + + + + + DCS + Data Link Controller Clock Select + 4 + 4 + read-write + + + 0 + Internal clean clock + #0 + + + 1 + External Clock source connected to CANMCLK pin + #1 + + + + + CMPOC + CAN-FD message Payload overflow configuration + 5 + 5 + read-write + + + 0 + Message is rejected + #0 + + + 1 + Message payload is cut to fit to configured message size + #1 + + + + + TSP + Timestamp Prescaler + 8 + 11 + read-write + + + TSSS + Timestamp Source Select + 12 + 12 + read-write + + + 0 + Source clock for Timestamp counter is peripheral clock + #0 + + + 1 + Source clock for Timestamp counter is bit time clock + #1 + + + + + TSBTCS + Timestamp Bit Time Channel Select + 13 + 15 + read-write + + + 000 + select clock from Channel 0 + #000 + + + 001 + select clock from Channel 1 + #001 + + + Others + Setting prohibited + true + + + + + ITRCP + Interval Timer Reference Clock Prescaler + 16 + 31 + read-write + + + + + CFDGCTR + Global Control Register + 0x0088 + 32 + read-write + 0x00000005 + 0xffffffff + + + GMDC + Global Mode Control + 0 + 1 + read-write + + + 00 + Global Operation Mode Request + #00 + + + 01 + Global Reset Mode Request + #01 + + + 10 + Global Halt Mode Request + #10 + + + 11 + Keep Current Value + #11 + + + + + GSLPR + Global Sleep Request + 2 + 2 + read-write + + + 0 + Global Sleep Request Disabled + #0 + + + 1 + Global Sleep Request Enabled + #1 + + + + + DEIE + DLC check Interrupt Enable + 8 + 8 + read-write + + + 0 + DLC check Interrupt Disabled + #0 + + + 1 + DLC check Interrupt Enabled + #1 + + + + + MEIE + Message lost Error Interrupt Enable + 9 + 9 + read-write + + + 0 + Message Lost Error Interrupt Disabled + #0 + + + 1 + Message Lost Error Interrupt Enabled + #1 + + + + + THLEIE + TX History List Entry Lost Interrupt Enable + 10 + 10 + read-write + + + 0 + TX History List Entry Lost Interrupt Disabled + #0 + + + 1 + TX History List Entry Lost Interrupt Enabled + #1 + + + + + CMPOFIE + CAN-FD message payload overflow Flag Interrupt enable + 11 + 11 + read-write + + + 0 + CAN-FD message payload overflow Flag Interrupt Disabled + #0 + + + 1 + CAN-FD message payload overflow Flag Interrupt Enabled + #1 + + + + + QMEIE + TXQ Message lost Error Interrupt Enable + 14 + 14 + read-write + + + 0 + TXQ Message Lost Error Interrupt Disabled + #0 + + + 1 + TXQ Message Lost Error Interrupt Enabled + #1 + + + + + MOWEIE + GW FIFO Message overwrite Error Interrupt Enable + 15 + 15 + read-write + + + 0 + GW FIFO Message overwrite Error Interrupt Disabled + #0 + + + 1 + GW FIFO Message overwrite Error Interrupt Enabled + #1 + + + + + TSRST + Timestamp Reset + 16 + 16 + read-write + + + 0 + Timestamp not reset + #0 + + + 1 + Timestamp reset + #1 + + + + + TSWR + Timestamp Write + 17 + 17 + read-write + + + 0 + Timestamp write disabled + #0 + + + 1 + Timestamp write enabled + #1 + + + + + + + CFDGSTS + Global Status Register + 0x008C + 32 + read-write + 0x0000000d + 0xffffffff + + + GRSTSTS + Global Reset Status + 0 + 0 + read-only + + + 0 + Not in Reset Mode + #0 + + + 1 + In Reset Mode + #1 + + + + + GHLTSTS + Global Halt Status + 1 + 1 + read-only + + + 0 + Not in Halt Mode + #0 + + + 1 + In Halt Mode + #1 + + + + + GSLPSTS + Global Sleep Status + 2 + 2 + read-only + + + 0 + Not in Sleep Mode + #0 + + + 1 + In Sleep Mode + #1 + + + + + GRAMINIT + Global RAM Initialisation + 3 + 3 + read-only + + + 0 + RAM initialisation is finished + #0 + + + 1 + RAM initialisation ongoing + #1 + + + + + + + CFDGERFL + Global Error Flag Register + 0x0090 + 32 + read-write + 0x00000000 + 0xffffffff + + + DEF + DLC Error Flag + 0 + 0 + read-write + + + 0 + DLC Error not detected + #0 + + + 1 + DLC Error detected + #1 + + + + + MES + Message Lost Error Status + 1 + 1 + read-only + + + 0 + Message lost Error not detected + #0 + + + 1 + Message lost Error detected + #1 + + + + + THLES + TX History List Entry Lost Error Status + 2 + 2 + read-only + + + 0 + TX History List Entry Lost Error not detected + #0 + + + 1 + TX History List Entry Lost Error detected + #1 + + + + + CMPOF + CAN-FD message payload overflow Flag + 3 + 3 + read-write + + + 0 + CAN-FD message payload overflow not detected + #0 + + + 1 + CAN-FD message payload overflow detected + #1 + + + + + QOWES + TXQ Message overwrite Error Status + 4 + 4 + read-only + + + 0 + TXQ Message overwrite Error not detected + #0 + + + 1 + TXQ Message overwrite Error detected + #1 + + + + + OTBMLTSTS + OTB FIFO Message Lost Status + 5 + 5 + read-only + + + 0 + Message lost Error not detected + #0 + + + 1 + Message lost Error detected + #1 + + + + + QMES + TXQ Message Lost Error Status + 6 + 6 + read-only + + + 0 + TXQ Message lost Error not detected + #0 + + + 1 + TXQ Message lost Error detected + #1 + + + + + RXSFAIL0 + RX Scan Fail of Channel 0 + 8 + 8 + read-write + + + 0 + RX Scan fail not detected + #0 + + + 1 + RX Scan fail detected + #1 + + + + + RXSFAIL1 + RX Scan Fail of Channel 1 + 9 + 9 + read-write + + + 0 + RX Scan fail not detected + #0 + + + 1 + RX Scan fail detected + #1 + + + + + EEF0 + ECC Error Flag for Channel 0 + 16 + 16 + read-write + + + 0 + ECC Error not detected during TX-SCAN + #0 + + + 1 + ECC Error detected during TX-SCAN + #1 + + + + + EEF1 + ECC Error Flag for Channel 1 + 17 + 17 + read-write + + + 0 + ECC Error not detected during TX-SCAN + #0 + + + 1 + ECC Error detected during TX-SCAN + #1 + + + + + + + CFDGTSC + Global Timestamp Counter Register + 0x0094 + 32 + read-write + 0x00000000 + 0xffffffff + + + TS + Timestamp Value + 0 + 15 + read-only + + + + + CFDGAFLECTR + Global Acceptance Filter List Entry Control Register + 0x0098 + 32 + read-write + 0x00000000 + 0xffffffff + + + AFLPN + Acceptance Filter List Page Number + 0 + 3 + read-write + + + AFLDAE + Acceptance Filter List Data Access Enable + 8 + 8 + read-write + + + 0 + Acceptance Filter List Data access disabled + #0 + + + 1 + Acceptance Filter List Data access enabled + #1 + + + + + + + CFDGAFLCFG0 + Global Acceptance Filter List Configuration Register 0 + 0x009C + 32 + read-write + 0x00000000 + 0xffffffff + + + RNC1 + Rule Number for Channel 1 + 0 + 8 + read-write + + + RNC0 + Rule Number for Channel 0 + 16 + 24 + read-write + + + + + CFDRMNB + RX Message Buffer Number Register + 0x00AC + 32 + read-write + 0x00000000 + 0xffffffff + + + NRXMB + Number of RX Message Buffers + 0 + 7 + read-write + + + RMPLS + Reception Message Buffer Payload Data Size + 8 + 10 + read-write + + + 000 + 8 Bytes + #000 + + + 001 + 12 Bytes + #001 + + + 010 + 16 Bytes + #010 + + + 011 + 20 Bytes + #011 + + + 100 + 24 Bytes + #100 + + + 101 + 32 Bytes + #101 + + + 110 + 48 Bytes + #110 + + + 111 + 64 Bytes + #111 + + + + + + + CFDRMND0 + RX Message Buffer New Data Register 0 + 0x00B0 + 32 + read-write + 0x00000000 + 0xffffffff + + + RMNSu + RX Message Buffer New Data Status + 0 + 31 + read-write + + + 0 + New Data not stored in corresponding RX Message Buffer + #0 + + + 1 + New Data stored in corresponding RX Message Buffer + #1 + + + + + + + 8 + 0x04 + CFDRFCC[%s] + RX FIFO Configuration / Control Registers + 0x00C0 + 32 + read-write + 0x00000000 + 0xffffffff + + + RFE + RX FIFO Enable + 0 + 0 + read-write + + + 0 + FIFO disabled + #0 + + + 1 + FIFO enabled + #1 + + + + + RFIE + RX FIFO Interrupt Enable + 1 + 1 + read-write + + + 0 + FIFO Interrupt generation disabled + #0 + + + 1 + FIFO Interrupt generation enabled + #1 + + + + + RFPLS + Rx FIFO Payload Data Size configuration + 4 + 6 + read-write + + + 000 + 8 Bytes + #000 + + + 001 + 12 Bytes + #001 + + + 010 + 16 Bytes + #010 + + + 011 + 20 Bytes + #011 + + + 100 + 24 Bytes + #100 + + + 101 + 32 Bytes + #101 + + + 110 + 48 Bytes + #110 + + + 111 + 64 Bytes + #111 + + + + + RFDC + RX FIFO Depth Configuration + 8 + 10 + read-write + + + 000 + FIFO Depth = 0 Messages + #000 + + + 001 + FIFO Depth = 4 Messages + #001 + + + 010 + FIFO Depth = 8 Messages + #010 + + + 011 + FIFO Depth = 16 Messages + #011 + + + 100 + FIFO Depth = 32 Messages + #100 + + + 101 + FIFO Depth = 48 Messages + #101 + + + 110 + FIFO Depth = 64 Messages + #110 + + + 111 + FIFO Depth = 128 Messages + #111 + + + + + RFIM + RX FIFO Interrupt Mode + 12 + 12 + read-write + + + 0 + Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV + #0 + + + 1 + Interrupt generated at the end of every received message storage + #1 + + + + + RFIGCV + RX FIFO Interrupt Generation Counter Value + 13 + 15 + read-write + + + 000 + Interrupt generated when FIFO is 1/8th Full + #000 + + + 001 + Interrupt generated when FIFO is 1/4th Full + #001 + + + 010 + Interrupt generated when FIFO is 3/8th Full + #010 + + + 011 + Interrupt generated when FIFO is 1/2 Full + #011 + + + 100 + Interrupt generated when FIFO is 5/8th Full + #100 + + + 101 + Interrupt generated when FIFO is 3/4th Full + #101 + + + 110 + Interrupt generated when FIFO is 7/8th Full + #110 + + + 111 + Interrupt generated when FIFO is Full + #111 + + + + + RFFIE + RX FIFO Full interrupt Enable + 16 + 16 + read-write + + + 0 + FIFO Interrupt generation disabled + #0 + + + 1 + FIFO Interrupt generation enabled + #1 + + + + + + + 8 + 0x04 + CFDRFSTS[%s] + RX FIFO Status Registers + 0x00E0 + 32 + read-write + 0x00000001 + 0xffffffff + + + RFEMP + RX FIFO Empty + 0 + 0 + read-only + + + 0 + FIFO Not Empty + #0 + + + 1 + FIFO Empty + #1 + + + + + RFFLL + RX FIFO Full + 1 + 1 + read-only + + + 0 + FIFO Not Full + #0 + + + 1 + FIFO Full + #1 + + + + + RFMLT + RX FIFO Message Lost + 2 + 2 + read-write + + + 0 + No Message Lost in FIFO + #0 + + + 1 + FIFO Message Lost + #1 + + + + + RFIF + RX FIFO Interrupt Flag + 3 + 3 + read-write + + + 0 + FIFO Interrupt condition not satisfied + #0 + + + 1 + FIFO Interrupt condition satisfied + #1 + + + + + RFMC + RX FIFO Message Count + 8 + 15 + read-only + + + RFFIF + RX FIFO Full Interrupt Flag + 16 + 16 + read-write + + + 0 + FIFO Full interrupt condition not satisfied + #0 + + + 1 + FIFO Full interrupt condition satisfied + #1 + + + + + + + 8 + 0x04 + CFDRFPCTR[%s] + RX FIFO Pointer Control Registers + 0x0100 + 32 + read-write + 0x00000000 + 0xffffffff + + + RFPC + RX FIFO Pointer Control + 0 + 7 + write-only + + + + + 6 + 0x04 + CFDCFCC[%s] + Common FIFO Configuration / Control Registers + 0x0120 + 32 + read-write + 0x00000000 + 0xffffffff + + + CFE + Common FIFO Enable + 0 + 0 + read-write + + + 0 + FIFO disabled + #0 + + + 1 + FIFO enabled + #1 + + + + + CFRXIE + Common FIFO RX Interrupt Enable + 1 + 1 + read-write + + + 0 + FIFO Interrupt generation disabled for Frame RX + #0 + + + 1 + FIFO Interrupt generation enabled for Frame RX + #1 + + + + + CFTXIE + Common FIFO TX Interrupt Enable + 2 + 2 + read-write + + + 0 + FIFO Interrupt generation disabled for Frame TX + #0 + + + 1 + FIFO Interrupt generation enabled for Frame TX + #1 + + + + + CFPLS + Common FIFO Payload Data size configuration + 4 + 6 + read-write + + + 000 + 8 bytes + #000 + + + 001 + 12 bytes + #001 + + + 010 + 16 bytes + #010 + + + 011 + 20 bytes + #011 + + + 100 + 24 bytes + #100 + + + 101 + 32 bytes + #101 + + + 110 + 48 bytes + #110 + + + 111 + 64 bytes + #111 + + + + + CFM + Common FIFO Mode + 8 + 9 + read-write + + + 00 + RX FIFO Mode + #00 + + + 01 + TX FIFO Mode + #01 + + + 10 + CAN - CAN GW FIFO Mode + #10 + + + 11 + Reserved + #11 + + + + + CFITSS + Common FIFO Interval Timer Source Select + 10 + 10 + read-write + + + 0 + Reference Clock (x1 / x10 period) + #0 + + + 1 + Bit Time Clock of related channel (FIFO is linked to fixed channel) + #1 + + + + + CFITR + Common FIFO Interval Timer Resolution + 11 + 11 + read-write + + + 0 + Reference Clock Period x1 + #0 + + + 1 + Reference Clock Period x10 + #1 + + + + + CFIM + Common FIFO Interrupt Mode + 12 + 12 + read-write + + + 0 + RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value +TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully +GW FIFO Mode: + For RX interrupt flag: + Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV + For TX interrupt flag: + Interrupt generated when FIFO transmits the last message successfully + + #0 + + + 1 + RX FIFO Mode: RX Interrupt generated at the end of every received message storage +TX FIFO Mode: Interrupt generated for every successfully transmitted message +GW FIFO Mode: + For RX interrupt flag: + Interrupt generated when a message is stored in the FIFO + For TX interrupt flag: + Interrupt generated when a message is successfully transmitted from the FIFO + + #1 + + + + + CFIGCV + Common FIFO Interrupt Generation Counter Value + 13 + 15 + read-write + + + 000 + Interrupt generated when FIFO is 1/8th Full + #000 + + + 001 + Interrupt generated when FIFO is 1/4th Full + #001 + + + 010 + Interrupt generated when FIFO is 3/8th Full + #010 + + + 011 + Interrupt generated when FIFO is 1/2 Full + #011 + + + 100 + Interrupt generated when FIFO is 5/8th Full + #100 + + + 101 + Interrupt generated when FIFO is 3/4th Full + #101 + + + 110 + Interrupt generated when FIFO is 7/8th Full + #110 + + + 111 + Interrupt generated when FIFO is Full + #111 + + + + + CFTML + Common FIFO TX Message Buffer Link + 16 + 20 + read-write + + + CFDC + Common FIFO Depth Configuration + 21 + 23 + read-write + + + 000 + FIFO Depth = 0 Messages + #000 + + + 001 + FIFO Depth = 4 Messages + #001 + + + 010 + FIFO Depth = 8 Messages + #010 + + + 011 + FIFO Depth = 16 Messages + #011 + + + 100 + FIFO Depth = 32 Messages + #100 + + + 101 + FIFO Depth = 48 Messages + #101 + + + 110 + FIFO Depth = 64 Messages + #110 + + + 111 + FIFO Depth = 128 Messages + #111 + + + + + CFITT + Common FIFO Interval Transmission Time + 24 + 31 + read-write + + + + + 6 + 0x04 + CFDCFCCE[%s] + Common FIFO Configuration / Control Enhancement Registers + 0x0180 + 32 + read-write + 0x00000000 + 0xffffffff + + + CFFIE + Common FIFO Full interrupt Enable + 0 + 0 + read-write + + + 0 + FIFO Interrupt generation disabled + #0 + + + 1 + FIFO Interrupt generation enabled + #1 + + + + + CFOFRXIE + Common FIFO One Frame Reception Interrupt Enable + 1 + 1 + read-write + + + 0 + One Frame RX Interrupt generation disabled + #0 + + + 1 + One Frame RX Interrupt generation enabled + #1 + + + + + CFOFTXIE + Common FIFO One Frame Transmission Interrupt Enable + 2 + 2 + read-write + + + 0 + One Frame TX Interrupt generation disabled + #0 + + + 1 + One Frame TX Interrupt generation enabled + #1 + + + + + CFMOWM + Common FIFO message overwrite mode + 8 + 8 + read-write + + + 0 + Message discarded mode + #0 + + + 1 + Message overwrite mode + #1 + + + + + CFBME + Common FIFO Buffering Mode Enable + 16 + 16 + read-write + + + 0 + Transmission from Common FIFO + #0 + + + 1 + Transmission halt from Common FIFO + #1 + + + + + + + 6 + 0x04 + CFDCFSTS[%s] + Common FIFO Status Registers + 0x01E0 + 32 + read-write + 0x00000001 + 0xffffffff + + + CFEMP + Common FIFO Empty + 0 + 0 + read-only + + + 0 + FIFO Not Empty + #0 + + + 1 + FIFO Empty + #1 + + + + + CFFLL + Common FIFO Full + 1 + 1 + read-only + + + 0 + FIFO Not Full + #0 + + + 1 + FIFO Full + #1 + + + + + CFMLT + Common FIFO Message Lost + 2 + 2 + read-write + + + 0 + No Message Lost in FIFO + #0 + + + 1 + FIFO Message Lost + #1 + + + + + CFRXIF + Common RX FIFO Interrupt Flag + 3 + 3 + read-write + + + 0 + FIFO Interrupt condition not satisfied after Frame Reception + #0 + + + 1 + FIFO Interrupt condition satisfied after Frame Reception + #1 + + + + + CFTXIF + Common TX FIFO Interrupt Flag + 4 + 4 + read-write + + + 0 + FIFO Interrupt condition not satisfied after Frame Transmission + #0 + + + 1 + FIFO Interrupt condition satisfied after Frame Transmission + #1 + + + + + CFMC + Common FIFO Message Count + 8 + 15 + read-only + + + CFFIF + Common FIFO Full Interrupt Flag + 16 + 16 + read-write + + + 0 + Interrupt condition not satisfied for FIFO Full interrupt + #0 + + + 1 + Interrupt condition satisfied for FIFO Full interrupt + #1 + + + + + CFOFRXIF + Common FIFO One Frame Reception Interrupt Flag + 17 + 17 + read-write + + + CFOFTXIF + Common FIFO One Frame Transmission Interrupt Flag + 18 + 18 + read-write + + + CFMOW + Common FIFO message overwrite + 24 + 24 + read-write + + + 0 + No Message overwrite occurred in FIFO + #0 + + + 1 + Message overwrite occurred in FIFO + #1 + + + + + + + 6 + 0x04 + CFDCFPCTR[%s] + Common FIFO Pointer Control Registers + 0x0240 + 32 + read-write + 0x00000000 + 0xffffffff + + + CFPC + Common FIFO Pointer Control + 0 + 7 + write-only + + + + + CFDFESTS + FIFO Empty Status Register + 0x02A0 + 32 + read-only + 0x00003fff + 0xffffffff + + + RFXEMP + RX FIF0 Empty Status + 0 + 7 + read-only + + + 0 + Corresponding FIFO not Empty + #0 + + + 1 + Corresponding FIFO Empty + #1 + + + + + CFXEMP + Common FIF0 Empty Status + 8 + 13 + read-only + + + 0 + Corresponding FIFO not Empty + #0 + + + 1 + Corresponding FIFO Empty + #1 + + + + + + + CFDFFSTS + FIFO Full Status Register + 0x02A4 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFXFLL + RX FIF0 Full Status + 0 + 7 + read-only + + + 0 + Corresponding FIFO not Full + #0 + + + 1 + Corresponding FIFO Full + #1 + + + + + CFXFLL + Common FIF0 Full Status + 8 + 13 + read-only + + + 0 + Corresponding FIFO not Full + #0 + + + 1 + Corresponding FIFO Full + #1 + + + + + + + CFDFMSTS + FIFO Message Lost Status Register + 0x02A8 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFXMLT + RX FIFO Msg Lost Status + 0 + 7 + read-only + + + 0 + Corresponding FIFO Msg Lost flag not set + #0 + + + 1 + Corresponding FIFO Msg Lost flag set + #1 + + + + + CFXMLT + Common FIFO Msg Lost Status + 8 + 13 + read-only + + + 0 + Corresponding FIFO Msg Lost flag not set + #0 + + + 1 + Corresponding FIFO Msg Lost flag set + #1 + + + + + + + CFDRFISTS + RX FIFO Interrupt Flag Status Register + 0x02AC + 32 + read-write + 0x00000000 + 0xffffffff + + + RFXIF + RX FIFO[x] Interrupt Flag Status + 0 + 7 + read-only + + + 0 + Corresponding RX FIFO interrupt flag not set + #0 + + + 1 + Corresponding RX FIFO interrupt flag set + #1 + + + + + RFXFFLL + RX FIFO[x] Interrupt Full Flag Status + 16 + 23 + read-only + + + 0 + Corresponding RX FIFO interrupt Full flag not set + #0 + + + 1 + Corresponding RX FIFO interrupt Full flag set + #1 + + + + + + + CFDCFRISTS + Common FIFO RX Interrupt Flag Status Register + 0x02B0 + 32 + read-write + 0x00000000 + 0xffffffff + + + CFXRXIF + Common FIFO [x] RX Interrupt Flag Status + 0 + 5 + read-only + + + 0 + Corresponding Common FIFO RX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO RX interrupt flag is set + #1 + + + + + + + CFDCFTISTS + Common FIFO TX Interrupt Flag Status Register + 0x02B4 + 32 + read-write + 0x00000000 + 0xffffffff + + + CFXTXIF + Common FIFO [x] TX Interrupt Flag Status + 0 + 5 + read-only + + + 0 + Corresponding Common FIFO TX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO TX interrupt flag is set + #1 + + + + + + + CFDCFOFRISTS + Common FIFO One Frame RX Interrupt Flag Status Register + 0x02B8 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFXOFRXIF + Common FIFO [x] One Frame RX Interrupt Flag Status + 0 + 5 + read-only + + + 0 + Corresponding Common FIFO One Frame RX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO One Frame RX interrupt flag is set + #1 + + + + + + + CFDCFOFTISTS + Common FIFO One Frame TX Interrupt Flag Status Register + 0x02BC + 32 + read-only + 0x00000000 + 0xffffffff + + + CFXOFTXIF + Common FIFO [x] One Frame TX Interrupt Flag Status + 0 + 5 + read-only + + + 0 + Corresponding Common FIFO One Frame TX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO One Frame TX interrupt flag is set + #1 + + + + + + + CFDCFMOWSTS + Common FIFO Message Over Write Status Register + 0x02C0 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFXMOW + Common FIFO [x] Massage overwrite status + 0 + 5 + read-only + + + 0 + Corresponding FIFO overwrite flag is not set + #0 + + + 1 + Corresponding FIFO overwrite flag is set + #1 + + + + + + + CFDFFFSTS + FIFO FDC Full Status Register + 0x02C4 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFXFFLL + RX FIFO FDC level full Status + 0 + 7 + read-only + + + 0 + Corresponding FIFO Full interrupt not set + #0 + + + 1 + Corresponding FIFO Full interrupt is set + #1 + + + + + CFXFFLL + COMMON FIFO FDC level full Status + 8 + 13 + read-only + + + 0 + Corresponding FIFO Full interrupt not set + #0 + + + 1 + Corresponding FIFO Full interrupt is set + #1 + + + + + + + 128 + 0x01 + CFDTMC[%s] + TX Message Buffer Control Registers + 0x02D0 + 8 + read-write + 0x00 + 0xff + + + TMTR + TX Message Buffer Transmission Request + 0 + 0 + read-write + + + 0 + TX Message Buffer Transmission not requested + #0 + + + 1 + TX Message Buffer Transmission requested + #1 + + + + + TMTAR + TX Message Buffer Transmission abort Request + 1 + 1 + read-write + + + 0 + TX Message Buffer transmission request abort not requested + #0 + + + 1 + TX Message Buffer transmission request abort requested + #1 + + + + + TMOM + TX Message Buffer One-shot Mode + 2 + 2 + read-write + + + 0 + TX Message Buffer not configured in one-shot mode + #0 + + + 1 + TX Message Buffer configured in one-shot mode + #1 + + + + + + + 128 + 0x01 + CFDTMSTS[%s] + TX Message Buffer Status Registers + 0x07D0 + 8 + read-write + 0x00 + 0xff + + + TMTSTS + TX Message Buffer Transmission Status + 0 + 0 + read-only + + + 0 + No transmission ongoing + #0 + + + 1 + Transmission ongoing + #1 + + + + + TMTRF + TX Message Buffer Transmission Result Flag + 1 + 2 + read-write + + + 00 + No Result + #00 + + + 01 + Transmission aborted from the TX MB + #01 + + + 10 + Transmission successful from the TX MB & Transmission abort was not requested + #10 + + + 11 + Transmission successful from the TX MB & Transmission abort was requested + #11 + + + + + TMTRM + TX Message Buffer Transmission Request Mirrored + 3 + 3 + read-only + + + 0 + TX Message Buffer Transmission not requested + #0 + + + 1 + TX Message Buffer Transmission requested + #1 + + + + + TMTARM + TX Message Buffer Transmission abort Request Mirrored + 4 + 4 + read-only + + + 0 + TX Message Buffer transmission request abort not requested + #0 + + + 1 + TX Message Buffer transmission request abort requested + #1 + + + + + + + 4 + 0x04 + CFDTMTRSTS[%s] + TX Message Buffer Transmission Request Status Register + 0x0CD0 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFDTMTRSTSg + TX Message Buffer Transmission Request Status + 0 + 7 + read-only + + + 0 + Transmission not requested for corresponding TX Message Buffer + #0 + + + 1 + Transmission requested for corresponding TX Message Buffer + #1 + + + + + + + 4 + 0x04 + CFDTMTARSTS[%s] + TX Message Buffer Transmission Abort Request Status Register + 0x0D70 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFDTMTARSTSg + TX Message Buffer Transmission abort Request Status + 0 + 7 + read-only + + + 0 + Transmission abort not requested for corresponding TX Message Buffer + #0 + + + 1 + Transmission abort requested for corresponding TX Message Buffer + #1 + + + + + + + 4 + 0x04 + CFDTMTCSTS[%s] + TX Message Buffer Transmission Completion Status Register + 0x0E10 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFDTMTCSTSg + TX Message Buffer Transmission Completion Status + 0 + 7 + read-only + + + 0 + Transmission not complete for corresponding TX Message Buffer + #0 + + + 1 + Transmission completed for corresponding TX Message Buffer + #1 + + + + + + + 4 + 0x04 + CFDTMTASTS[%s] + TX Message Buffer Transmission Abort Status Register + 0x0EB0 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFDTMTASTSg + TX Message Buffer Transmission abort Status + 0 + 7 + read-only + + + 0 + Transmission not aborted for corresponding TX Message Buffer + #0 + + + 1 + Transmission aborted for corresponding TX Message Buffer + #1 + + + + + + + 4 + 0x04 + CFDTMIEC[%s] + TX Message Buffer Interrupt Enable Configuration Register + 0x0F50 + 32 + read-write + 0x00000000 + 0xffffffff + + + TMIEg + TX Message Buffer Interrupt Enable + 0 + 7 + read-write + + + 0 + TX Message Buffer Interrupt disabled for corresponding TX message buffer + #0 + + + 1 + TX Message Buffer Interrupt enabled for corresponding TX message buffer + #1 + + + + + + + 2 + 0x04 + CFDTXQCC0[%s] + TX Queue Configuration / Control Registers 0 + 0x1000 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQE + TX Queue Enable + 0 + 0 + read-write + + + 0 + TX Queue disabled + #0 + + + 1 + TX Queue enabled + #1 + + + + + TXQGWE + TX Queue Gateway Mode Enable + 1 + 1 + read-write + + + 0 + TX Queue GW mode disabled + #0 + + + 1 + TX Queue GW mode enabled + #1 + + + + + TXQTXIE + TX Queue TX Interrupt Enable + 5 + 5 + read-write + + + 0 + TX Queue TX Interrupt disabled + #0 + + + 1 + TX Queue TX Interrupt enabled + #1 + + + + + TXQIM + TX Queue Interrupt Mode + 7 + 7 + read-write + + + 0 + When the last message is successfully transmitted + #0 + + + 1 + At every successful transmission + #1 + + + + + TXQDC + TX Queue Depth Configuration + 8 + 12 + read-write + + + TXQFIE + TXQ Full interrupt Enable + 16 + 16 + read-write + + + 0 + TX Queue Full Interrupt generation disabled + #0 + + + 1 + TX Queue Full Interrupt generation enabled + #1 + + + + + TXQOFRXIE + TXQ One Frame Reception Interrupt Enable + 17 + 17 + read-write + + + 0 + One Frame RX Interrupt generation disabled + #0 + + + 1 + One Frame RX Interrupt generation enabled + #1 + + + + + TXQOFTXIE + TXQ One Frame Transmission Interrupt Enable + 18 + 18 + read-write + + + 0 + One Frame TX Interrupt generation disabled + #0 + + + 1 + One Frame TX Interrupt generation enabled + #1 + + + + + + + 2 + 0x04 + CFDTXQSTS0[%s] + TX Queue Status Registers 0 + 0x1020 + 32 + read-write + 0x00000001 + 0xffffffff + + + TXQEMP + TX Queue Empty + 0 + 0 + read-only + + + 0 + TX Queue Not Empty + #0 + + + 1 + TX Queue Empty + #1 + + + + + TXQFLL + TX Queue Full + 1 + 1 + read-only + + + 0 + TX Queue Not Full + #0 + + + 1 + TX Queue Full + #1 + + + + + TXQTXIF + TX Queue TX Interrupt Flag + 2 + 2 + read-write + + + 0 + TX Queue interrupt condition not satisfied after Frame TX + #0 + + + 1 + TX Queue interrupt condition satisfied after Frame TX + #1 + + + + + TXQMC + TX Queue Message Count + 8 + 13 + read-only + + + TXQFIF + TXQ Full Interrupt Flag + 16 + 16 + read-write + + + TXQOFRXIF + TXQ One Frame Reception Interrupt Flag + 17 + 17 + read-write + + + TXQOFTXIF + TXQ One Frame Transmission Interrupt Flag + 18 + 18 + read-write + + + TXQMLT + TXQ Message Lost + 19 + 19 + read-write + + + 0 + No Message Lost in TXQ + #0 + + + 1 + TXQ Message Lost + #1 + + + + + + + 2 + 0x04 + CFDTXQPCTR0[%s] + TX Queue Pointer Control Registers 0 + 0x1040 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQPC + TX Queue Pointer Control + 0 + 7 + write-only + + + + + 2 + 0x04 + CFDTXQCC1[%s] + TX Queue Configuration / Control Registers 1 + 0x1060 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQE + TX Queue Enable + 0 + 0 + read-write + + + 0 + TX Queue disabled + #0 + + + 1 + TX Queue enabled + #1 + + + + + TXQGWE + TX Queue Gateway Mode Enable + 1 + 1 + read-write + + + 0 + TX Queue GW mode disabled + #0 + + + 1 + TX Queue GW mode enabled + #1 + + + + + TXQTXIE + TX Queue TX Interrupt Enable + 5 + 5 + read-write + + + 0 + TX Queue TX Interrupt disabled + #0 + + + 1 + TX Queue TX Interrupt enabled + #1 + + + + + TXQIM + TX Queue Interrupt Mode + 7 + 7 + read-write + + + 0 + When the last message is successfully transmitted + #0 + + + 1 + At every successful transmission + #1 + + + + + TXQDC + TX Queue Depth Configuration + 8 + 12 + read-write + + + TXQFIE + TXQ Full Interrupt Enable + 16 + 16 + read-write + + + 0 + TX Queue Full Interrupt generation disabled + #0 + + + 1 + TX Queue Full Interrupt generation enabled + #1 + + + + + TXQOFRXIE + TXQ One Frame Reception Interrupt Enable + 17 + 17 + read-write + + + 0 + One Frame RX Interrupt generation disabled + #0 + + + 1 + One Frame RX Interrupt generation enabled + #1 + + + + + TXQOFTXIE + TXQ One Frame Transmission Interrupt Enable + 18 + 18 + read-write + + + 0 + One Frame TX Interrupt generation disabled + #0 + + + 1 + One Frame TX Interrupt generation enabled + #1 + + + + + + + 2 + 0x04 + CFDTXQSTS1[%s] + TX Queue Status Registers 1 + 0x1080 + 32 + read-write + 0x00000001 + 0xffffffff + + + TXQEMP + TX Queue Empty + 0 + 0 + read-only + + + 0 + TX Queue Not Empty + #0 + + + 1 + TX Queue Empty + #1 + + + + + TXQFLL + TX Queue Full + 1 + 1 + read-only + + + 0 + TX Queue Not Full + #0 + + + 1 + TX Queue Full + #1 + + + + + TXQTXIF + TX Queue TX Interrupt Flag + 2 + 2 + read-write + + + 0 + TX Queue interrupt condition not satisfied after Frame TX + #0 + + + 1 + TX Queue interrupt condition satisfied after Frame TX + #1 + + + + + TXQMC + TX Queue Message Count + 8 + 13 + read-only + + + TXQFIF + TXQ Full Interrupt Flag + 16 + 16 + read-write + + + TXQOFRXIF + TXQ One Frame Reception Interrupt Flag + 17 + 17 + read-write + + + TXQOFTXIF + TXQ One Frame Transmission Interrupt Flag + 18 + 18 + read-write + + + TXQMLT + TXQ Message Lost + 19 + 19 + read-write + + + 0 + No Message Lost in TXQ + #0 + + + 1 + TXQ Message Lost + #1 + + + + + + + 2 + 0x04 + CFDTXQPCTR1[%s] + TX Queue Pointer Control Registers 1 + 0x10A0 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQPC + TX Queue Pointer Control + 0 + 7 + write-only + + + + + 2 + 0x04 + CFDTXQCC2[%s] + TX Queue Configuration / Control Registers 2 + 0x10C0 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQE + TX Queue Enable + 0 + 0 + read-write + + + 0 + TX Queue disabled + #0 + + + 1 + TX Queue enabled + #1 + + + + + TXQGWE + TX Queue Gateway Mode Enable + 1 + 1 + read-write + + + 0 + TX Queue GW mode disabled + #0 + + + 1 + TX Queue GW mode enabled + #1 + + + + + TXQTXIE + TX Queue TX Interrupt Enable + 5 + 5 + read-write + + + 0 + TX Queue TX Interrupt disabled + #0 + + + 1 + TX Queue TX Interrupt enabled + #1 + + + + + TXQIM + TX Queue Interrupt Mode + 7 + 7 + read-write + + + 0 + When the last message is successfully transmitted + #0 + + + 1 + At every successful transmission + #1 + + + + + TXQDC + TX Queue Depth Configuration + 8 + 12 + read-write + + + TXQFIE + TXQ Full interrupt Enable + 16 + 16 + read-write + + + 0 + TX Queue Full Interrupt generation disabled + #0 + + + 1 + TX Queue Full Interrupt generation enabled + #1 + + + + + TXQOFRXIE + TXQ One Frame Reception Interrupt Enable + 17 + 17 + read-write + + + 0 + One Frame RX Interrupt generation disabled + #0 + + + 1 + One Frame RX Interrupt generation enabled + #1 + + + + + TXQOFTXIE + TXQ One Frame Transmission Interrupt Enable + 18 + 18 + read-write + + + 0 + One Frame TX Interrupt generation disabled + #0 + + + 1 + One Frame TX Interrupt generation enabled + #1 + + + + + + + 2 + 0x04 + CFDTXQSTS2[%s] + TX Queue Status Registers 2 + 0x10E0 + 32 + read-write + 0x00000001 + 0xffffffff + + + TXQEMP + TX Queue Empty + 0 + 0 + read-only + + + 0 + TX Queue Not Empty + #0 + + + 1 + TX Queue Empty + #1 + + + + + TXQFLL + TX Queue Full + 1 + 1 + read-only + + + 0 + TX Queue Not Full + #0 + + + 1 + TX Queue Full + #1 + + + + + TXQTXIF + TX Queue TX Interrupt Flag + 2 + 2 + read-write + + + 0 + TX Queue interrupt condition not satisfied after Frame TX + #0 + + + 1 + TX Queue interrupt condition satisfied after Frame TX + #1 + + + + + TXQMC + TX Queue Message Count + 8 + 13 + read-only + + + TXQFIF + TXQ Full Interrupt Flag + 16 + 16 + read-write + + + TXQOFRXIF + TXQ One Frame Reception Interrupt Flag + 17 + 17 + read-write + + + TXQOFTXIF + TXQ One Frame Transmission Interrupt Flag + 18 + 18 + read-write + + + TXQMLT + TXQ Message Lost + 19 + 19 + read-write + + + 0 + No Message Lost in TXQ + #0 + + + 1 + TXQ Message Lost + #1 + + + + + + + 2 + 0x04 + CFDTXQPCTR2[%s] + TX Queue Pointer Control Registers 2 + 0x1100 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQPC + TX Queue Pointer Control + 0 + 7 + write-only + + + + + 2 + 0x04 + CFDTXQCC3[%s] + TX Queue Configuration / Control Registers 3 + 0x1120 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQE + TX Queue Enable + 0 + 0 + read-write + + + 0 + TX Queue disabled + #0 + + + 1 + TX Queue enabled + #1 + + + + + TXQTXIE + TX Queue TX Interrupt Enable + 5 + 5 + read-write + + + 0 + TX Queue TX Interrupt disabled + #0 + + + 1 + TX Queue TX Interrupt enabled + #1 + + + + + TXQIM + TX Queue Interrupt Mode + 7 + 7 + read-write + + + 0 + When the last message is successfully transmitted + #0 + + + 1 + At every successful transmission + #1 + + + + + TXQDC + TX Queue Depth Configuration + 8 + 12 + read-write + + + TXQOFTXIE + TXQ One Frame Transmission Interrupt Enable + 18 + 18 + read-write + + + 0 + One Frame TX Interrupt generation disabled + #0 + + + 1 + One Frame TX Interrupt generation enabled + #1 + + + + + + + 2 + 0x04 + CFDTXQSTS3[%s] + TX Queue Status Registers 3 + 0x1140 + 32 + read-write + 0x00000001 + 0xffffffff + + + TXQEMP + TX Queue Empty + 0 + 0 + read-only + + + 0 + TX Queue Not Empty + #0 + + + 1 + TX Queue Empty + #1 + + + + + TXQFLL + TX Queue Full + 1 + 1 + read-only + + + 0 + TX Queue Not Full + #0 + + + 1 + TX Queue Full + #1 + + + + + TXQTXIF + TX Queue TX Interrupt Flag + 2 + 2 + read-write + + + 0 + TX Queue interrupt condition not satisfied after Frame TX + #0 + + + 1 + TX Queue interrupt condition satisfied after Frame TX + #1 + + + + + TXQMC + TX Queue Message Count + 8 + 13 + read-only + + + TXQOFTXIF + TXQ One Frame Transmission Interrupt Flag + 18 + 18 + read-write + + + + + 2 + 0x04 + CFDTXQPCTR3[%s] + TX Queue Pointer Control Registers 3 + 0x1160 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQPC + TX Queue Pointer Control + 0 + 7 + write-only + + + + + CFDTXQESTS + TX Queue Empty Status Register + 0x1180 + 32 + read-only + 0x000000ff + 0xffffffff + + + TXQxEMP + TXQ empty Status + 0 + 7 + read-only + + + 0 + TXQ not empty + #0 + + + 1 + TXQ empty + #1 + + + + + + + CFDTXQFISTS + TX Queue Full Interrupt Status Register + 0x1184 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQ0FULL + TXQ Full Interrupt Status for channel 0 + 0 + 2 + read-only + + + 0 + TXQ Full Interrupt is not set + #0 + + + 1 + TXQ Full Interrupt is set + #1 + + + + + TXQ1FULL + TXQ Full Interrupt Status for channel 1 + 4 + 6 + read-only + + + 0 + TXQ Full Interrupt is not set + #0 + + + 1 + TXQ Full Interrupt is set + #1 + + + + + + + CFDTXQMSTS + TX Queue Message Lost Status Register + 0x1188 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQ0ML + TXQ message lost Status for channel 0 + 0 + 2 + read-only + + + 0 + TXQ message lost flag is not set + #0 + + + 1 + TXQ message lost flag is set + #1 + + + + + TXQ1ML + TXQ message lost Status for channel 1 + 4 + 6 + read-only + + + 0 + TXQ message lost flag is not set + #0 + + + 1 + TXQ message lost flag is set + #1 + + + + + + + CFDTXQISTS + TX Queue Interrupt Status Register + 0x1190 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQ0ISF + TXQ Interrupt Status Flag for channel 0 + 0 + 3 + read-only + + + 0 + TXQ Interrupt flag is not set + #0 + + + 1 + TXQ Interrupt flag is set + #1 + + + + + TXQ1ISF + TXQ Interrupt Status Flag for channel 1 + 4 + 7 + read-only + + + 0 + TXQ Interrupt flag is not set + #0 + + + 1 + TXQ Interrupt flag is set + #1 + + + + + + + CFDTXQOFTISTS + TX Queue One Frame TX Interrupt Status Register + 0x1194 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQ0OFTISF + TXQ One Frame TX Interrupt Status Flag for channel 0 + 0 + 3 + read-only + + + 0 + TXQ One Frame TX Interrupt flag is not set + #0 + + + 1 + TXQ One Frame TX Interrupt flag is set + #1 + + + + + TXQ1OFTISF + TXQ One Frame TX Interrupt Status Flag for channel 1 + 4 + 7 + read-only + + + 0 + TXQ One Frame TX Interrupt flag is not set + #0 + + + 1 + TXQ One Frame TX Interrupt flag is set + #1 + + + + + + + CFDTXQOFRISTS + TX Queue One Frame RX Interrupt Status Register + 0x1198 + 32 + read-write + 0x00000000 + 0xffffffff + + + TXQ0OFRISF + TXQ One Frame RX Interrupt Status Flag + 0 + 2 + read-only + + + 0 + TXQ One Frame RX Interrupt flag is not set + #0 + + + 1 + TXQ One Frame RX Interrupt flag is set + #1 + + + + + TXQ1OFRISF + TXQ One Frame RX Interrupt Status Flag + 4 + 6 + read-only + + + 0 + TXQ One Frame RX Interrupt flag is not set + #0 + + + 1 + TXQ One Frame RX Interrupt flag is set + #1 + + + + + + + CFDTXQFSTS + TX Queue Full Status Register + 0x119C + 32 + read-only + 0x00000000 + 0xffffffff + + + TXQ0FSF + TXQ Full Status Flag for channel 0 + 0 + 3 + read-only + + + 0 + TXQ Full flag is not set + #0 + + + 1 + TXQ Full flag is set + #1 + + + + + TXQ1FSF + TXQ Full Status Flag for channel 1 + 4 + 7 + read-only + + + 0 + TXQ Full flag is not set + #0 + + + 1 + TXQ Full flag is set + #1 + + + + + + + 2 + 0x04 + CFDTHLCC[%s] + TX History List Configuration / Control Register + 0x1200 + 32 + read-write + 0x00000000 + 0xffffffff + + + THLE + TX History List Enable + 0 + 0 + read-write + + + 0 + TX History List disabled + #0 + + + 1 + TX History List enabled + #1 + + + + + THLIE + TX History List Interrupt Enable + 8 + 8 + read-write + + + 0 + TX History List Interrupt disabled + #0 + + + 1 + TX History List Interrupt enabled + #1 + + + + + THLIM + TX History List Interrupt Mode + 9 + 9 + read-write + + + 0 + Interrupt generated if TX History List level reaches 3/4 of the TX History List depth. + #0 + + + 1 + Interrupt generated for every successfully stored entry + #1 + + + + + THLDTE + TX History List Dedicated TX Enable + 10 + 10 + read-write + + + 0 + TX FIFO + TX Queue + #0 + + + 1 + Flat TX MB + TX FIFO + TX Queue + #1 + + + + + THLDGE + TX History List Dedicated GW Enable + 11 + 11 + read-write + + + 0 + Not dedicate Gateway FIFO + Gateway TX Queue + #0 + + + 1 + Dedicate Gateway FIFO + Gateway TX Queue + #1 + + + + + + + 2 + 0x04 + CFDTHLSTS[%s] + TX History List Status Register + 0x1220 + 32 + read-write + 0x00000001 + 0xffffffff + + + THLEMP + TX History List Empty + 0 + 0 + read-only + + + 0 + TX History List Not Empty + #0 + + + 1 + TX History List Empty + #1 + + + + + THLFLL + TX History List Full + 1 + 1 + read-only + + + 0 + TX History List Not Full + #0 + + + 1 + TX History List Full + #1 + + + + + THLELT + TX History List Entry Lost + 2 + 2 + read-write + + + 0 + No Entry Lost in TX History List + #0 + + + 1 + TX History List Entry Lost + #1 + + + + + THLIF + TX History List Interrupt Flag + 3 + 3 + read-write + + + 0 + TX History List Interrupt condition not satisfied + #0 + + + 1 + TX History List Interrupt condition satisfied + #1 + + + + + THLMC + TX History List Message Count + 8 + 13 + read-only + + + + + 2 + 0x04 + CFDTHLPCTR[%s] + TX History List Pointer Control Registers + 0x1240 + 32 + read-write + 0x00000000 + 0xffffffff + + + THLPC + TX History List Pointer Control + 0 + 7 + write-only + + + + + CFDGTINTSTS0 + Global TX Interrupt Status Register 0 + 0x1300 + 32 + read-write + 0x00000000 + 0xffffffff + + + TSIF0 + TX Successful Interrupt Flag Channel 0 + 0 + 0 + read-only + + + 0 + Channel n TX Successful completion Interrupt flag not set + #0 + + + 1 + Channel n TX Successful completion Interrupt flag set + #1 + + + + + TAIF0 + TX Abort Interrupt Flag Channel 0 + 1 + 1 + read-only + + + 0 + Channel n TX abort Interrupt flag not set + #0 + + + 1 + Channel n TX abort Interrupt flag set + #1 + + + + + TQIF0 + TX Queue Interrupt Flag Channel 0 + 2 + 2 + read-only + + + 0 + Channel n TX Queue Interrupt flag not set + #0 + + + 1 + Channel n TX Queue Interrupt flag set + #1 + + + + + CFTIF0 + COM FIFO TX/GW Mode Interrupt Flag Channel 0 + 3 + 3 + read-only + + + 0 + Channel n COM FIFO TX/GW mode Interrupt flag not set + #0 + + + 1 + Channel n COM FIFO TX/GW mode Interrupt flag set + #1 + + + + + THIF0 + TX History List Interrupt Channel 0 + 4 + 4 + read-only + + + 0 + Channel n TX History List Interrupt flag not set + #0 + + + 1 + Channel n TX History List Interrupt flag set + #1 + + + + + TQOFIF0 + TX Queue One Frame Transmission Interrupt Flag Channel 0 + 5 + 5 + read-only + + + 0 + Channel n TX Queue One Frame Transmission Interrupt flag not set + #0 + + + 1 + Channel n TX Queue One Frame Transmission Interrupt flag set + #1 + + + + + CFOTIF0 + COM FIFO One Frame Transmission Interrupt Flag Channel 0 + 6 + 6 + read-only + + + 0 + Channel n COM FIFO One Frame Transmission Interrupt flag not set + #0 + + + 1 + Channel n COM FIFO One Frame Transmission Interrupt flag set + #1 + + + + + TSIF1 + TX Successful Interrupt Flag Channel 1 + 8 + 8 + read-only + + + 0 + Channel n TX Successful completion Interrupt flag not set + #0 + + + 1 + Channel n TX Successful completion Interrupt flag set + #1 + + + + + TAIF1 + TX Abort Interrupt Flag Channel 1 + 9 + 9 + read-only + + + 0 + Channel n TX abort Interrupt flag not set + #0 + + + 1 + Channel n TX abort Interrupt flag set + #1 + + + + + TQIF1 + TX Queue Interrupt Flag Channel 1 + 10 + 10 + read-only + + + 0 + Channel n TX Queue Interrupt flag not set + #0 + + + 1 + Channel n TX Queue Interrupt flag set + #1 + + + + + CFTIF1 + COM FIFO TX/GW Mode Interrupt Flag Channel 1 + 11 + 11 + read-only + + + 0 + Channel n COM FIFO TX/GW mode Interrupt flag not set + #0 + + + 1 + Channel n COM FIFO TX/GW mode Interrupt flag set + #1 + + + + + THIF1 + TX History List Interrupt Channel 1 + 12 + 12 + read-only + + + 0 + Channel n TX History List Interrupt flag not set + #0 + + + 1 + Channel n TX History List Interrupt flag set + #1 + + + + + TQOFIF1 + TX Queue One Frame Transmission Interrupt Flag Channel 1 + 13 + 13 + read-only + + + 0 + Channel n TX Queue One Frame Transmission Interrupt flag not set + #0 + + + 1 + Channel n TX Queue One Frame Transmission Interrupt flag set + #1 + + + + + CFOTIF1 + COM FIFO One Frame Transmission Interrupt Flag Channel 1 + 14 + 14 + read-only + + + 0 + Channel n COM FIFO One Frame Transmission Interrupt flag not set + #0 + + + 1 + Channel n COM FIFO One Frame Transmission Interrupt flag set + #1 + + + + + + + CFDGTSTCFG + Global Test Configuration Register + 0x1308 + 32 + read-write + 0x00000000 + 0xffffffff + + + ICBCE + Channel n Internal CAN Bus Communication Test Mode Enable + 0 + 1 + read-write + + + 0 + Channel n internal CAN bus communication disabled + #0 + + + 1 + Channel n internal CAN bus communication enabled + #1 + + + + + RTMPS + RAM Test Mode Page Select + 16 + 25 + read-write + + + + + CFDGTSTCTR + Global Test Control Register + 0x130C + 32 + read-write + 0x00000000 + 0xffffffff + + + ICBCTME + Internal CAN Bus Communication Test Mode Enable + 0 + 0 + read-write + + + 0 + Internal CAN Bus communication test mode disabled + #0 + + + 1 + Internal CAN Bus communication test mode enabled + #1 + + + + + RTME + RAM Test Mode Enable + 2 + 2 + read-write + + + 0 + RAM Test Mode disabled + #0 + + + 1 + RAM Test Mode enabled + #1 + + + + + + + CFDGFDCFG + Global FD Configuration register + 0x1314 + 32 + read-write + 0x00000000 + 0xffffffff + + + RPED + RES bit Protocol exception disable + 0 + 0 + read-write + + + 0 + Protocol exception event detection enabled + #0 + + + 1 + Protocol exception event detection disabled + #1 + + + + + TSCCFG + Timestamp capture configuration + 8 + 9 + read-write + + + 00 + Timestamp capture at the sample point of SOF (start of frame) + #00 + + + 01 + Timestamp capture at frame valid indication + #01 + + + 10 + Timestamp capture at the sample point of RES bit + #10 + + + 11 + reserved + #11 + + + + + + + CFDGCRCCFG + Global FD CRC Configuration register + 0x1318 + 32 + read-write + 0x00000000 + 0xffffffff + + + NIE + Non ISO enable + 0 + 0 + read-write + + + 0 + CAN FD frame format according to ISO 11898-1 + #0 + + + 1 + CAN FD frame format according to Bosch CAN FD Specification V1.0 + #1 + + + + + + + CFDGLOCKK + Global Lock Key Register + 0x131C + 32 + read-write + 0x00000000 + 0xffffffff + + + LOCK + Lock Key + 0 + 15 + write-only + + + + + CFDGLOTB + Global OTB FIFO Configuration / Status Register + 0x1320 + 32 + read-write + 0x00000101 + 0xffffffff + + + OTBFE + OTB FIFO Enable + 0 + 0 + read-write + + + 0 + FIFO disabled + #0 + + + 1 + FIFO enabled + #1 + + + + + OTBEMP + OTB FIFO Empty + 8 + 8 + read-only + + + 0 + FIFO Not Empty + #0 + + + 1 + FIFO Empty + #1 + + + + + OTBFLL + OTB FIFO Full + 9 + 9 + read-only + + + 0 + FIFO Not Full + #0 + + + 1 + FIFO Full + #1 + + + + + OTBMLT + OTB FIFO Message Lost + 10 + 10 + read-write + + + 0 + No Message Lost in FIFO + #0 + + + 1 + FIFO Message Lost + #1 + + + + + OTBMC + OTB FIFO Message Count + 11 + 15 + read-only + + + + + CFDGAFLIGNENT + Global AFL Ignore Entry Register + 0x1324 + 32 + read-write + 0x00000000 + 0xffffffff + + + IRN + Ignore Rule Number + 0 + 8 + read-write + + + ICN + Ignore Channel Number + 16 + 18 + read-write + + + + + CFDGAFLIGNCTR + Global AFL Ignore Control Register + 0x1328 + 32 + read-write + 0x00000000 + 0xffffffff + + + IREN + Ignore Rule Enable + 0 + 0 + read-write + + + 0 + AFL entry number does not ignore + #0 + + + 1 + AFL entry number ignores + #1 + + + + + KEY + Key code + 8 + 15 + write-only + + + + + CFDCDTCT + DMA Transfer Control Register + 0x1330 + 32 + read-write + 0x00000000 + 0xffffffff + + + RFDMAE0 + DMA Transfer Enable for RXFIFO 0 + 0 + 0 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE1 + DMA Transfer Enable for RXFIFO 1 + 1 + 1 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE2 + DMA Transfer Enable for RXFIFO 2 + 2 + 2 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE3 + DMA Transfer Enable for RXFIFO 3 + 3 + 3 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE4 + DMA Transfer Enable for RXFIFO 4 + 4 + 4 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE5 + DMA Transfer Enable for RXFIFO 5 + 5 + 5 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE6 + DMA Transfer Enable for RXFIFO 6 + 6 + 6 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + RFDMAE7 + DMA Transfer Enable for RXFIFO 7 + 7 + 7 + read-write + + + 0 + DMA Transfer Request disabled + #0 + + + 1 + DMA Transfer Request enabled + #1 + + + + + CFDMAE0 + DMA Transfer Enable for Common FIFO 0 of channel 0 + 8 + 8 + read-write + + + 0 + DMA Transfer Request disabled for channel n + #0 + + + 1 + DMA Transfer Request enabled for channel n + #1 + + + + + CFDMAE1 + DMA Transfer Enable for Common FIFO 0 of channel 1 + 9 + 9 + read-write + + + 0 + DMA Transfer Request disabled for channel n + #0 + + + 1 + DMA Transfer Request enabled for channel n + #1 + + + + + + + CFDCDTSTS + DMA Transfer Status Register + 0x1334 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFDMASTS0 + DMA Transfer Status for RX FIFO 0 + 0 + 0 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS1 + DMA Transfer Status for RX FIFO 1 + 1 + 1 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS2 + DMA Transfer Status for RX FIFO 2 + 2 + 2 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS3 + DMA Transfer Status for RX FIFO 3 + 3 + 3 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS4 + DMA Transfer Status for RX FIFO 4 + 4 + 4 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS5 + DMA Transfer Status for RX FIFO 5 + 5 + 5 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS6 + DMA Transfer Status for RX FIFO 6 + 6 + 6 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + RFDMASTS7 + DMA Transfer Status for RX FIFO 7 + 7 + 7 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + CFDMASTS0 + DMA Transfer Status only for Common FIFO 0 of channel 0 + 8 + 8 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + CFDMASTS1 + DMA Transfer Status only for Common FIFO 0 of channel 1 + 9 + 9 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer ongoing + #1 + + + + + + + CFDCDTTCT + DMA TX Transfer Control Register + 0x1340 + 32 + read-write + 0x00000000 + 0xffffffff + + + TQ0DMAE0 + DMA TX Transfer Enable for TXQ 0 of channel 0 + 0 + 0 + read-write + + + 0 + DMA TX Transfer Request disabled + #0 + + + 1 + DMA TX Transfer Request enabled + #1 + + + + + TQ0DMAE1 + DMA TX Transfer Enable for TXQ 0 of channel 1 + 1 + 1 + read-write + + + 0 + DMA TX Transfer Request disabled + #0 + + + 1 + DMA TX Transfer Request enabled + #1 + + + + + TQ3DMAE0 + DMA TX Transfer Enable for TXQ 3 of channel 0 + 8 + 8 + read-write + + + 0 + DMA TX Transfer Request disabled + #0 + + + 1 + DMA TX Transfer Request enabled + #1 + + + + + TQ3DMAE1 + DMA TX Transfer Enable for TXQ 3 of channel 1 + 9 + 9 + read-write + + + 0 + DMA TX Transfer Request disabled + #0 + + + 1 + DMA TX Transfer Request enabled + #1 + + + + + CFDMAE0 + DMA TX Transfer Enable for Common FIFO 2 of channel 0 + 16 + 16 + read-write + + + 0 + DMA TX Transfer Request disabled for channel n + #0 + + + 1 + DMA TX Transfer Request enabled for channel n + #1 + + + + + CFDMAE1 + DMA TX Transfer Enable for Common FIFO 2 of channel 1 + 17 + 17 + read-write + + + 0 + DMA TX Transfer Request disabled for channel n + #0 + + + 1 + DMA TX Transfer Request enabled for channel n + #1 + + + + + + + CFDCDTTSTS + DMA TX Transfer Status Register + 0x1344 + 32 + read-write + 0x00000000 + 0xffffffff + + + TQ0DMASTS0 + DMA TX Transfer Status for TXQ0 of channel 0 + 0 + 0 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + TQ0DMASTS1 + DMA TX Transfer Status for TXQ0 of channel 1 + 1 + 1 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + TQ3DMASTS0 + DMA TX Transfer Status for TXQ3 of channel 0 + 8 + 8 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + TQ3DMASTS1 + DMA TX Transfer Status for TXQ3 of channel 1 + 9 + 9 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + CFDMASTS0 + DMA TX Transfer Status only for Common FIFO 2 of channel 0 + 16 + 16 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + CFDMASTS1 + DMA TX Transfer Status only for Common FIFO 2 of channel 1 + 17 + 17 + read-only + + + 0 + DMA transfer stopped + #0 + + + 1 + DMA transfer enable + #1 + + + + + + + 2 + 0x04 + CFDGRINTSTS[%s] + Global RX Interrupt Status Register + 0x1350 + 32 + read-write + 0x00000000 + 0xffffffff + + + QFIF + TXQ Full Interrupt Flag Channel n + 0 + 2 + read-only + + + 0 + Corresponding TXQ Full interrupt flag is not set + #0 + + + 1 + Corresponding TXQ Full interrupt flag is set + #1 + + + + + QOFRIF + TXQ One Frame RX Interrupt Flag Channel n + 8 + 10 + read-only + + + 0 + Corresponding TXQ One Frame RX interrupt flag is not set + #0 + + + 1 + Corresponding TXQ One Frame RX interrupt flag is set + #1 + + + + + CFRIF + Common FIFO RX Interrupt Flag Channel n + 16 + 18 + read-only + + + 0 + Corresponding Common FIFO RX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO RX interrupt flag is set + #1 + + + + + CFRFIF + Common FIFO FDC level Full Interrupt Flag Channel n + 24 + 26 + read-only + + + 0 + Corresponding Common FIFO Full interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO Full interrupt flag is set + #1 + + + + + CFOFRIF + Common FIFO One Frame RX Interrupt Flag Channel n + 28 + 30 + read-only + + + 0 + Corresponding Common FIFO One Frame RX interrupt flag is not set + #0 + + + 1 + Corresponding Common FIFO One Frame RX interrupt flag is set + #1 + + + + + + + CFDGRSTC + Global SW reset Register + 0x1380 + 32 + read-write + 0x00000000 + 0xffffffff + + + SRST + SW reset + 0 + 0 + read-write + + + 0 + normal state + #0 + + + 1 + SW reset state + #1 + + + + + KEY + Key code + 8 + 15 + write-only + + + + + 2 + 0x20 + CFDC2[%s] + Channel Configuration Registers + 0x1400 + + DCFG + Channel Data Bitrate Configuration Register + 0x0000 + 32 + read-write + 0x00000000 + 0xffffffff + + + DBRP + Channel Data Baud Rate Prescaler + 0 + 7 + read-write + + + DTSEG1 + Timing Segment 1 + 8 + 12 + read-write + + + DTSEG2 + Timing Segment 2 + 16 + 19 + read-write + + + DSJW + Resynchronization Jump Width + 24 + 27 + read-write + + + + + FDCFG + Channel CAN-FD Configuration Register + 0x0004 + 32 + read-write + 0x00000000 + 0xffffffff + + + EOCCFG + Error Occurrence Counter Configuration + 0 + 2 + read-write + + + 000 + All Transmitter or Receiver CAN Frames + #000 + + + 001 + All Transmitter CAN Frames + #001 + + + 010 + All Receiver CAN Frames + #010 + + + 011 + Reserved + #011 + + + 100 + Only Transmitter or Receiver CAN-FD Data-Phase (fast bits) + #100 + + + 101 + Only Transmitter CAN-FD Data-Phase (fast bits) + #101 + + + 110 + Only Receiver CAN-FD Data-Phase (fast bits) + #110 + + + 111 + Reserved + #111 + + + + + TDCOC + Transceiver Delay Compensation Offset Configuration + 8 + 8 + read-write + + + 0 + Measured + offset + #0 + + + 1 + offset only + #1 + + + + + TDCE + Transceiver Delay Compensation Enable + 9 + 9 + read-write + + + 0 + Transceiver Delay Compensation disabled + #0 + + + 1 + Transceiver Delay Compensation enabled + #1 + + + + + ESIC + Error State Indication Configuration + 10 + 10 + read-write + + + 0 + The ESI bit in the frame will be representing the Error state of the node itself. + #0 + + + 1 + The ESI bit in the frame will be representing the Error state of message buffer if the node itself is not in error passive. If the node is in Error Passive then the ESI bit will be driven by the node itself. + #1 + + + + + TDCO + Transceiver Delay Compensation Offset + 16 + 23 + read-write + + + GWEN + CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable + 24 + 24 + read-write + + + 0 + Multi Gateway Disabled + #0 + + + 1 + Multi Gateway Enable + #1 + + + + + GWFDF + Gateway FDF configuration bit + 25 + 25 + read-write + + + 0 + GW frame is transmitted as Classical CAN frame. + #0 + + + 1 + GW frame is transmitted as CAN-FD frame . + #1 + + + + + GWBRS + Gateway BRS configuration bit + 26 + 26 + read-write + + + 0 + GW frame is transmitted with BRS = 0 + #0 + + + 1 + GW frame is transmitted with BRS = 1 + #1 + + + + + FDOE + FD only enable + 28 + 28 + read-write + + + 0 + FD only mode disabled + #0 + + + 1 + FD only mode enabled + #1 + + + + + REFE + RX edge filter enable + 29 + 29 + read-write + + + 0 + RX edge filter disabled + #0 + + + 1 + RX edge filter enabled + #1 + + + + + CLOE + Classical CAN only enable + 30 + 30 + read-write + + + 0 + Classical only mode disabled + #0 + + + 1 + Classical only mode enabled + #1 + + + + + CFDTE + CAN-FD frame Distinction enable + 31 + 31 + read-write + + + 0 + CAN-FD frame distinction disabled + #0 + + + 1 + CAN-FD frame distinction enabled + #1 + + + + + + + FDCTR + Channel CAN-FD Control Register + 0x0008 + 32 + read-write + 0x00000000 + 0xffffffff + + + EOCCLR + Error Occurrence Counter Clear + 0 + 0 + read-write + + + 0 + No Error Occurrence Counter clear + #0 + + + 1 + Clear Error Occurrence Counter + #1 + + + + + SOCCLR + Successful Occurrence Counter Clear + 1 + 1 + read-write + + + 0 + No Successful Occurrence Counter clear + #0 + + + 1 + Clear Successful Occurrence Counter + #1 + + + + + + + FDSTS + Channel CAN-FD Status Register + 0x000C + 32 + read-write + 0x00000000 + 0xffffffff + + + TDCR + Transceiver Delay Compensation Result + 0 + 7 + read-only + + + EOCO + Error occurrence counter overflow + 8 + 8 + read-write + + + 0 + Error occurrence counter has not overflowed + #0 + + + 1 + Error occurrence counter has overflowed + #1 + + + + + SOCO + Successful occurrence counter overflow + 9 + 9 + read-write + + + 0 + Successful occurrence counter has not overflowed + #0 + + + 1 + Successful occurrence counter has overflowed + #1 + + + + + TDCVF + Transceiver Delay Compensation Violation Flag + 15 + 15 + read-write + + + 0 + Transceiver Delay Compensation Violation has not occurred + #0 + + + 1 + Transceiver Delay Compensation Violation has occurred + #1 + + + + + EOC + Error occurrence counter register + 16 + 23 + read-only + + + SOC + Successful occurrence counter register + 24 + 31 + read-only + + + + + FDCRC + Channel CAN-FD CRC Register + 0x0010 + 32 + read-write + 0x00000000 + 0xffffffff + + + CRCREG + CRC Register value + 0 + 20 + read-only + + + SCNT + Stuff bit count + 24 + 27 + read-only + + + + + BLCT + Channel Bus load Control Register + 0x0018 + 32 + read-write + 0x00000000 + 0xffffffff + + + BLCE + BUS Load counter Enable + 0 + 0 + read-write + + + 0 + BUS Load counter disable + #0 + + + 1 + BUS Load counter enable + #1 + + + + + BLCLD + BUS Load counter load + 8 + 8 + write-only + + + + + BLSTS + Channel Bus load Status Register + 0x001C + 32 + read-write + 0x00000000 + 0xffffffff + + + BLC + BUS Load counter Status + 3 + 31 + read-only + + + + + + 16 + 0x10 + CFDGAFL[%s] + Global Acceptance Filter List Registers + 0x1800 + + ID + Global Acceptance Filter List ID Registers + 0x0000 + 32 + read-write + 0x00000000 + 0xffffffff + + + GAFLID + Global Acceptance Filter List Entry ID Field + 0 + 28 + read-write + + + GAFLLB + Global Acceptance Filter List Entry Loopback Configuration + 29 + 29 + read-write + + + 0 + Global Acceptance Filter List entry ID for acceptance filtering has attribute RX + #0 + + + 1 + Global Acceptance Filter List entry ID for acceptance filtering has attribute TX + #1 + + + + + GAFLRTR + Global Acceptance Filter List Entry RTR Field + 30 + 30 + read-write + + + 0 + Data Frame + #0 + + + 1 + Remote Frame + #1 + + + + + GAFLIDE + Global Acceptance Filter List Entry IDE Field + 31 + 31 + read-write + + + 0 + Standard Identifier of Rule entry ID is valid for acceptance filtering + #0 + + + 1 + Extended Identifier of Rule entry ID is valid for acceptance filtering + #1 + + + + + + + M + Global Acceptance Filter List Mask Registers + 0x0004 + 32 + read-write + 0x00000000 + 0xffffffff + + + GAFLIDM + Global Acceptance Filter List ID Mask Field + 0 + 28 + read-write + + + GAFLIFL1 + Global Acceptance Filter List Information Label 1 + 29 + 29 + read-write + + + GAFLRTRM + Global Acceptance Filter List Entry RTR Mask + 30 + 30 + read-write + + + 0 + RTR bit is not considered for ID matching + #0 + + + 1 + RTR bit is considered for ID matching + #1 + + + + + GAFLIDEM + Global Acceptance Filter List IDE Mask + 31 + 31 + read-write + + + 0 + IDE bit is not considered for ID matching + #0 + + + 1 + IDE bit is considered for ID matching + #1 + + + + + + + P0 + Global Acceptance Filter List Pointer 0 Registers + 0x0008 + 32 + read-write + 0x00000000 + 0xffffffff + + + GAFLDLC + Global Acceptance Filter List DLC Field + 0 + 3 + read-write + + + GAFLSRD0 + Global Acceptance Filter List Select Routing destination 0 + 4 + 4 + read-write + + + 0 + Routing target is CFIFO0 + #0 + + + 1 + Routing target is TX Queue 0 instead of CFIFO0 + #1 + + + + + GAFLSRD1 + Global Acceptance Filter List Select Routing destination 1 + 5 + 5 + read-write + + + 0 + Routing target is CFIFO1 + #0 + + + 1 + Routing target is TX Queue 1 instead of CFIFO1 + #1 + + + + + GAFLSRD2 + Global Acceptance Filter List Select Routing destination 2 + 6 + 6 + read-write + + + 0 + Routing target is CFIFO2 + #0 + + + 1 + Routing target is TX Queue 2 instead of CFIFO2 + #1 + + + + + GAFLIFL0 + Global Acceptance Filter List Information Label 0 + 7 + 7 + read-write + + + GAFLRMDP + Global Acceptance Filter List RX Message Buffer Direction Pointer + 8 + 12 + read-write + + + GAFLRMV + Global Acceptance Filter List RX Message Buffer Valid + 15 + 15 + read-write + + + 0 + Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid + #0 + + + 1 + Global Acceptance Filter List Single Message Buffer Direction Pointer is valid + #1 + + + + + GAFLPTR + Global Acceptance Filter List Pointer Field + 16 + 31 + read-write + + + + + P1 + Global Acceptance Filter List Pointer 1 Registers + 0x000C + 32 + read-write + 0x00000000 + 0xffffffff + + + GAFLFDP + Global Acceptance Filter List FIFO Direction Pointer + 0 + 13 + read-write + + + + + + 2 + 0x08 + CFDTHL[%s] + Channel TX History List + 0x8000 + + ACC0 + Channel TX History List Access Registers 0 + 0x0000 + 32 + read-only + 0x00000000 + 0xffffffff + + + BT + Buffer Type + 0 + 2 + read-only + + + 001 + Flat TX Message Buffer + #001 + + + 010 + TX FIFO MB No and GW FIFO MB No. + #010 + + + 100 + TX Queue MB No. + #100 + + + + + BN + Buffer No. + 3 + 9 + read-only + + + TGW + Transmit Gateway Buffer indication + 15 + 15 + read-only + + + 0 + not transmission from Gateway + #0 + + + 1 + transmission from Gateway + #1 + + + + + TMTS + Transmit Timestamp + 16 + 31 + read-only + + + + + ACC1 + Channel TX History List Access Registers 1 + 0x0004 + 32 + read-write + 0x00000000 + 0xffffffff + + + TID + Transmit ID + 0 + 15 + read-only + + + TIFL + Transmit Information Label + 16 + 17 + read-only + + + + + + 64 + 0x04 + CFDRPGACC[%s] + RAM Test Page Access Registers + 0x8400 + 32 + read-write + 0x00000000 + 0xffffffff + + + RDTA + RAM Data Test Access + 0 + 31 + read-write + + + + + 32 + 0x80 + CFDRM[%s] + RX Message Buffer Access Registers + 0x2000 + + ID + RX Message Buffer ID Register + 0x0000 + 32 + read-only + 0x00000000 + 0xffffffff + + + RMID + RX Message Buffer ID Field + 0 + 28 + read-only + + + RMRTR + RX Message Buffer RTR Frame + 30 + 30 + read-only + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + RMIDE + RX Message Buffer IDE Bit + 31 + 31 + read-only + + + 0 + STD-ID is stored + #0 + + + 1 + EXT-ID is stored + #1 + + + + + + + PTR + RX Message Buffer Pointer Register + 0x0004 + 32 + read-only + 0x00000000 + 0xffffffff + + + RMTS + RX Message Buffer Timestamp Field + 0 + 15 + read-only + + + RMDLC + RX Message Buffer DLC Field + 28 + 31 + read-only + + + + + FDSTS + RX Message Buffer CAN-FD Status Register + 0x0008 + 32 + read-only + 0x00000000 + 0xffffffff + + + RMESI + Error State Indicator bit + 0 + 0 + read-only + + + 0 + CAN-FD frame received from error active node + #0 + + + 1 + CAN-FD frame received from error passive node + #1 + + + + + RMBRS + Bit Rate Switch bit + 1 + 1 + read-only + + + 0 + CAN-FD frame received with no bit rate switch + #0 + + + 1 + CAN-FD frame received with bit rate switch + #1 + + + + + RMFDF + CAN FD Format bit + 2 + 2 + read-only + + + 0 + Non CAN-FD frame received + #0 + + + 1 + CAN-FD frame received + #1 + + + + + RMIFL + RX Message Buffer Information Label Field + 8 + 9 + read-only + + + RMPTR + RX Message Buffer Pointer Field + 16 + 31 + read-only + + + + + 64 + 0x01 + DF[%s] + RX Message Buffer Data Field Registers + 0x000C + 8 + read-only + 0x00 + 0xff + + + RMDB + RX Message Buffer Data Byte + 0 + 7 + read-only + + + + + + 8 + 0x80 + CFDRF[%s] + RX FIFO Access Registers + 0x6000 + + ID + RX FIFO Access ID Register + 0x0000 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFID + RX FIFO Buffer ID Field + 0 + 28 + read-only + + + RFRTR + RX FIFO Buffer RTR Frame + 30 + 30 + read-only + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + RFIDE + RX FIFO Buffer IDE Bit + 31 + 31 + read-only + + + 0 + STD-ID is stored + #0 + + + 1 + EXT-ID is stored + #1 + + + + + + + PTR + RX FIFO Access Pointer Register + 0x0004 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFTS + RX FIFO Timestamp Field + 0 + 15 + read-only + + + RFDLC + RX FIFO Buffer DLC Field + 28 + 31 + read-only + + + + + FDSTS + RX FIFO Access CAN-FD Status Register + 0x0008 + 32 + read-only + 0x00000000 + 0xffffffff + + + RFESI + Error State Indicator bit + 0 + 0 + read-only + + + 0 + CAN-FD frame received from error active node + #0 + + + 1 + CAN-FD frame received from error passive node + #1 + + + + + RFBRS + Bit Rate Switch bit + 1 + 1 + read-only + + + 0 + CAN-FD frame received with no bit rate switch + #0 + + + 1 + CAN-FD frame received with bit rate switch + #1 + + + + + RFFDF + CAN FD Format bit + 2 + 2 + read-only + + + 0 + Non CAN-FD frame received + #0 + + + 1 + CAN-FD frame received + #1 + + + + + RFIFL + RX FIFO Buffer Information Label Field + 8 + 9 + read-only + + + RFPTR + RX FIFO Buffer Pointer Field + 16 + 31 + read-only + + + + + 64 + 0x01 + DF[%s] + RX FIFO Access Data Field Registers + 0x000C + 8 + read-only + 0x00 + 0xff + + + RFDB + RX FIFO Buffer Data Byte + 0 + 7 + read-only + + + + + + 5 + 0x80 + CFDCF[%s] + Common FIFO Access Registers + 0x6420 + + ID + Common FIFO Access ID Register + 0x0000 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFID + Common FIFO Buffer ID Field + 0 + 28 + read-only + + + CFRTR + Common FIFO Buffer RTR Frame + 30 + 30 + read-only + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + CFIDE + Common FIFO Buffer IDE Bit + 31 + 31 + read-only + + + 0 + STD-ID is stored + #0 + + + 1 + EXT-ID is stored + #1 + + + + + + + PTR + Common FIFO Access Pointer Register + 0x0004 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFTS + Common FIFO Timestamp Field + 0 + 15 + read-only + + + CFDLC + Common FIFO Buffer DLC Field + 28 + 31 + read-only + + + + + FDSTS + Common FIFO Access CAN-FD Status Register + 0x0008 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFESI + Error State Indicator bit + 0 + 0 + read-only + + + 0 + CAN-FD frame received from error active node + #0 + + + 1 + CAN-FD frame received from error passive node + #1 + + + + + CFBRS + Bit Rate Switch bit + 1 + 1 + read-only + + + 0 + CAN-FD frame received with no bit rate switch + #0 + + + 1 + CAN-FD frame received with bit rate switch + #1 + + + + + CFFDF + CAN FD Format bit + 2 + 2 + read-only + + + 0 + Non CAN-FD frame received + #0 + + + 1 + CAN-FD frame received + #1 + + + + + CFIFL + Common FIFO Buffer Information Label Field + 8 + 9 + read-only + + + CFPTR + Common FIFO Buffer Pointer Field + 16 + 31 + read-only + + + + + 64 + 0x01 + DF[%s] + Common FIFO Access Data Field Registers + 0x000C + 8 + read-only + 0x00 + 0xff + + + CFDB + Common FIFO Buffer Data Byte + 0 + 7 + read-only + + + + + + 32 + 0x80 + CFDTM[%s] + TX Message Buffer Access Registers + 0x10000 + + ID + TX Message Buffer ID Register + 0x0000 + 32 + read-write + 0x00000000 + 0xffffffff + + + TMID + TX Message Buffer ID Field + 0 + 28 + read-write + + + TMRTR + TX Message Buffer RTR Frame + 30 + 30 + read-write + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + TMIDE + TX Message Buffer IDE Bit + 31 + 31 + read-write + + + 0 + STD-ID is stored + #0 + + + 1 + EXT-ID is stored + #1 + + + + + + + PTR + TX Message Buffer Pointer Register + 0x0004 + 32 + read-write + 0x00000000 + 0xffffffff + + + TMTS + TX Message Buffer Timestamp Field + 0 + 15 + read-write + + + TMDLC + TX Message Buffer DLC Field + 28 + 31 + read-write + + + + + FDSTS + TX Message Buffer CAN-FD Status Register + 0x0008 + 32 + read-write + 0x00000000 + 0xffffffff + + + TMESI + Error State Indicator bit + 0 + 0 + read-write + + + 0 + CAN-FD frame received from error active node + #0 + + + 1 + CAN-FD frame received from error passive node + #1 + + + + + TMBRS + Bit Rate Switch bit + 1 + 1 + read-write + + + 0 + CAN-FD frame received with no bit rate switch + #0 + + + 1 + CAN-FD frame received with bit rate switch + #1 + + + + + TMFDF + CAN FD Format bit + 2 + 2 + read-write + + + 0 + Non CAN-FD frame received + #0 + + + 1 + CAN-FD frame received + #1 + + + + + TMIFL + TX Message Buffer Information Label Field + 8 + 9 + read-write + + + TMPTR + TX Message Buffer Pointer Field + 16 + 31 + read-write + + + + + 64 + 0x01 + DF[%s] + TX Message Buffer Data Field Registers + 0x000C + 8 + read-write + 0x00 + 0xff + + + TMDB + TX Message Buffer Data Byte + 0 + 7 + read-write + + + + + + + + R_CRC + Cyclic Redundancy Check (CRC) Calculator + 0x40074000 + + 0x00000000 + 0x002 + registers + + + 0x00000004 + 0x00A + registers + + + + CRCCR0 + CRC Control Register0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + DORCLR + CRCDOR Register Clear + 7 + 7 + write-only + + + 0 + No effect. + #0 + + + 1 + Clears the CRCDOR register. + #1 + + + + + LMS + CRC Calculation Switching + 6 + 6 + read-write + + + 0 + Generates CRC for LSB first communication. + #0 + + + 1 + Generates CRC for MSB first communication. + #1 + + + + + GPS + CRC Generating Polynomial Switching + 0 + 2 + read-write + + + 000 + No calculation is executed. + #000 + + + 001 + 8-bit CRC-8 (X8 + X2 + X + 1) + #001 + + + 010 + 16-bit CRC-16 (X16 + X15 + X2 + 1) + #010 + + + 011 + 16-bit CRC-CCITT (X16 + X12 + X5 + 1) + #011 + + + 100 + 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) + #100 + + + 101 + 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) + #101 + + + others + No calculation is executed. + true + + + + + + + CRCCR1 + CRC Control Register1 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + CRCSEN + Snoop enable bit + 7 + 7 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + CRCSWR + Snoop-on-write/read switch bit + 6 + 6 + read-write + + + 0 + Snoop-on-read + #0 + + + 1 + Snoop-on-write + #1 + + + + + + + CRCDIR + CRC Data Input Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRCDIR + Calculation input Data (Case of CRC-32, CRC-32C ) + 0 + 31 + read-write + + + + + CRCDIR_BY + CRC Data Input Register (byte access) + CRCDIR + 0x04 + 8 + read-write + 0x00 + 0xFF + + + CRCDIR_BY + Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) + 0 + 7 + read-write + + + + + CRCDOR + CRC Data Output Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRCDOR + Calculation output Data (Case of CRC-32, CRC-32C ) + 0 + 31 + read-write + + + + + CRCDOR_HA + CRC Data Output Register (halfword access) + CRCDOR + 0x08 + 16 + read-write + 0x0000 + 0xFFFF + + + CRCDOR_HA + Calculation output Data (Case of CRC-16 or CRC-CCITT ) + 0 + 15 + read-write + + + + + CRCDOR_BY + CRC Data Output Register(byte access) + CRCDOR + 0x08 + 8 + read-write + 0x00 + 0xFF + + + CRCDOR_BY + Calculation output Data (Case of CRC-8 ) + 0 + 7 + read-write + + + + + CRCSAR + Snoop Address Register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + CRCSA + snoop address bitSet the I/O register address to snoop + 0 + 13 + read-write + + + 0x0003 + SCI0.TDR + 0x0003 + + + 0x0005 + SCI0.RDR + 0x0005 + + + 0x0023 + SCI1.TDR + 0x0023 + + + 0x0025 + SCI1.RDR + 0x0025 + + + 0x0043 + SCI2.TDR + 0x0043 + + + 0x0045 + SCI2.RDR + 0x0045 + + + 0x0063 + SCI3.TDR + 0x0063 + + + 0x0065 + SCI3.RDR + 0x0065 + + + 0x0083 + SCI4.TDR + 0x0083 + + + 0x0085 + SCI4.RDR + 0x0085 + + + 0x00A3 + SCI5.TDR + 0x00A3 + + + 0x00A5 + SCI5.RDR + 0x00A5 + + + 0x00C3 + SCI6.TDR + 0x00C3 + + + 0x00C5 + SCI6.RDR + 0x00C5 + + + 0x00E3 + SCI7.TDR + 0x00E3 + + + 0x00E5 + SCI7.RDR + 0x00E5 + + + 0x0103 + SCI8.TDR + 0x0103 + + + 0x0105 + SCI8.RDR + 0x0105 + + + 0x0123 + SCI9.TDR + 0x0123 + + + 0x0125 + SCI9.RDR + 0x0125 + + + others + Settings other than above are prohibited. + true + + + + + + + + + R_CTSU + Capacitive Touch Sensing Unit + 0x40081000 + + 0x00000000 + 0x01E + registers + + + + CTSUCR0 + CTSU Control Register 0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CTSUTXVSEL + CTSU Transmission power supply selection + 7 + 7 + read-write + + + 0 + Select Vcc + #0 + + + 1 + Select internal logic power supply + #1 + + + + + CTSUINIT + CTSU Control Block Initialization + 4 + 4 + read-write + + + 0 + Writing a 0 has no effect, this bit is read as 0. + #0 + + + 1 + initializes the CTSU control block and registers. + #1 + + + + + CTSUIOC + CTSU Transmit Pin Control + 3 + 3 + read-write + + + 0 + Low-level output from transmit channel non-measurement pin. + #0 + + + 1 + High-level output from transmit channel non-measurement pin. + #1 + + + + + CTSUSNZ + CTSU Wait State Power-Saving Enable + 2 + 2 + read-write + + + 0 + Power-saving function during wait state is disabled. + #0 + + + 1 + Power-saving function during wait state is enabled. + #1 + + + + + CTSUCAP + CTSU Measurement Operation Start Trigger Select + 1 + 1 + read-write + + + 0 + Software trigger. + #0 + + + 1 + External trigger. + #1 + + + CTSUSTRT CTSU Measurement Operation Start @@ -39896,227 +48479,5304 @@ FMS2,1,0: - 256 - 0x4 - GR1_CLUT0[%s] - Color Palette 0 Plane for Graphics 1 Plane - 0x0000 + 256 + 0x4 + GR1_CLUT0[%s] + Color Palette 0 Plane for Graphics 1 Plane + 0x0000 + 32 + read-write + 0x00000000 + 0x00000000 + + + A + Alpha Blending Value of Color Palette n Plane for Graphics m Plane + 24 + 31 + read-write + + + R + R Value of Color Palette n Plane for Graphics m Plane + 16 + 23 + read-write + + + G + G Value of Color Palette n Plane for Graphics m Plane + 8 + 15 + read-write + + + B + B Value of Color Palette n Plane for Graphics m Plane + 0 + 7 + read-write + + + + + GR1_CLUT1[%s] + Color Palette 1 Plane for Graphics 1 Plane + 0x0400 + + + + GR2_CLUT0[%s] + Color Palette 0 Plane for Graphics 2 Plane + 0x0800 + + + + GR2_CLUT1[%s] + Color Palette 1 Plane for Graphics 2 Plane + 0x0C00 + + + + + + R_GPT0 + General PWM Timer + 0x40078000 + + 0x00000000 + 0x0A4 + registers + + + + GTWP + General PWM Timer Write-Protection Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRKEY + GTWP Key Code + 8 + 15 + write-only + + + 0xA5 + Written to these bits, the WP bits write is permitted. + 0xA5 + + + others + The WP bits write is not permitted. + true + + + + + WP + Register Write Disable + 0 + 0 + read-write + + + 0 + Write to the register is enabled + #0 + + + 1 + Write to the register is disabled + #1 + + + + + STRWP + GTSTR.CSTRT Bit Write Disable + 1 + 1 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + STPWP + GTSTP.CSTOP Bit Write Disable + 2 + 2 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + CLRWP + GTCLR.CCLR Bit Write Disable + 3 + 3 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + CMNWP + Common Register Write Disabled + 4 + 4 + read-write + + + 0 + Write to the register is enabled + #0 + + + 1 + Write to the register is disabled + #1 + + + + + + + GTSTR + General PWM Timer Software Start Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CSTRT%s + Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. + 0 + 0 + read-write + + + 0 + No effect (write) / counter stop (read) + #0 + + + 1 + GTCNT counter starts (write) / Counter running (read) + #1 + + + + + + + GTSTP + General PWM Timer Software Stop Register + 0x08 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + 14 + 1 + CSTOP%s + Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. + 0 + 0 + read-write + + + 0 + No effect (write) / counter running (read) + #0 + + + 1 + GPT GTCNT counter stops (write) / Counter stop (read) + #1 + + + + + + + GTCLR + General PWM Timer Software Clear Register + 0x0C + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CCLR%s + Channel GTCNT Count Clear + 0 + 0 + write-only + + + 0 + No effect + #0 + + + 1 + GPT GTCNT counter clears + #1 + + + + + + + GTSSR + General PWM Timer Start Source Select Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTRT + Software Source Counter Start Enable + 31 + 31 + read-write + + + 0 + Counter start is disable by the GTSTR register + #0 + + + 1 + Counter start is enable by the GTSTR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + SSELC%s + ELC_GPT Event Source Counter Start Enable + 16 + 16 + read-write + + + 0 + Counter start is disable at the ELC_GPT input + #0 + + + 1 + Counter start is enable at the ELC_GPT input + #1 + + + + + SSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable + 15 + 15 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable + 14 + 14 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable + 13 + 13 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable + 12 + 12 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable + 11 + 11 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable + 10 + 10 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + SSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable + 9 + 9 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable + 8 + 8 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sF + GTETRG Pin Falling Input Source Counter Start Enable + 1 + 1 + read-write + + + 0 + Counter start is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter start is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sR + GTETRG Pin Rising Input Source Counter Start Enable + 0 + 0 + read-write + + + 0 + Counter start is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter start is enable at the rising edge of GTETRG input + #1 + + + + + + + GTPSR + General PWM Timer Stop Source Select Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTOP + Software Source Counter Stop Enable + 31 + 31 + read-write + + + 0 + Counter stop is disable by the GTSTP register + #0 + + + 1 + Counter stop is enable by the GTSTP register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + PSELC%s + ELC_GPTA Event Source Counter Stop Enable + 16 + 16 + read-write + + + 0 + Counter stop is disable at the ELC_GPTA input + #0 + + + 1 + Counter stop is enable at the ELC_GPTA input + #1 + + + + + PSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable + 15 + 15 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable + 14 + 14 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable + 13 + 13 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable + 12 + 12 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable + 11 + 11 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable + 10 + 10 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + PSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable + 9 + 9 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable + 8 + 8 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sF + GTETRG Pin Falling Input Source Counter Stop Enable + 1 + 1 + read-write + + + 0 + Counter stop is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sR + GTETRG Pin Rising Input Source Counter Stop Enable + 0 + 0 + read-write + + + 0 + Counter stop is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the rising edge of GTETRG input + #1 + + + + + + + GTCSR + General PWM Timer Clear Source Select Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCLR + Software Source Counter Clear Enable + 31 + 31 + read-write + + + 0 + Counter clear is disable by the GTCLR register + #0 + + + 1 + Counter clear is enable by the GTCLR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + CSELC%s + ELC_GPTA Event Source Counter Clear Enable + 16 + 16 + read-write + + + 0 + Counter clear is disable at the ELC_GPTA input + #0 + + + 1 + Counter clear is enable at the ELC_GPTA input + #1 + + + + + CSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable + 15 + 15 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable + 14 + 14 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable + 13 + 13 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable + 12 + 12 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable + 11 + 11 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable + 10 + 10 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + CSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable + 9 + 9 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable + 8 + 8 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sF + GTETRG Pin Falling Input Source Counter Clear Enable + 1 + 1 + read-write + + + 0 + Counter clear is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sR + GTETRG Pin Rising Input Source Counter Clear Enable + 0 + 0 + read-write + + + 0 + Counter clear is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the rising edge of GTETRG input + #1 + + + + + + + GTUPSR + General PWM Timer Up Count Source Select Register + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + USELC%s + ELC_GPT Event Source Counter Count Up Enable + 16 + 16 + read-write + + + 0 + Counter count up is disable at the ELC_GPT input + #0 + + + 1 + Counter count up is enable at the ELC_GPT input + #1 + + + + + USCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable + 15 + 15 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable + 14 + 14 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable + 13 + 13 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable + 12 + 12 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable + 11 + 11 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable + 10 + 10 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + USCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable + 9 + 9 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable + 8 + 8 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sF + GTETRG Pin Falling Input Source Counter Count Up Enable + 1 + 1 + read-write + + + 0 + Counter count up is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sR + GTETRG Pin Rising Input Source Counter Count Up Enable + 0 + 0 + read-write + + + 0 + Counter count up is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the rising edge of GTETRG input + #1 + + + + + + + GTDNSR + General PWM Timer Down Count Source Select Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + DSELC%s + ELC_GPT Event Source Counter Count Down Enable + 16 + 16 + read-write + + + 0 + Counter count down is disable at the ELC_GPT input + #0 + + + 1 + Counter count down is enable at the ELC_GPT input + #1 + + + + + DSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable + 15 + 15 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable + 14 + 14 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable + 13 + 13 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable + 12 + 12 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable + 11 + 11 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable + 10 + 10 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + DSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable + 9 + 9 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable + 8 + 8 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sF + GTETRG Pin Falling Input Source Counter Count Down Enable + 1 + 1 + read-write + + + 0 + Counter count down is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sR + GTETRG Pin Rising Input Source Counter Count Down Enable + 0 + 0 + read-write + + + 0 + Counter count down is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the rising edge of GTETRG input + #1 + + + + + + + GTICASR + General PWM Timer Input Capture Source Select Register A + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + ASELC%s + ELC_GPT Event Source GTCCRA Input Capture Enable + 16 + 16 + read-write + + + 0 + GTCCRA input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRA input capture is enable at the ELC_GPT input + #1 + + + + + ASCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 15 + 15 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + ASCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 14 + 14 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + ASCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 13 + 13 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + ASCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 12 + 12 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + ASCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 11 + 11 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 10 + 10 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + ASCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 8 + 8 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + ASGTRG%sF + GTETRG Pin Falling Input Source GTCCRA Input Capture Enable + 1 + 1 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + ASGTRG%sR + GTETRG Pin Rising Input Source GTCCRA Input Capture Enable + 0 + 0 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTETRG input + #1 + + + + + + + GTICBSR + General PWM Timer Input Capture Source Select Register B + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + BSELC%s + ELC_GPT Event Source GTCCRB Input Capture Enable + 16 + 16 + read-write + + + 0 + GTCCRB input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRB input capture is enable at the ELC_GPT input + #1 + + + + + BSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 15 + 15 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + BSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 14 + 14 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + BSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 13 + 13 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + BSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 12 + 12 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + BSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 11 + 11 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + BSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 10 + 10 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + BSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + BSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 8 + 8 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + BSGTRG%sF + GTETRG Pin Falling Input Source GTCCRB Input Capture Enable + 1 + 1 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + BSGTRG%sR + GTETRG Pin Rising Input Source GTCCRB Input Capture Enable + 0 + 0 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTETRG input + #1 + + + + + + + GTCR + General PWM Timer Control Register + 0x2C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPCS + Timer Prescaler Select + 23 + 26 + read-write + + + 0000 + PCLK/1 + #0000 + + + 0001 + PCLK/2 + #0001 + + + 0010 + PCLK/4 + #0010 + + + 0011 + PCLK/8 + #0011 + + + 0100 + PCLK/16 + #0100 + + + 0101 + PCLK/32 + #0101 + + + 0110 + PCLK/64 + #0110 + + + 1000 + PCLK/256 + #1000 + + + 1010 + PCLK/1024 + #1010 + + + 1100 + GTETRGA + #1100 + + + 1101 + GTETRGB + #1101 + + + 1110 + GTETRGC + #1110 + + + 1111 + GTETRGD + #1111 + + + others + Setting prohibied + true + + + + + MD + Mode Select + 16 + 18 + read-write + + + 000 + Saw-wave PWM mode (single buffer or double buffer possible) + #000 + + + 001 + Saw-wave one-shot pulse mode (fixed buffer operation) + #001 + + + 010 + Setting prohibited + #010 + + + 011 + Setting prohibited + #011 + + + 100 + Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) + #100 + + + 101 + Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) + #101 + + + 110 + Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) + #110 + + + 111 + Setting prohibited + #111 + + + + + CST + Count Start + 0 + 0 + read-write + + + 0 + Count operation is stopped + #0 + + + 1 + Count operation is performed + #1 + + + + + + + GTUDDTYC + General PWM Timer Count Direction and Duty Setting Register + 0x30 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + OBDTYR + GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 27 + 27 + read-write + + + 0 + Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + #0 + + + 1 + Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + #1 + + + + + OBDTYF + Forcible GTIOCB Output Duty Setting + 26 + 26 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + OBDTY + GTIOCB Output Duty Setting + 24 + 25 + read-write + + + 00 + GTIOCB pin duty is depend on compare match + #00 + + + 01 + GTIOCB pin duty is depend on compare match + #01 + + + 10 + GTIOCB pin duty 0 percent + #10 + + + 11 + GTIOCB pin duty 100 percent + #11 + + + + + OADTYR + GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 19 + 19 + read-write + + + 0 + Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + #0 + + + 1 + Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + #1 + + + + + OADTYF + Forcible GTIOCA Output Duty Setting + 18 + 18 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + OADTY + GTIOCA Output Duty Setting + 16 + 17 + read-write + + + 00 + GTIOCA pin duty is depend on compare match + #00 + + + 01 + GTIOCA pin duty is depend on compare match + #01 + + + 10 + GTIOCA pin duty 0 percent + #10 + + + 11 + GTIOCA pin duty 100 percent + #11 + + + + + UDF + Forcible Count Direction Setting + 1 + 1 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + UD + Count Direction Setting + 0 + 0 + read-write + + + 0 + GTCNT counts down. + #0 + + + 1 + GTCNT counts up. + #1 + + + + + + + GTIOR + General PWM Timer I/O Control Register + 0x34 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NFCSB + Noise Filter B Sampling Clock Select + 30 + 31 + read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFBEN + Noise Filter B Enable + 29 + 29 + read-write + + + 0 + The noise filter for the GTIOCB pin is disabled. + #0 + + + 1 + The noise filter for the GTIOCB pin is enabled. + #1 + + + + + OBDF + GTIOCB Pin Disable Value Setting + 25 + 26 + read-write + + + 00 + Output disable is prohibited. + #00 + + + 01 + GTIOCB pin is set to Hi-Z when output disable is performed. + #01 + + + 10 + GTIOCB pin is set to 0 when output disable is performed. + #10 + + + 11 + GTIOCB pin is set to 1 when output disable is performed. + #11 + + + + + OBE + GTIOCB Pin Output Enable + 24 + 24 + read-write + + + 0 + Output is disabled + #0 + + + 1 + Output is enabled + #1 + + + + + OBHLD + GTIOCB Pin Output Setting at the Start/Stop Count + 23 + 23 + read-write + + + 0 + The GTIOCB pin output level at start/stop of counting depends on the register setting. + #0 + + + 1 + The GTIOCB pin output level is retained at start/stop of counting. + #1 + + + + + OBDFLT + GTIOCB Pin Output Value Setting at the Count Stop + 22 + 22 + read-write + + + 0 + The GTIOCB pin outputs low when counting is stopped. + #0 + + + 1 + The GTIOCB pin outputs high when counting is stopped. + #1 + + + + + GTIOB + GTIOCB Pin Function Select + 16 + 20 + read-write + + + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. + #00000 + + + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. + #00001 + + + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. + #00010 + + + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. + #00011 + + + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. + #00100 + + + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. + #00101 + + + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. + #00110 + + + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. + #00111 + + + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. + #01000 + + + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. + #01001 + + + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRB compare match. + #01010 + + + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. + #01011 + + + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. + #01100 + + + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. + #01101 + + + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. + #01110 + + + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #01111 + + + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. + #10000 + + + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. + #10001 + + + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. + #10010 + + + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRB compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRB compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRB compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #11111 + + + + + NFCSA + Noise Filter A Sampling Clock Select + 14 + 15 + read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFAEN + Noise Filter A Enable + 13 + 13 + read-write + + + 0 + The noise filter for the GTIOCA pin is disabled. + #0 + + + 1 + The noise filter for the GTIOCA pin is enabled. + #1 + + + + + OADF + GTIOCA Pin Disable Value Setting + 9 + 10 + read-write + + + 00 + Output disable is prohibited. + #00 + + + 01 + GTIOCA pin is set to Hi-Z when output disable is performed. + #01 + + + 10 + GTIOCA pin is set to 0 when output disable is performed. + #10 + + + 11 + GTIOCA pin is set to 1 when output disable is performed. + #11 + + + + + OAE + GTIOCA Pin Output Enable + 8 + 8 + read-write + + + 0 + Output is disabled + #0 + + + 1 + Output is enabled + #1 + + + + + OAHLD + GTIOCA Pin Output Setting at the Start/Stop Count + 7 + 7 + read-write + + + 0 + The GTIOCA pin output level at start/stop of counting depends on the register setting. + #0 + + + 1 + The GTIOCA pin output level is retained at start/stop of counting. + #1 + + + + + OADFLT + GTIOCA Pin Output Value Setting at the Count Stop + 6 + 6 + read-write + + + 0 + The GTIOCA pin outputs low when counting is stopped. + #0 + + + 1 + The GTIOCA pin outputs high when counting is stopped. + #1 + + + + + GTIOA + GTIOCA Pin Function Select + 0 + 4 + read-write + + + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. + #00000 + + + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. + #00001 + + + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. + #00010 + + + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. + #00011 + + + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. + #00100 + + + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. + #00101 + + + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. + #00110 + + + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. + #00111 + + + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. + #01000 + + + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. + #01001 + + + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRA compare match. + #01010 + + + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. + #01011 + + + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. + #01100 + + + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. + #01101 + + + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. + #01110 + + + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #01111 + + + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. + #10000 + + + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. + #10001 + + + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. + #10010 + + + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRA compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRA compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRA compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #11111 + + + + + + + GTINTAD + General PWM Timer Interrupt Output Setting Register + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GRPABL + Same Time Output Level Low Disable Request Enable + 30 + 30 + read-write + + + 0 + Same time output level low disable request is disabled. + #0 + + + 1 + Same time output level low disable request is enabled. + #1 + + + + + GRPABH + Same Time Output Level High Disable Request Enable + 29 + 29 + read-write + + + 0 + Same time output level high disable request is disabled. + #0 + + + 1 + Same time output level high disable request is enabled. + #1 + + + + + GRPDTE + Dead Time Error Output Disable Request Enable + 28 + 28 + read-write + + + 0 + Disable dead time error output disable request + #0 + + + 1 + Enable dead time error output disable request + #1 + + + + + GRP + Output Disable Source Select + 24 + 25 + read-write + + + 00 + Group A output disable request + #00 + + + 01 + Group B output disable request + #01 + + + 10 + Group C output disable request + #10 + + + 11 + Group D output disable request + #11 + + + others + Setting prohibited + true + + + + + GTINTPC + Period Count Function Finish Interrupt Enable + 31 + 31 + read-write + + + 0 + Interrupt request is disabled + #0 + + + 1 + Interrupt request is enabled + #1 + + + + + + + GTST + General PWM Timer Status Register + 0x3C + 32 + read-write + 0x00008000 + 0xFFFFFFFF + + + OABLF + Same Time Output Level Low Disable Request Enable + 30 + 30 + read-only + + + 0 + GTIOCA pin and GTIOCB pin don't output 0 at the same time. + #0 + + + 1 + GTIOCA pin and GTIOCB pin output 0 at the same time. + #1 + + + + + OABHF + Same Time Output Level High Disable Request Enable + 29 + 29 + read-only + + + 0 + GTIOCA pin and GTIOCB pin don't output 1 at the same time. + #0 + + + 1 + GTIOCA pin and GTIOCB pin output 1 at the same time. + #1 + + + + + DTEF + Dead Time Error Flag + 28 + 28 + read-only + + + 0 + No dead time error has occurred. + #0 + + + 1 + A dead time error has occurred. + #1 + + + + + ODF + Output Disable Flag + 24 + 24 + read-only + + + 0 + No output disable request is generated. + #0 + + + 1 + An output disable request is generated. + #1 + + + + + ADTRBDF + GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag + 19 + 19 + read-write + + + 0 + No compare match of GTADTRB at down-counting is generated. + #0 + + + 1 + A compare match of GTADTRB at down-counting is generated. + #1 + + + + + ADTRBUF + GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag + 18 + 18 + read-write + + + 0 + No compare match of GTADTRB at up-counting is generated. + #0 + + + 1 + A compare match of GTADTRB at up-counting is generated. + #1 + + + + + ADTRADF + GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag + 17 + 17 + read-write + + + 0 + No compare match of GTADTRA at down-counting is generated. + #0 + + + 1 + A compare match of GTADTRA at down-counting is generated. + #1 + + + + + ADTRAUF + GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable + 16 + 16 + read-write + + + 0 + No compare match of GTADTRA at up-counting is generated. + #0 + + + 1 + A compare match of GTADTRA at up-counting is generated. + #1 + + + + + TUCF + Count Direction Flag + 15 + 15 + read-only + + + 0 + The GTCNT counter counts downward. + #0 + + + 1 + The GTCNT counter counts upward. + #1 + + + + + ITCNT + GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) + 8 + 10 + read-only + + + TCFPU + Underflow Flag + 7 + 7 + read-write + + + 0 + No underflow (trough) has occurred. + #0 + + + 1 + An underflow (trough) has occurred. + #1 + + + + + TCFPO + Overflow Flag + 6 + 6 + read-write + + + 0 + No overflow (crest) has occurred. + #0 + + + 1 + An overflow (crest) has occurred. + #1 + + + + + TCFF + Input Compare Match Flag F + 5 + 5 + read-write + + + 0 + No compare match of GTCCRF is generated. + #0 + + + 1 + A compare match of GTCCRF is generated. + #1 + + + + + TCFE + Input Compare Match Flag E + 4 + 4 + read-write + + + 0 + No compare match of GTCCRE is generated. + #0 + + + 1 + A compare match of GTCCRE is generated. + #1 + + + + + TCFD + Input Compare Match Flag D + 3 + 3 + read-write + + + 0 + No compare match of GTCCRD is generated. + #0 + + + 1 + A compare match of GTCCRD is generated. + #1 + + + + + TCFC + Input Compare Match Flag C + 2 + 2 + read-write + + + 0 + No compare match of GTCCRC is generated. + #0 + + + 1 + A compare match of GTCCRC is generated. + #1 + + + + + TCFB + Input Capture/Compare Match Flag B + 1 + 1 + read-write + + + 0 + No input capture/compare match of GTCCRB is generated. + #0 + + + 1 + An input capture/compare match of GTCCRB is generated. + #1 + + + + + TCFA + Input Capture/Compare Match Flag A + 0 + 0 + read-write + + + 0 + No input capture/compare match of GTCCRA is generated. + #0 + + + 1 + An input capture/compare match of GTCCRA is generated. + #1 + + + + + PCF + Period Count Function Finish Flag + 31 + 31 + read-write + + + 0 + No period count function finish has occurred + #0 + + + 1 + A period count function finish has occurred + #1 + + + + + + + GTBER + General PWM Timer Buffer Enable Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADTDB + GTADTRB Double Buffer Operation + 30 + 30 + read-write + + + 0 + Single buffer operation (GTADTBRB --> GTADTRB) + #0 + + + 1 + Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) + #1 + + + + + ADTTB + GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 28 + 29 + read-write + + + 00 + No transfer + #00 + + + 01 + Transfer at crest + #01 + + + 10 + Transfer at trough + #10 + + + 11 + Transfer at both crest and trough + #11 + + + + + ADTDA + GTADTRA Double Buffer Operation + 26 + 26 + read-write + + + 0 + Single buffer operation (GTADTBRA --> GTADTRA) + #0 + + + 1 + Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) + #1 + + + + + ADTTA + GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 24 + 25 + read-write + + + 00 + No transfer + #00 + + + 01 + Transfer at crest + #01 + + + 10 + Transfer at trough + #10 + + + 11 + Transfer at both crest and trough + #11 + + + + + CCRSWT + GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. + 22 + 22 + write-only + + + 0 + no effect + #0 + + + 1 + Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. + #1 + + + + + PR + GTPR Buffer Operation + 20 + 21 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTPBR --> GTPR) + #01 + + + others + Setting prohibited + true + + + + + CCRB + GTCCRB Buffer Operation + 18 + 19 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTCCRB <--> GTCCRE) + #01 + + + 10 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #10 + + + 11 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #11 + + + + + CCRA + GTCCRA Buffer Operation + 16 + 17 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTCCRA <--> GTCCRC) + #01 + + + 10 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #10 + + + 11 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #11 + + + + + BD3 + BD[3]: GTDV Buffer Operation DisableBD[2] + 3 + 3 + read-write + + + 0 + Enable buffer operation + #0 + + + 1 + Disable buffer operation + #1 + + + + + BD2 + BD[2]: GTADTR Buffer Operation DisableBD + 2 + 2 + read-write + + + 0 + Enable buffer operation + #0 + + + 1 + Disable buffer operation + #1 + + + + + BD1 + BD[1]: GTPR Buffer Operation Disable + 1 + 1 + read-write + + + 0 + Buffer operation is enabled + #0 + + + 1 + Buffer operation is disabled + #1 + + + + + BD0 + BD[0]: GTCCR Buffer Operation Disable + 0 + 0 + read-write + + + 0 + Buffer operation is enabled + #0 + + + 1 + Buffer operation is disabled + #1 + + + + + + + GTITC + General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register + 0x44 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADTBL + GTADTRB A/D Converter Start Request Link + 14 + 14 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ADTAL + GTADTRA A/D Converter Start Request Link + 12 + 12 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function + #1 + + + + + IVTT + GPT_OVF/GPT_UDF Interrupt Skipping Count Select + 8 + 10 + read-write + + + 000 + No skipping + #000 + + + 001 + Skipping count of 1 + #001 + + + 010 + Skipping count of 2 + #010 + + + 011 + Skipping count of 3 + #011 + + + 100 + Skipping count of 4 + #100 + + + 101 + Skipping count of 5 + #101 + + + 110 + Skipping count of 6 + #110 + + + 111 + Skipping count of 7. + #111 + + + + + IVTC + GPT_OVF/GPT_UDF Interrupt Skipping Function Select + 6 + 7 + read-write + + + 00 + Do not perform skipping + #00 + + + 01 + Count and skip both overflow and underflow for saw waves and crest for triangle waves + #01 + + + 10 + Count and skip both overflow and underflow for saw waves and trough for triangle waves + #10 + + + 11 + Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. + #11 + + + + + ITLF + GTCCRF Compare Match Interrupt Link + 5 + 5 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLE + GTCCRE Compare Match Interrupt Link + 4 + 4 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLD + GTCCRD Compare Match Interrupt Link + 3 + 3 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLC + GTCCRC Compare Match Interrupt Link + 2 + 2 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLB + GTCCRB Compare Match/Input Capture Interrupt Link + 1 + 1 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLA + GTCCRA Compare Match/Input Capture Interrupt Link + 0 + 0 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + + + GTCNT + General PWM Timer Counter + 0x48 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GTCNT + Counter + 0 + 31 + read-write + + + + + 6 + 4 + + + A + A + 0 + + + B + B + 1 + + + C + C + 2 + + + E + E + 3 + + + D + D + 4 + + + F + F + 5 + + + GTCCR[%s] + General PWM Timer Compare Capture Register + 0x4C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTCCR + Compare Capture Register A + 0 + 31 + read-write + + + + + GTPR + General PWM Timer Cycle Setting Register + 0x64 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPR + Cycle Setting Register + 0 + 31 + read-write + + + + + GTPBR + General PWM Timer Cycle Setting Buffer Register + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPBR + Cycle Setting Buffer Register + 0 + 31 + read-write + + + + + GTPDBR + General PWM Timer Cycle Setting Double-Buffer Register + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPDBR + Cycle Setting Double-Buffer Register + 0 + 31 + read-write + + + + + GTADTRA + A/D Converter Start Request Timing Register A + 0x70 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRA + A/D Converter Start Request Timing Register A + 0 + 31 + read-write + + + + + GTADTRB + A/D Converter Start Request Timing Register B + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRB + A/D Converter Start Request Timing Register B + 0 + 31 + read-write + + + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0 + 31 + read-write + + + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0 + 31 + read-write + + + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0 + 31 + read-write + + + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0 + 31 + read-write + + + + + GTDTCR + General PWM Timer Dead Time Control Register + 0x88 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDFER + GTDVD Setting + 8 + 8 + read-write + + + 0 + Set GTDVU and GTDVD separately + #0 + + + 1 + Automatically set the value written to GTDVU to GTDVD + #1 + + + + + TDBDE + GTDVD Buffer Operation Enable + 5 + 5 + read-write + + + 0 + Disable GTDVD buffer operation + #0 + + + 1 + Enable GTDVD buffer operation + #1 + + + + + TDBUE + GTDVU Buffer Operation Enable + 4 + 4 + read-write + + + 0 + Disable GTDVU buffer operation + #0 + + + 1 + Enable GTDVU buffer operation + #1 + + + + + TDE + Negative-Phase Waveform Setting + 0 + 0 + read-write + + + 0 + GTCCRB is set without using GTDVU and GTDVD. + #0 + + + 1 + GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. + #1 + + + + + + + GTDVU + General PWM Timer Dead Time Value Register U + 0x8C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVU + Dead Time Value Register U + 0 + 31 + read-write + + + + + GTDVD + General PWM Timer Dead Time Value Register D + 0x90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVD + Dead Time Value Register D + 0 + 31 + read-write + + + + + GTDBU + General PWM Timer Dead Time Buffer Register U + 0x94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVU + Dead Time Buffer Register U + 0 + 31 + read-write + + + + + GTDBD + General PWM Timer Dead Time Buffer Register D + 0x98 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDBD + Dead Time Buffer Register D + 0 + 31 + read-write + + + + + GTSOS + General PWM Timer Output Protection Function Status Register + 0x9C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SOS + Output Protection Function Status + 0 + 1 + read-only + + + 00 + Normal operation + #00 + + + 01 + Protected state (GTCCRA = 0 is set during transfer at trough or crest) + #01 + + + 10 + Protected state (GTCCRA >= GTPR is set during transfer at trough) + #10 + + + 11 + Protected state (GTCCRA >= GTPR is set during transfer at crest) + #11 + + + + + + + GTSOTR + General PWM Timer Output Protection Function Temporary Release Register + 0xA0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SOTR + Output Protection Function Temporary Release + 0 + 0 + read-write + + + 0 + Do not release protected state + #0 + + + 1 + Release protected state + #1 + + + + + + + GTICLF + General PWM Timer Inter Channel Logical Operation Function Setting Register + 0xB8 + 32 + read-write + 0x00000000 + 0xffffffff + + + ICLFA + GTIOCnA Output Logical Operation Function Select + 0 + 2 + read-write + + + 000 + A (no delay) + #000 + + + 001 + NOT A (no delay) + #001 + + + 010 + C (1PCLKGPT delay) + #010 + + + 011 + NOT C (1PCLKGPT delay) + #011 + + + 100 + A AND C (1PCLKGPT delay) + #100 + + + 101 + A OR C (1PCLKGPT delay) + #101 + + + 110 + A EXOR C (1PCLKGPT delay) + #110 + + + 111 + A NOR C (1PCLKGPT delay) + #111 + + + + + ICLFSELC + Inter Channel Signal C Select + 4 + 9 + read-write + + + 0x00 + GTIOC0A + 0x00 + + + 0x01 + GTIOC0B + 0x01 + + + 0x02 + GTIOC1A + 0x02 + + + 0x03 + GTIOC1B + 0x03 + + + 0x04 + GTIOC2A + 0x04 + + + 0x05 + GTIOC2B + 0x05 + + + 0x06 + GTIOC3A + 0x06 + + + 0x07 + GTIOC3B + 0x07 + + + 0x08 + GTIOC4A + 0x08 + + + 0x09 + GTIOC4B + 0x09 + + + 0x0A + GTIOC5A + 0x0a + + + 0x0B + GTIOC5B + 0x0b + + + 0x0C + GTIOC6A + 0x0c + + + 0x0D + GTIOC6B + 0x0d + + + 0x0E + GTIOC7A + 0x0e + + + 0x0F + GTIOC7B + 0x0f + + + 0x10 + GTIOC8A + 0x10 + + + 0x11 + GTIOC8B + 0x11 + + + 0x12 + GTIOC9A + 0x12 + + + 0x13 + GTIOC9B + 0x13 + + + Others + Setting prohibited + true + + + + + ICLFB + GTIOCnB Output Logical Operation Function Select + 16 + 18 + read-write + + + 000 + B (no delay) + #000 + + + 001 + NOT B (no delay) + #001 + + + 010 + D (1PCLKGPT delay) + #010 + + + 011 + NOT D (1PCLKGPT delay) + #011 + + + 100 + B AND D (1PCLKGPT delay) + #100 + + + 101 + B OR D (1PCLKGPTn delay) + #101 + + + 110 + B EXOR D (1PCLKGPT delay) + #110 + + + 111 + B NOR D (1PCLKGPT delay) + #111 + + + + + ICLFSELD + Inter Channel Signal D Select + 20 + 25 + read-write + + + 0x00 + GTIOC0A + 0x00 + + + 0x01 + GTIOC0B + 0x01 + + + 0x02 + GTIOC1A + 0x02 + + + 0x03 + GTIOC1B + 0x03 + + + 0x04 + GTIOC2A + 0x04 + + + 0x05 + GTIOC2B + 0x05 + + + 0x06 + GTIOC3A + 0x06 + + + 0x07 + GTIOC3B + 0x07 + + + 0x08 + GTIOC4A + 0x08 + + + 0x09 + GTIOC4B + 0x09 + + + 0x0A + GTIOC5A + 0x0a + + + 0x0B + GTIOC5B + 0x0b + + + 0x0C + GTIOC6A + 0x0c + + + 0x0D + GTIOC6B + 0x0d + + + 0x0E + GTIOC7A + 0x0e + + + 0x0F + GTIOC7B + 0x0f + + + 0x10 + GTIOC8A + 0x10 + + + 0x11 + GTIOC8B + 0x11 + + + 0x12 + GTIOC9A + 0x12 + + + 0x13 + GTIOC9B + 0x13 + + + Others + Setting prohibited + true + + + + + + + GTPC + General PWM Timer Period Count Register + 0xBC 32 read-write 0x00000000 - 0x00000000 + 0xffffffff - A - Alpha Blending Value of Color Palette n Plane for Graphics m Plane - 24 - 31 + PCEN + Period Count Function Enable + 0 + 0 + read-write + + + 0 + Period count function is disabled + #0 + + + 1 + Period count function is enabled + #1 + + + + + ASTP + Automatic Stop Function Enable + 8 + 8 read-write + + + 0 + Automatic stop function is disabled + #0 + + + 1 + Automatic stop function is enabled + #1 + + - R - R Value of Color Palette n Plane for Graphics m Plane + PCNT + Period Counter 16 - 23 + 27 + read-write + + + + + GTSECSR + General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register + 0xD0 + 32 + read-write + 0x00000000 + 0xffffffff + + + SECSEL0 + Channel 0 Operation Enable Bit Simultaneous Control Channel Select + 0 + 0 read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + - G - G Value of Color Palette n Plane for Graphics m Plane + SECSEL1 + Channel 1 Operation Enable Bit Simultaneous Control Channel Select + 1 + 1 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL2 + Channel 2 Operation Enable Bit Simultaneous Control Channel Select + 2 + 2 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL3 + Channel 3 Operation Enable Bit Simultaneous Control Channel Select + 3 + 3 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL4 + Channel 4 Operation Enable Bit Simultaneous Control Channel Select + 4 + 4 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL5 + Channel 5 Operation Enable Bit Simultaneous Control Channel Select + 5 + 5 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL6 + Channel 6 Operation Enable Bit Simultaneous Control Channel Select + 6 + 6 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL7 + Channel 7 Operation Enable Bit Simultaneous Control Channel Select + 7 + 7 + read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + + + + SECSEL8 + Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 - 15 + 8 read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + - B - B Value of Color Palette n Plane for Graphics m Plane - 0 - 7 + SECSEL9 + Channel 9 Operation Enable Bit Simultaneous Control Channel Select + 9 + 9 read-write + + + 0 + Disable simultaneous control + #0 + + + 1 + Enable simultaneous control + #1 + + - - GR1_CLUT1[%s] - Color Palette 1 Plane for Graphics 1 Plane - 0x0400 - - - - GR2_CLUT0[%s] - Color Palette 0 Plane for Graphics 2 Plane - 0x0800 - - - - GR2_CLUT1[%s] - Color Palette 1 Plane for Graphics 2 Plane - 0x0C00 - - - - - - R_GPT0 - General PWM Timer - 0x40078000 - - 0x00000000 - 0x0A4 - registers - - - GTWP - General PWM Timer Write-Protection Register - 0x00 + GTSECR + General PWM Timer Operation Enable Bit Simultaneous Control Register + 0xD4 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - PRKEY - GTWP Key Code - 8 - 15 - write-only + SBDCE + GTCCR Register Buffer Operation Simultaneous Enable + 0 + 0 + read-write - 0xA5 - Written to these bits, the WP bits write is permitted. - 0xA5 + 0 + Disable simultaneous enabling GTCCR buffer operations + #0 - others - The WP bits write is not permitted. - true + 1 + Enable GTCCR register buffer operations simultaneously + #1 - WP - Register Write Disable - 0 - 0 + SBDPE + GTPR Register Buffer Operation Simultaneous Enable + 1 + 1 read-write 0 - Write to the register is enabled + Disable simultaneous enabling GTPR buffer operations #0 1 - Write to the register is disabled + Enable GTPR register buffer operations simultaneously #1 - STRWP - GTSTR.CSTRT Bit Write Disable - 1 - 1 + SBDCD + GTCCR Register Buffer Operation Simultaneous Disable + 8 + 8 read-write 0 - Write to the bit is enabled + Disable simultaneous disabling GTCCR buffer operations #0 1 - Write to the bit is disabled + Disable GTCCR register buffer operations simultaneously #1 - STPWP - GTSTP.CSTOP Bit Write Disable - 2 - 2 + SBDPD + GTPR Register Buffer Operation Simultaneous Disable + 9 + 9 read-write 0 - Write to the bit is enabled + Disable simultaneous disabling GTPR buffer operations #0 1 - Write to the bit is disabled + Disable GTPR register buffer operations simultaneously #1 - CLRWP - GTCLR.CCLR Bit Write Disable - 3 - 3 + SPCE + Period Count Function Simultaneous Enable + 16 + 16 read-write 0 - Write to the bit is enabled + Disable simultaneous enabling period count function #0 1 - Write to the bit is disabled + Enable period count function simultaneously #1 - CMNWP - Common Register Write Disabled - 4 - 4 + SPCD + Period Count Function Simultaneous Disable + 24 + 24 read-write 0 - Write to the register is enabled + Disable simultaneous disabling period count function #0 1 - Write to the register is disabled + Disable period count function simultaneously #1 + + + + R_GPT1 + 0x40078100 + + + R_GPT2 + 0x40078200 + + + R_GPT3 + 0x40078300 + + + R_GPT4 + 0x40078400 + + + R_GPT5 + 0x40078500 + + + R_GPT6 + 0x40078600 + + + R_GPT7 + 0x40078700 + + + R_GPT8 + 0x40078800 + + + R_GPT9 + 0x40078900 + + + R_GPT10 + 0x40078A00 + + + R_GPT11 + 0x40078B00 + + + R_GPT12 + 0x40078C00 + + + R_GPT13 + 0x40078D00 + + + R_GPT_ODC + PWM Delay Generation Circuit + 0x4007B000 + + 0x00000000 + 0x004 + registers + + + 0x00000018 + 0x020 + registers + + + + 4 + 4 + GTDLYR[%s] + PWM DELAY RISING + 0x18 + + A + GTIOCA Output Delay Register + 0 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + B + GTIOCB Output Delay Register + 2 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + + GTDLYF[%s] + PWM DELAY FALLING + 0x28 + - GTSTR - General PWM Timer Software Start Register - 0x04 - 32 + GTDLYCR1 + PWM Output Delay Control Register1 + 0x00 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - 14 - 1 - CSTRT%s - Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. + DLLMOD + DLL Mode Select + 8 + 8 + read-write + + + 0 + 5 bit-mode + #0 + + + 1 + 4 bit-mode + #1 + + + + + DLYRST + PWM Delay Generation Circuit Reset + 1 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Reset + #1 + + + + + DLLEN + DLL Operation Enable 0 0 read-write 0 - No effect (write) / counter stop (read) + DLL operation is disabled #0 1 - GTCNT counter starts (write) / Counter running (read) + DLL operation is enabled #1 @@ -40124,3446 +53784,3487 @@ FMS2,1,0: - GTSTP - General PWM Timer Software Stop Register - 0x08 - 32 + GTDLYCR2 + PWM Output Delay Control Register2 + 0x02 + 16 read-write - 0xFFFFFFFF - 0xFFFFFFFF + 0x0000 + 0xFFFF - 14 + 1 1 - CSTOP%s - Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. - 0 - 0 + DLYDENB%s + PWM Delay Generation Circuit Disenable for GTIOCB + 12 + 12 read-write 0 - No effect (write) / counter running (read) + Delay generation circuit of GTIOCB is based on DLYEN1. #0 1 - GPT GTCNT counter stops (write) / Counter stop (read) + Delay generation circuit of GTIOCB is disabled. #1 - - - - GTCLR - General PWM Timer Software Clear Register - 0x0C - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - 14 + 1 1 - CCLR%s - Channel GTCNT Count Clear + DLYEN%s + PWM Delay Generation Circuit enable + 8 + 8 + read-write + + + 0 + Delay generation circuit of channel is enabled + #0 + + + 1 + Delay generation circuit of channel is disabled. + #1 + + + + + 4 + 1 + DLYBS%s + PWM Delay Generation Circuit bypass 0 0 - write-only + read-write 0 - No effect + Delay generation circuit of channel is bypassed. #0 1 - GPT GTCNT counter clears + Delay generation circuit of channel is not bypassed. #1 + + + + R_GPT_OPS + Output Phase Switching for GPT + 0x40078FF0 + + 0x00000000 + 0x04 + registers + + - GTSSR - General PWM Timer Start Source Select Register - 0x10 + OPSCR + Output Phase Switching Control Register + 0x00 32 read-write 0x00000000 0xFFFFFFFF - CSTRT - Software Source Counter Start Enable - 31 + NFCS + External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. + 30 31 read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFEN + External Input Noise Filter Enable + 29 + 29 + read-write 0 - Counter start is disable by the GTSTR register + Do not use a noise filter to the external input. #0 1 - Counter start is enable by the GTSTR register + Use a noise filter to the external input. #1 - 8 - 1 - A,B,C,D,E,F,G,H - SSELC%s - ELC_GPT Event Source Counter Start Enable - 16 - 16 + GODF + Group output disable function + 26 + 26 read-write 0 - Counter start is disable at the ELC_GPT input + This bit function is ignored. #0 1 - Counter start is enable at the ELC_GPT input + Group disable will clear OPSCR.EN Bit. #1 - SSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable - 15 - 15 + GRP + Output disabled source selection + 24 + 25 read-write - 0 - Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + 00 + Select Group A output disable source + #00 + + + 01 + Select Group B output disable source + #01 + + + 10 + Select Group C output disable source + #10 - 1 - Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + 11 + Select Group D output disable source + #11 - SSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable - 14 - 14 + ALIGN + Input phase alignment + 21 + 21 read-write 0 - Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Input phase is aligned to PCLK. #0 1 - Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Input phase is aligned PWM. #1 - SSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable - 13 - 13 + RV + Output phase rotation direction reversal + 20 + 20 read-write 0 - Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + U/V/W-Phase output #0 1 - Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + Output to reverse the V / W-phase #1 - SSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable - 12 - 12 + INV + Invert-Phase Output Control + 19 + 19 read-write 0 - Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Positive Logic (Active High)output #0 1 - Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Negative Logic (Active Low)output #1 - SSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable - 11 - 11 + N + Negative-Phase Output (N) Control + 18 + 18 read-write 0 - Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + Level signal output #0 1 - Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + PWM signal output (PWM of GPT0) #1 - SSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable - 10 - 10 + P + Positive-Phase Output (P) Control + 17 + 17 read-write 0 - Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + Level signal output #0 1 - Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + PWM signal output (PWM of GPT0) #1 - SSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable - 9 - 9 + FB + External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. + 16 + 16 read-write 0 - Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Select the external input. #0 1 - Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Select the soft setting(OPSCR.UF, VF, WF). #1 - SSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable + EN + Enable-Phase Output Control 8 8 read-write 0 - Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + Not Output(Hi-Z external terminals). #0 1 - Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Output #1 - 4 - 2 - A,B,C,D - SSGTRG%sF - GTETRG Pin Falling Input Source Counter Start Enable + W + Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 6 + 6 + read-only + + + V + Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 5 + 5 + read-only + + + U + Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 4 + 4 + read-only + + + WF + Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 2 + 2 + read-write + + + VF + Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 1 1 read-write - - - 0 - Counter start is disable at the falling edge of GTETRG input - #0 - - - 1 - Counter start is enable at the falling edge of GTETRG input - #1 - - - 4 - 2 - A,B,C,D - SSGTRG%sR - GTETRG Pin Rising Input Source Counter Start Enable + UF + Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 0 0 read-write - - - 0 - Counter start is disable at the rising edge of GTETRG input - #0 - - - 1 - Counter start is enable at the rising edge of GTETRG input - #1 - - + + + + R_GPT_POEG0 + Port Output Enable for GPT + 0x40042000 + + 0x00000000 + 0x04 + registers + + - GTPSR - General PWM Timer Stop Source Select Register - 0x14 + POEGG + POEG Group Setting Register + 0x00 32 read-write 0x00000000 0xFFFFFFFF - CSTOP - Software Source Counter Stop Enable - 31 + NFCS + Noise Filter Clock Select + 30 31 read-write - 0 - Counter stop is disable by the GTSTP register - #0 + 00 + Sampling GTETRG pin input level for three times in every PCLKB. + #00 - 1 - Counter stop is enable by the GTSTP register - #1 + 01 + Sampling GTETRG pin input level for three times in every PCLKB /8. + #01 + + + 10 + Sampling GTETRG pin input level for three times in every PCLKB /32. + #10 + + + 11 + Sampling GTETRG pin input level for three times in every PCLKB /128. + #11 - 8 - 1 - A,B,C,D,E,F,G,H - PSELC%s - ELC_GPTA Event Source Counter Stop Enable - 16 - 16 + NFEN + Noise Filter Enable + 29 + 29 read-write 0 - Counter stop is disable at the ELC_GPTA input + Filtering noise disabled #0 1 - Counter stop is enable at the ELC_GPTA input + Filtering noise enabled #1 - PSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable - 15 - 15 + INV + GTETRG Input Reverse + 28 + 28 read-write 0 - Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + GTETRG Input #0 1 - Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + GTETRG Input Reversed. #1 - PSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable - 14 - 14 - read-write + ST + GTETRG Input Status Flag + 16 + 16 + read-only 0 - Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + GTETRG input after filtering is 0. #0 1 - Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + GTETRG input after filtering is 1. #1 - PSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable - 13 - 13 + 6 + 1 + CDRE%s + Comparator Disable Request Enable. Note: Can be modified only once after a reset. + 8 + 8 read-write 0 - Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + A disable request of comparator 0 disabled. #0 1 - Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + A disable request of comparator 0 enabled. #1 - PSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable - 12 - 12 + OSTPE + Oscillation Stop Detection EnableNote: Can be modified only once after a reset. + 6 + 6 read-write 0 - Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + A output-disable request from the oscillation stop detection disabled. #0 1 - Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + A output-disable request from the oscillation stop detection enabled. #1 - PSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable - 11 - 11 + IOCE + Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. + 5 + 5 read-write 0 - Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + Disable output-disable requests from GPT disable request #0 1 - Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Enable output-disable requests from GPT disable request #1 - PSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable - 10 - 10 + PIDE + Port Input Detection EnableNote: Can be modified only once after a reset. + 4 + 4 read-write 0 - Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + A output-disable request from the GTETRG pins disabled. #0 1 - Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + A output-disable request from the GTETRG pins enabled. #1 - PSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable - 9 - 9 + SSF + Software Stop Flag + 3 + 3 read-write 0 - Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + A output-disable request from software has not been generated. #0 1 - Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + A output-disable request from software has been generated. #1 - PSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable - 8 - 8 + OSTPF + Oscillation Stop Detection Flag + 2 + 2 read-write + zeroToClear + modify 0 - Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + A output-disable request from the oscillation stop detection has not been generated. #0 1 - Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + A output-disable request from the oscillation stop detection has been generated. #1 - 4 - 2 - A,B,C,D - PSGTRG%sF - GTETRG Pin Falling Input Source Counter Stop Enable + IOCF + Real Time Overcurrent Detection Flag 1 1 read-write + zeroToClear + modify 0 - Counter stop is disable at the falling edge of GTETRG input + A output-disable request from GPT disable request or comparator interrupt has not been generated. #0 1 - Counter stop is enable at the falling edge of GTETRG input + A output-disable request from GPT disable request or comparator interrupt has been generated. #1 - 4 - 2 - A,B,C,D - PSGTRG%sR - GTETRG Pin Rising Input Source Counter Stop Enable + PIDF + Port Input Detection Flag 0 0 read-write + zeroToClear + modify 0 - Counter stop is disable at the rising edge of GTETRG input + A output-disable request from the GTETRG pin has not been generated. #0 1 - Counter stop is enable at the rising edge of GTETRG input + A output-disable request from the GTETRG pin has been generated. #1 + + + + R_GPT_POEG1 + 0x40042100 + + + R_GPT_POEG2 + 0x40042200 + + + R_GPT_POEG3 + 0x40042300 + + + R_ICU + Interrupt Controller Unit + 0x40006000 + + 0x00000000 + 0x010 + registers + + + 0x00000100 + 0x01 + registers + + + 0x00000120 + 0x02 + registers + + + 0x00000130 + 0x02 + registers + + + 0x00000140 + 0x02 + registers + + + 0x000001A0 + 0x04 + registers + + + 0x00000200 + 0x02 + registers + + + 0x00000280 + 0x020 + registers + + + 0x00000300 + 0x180 + registers + + - GTCSR - General PWM Timer Clear Source Select Register - 0x18 - 32 + 16 + 0x1 + IRQCR[%s] + IRQ Control Register %s + 0x000 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - CCLR - Software Source Counter Clear Enable - 31 - 31 + FLTEN + IRQ Digital Filter Enable + 7 + 7 read-write 0 - Counter clear is disable by the GTCLR register + Digital filter disabled. #0 1 - Counter clear is enable by the GTCLR register + Digital filter enabled. #1 - 8 - 1 - A,B,C,D,E,F,G,H - CSELC%s - ELC_GPTA Event Source Counter Clear Enable - 16 - 16 + FCLKSEL + IRQ Digital Filter Sampling Clock Select + 4 + 5 read-write - 0 - Counter clear is disable at the ELC_GPTA input - #0 + 00 + PCLKB + #00 - 1 - Counter clear is enable at the ELC_GPTA input - #1 + 01 + PCLKB/8 + #01 - - - - CSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable - 15 - 15 - read-write - - 0 - Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + 10 + PCLKB/32 + #10 - 1 - Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + 11 + PCLKB/64 + #11 - CSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable - 14 - 14 + IRQMD + IRQ Detection Sense Select + 0 + 1 read-write - 0 - Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 - #0 - - - 1 - Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 - #1 + 00 + Falling edge + #00 - - - - CSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable - 13 - 13 - read-write - - 0 - Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + 01 + Rising edge + #01 - 1 - Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + 10 + Rising and falling edges + #10 + + + 11 + Low level + #11 + + + + NMISR + Non-Maskable Interrupt Status Register + 0x140 + 16 + read-only + 0x0000 + 0xFFFF + - CSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable + SPEST + CPU Stack pointer monitor Interrupt Status Flag 12 12 - read-write + read-only 0 - Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Interrupt not requested #0 1 - Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Interrupt requested. #1 - CSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable + BUSMST + MPU Bus Master Error Interrupt Status Flag 11 11 - read-write + read-only 0 - Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + Interrupt not requested #0 1 - Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Interrupt requested. #1 - CSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable + BUSSST + MPU Bus Slave Error Interrupt Status Flag 10 10 - read-write + read-only 0 - Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + Interrupt not requested #0 1 - Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Interrupt requested. #1 - CSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable + RECCST + RAM ECC Error Interrupt Status Flag 9 9 - read-write + read-only 0 - Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Interrupt not requested #0 1 - Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Interrupt requested. #1 - CSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable + RPEST + RAM Parity Error Interrupt Status Flag 8 8 - read-write + read-only 0 - Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + Interrupt not requested #0 1 - Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Interrupt requested. #1 - 4 - 2 - A,B,C,D - CSGTRG%sF - GTETRG Pin Falling Input Source Counter Clear Enable - 1 - 1 - read-write + NMIST + NMI Status Flag + 7 + 7 + read-only 0 - Counter clear is disable at the falling edge of GTETRG input + Interrupt not requested #0 1 - Counter clear is enable at the falling edge of GTETRG input + Interrupt requested. #1 - 4 - 2 - A,B,C,D - CSGTRG%sR - GTETRG Pin Rising Input Source Counter Clear Enable - 0 - 0 - read-write + OSTST + Oscillation Stop Detection Interrupt Status Flag + 6 + 6 + read-only 0 - Counter clear is disable at the rising edge of GTETRG input + Interrupt not requested for main oscillation stop #0 1 - Counter clear is enable at the rising edge of GTETRG input + Interrupt requested for main oscillation stop. #1 - - - - GTUPSR - General PWM Timer Up Count Source Select Register - 0x1C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 8 - 1 - A,B,C,D,E,F,G,H - USELC%s - ELC_GPT Event Source Counter Count Up Enable - 16 - 16 - read-write + VBATTST + VBATT monitor Interrupt Status Flag + 4 + 4 + read-only 0 - Counter count up is disable at the ELC_GPT input + Interrupt not requested #0 1 - Counter count up is enable at the ELC_GPT input + Interrupt requested. #1 - USCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable - 15 - 15 - read-write + LVD2ST + Voltage-Monitoring 2 Interrupt Status Flag + 3 + 3 + read-only 0 - Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + Interrupt not requested #0 1 - Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Interrupt requested. #1 - USCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable - 14 - 14 - read-write + LVD1ST + Voltage-Monitoring 1 Interrupt Status Flag + 2 + 2 + read-only 0 - Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Interrupt not requested #0 1 - Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Interrupt requested. #1 - USCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable - 13 - 13 - read-write + WDTST + WDT Underflow/Refresh Error Status Flag + 1 + 1 + read-only 0 - Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + Interrupt not requested #0 1 - Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + Interrupt requested. #1 - USCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable - 12 - 12 - read-write + IWDTST + IWDT Underflow/Refresh Error Status Flag + 0 + 0 + read-only 0 - Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Interrupt not requested #0 1 - Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Interrupt requested. #1 - USCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable - 11 - 11 - read-write + TZFST + 13 + 13 + read-only 0 - Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + TRUST Zone Filter Error interrupt is not requested. #0 1 - Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + TRUST Zone Filter Error interrupt is requested. #1 - USCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable - 10 - 10 - read-write + CPEST + 15 + 15 + read-only 0 - Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + Cache RAM Parity Error interrupt is not requested. #0 1 - Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Cache RAM Parity Error interrupt is requested. #1 + + + + NMIER + Non-Maskable Interrupt Enable Register + 0x120 + 16 + read-write + 0x0000 + 0xFFFF + - USCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable - 9 - 9 + SPEEN + CPU Stack pointer monitor Interrupt Enable + 12 + 12 read-write 0 - Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Disabled #0 1 - Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Enabled. #1 - USCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable - 8 - 8 + BUSMEN + MPU Bus Master Error Interrupt Enable + 11 + 11 read-write 0 - Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + Disabled #0 1 - Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Enabled. #1 - 4 - 2 - A,B,C,D - USGTRG%sF - GTETRG Pin Falling Input Source Counter Count Up Enable - 1 - 1 + BUSSEN + MPU Bus Slave Error Interrupt Enable + 10 + 10 read-write 0 - Counter count up is disable at the falling edge of GTETRG input + Disabled #0 1 - Counter count up is enable at the falling edge of GTETRG input + Enabled. #1 - 4 - 2 - A,B,C,D - USGTRG%sR - GTETRG Pin Rising Input Source Counter Count Up Enable - 0 - 0 + RECCEN + RAM ECC Error Interrupt Enable + 9 + 9 read-write 0 - Counter count up is disable at the rising edge of GTETRG input + Disabled #0 1 - Counter count up is enable at the rising edge of GTETRG input + Enabled. #1 - - - - GTDNSR - General PWM Timer Down Count Source Select Register - 0x20 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 8 - 1 - A,B,C,D,E,F,G,H - DSELC%s - ELC_GPT Event Source Counter Count Down Enable - 16 - 16 + RPEEN + RAM Parity Error Interrupt Enable + 8 + 8 read-write 0 - Counter count down is disable at the ELC_GPT input + Disabled #0 1 - Counter count down is enable at the ELC_GPT input + Enabled. #1 - DSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable - 15 - 15 + NMIEN + NMI Pin Interrupt Enable + 7 + 7 read-write 0 - Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + Disabled #0 1 - Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Enabled. #1 - DSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable - 14 - 14 + OSTEN + Oscillation Stop Detection Interrupt Enable + 6 + 6 read-write 0 - Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Disabled #0 1 - Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Enabled. #1 - DSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable - 13 - 13 + VBATTEN + VBATT monitor Interrupt Enable + 4 + 4 read-write 0 - Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + Disabled #0 1 - Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + Enabled. #1 - DSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable - 12 - 12 + LVD2EN + Voltage-Monitoring 2 Interrupt Enable + 3 + 3 read-write 0 - Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Disabled #0 1 - Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Enabled. #1 - DSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable - 11 - 11 + LVD1EN + Voltage-Monitoring 1 Interrupt Enable + 2 + 2 read-write 0 - Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + Disabled #0 1 - Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Enabled. #1 - DSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable - 10 - 10 + WDTEN + WDT Underflow/Refresh Error Interrupt Enable + 1 + 1 read-write 0 - Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + Disabled #0 1 - Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Enabled. #1 - DSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable - 9 - 9 + IWDTEN + IWDT Underflow/Refresh Error Interrupt Enable + 0 + 0 read-write 0 - Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Disabled #0 1 - Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Enabled. #1 - DSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable - 8 - 8 + TZFEN + 13 + 13 read-write 0 - Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + Disabled #0 1 - Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Enabled #1 - 4 - 2 - A,B,C,D - DSGTRG%sF - GTETRG Pin Falling Input Source Counter Count Down Enable - 1 - 1 + CPEEN + 15 + 15 read-write 0 - Counter count down is disable at the falling edge of GTETRG input + Disabled #0 1 - Counter count down is enable at the falling edge of GTETRG input + Enabled #1 + + + + NMICLR + Non-Maskable Interrupt Status Clear Register + 0x130 + 16 + read-write + 0x0000 + 0xFFFF + - 4 - 2 - A,B,C,D - DSGTRG%sR - GTETRG Pin Rising Input Source Counter Count Down Enable - 0 - 0 - read-write + SPECLR + CPU Stack Pointer Monitor Interrupt Clear + 12 + 12 + write-only 0 - Counter count down is disable at the rising edge of GTETRG input + No effect. #0 1 - Counter count down is enable at the rising edge of GTETRG input + Clear the NMISR.SPEST flag. #1 - - - - GTICASR - General PWM Timer Input Capture Source Select Register A - 0x24 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 8 - 1 - A,B,C,D,E,F,G,H - ASELC%s - ELC_GPT Event Source GTCCRA Input Capture Enable - 16 - 16 - read-write + BUSMCLR + Bus Master Error Clear + 11 + 11 + write-only 0 - GTCCRA input capture is disable at the ELC_GPT input + No effect. #0 1 - GTCCRA input capture is enable at the ELC_GPT input + Clear the NMISR.BUSMST flag. #1 - ASCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable - 15 - 15 - read-write + BUSSCLR + Bus Slave Error Clear + 10 + 10 + write-only 0 - GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + No effect. #0 1 - GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Clear the NMISR.BUSSST flag. #1 - ASCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable - 14 - 14 - read-write + RECCCLR + SRAM ECC Error Clear + 9 + 9 + write-only 0 - GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + No effect. #0 1 - GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Clear the NMISR.RECCST flag. #1 - - ASCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable - 13 - 13 - read-write + + RPECLR + SRAM Parity Error Clear + 8 + 8 + write-only 0 - GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + No effect. #0 1 - GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + Clear the NMISR.RPEST flag. #1 - ASCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable - 12 - 12 - read-write + NMICLR + NMI Clear + 7 + 7 + write-only 0 - GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + No effect. #0 1 - GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Clear the NMISR.NMIST flag. #1 - ASCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable - 11 - 11 - read-write + OSTCLR + OST Clear + 6 + 6 + write-only 0 - GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + No effect. #0 1 - GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Clear the NMISR.OSTST flag. #1 - ASCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable - 10 - 10 - read-write + VBATTCLR + VBATT Clear + 4 + 4 + write-only 0 - GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + No effect. #0 1 - GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Clear the NMISR.VBATTST flag. #1 - ASCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable - 9 - 9 - read-write + LVD2CLR + LVD2 Clear + 3 + 3 + write-only 0 - GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + No effect. #0 1 - GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Clear the NMISR.LVD2ST flag. #1 - ASCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable - 8 - 8 - read-write + LVD1CLR + LVD1 Clear + 2 + 2 + write-only 0 - GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + No effect. #0 1 - GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Clear the NMISR.LVD1ST flag. #1 - 4 - 2 - A,B,C,D - ASGTRG%sF - GTETRG Pin Falling Input Source GTCCRA Input Capture Enable + WDTCLR + WDT Clear 1 1 - read-write + write-only 0 - GTCCRA input capture is disable at the falling edge of GTETRG input + No effect. #0 1 - GTCCRA input capture is enable at the falling edge of GTETRG input + Clear the NMISR.WDTST flag. #1 - 4 - 2 - A,B,C,D - ASGTRG%sR - GTETRG Pin Rising Input Source GTCCRA Input Capture Enable + IWDTCLR + IWDT Clear 0 0 - read-write + write-only 0 - GTCCRA input capture is disable at the rising edge of GTETRG input + No effect. #0 1 - GTCCRA input capture is enable at the rising edge of GTETRG input + Clear the NMISR.IWDTST flag. #1 - - - - GTICBSR - General PWM Timer Input Capture Source Select Register B - 0x28 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 8 - 1 - A,B,C,D,E,F,G,H - BSELC%s - ELC_GPT Event Source GTCCRB Input Capture Enable - 16 - 16 + TZFCLR + 13 + 13 read-write 0 - GTCCRB input capture is disable at the ELC_GPT input + No effect #0 1 - GTCCRB input capture is enable at the ELC_GPT input + Clear the NMISR.TZFCLR flag #1 - BSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable + CPECLR 15 15 read-write 0 - GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + No effect #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Clear the NMISR.CPECLR flag #1 + + + + NMICR + NMI Pin Interrupt Control Register + 0x100 + 8 + read-write + 0x00 + 0xFF + - BSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable - 14 - 14 + NFLTEN + NMI Digital Filter Enable + 7 + 7 read-write 0 - GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Digital filter is disabled. #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Digital filter is enabled. #1 - BSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable - 13 - 13 + NFCLKSEL + NMI Digital Filter Sampling Clock Select + 4 + 5 read-write - 0 - GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + 00 + PCLKB + #00 - 1 - GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + 01 + PCLKB/8 + #01 + + + 10 + PCLKB/32 + #10 + + + 11 + PCLKB/64 + #11 - BSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable - 12 - 12 + NMIMD + NMI Detection Set + 0 + 0 read-write 0 - GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Falling edge #0 1 - GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Rising edge #1 + + + + 96 + 0x4 + IELSR[%s] + ICU Event Link Setting Register %s + 0x300 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - BSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable - 11 - 11 + DTCE + DTC Activation Enable + 24 + 24 read-write 0 - GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + DTC activation is disabled #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + DTC activation is enabled #1 - BSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable - 10 - 10 + IR + Interrupt Status Flag + 16 + 16 read-write 0 - GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + No interrupt request is generated #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 - BSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable - 9 - 9 + IELS + ICU Event selection to NVICSet the number for the event signal to be linked . + 0 + 8 read-write - 0 - GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 - #0 + 0x000 + Nothing is selected + 0x000 - 1 - GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 - #1 + others + See Event Table + true + + + + 8 + 0x4 + DELSR[%s] + DMAC Event Link Setting Register + 0x280 + 32 + read-write + 0x0000 + 0xFFFF + - BSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable - 8 - 8 + IR + Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited. + 16 + 16 read-write - 0 - GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + 0x0 + No interrupt request is generated. #0 - 1 - GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + 0x1 + An interrupt request is generated. #1 - 4 - 2 - A,B,C,D - BSGTRG%sF - GTETRG Pin Falling Input Source GTCCRB Input Capture Enable - 1 - 1 + DELS + Event selection to DMAC Start request + 0 + 8 read-write - 0 - GTCCRB input capture is disable at the falling edge of GTETRG input - #0 + 0x000 + Nothing is selected. + 0x000 - 1 - GTCCRB input capture is enable at the falling edge of GTETRG input - #1 + others + See Event Table + true + + + + SELSR0 + Snooze Event Link Setting Register + 0x200 + 16 + read-write + 0x0000 + 0xFFFF + - 4 - 2 - A,B,C,D - BSGTRG%sR - GTETRG Pin Rising Input Source GTCCRB Input Capture Enable + SELS + SYS Event Link Select 0 - 0 + 8 read-write - 0 - GTCCRB input capture is disable at the rising edge of GTETRG input - #0 - - - 1 - GTCCRB input capture is enable at the rising edge of GTETRG input - #1 + 0x000 + Nothing is selected + 0x000 - GTCR - General PWM Timer Control Register - 0x2C + WUPEN + Wake Up Interrupt Enable Register + 0x1A0 32 read-write 0x00000000 0xFFFFFFFF - TPCS - Timer Prescaler Select - 23 - 26 + IIC0WUPEN + IIC0 address match interrupt S/W standby returns enable + 31 + 31 read-write - 0000 - PCLK/1 - #0000 - - - 0001 - PCLK/2 - #0001 - - - 0010 - PCLK/4 - #0010 - - - 0011 - PCLK/8 - #0011 - - - 0100 - PCLK/16 - #0100 - - - 0101 - PCLK/32 - #0101 - - - 0110 - PCLK/64 - #0110 - - - 1000 - PCLK/256 - #1000 - - - 1010 - PCLK/1024 - #1010 - - - 1100 - GTETRGA - #1100 - - - 1101 - GTETRGB - #1101 - - - 1110 - GTETRGC - #1110 - - - 1111 - GTETRGD - #1111 + 0 + S/W standby returns by IIC0 address match interrupt is disabled + #0 - others - Setting prohibied - true + 1 + S/W standby returns by IIC0 address match interrupt is enabled + #1 - MD - Mode Select - 16 - 18 + AGT1CBWUPEN + AGT1 compare match B interrupt S/W standby returns enable + 30 + 30 read-write - 000 - Saw-wave PWM mode (single buffer or double buffer possible) - #000 - - - 001 - Saw-wave one-shot pulse mode (fixed buffer operation) - #001 - - - 010 - Setting prohibited - #010 - - - 011 - Setting prohibited - #011 - - - 100 - Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) - #100 - - - 101 - Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) - #101 - - - 110 - Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) - #110 + 0 + S/W standby returns by AGT1 compare match B interrupt is disabled + #0 - 111 - Setting prohibited - #111 + 1 + S/W standby returns by AGT1 compare match B interrupt is enabled + #1 - CST - Count Start - 0 - 0 + AGT1CAWUPEN + AGT1 compare match A interrupt S/W standby returns enable + 29 + 29 read-write 0 - Count operation is stopped + S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 - Count operation is performed + S/W standby returns by AGT1 compare match A interrupt is enabled + #1 + + + + + AGT1UDWUPEN + AGT1 underflow interrupt S/W standby returns enable + 28 + 28 + read-write + + + 0 + S/W standby returns by AGT1 underflow interrupt is disabled + #0 + + + 1 + S/W standby returns by AGT1 underflow interrupt is enabled #1 - - - - GTUDDTYC - General PWM Timer Count Direction and Duty Setting Register - 0x30 - 32 - read-write - 0x00000001 - 0xFFFFFFFF - - OBDTYR - GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + USBFSWUPEN + USBFS interrupt S/W standby returns enable 27 27 read-write 0 - Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + S/W standby returns by USBFS interrupt is disabled #0 1 - Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + S/W standby returns by USBFS interrupt is enabled #1 - OBDTYF - Forcible GTIOCB Output Duty Setting + USBHSWUPEN + USBHS interrupt S/W standby returns enable bit 26 26 read-write 0 - Not forcibly set + S/W standby returns by USBHS interrupt is disabled #0 1 - Forcibly set + S/W standby returns by USBHS interrupt is enabled #1 - OBDTY - GTIOCB Output Duty Setting - 24 + RTCPRDWUPEN + RCT period interrupt S/W standby returns enable + 25 25 read-write - 00 - GTIOCB pin duty is depend on compare match - #00 - - - 01 - GTIOCB pin duty is depend on compare match - #01 - - - 10 - GTIOCB pin duty 0 percent - #10 + 0 + S/W standby returns by RTC period interrupt is disabled + #0 - 11 - GTIOCB pin duty 100 percent - #11 + 1 + S/W standby returns by RTC period interrupt is enabled + #1 - OADTYR - GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting - 19 - 19 + RTCALMWUPEN + RTC alarm interrupt S/W standby returns enable + 24 + 24 read-write 0 - Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + S/W standby returns by RTC alarm interrupt is disabled #0 1 - Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + S/W standby returns by RTC alarm interrupt is enabled #1 - OADTYF - Forcible GTIOCA Output Duty Setting - 18 - 18 + ACMPLP0WUPEN + ACMPLP0 interrupt S/W standby returns enable + 23 + 23 read-write 0 - Not forcibly set + S/W standby returns by ACMPLP0 interrupt is disabled #0 1 - Forcibly set + S/W standby returns by ACMPLP0 interrupt is enabled #1 - OADTY - GTIOCA Output Duty Setting - 16 - 17 + ACMPHS0WUPEN + ACMPHS0 interrupt S/W standby returns enable bit + 22 + 22 read-write - 00 - GTIOCA pin duty is depend on compare match - #00 - - - 01 - GTIOCA pin duty is depend on compare match - #01 - - - 10 - GTIOCA pin duty 0 percent - #10 + 0 + S/W standby returns by ACMPHS0 interrupt is disabled + #0 - 11 - GTIOCA pin duty 100 percent - #11 + 1 + S/W standby returns by ACMPHS0 interrupt is enabled + #1 - UDF - Forcible Count Direction Setting - 1 - 1 + VBATTWUPEN + VBATT monitor interrupt S/W standby returns enable + 20 + 20 read-write 0 - Not forcibly set + S/W standby returns by VBATT monitor interrupt is disabled #0 1 - Forcibly set + S/W standby returns by VBATT monitor interrupt is enabled #1 - UD - Count Direction Setting - 0 - 0 + LVD2WUPEN + LVD2 interrupt S/W standby returns enable + 19 + 19 read-write 0 - GTCNT counts down. + S/W standby returns by LVD2 interrupt is disabled #0 1 - GTCNT counts up. + S/W standby returns by LVD2 interrupt is enabled #1 - - - - GTIOR - General PWM Timer I/O Control Register - 0x34 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - NFCSB - Noise Filter B Sampling Clock Select - 30 - 31 + LVD1WUPEN + LVD1 interrupt S/W standby returns enable + 18 + 18 read-write - 00 - PCLK/1 - #00 - - - 01 - PCLK/4 - #01 - - - 10 - PCLK/16 - #10 + 0 + S/W standby returns by LVD1 interrupt is disabled + #0 - 11 - PCLK/64 - #11 + 1 + S/W standby returns by LVD1 interrupt is enabled + #1 - NFBEN - Noise Filter B Enable - 29 - 29 + KEYWUPEN + Key interrupt S/W standby returns enable + 17 + 17 read-write 0 - The noise filter for the GTIOCB pin is disabled. + S/W standby returns by KEY interrupt is disabled #0 1 - The noise filter for the GTIOCB pin is enabled. + S/W standby returns by KEY interrupt is enabled #1 - OBDF - GTIOCB Pin Disable Value Setting - 25 - 26 + IWDTWUPEN + IWDT interrupt S/W standby returns enable + 16 + 16 read-write - 00 - Output disable is prohibited. - #00 - - - 01 - GTIOCB pin is set to Hi-Z when output disable is performed. - #01 - - - 10 - GTIOCB pin is set to 0 when output disable is performed. - #10 + 0 + S/W standby returns by IWDT interrupt is disabled + #0 - 11 - GTIOCB pin is set to 1 when output disable is performed. - #11 + 1 + S/W standby returns by IWDT interrupt is enabled + #1 - OBE - GTIOCB Pin Output Enable - 24 - 24 + 16 + 0x01 + IRQWUPEN%s + IRQ interrupt S/W standby returns enable + 0 + 0 read-write 0 - Output is disabled + S/W standby returns by IRQ interrupt is disabled #0 1 - Output is enabled + S/W standby returns by IRQ interrupt is enabled #1 + + + + WUPEN1 + Wake Up interrupt enable register 1 + 0x1A4 + 32 + read-write + 0x00000000 + 0xffffffff + - OBHLD - GTIOCB Pin Output Setting at the Start/Stop Count - 23 - 23 + AGT3UDWUPEN + AGT3 underflow interrupt S/W standby returns enable bit + 0 + 0 read-write 0 - The GTIOCB pin output level at start/stop of counting depends on the register setting. + S/W standby returns by AGT3 underflow interrupt is disabled #0 1 - The GTIOCB pin output level is retained at start/stop of counting. + S/W standby returns by AGT3 underflow interrupt is enabled #1 - OBDFLT - GTIOCB Pin Output Value Setting at the Count Stop - 22 - 22 + AGT3CAWUPEN + AGT3 compare match A interrupt S/W standby returns enable bit + 1 + 1 read-write 0 - The GTIOCB pin outputs low when counting is stopped. + S/W standby returns by AGT3 compare match A interrupt is disabled #0 1 - The GTIOCB pin outputs high when counting is stopped. + S/W standby returns by AGT3 compare match A interrupt is enabled #1 - GTIOB - GTIOCB Pin Function Select - 16 - 20 + AGT3CBWUPEN + AGT3 compare match B interrupt S/W standby returns enable bit + 2 + 2 read-write - 00000 - Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. - #00000 - - - 00001 - Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. - #00001 - - - 00010 - Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. - #00010 - - - 00011 - Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. - #00011 - - - 00100 - Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. - #00100 - - - 00101 - Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. - #00101 - - - 00110 - Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. - #00110 - - - 00111 - Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. - #00111 - - - 01000 - Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. - #01000 - - - 01001 - Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. - #01001 - - - 01010 - Initial output is Low. High output at cycle end. High output at GTCCRB compare match. - #01010 - - - 01011 - Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. - #01011 - - - 01100 - Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. - #01100 - - - 01101 - Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. - #01101 - - - 01110 - Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. - #01110 - - - 01111 - Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. - #01111 - - - 10000 - Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. - #10000 - - - 10001 - Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. - #10001 - - - 10010 - Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. - #10010 - - - 10011 - Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. - #10011 - - - 10100 - Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. - #10100 - - - 10101 - Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. - #10101 - - - 10110 - Initial output is High. Low output at cycle end. High output at GTCCRB compare match. - #10110 - - - 10111 - Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. - #10111 - - - 11000 - Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. - #11000 - - - 11001 - Initial output is High. High output at cycle end. Low output at GTCCRB compare match. - #11001 - - - 11010 - Initial output is High. High output at cycle end. High output at GTCCRB compare match. - #11010 + 0 + S/W standby returns by AGT3 compare match B interrupt is disabled + #0 - 11011 - Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. - #11011 + 1 + S/W standby returns by AGT3 compare match B interrupt is enabled + #1 + + + + + + + + R_IIC0 + I2C Bus Interface + 0x40053000 + + 0x00000000 + 0x014 + registers + + + 0x00000016 + 0x002 + registers + + + + 3 + 0x2 + SAR[%s] + Slave Address Registers + 0x0A + 16 + + L + Slave Address Register L + 0x0 + 8 + read-write + 0x00 + 0xFF + + + SVA + A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } + 0 + 7 + read-write + + + + + U + Slave Address Register U + 0x01 + 8 + read-write + 0x00 + 0xFF + + + SVA9 + 10-Bit Address(bit9) + 2 + 2 + read-write + + + SVA8 + 10-Bit Address(bit8) + 1 + 1 + read-write + + + FS + 7-Bit/10-Bit Address Format Selection + 0 + 0 + read-write + + + 0 + The 7-bit address format is selected. + #0 + + + 1 + The 10-bit address format is selected. + #1 + + + + + + + + ICCR1 + I2C Bus Control Register 1 + 0x00 + 8 + read-write + 0x1F + 0xFF + + + ICE + I2C Bus Interface Enable + 7 + 7 + read-write + - 11100 - Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. - #11100 + 0 + Disable (SCLn and SDAn pins in inactive state) + #0 - 11101 - Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. - #11101 + 1 + Enable (SCLn and SDAn pins in active state) + #1 + + + + IICRST + I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). + 6 + 6 + read-write + - 11110 - Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. - #11110 + 0 + Releases the RIIC reset or internal reset. + #0 - 11111 - Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. - #11111 + 1 + Initiates the RIIC reset or internal reset. + #1 - NFCSA - Noise Filter A Sampling Clock Select - 14 - 15 + CLO + Extra SCL Clock Cycle Output + 5 + 5 read-write - 00 - PCLK/1 - #00 + 0 + Does not output an extra SCL clock cycle. + #0 - 01 - PCLK/4 - #01 + 1 + Outputs an extra SCL clock cycle. + #1 + + + + SOWP + SCLO/SDAO Write Protect + 4 + 4 + read-write + - 10 - PCLK/16 - #10 + 0 + Bits SCLO and SDAO can be written + #0 - 11 - PCLK/64 - #11 + 1 + Bits SCLO and SDAO are protected. + #1 - NFAEN - Noise Filter A Enable - 13 - 13 + SCLO + SCL Output Control/Monitor + 3 + 3 read-write 0 - The noise filter for the GTIOCA pin is disabled. + (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 - The noise filter for the GTIOCA pin is enabled. + (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 - OADF - GTIOCA Pin Disable Value Setting - 9 - 10 + SDAO + SDA Output Control/Monitor + 2 + 2 read-write - 00 - Output disable is prohibited. - #00 + 0 + (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. + #0 - 01 - GTIOCA pin is set to Hi-Z when output disable is performed. - #01 + 1 + (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. + #1 + + + + SCLI + SCL Line Monitor + 1 + 1 + read-only + - 10 - GTIOCA pin is set to 0 when output disable is performed. - #10 + 0 + SCLn line is low. + #0 - 11 - GTIOCA pin is set to 1 when output disable is performed. - #11 + 1 + SCLn line is high. + #1 - OAE - GTIOCA Pin Output Enable - 8 - 8 - read-write + SDAI + SDA Line Monitor + 0 + 0 + read-only 0 - Output is disabled + SDAn line is low. #0 1 - Output is enabled + SDAn line is high. #1 + + + + ICCR2 + I2C Bus Control Register 2 + 0x01 + 8 + read-write + 0x00 + 0xFF + - OAHLD - GTIOCA Pin Output Setting at the Start/Stop Count + BBSY + Bus Busy Detection Flag 7 7 - read-write + read-only 0 - The GTIOCA pin output level at start/stop of counting depends on the register setting. + The I2C bus is released (bus free state). #0 1 - The GTIOCA pin output level is retained at start/stop of counting. + The I2C bus is occupied (bus busy state). #1 - OADFLT - GTIOCA Pin Output Value Setting at the Count Stop + MST + Master/Slave Mode 6 6 read-write 0 - The GTIOCA pin outputs low when counting is stopped. + Slave mode #0 1 - The GTIOCA pin outputs high when counting is stopped. + Master mode #1 - GTIOA - GTIOCA Pin Function Select - 0 - 4 + TRS + Transmit/Receive Mode + 5 + 5 read-write - 00000 - Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. - #00000 - - - 00001 - Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. - #00001 - - - 00010 - Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. - #00010 - - - 00011 - Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. - #00011 - - - 00100 - Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. - #00100 + 0 + Receive mode + #0 - 00101 - Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. - #00101 + 1 + Transmit mode + #1 + + + + SP + Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. + 3 + 3 + read-write + - 00110 - Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. - #00110 + 0 + Does not request to issue a stop condition. + #0 - 00111 - Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. - #00111 + 1 + Requests to issue a stop condition. + #1 + + + + RS + Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. + 2 + 2 + read-write + - 01000 - Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. - #01000 + 0 + Does not request to issue a restart condition. + #0 - 01001 - Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. - #01001 + 1 + Requests to issue a restart condition. + #1 + + + + ST + Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). + 1 + 1 + read-write + - 01010 - Initial output is Low. High output at cycle end. High output at GTCCRA compare match. - #01010 + 0 + Does not request to issue a start condition. + #0 - 01011 - Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. - #01011 + 1 + Requests to issue a start condition. + #1 + + + + + + ICMR1 + I2C Bus Mode Register 1 + 0x02 + 8 + read-write + 0x08 + 0xFF + + + MTWP + MST/TRS Write Protect + 7 + 7 + read-write + - 01100 - Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. - #01100 + 0 + Disables writing to the MST and TRS bits in ICCR2. + #0 - 01101 - Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. - #01101 + 1 + Enables writing to the MST and TRS bits in ICCR2. + #1 + + + + CKS + Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) + 4 + 6 + read-write + - 01110 - Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. - #01110 + 000 + PCLKB/1 clock + #000 - 01111 - Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. - #01111 + 001 + PCLKB/2 clock + #001 - 10000 - Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. - #10000 + 010 + PCLKB/4 clock + #010 - 10001 - Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. - #10001 + 011 + PCLKB/8 clock + #011 - 10010 - Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. - #10010 + 100 + PCLKB/16 clock + #100 - 10011 - Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. - #10011 + 101 + PCLKB/32 clock + #101 - 10100 - Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. - #10100 + 110 + PCLKB/64 clock + #110 - 10101 - Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. - #10101 + 111 + PCLKB/128 clock + #111 + + + + BCWP + BC Write Protect(This bit is read as 1.) + 3 + 3 + write-only + - 10110 - Initial output is High. Low output at cycle end. High output at GTCCRA compare match. - #10110 + 0 + Enables a value to be written in the BC[2:0] bits. + #0 - 10111 - Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. - #10111 + 1 + Disables a value to be written in the BC[2:0] bits. + #1 + + + + BC + Bit Counter + 0 + 2 + read-write + - 11000 - Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. - #11000 + 000 + 9 bits + #000 - 11001 - Initial output is High. High output at cycle end. Low output at GTCCRA compare match. - #11001 + 001 + 2 bits + #001 - 11010 - Initial output is High. High output at cycle end. High output at GTCCRA compare match. - #11010 + 010 + 3 bits + #010 - 11011 - Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. - #11011 + 011 + 4 bits + #011 - 11100 - Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. - #11100 + 100 + 5 bits + #100 - 11101 - Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. - #11101 + 101 + 6 bits + #101 - 11110 - Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. - #11110 + 110 + 7 bits + #110 - 11111 - Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. - #11111 + 111 + 8 bits + #111 - GTINTAD - General PWM Timer Interrupt Output Setting Register - 0x38 - 32 + ICMR2 + I2C Bus Mode Register 2 + 0x03 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x06 + 0xFF - GRPABL - Same Time Output Level Low Disable Request Enable - 30 - 30 + DLCS + SDA Output Delay Clock Source Select + 7 + 7 read-write 0 - Same time output level low disable request is disabled. + The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 - Same time output level low disable request is enabled. + The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 - GRPABH - Same Time Output Level High Disable Request Enable - 29 - 29 + SDDL + SDA Output Delay Counter + 4 + 6 read-write - 0 - Same time output level high disable request is disabled. - #0 - - - 1 - Same time output level high disable request is enabled. - #1 + 000 + No output delay + #000 - - - - GRPDTE - Dead Time Error Output Disable Request Enable - 28 - 28 - read-write - - 0 - Disable dead time error output disable request - #0 + 001 + 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) + #001 - 1 - Enable dead time error output disable request - #1 + 010 + 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) + #010 - - - - GRP - Output Disable Source Select - 24 - 25 - read-write - - 00 - Group A output disable request - #00 + 011 + 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) + #011 - 01 - Group B output disable request - #01 + 100 + 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) + #100 - 10 - Group C output disable request - #10 + 101 + 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) + #101 - 11 - Group D output disable request - #11 + 110 + 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) + #110 - others - Setting prohibited - true + 111 + 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) + #111 - GTINTPC - Period Count Function Finish Interrupt Enable - 31 - 31 + TMOH + Timeout H Count Control + 2 + 2 read-write 0 - Interrupt request is disabled + Count is disabled while the SCLn line is at a high level. #0 1 - Interrupt request is enabled + Count is enabled while the SCLn line is at a high level. #1 - - - - GTST - General PWM Timer Status Register - 0x3C - 32 - read-write - 0x00008000 - 0xFFFFFFFF - - OABLF - Same Time Output Level Low Disable Request Enable - 30 - 30 - read-only + TMOL + Timeout L Count Control + 1 + 1 + read-write 0 - GTIOCA pin and GTIOCB pin don't output 0 at the same time. + Count is disabled while the SCLn line is at a low level. #0 1 - GTIOCA pin and GTIOCB pin output 0 at the same time. + Count is enabled while the SCLn line is at a low level. #1 - OABHF - Same Time Output Level High Disable Request Enable - 29 - 29 - read-only + TMOS + Timeout Detection Time Select + 0 + 0 + read-write 0 - GTIOCA pin and GTIOCB pin don't output 1 at the same time. + Long mode is selected. #0 1 - GTIOCA pin and GTIOCB pin output 1 at the same time. + Short mode is selected. #1 + + + + ICMR3 + I2C Bus Mode Register 3 + 0x04 + 8 + read-write + 0x00 + 0xFF + - DTEF - Dead Time Error Flag - 28 - 28 - read-only + SMBS + SMBus/I2C Bus Selection + 7 + 7 + read-write 0 - No dead time error has occurred. + The I2C bus is selected. #0 1 - A dead time error has occurred. + The SMBus is selected. #1 - ODF - Output Disable Flag - 24 - 24 - read-only + WAIT + WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. + 6 + 6 + read-write 0 - No output disable request is generated. + No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 - An output disable request is generated. + WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 - ADTRBDF - GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag - 19 - 19 + RDRFS + RDRF Flag Set Timing Selection + 5 + 5 read-write 0 - No compare match of GTADTRB at down-counting is generated. + The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 - A compare match of GTADTRB at down-counting is generated. + The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 - ADTRBUF - GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag - 18 - 18 + ACKWP + ACKBT Write Protect + 4 + 4 read-write 0 - No compare match of GTADTRB at up-counting is generated. + Modification of the ACKBT bit is disabled. #0 1 - A compare match of GTADTRB at up-counting is generated. + Modification of the ACKBT bit is enabled. #1 - ADTRADF - GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag - 17 - 17 + ACKBT + Transmit Acknowledge + 3 + 3 read-write 0 - No compare match of GTADTRA at down-counting is generated. + A 0 is sent as the acknowledge bit (ACK transmission). #0 1 - A compare match of GTADTRA at down-counting is generated. + A 1 is sent as the acknowledge bit (NACK transmission). #1 - ADTRAUF - GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable - 16 - 16 - read-write + ACKBR + Receive Acknowledge + 2 + 2 + read-only 0 - No compare match of GTADTRA at up-counting is generated. + A 0 is received as the acknowledge bit (ACK reception). #0 1 - A compare match of GTADTRA at up-counting is generated. + A 1 is received as the acknowledge bit (NACK reception). #1 - TUCF - Count Direction Flag - 15 - 15 - read-only + NF + Noise Filter Stage Selection + 0 + 1 + read-write - 0 - The GTCNT counter counts downward. - #0 + 00 + Noise of up to one fIIC cycle is filtered out (single-stage filter). + #00 - 1 - The GTCNT counter counts upward. - #1 + 01 + Noise of up to two fIIC cycles is filtered out (2-stage filter). + #01 + + + 10 + Noise of up to three fIIC cycles is filtered out (3-stage filter). + #10 + + + 11 + Noise of up to four fIIC cycles is filtered out (4-stage filter) + #11 + + + + ICFER + I2C Bus Function Enable Register + 0x05 + 8 + read-write + 0x72 + 0xFF + - ITCNT - GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) - 8 - 10 - read-only - - - TCFPU - Underflow Flag + FMPE + Fast-mode Plus Enable 7 7 read-write 0 - No underflow (trough) has occurred. + No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #0 1 - An underflow (trough) has occurred. + An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #1 - TCFPO - Overflow Flag + SCLE + SCL Synchronous Circuit Enable 6 6 read-write 0 - No overflow (crest) has occurred. + No SCL synchronous circuit is used. #0 1 - An overflow (crest) has occurred. + An SCL synchronous circuit is used. #1 - TCFF - Input Compare Match Flag F + NFE + Digital Noise Filter Circuit Enable 5 5 read-write 0 - No compare match of GTCCRF is generated. + No digital noise filter circuit is used. #0 1 - A compare match of GTCCRF is generated. + A digital noise filter circuit is used. #1 - TCFE - Input Compare Match Flag E + NACKE + NACK Reception Transfer Suspension Enable 4 4 read-write 0 - No compare match of GTCCRE is generated. + Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 - A compare match of GTCCRE is generated. + Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 - TCFD - Input Compare Match Flag D + SALE + Slave Arbitration-Lost Detection Enable 3 3 read-write 0 - No compare match of GTCCRD is generated. + Slave arbitration-lost detection is disabled. #0 1 - A compare match of GTCCRD is generated. + Slave arbitration-lost detection is enabled. #1 - TCFC - Input Compare Match Flag C + NALE + NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 - No compare match of GTCCRC is generated. + NACK transmission arbitration-lost detection is disabled. #0 1 - A compare match of GTCCRC is generated. + NACK transmission arbitration-lost detection is enabled. #1 - TCFB - Input Capture/Compare Match Flag B + MALE + Master Arbitration-Lost Detection Enable 1 1 read-write 0 - No input capture/compare match of GTCCRB is generated. + Master arbitration-lost detection is disabled. #0 1 - An input capture/compare match of GTCCRB is generated. + Master arbitration-lost detection is enabled. #1 - TCFA - Input Capture/Compare Match Flag A + TMOE + Timeout Function Enable 0 0 read-write 0 - No input capture/compare match of GTCCRA is generated. + The timeout function is disabled. #0 1 - An input capture/compare match of GTCCRA is generated. + The timeout function is enabled. #1 + + + + ICSER + I2C Bus Status Enable Register + 0x06 + 8 + read-write + 0x09 + 0xFF + - PCF - Period Count Function Finish Flag - 31 - 31 + HOAE + Host Address Enable + 7 + 7 read-write 0 - No period count function finish has occurred + Host address detection is disabled. #0 1 - A period count function finish has occurred + Host address detection is enabled. #1 - - - - GTBER - General PWM Timer Buffer Enable Register - 0x40 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - ADTDB - GTADTRB Double Buffer Operation - 30 - 30 + DIDE + Device-ID Address Detection Enable + 5 + 5 read-write 0 - Single buffer operation (GTADTBRB --> GTADTRB) + Device-ID address detection is disabled. #0 1 - Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) + Device-ID address detection is enabled. #1 - ADTTB - GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. - 28 - 29 + GCAE + General Call Address Enable + 3 + 3 read-write - 00 - No transfer - #00 - - - 01 - Transfer at crest - #01 - - - 10 - Transfer at trough - #10 + 0 + General call address detection is disabled. + #0 - 11 - Transfer at both crest and trough - #11 + 1 + General call address detection is enabled. + #1 - ADTDA - GTADTRA Double Buffer Operation - 26 - 26 + SAR2E + Slave Address Register 2 Enable + 2 + 2 read-write 0 - Single buffer operation (GTADTBRA --> GTADTRA) + Slave address in SARL2 and SARU2 is disabled. #0 1 - Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) + Slave address in SARL2 and SARU2 is enabled #1 - ADTTA - GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. - 24 - 25 + SAR1E + Slave Address Register 1 Enable + 1 + 1 read-write - 00 - No transfer - #00 - - - 01 - Transfer at crest - #01 - - - 10 - Transfer at trough - #10 + 0 + Slave address in SARL1 and SARU1 is disabled. + #0 - 11 - Transfer at both crest and trough - #11 + 1 + Slave address in SARL1 and SARU1 is enabled. + #1 - CCRSWT - GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. - 22 - 22 - write-only + SAR0E + Slave Address Register 0 Enable + 0 + 0 + read-write 0 - no effect + Slave address in SARL0 and SARU0 is disabled. #0 1 - Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. + Slave address in SARL0 and SARU0 is enabled. #1 + + + + ICIER + I2C Bus Interrupt Enable Register + 0x07 + 8 + read-write + 0x00 + 0xFF + - PR - GTPR Buffer Operation - 20 - 21 + TIE + Transmit Data Empty Interrupt Request Enable + 7 + 7 read-write - 00 - Buffer operation is not performed - #00 - - - 01 - Single buffer operation (GTPBR --> GTPR) - #01 + 0 + Transmit data empty interrupt request (IIC_TXI) is disabled. + #0 - others - Setting prohibited - true + 1 + Transmit data empty interrupt request (IIC_TXI) is enabled. + #1 - CCRB - GTCCRB Buffer Operation - 18 - 19 + TEIE + Transmit End Interrupt Request Enable + 6 + 6 read-write - 00 - Buffer operation is not performed - #00 - - - 01 - Single buffer operation (GTCCRB <--> GTCCRE) - #01 - - - 10 - Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) - #10 + 0 + Transmit end interrupt request (IIC_TEI) is disabled. + #0 - 11 - Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) - #11 + 1 + Transmit end interrupt request (IIC_TEI) is enabled. + #1 - CCRA - GTCCRA Buffer Operation - 16 - 17 + RIE + Receive Data Full Interrupt Request Enable + 5 + 5 read-write - 00 - Buffer operation is not performed - #00 + 0 + Receive data full interrupt request (IIC_RXI) is disabled. + #0 - 01 - Single buffer operation (GTCCRA <--> GTCCRC) - #01 + 1 + Receive data full interrupt request (IIC_RXI) is enabled. + #1 + + + + NAKIE + NACK Reception Interrupt Request Enable + 4 + 4 + read-write + - 10 - Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) - #10 + 0 + NACK reception interrupt request (NAKI) is disabled. + #0 - 11 - Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) - #11 + 1 + NACK reception interrupt request (NAKI) is enabled. + #1 - BD3 - BD[3]: GTDV Buffer Operation DisableBD[2] + SPIE + Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 - Enable buffer operation + Stop condition detection interrupt request (SPI) is disabled. #0 1 - Disable buffer operation + Stop condition detection interrupt request (SPI) is enabled. #1 - BD2 - BD[2]: GTADTR Buffer Operation DisableBD + STIE + Start Condition Detection Interrupt Request Enable 2 2 read-write 0 - Enable buffer operation + Start condition detection interrupt request (STI) is disabled. #0 1 - Disable buffer operation + Start condition detection interrupt request (STI) is enabled. #1 - BD1 - BD[1]: GTPR Buffer Operation Disable + ALIE + Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 - Buffer operation is enabled + Arbitration-lost interrupt request (ALI) is disabled. #0 1 - Buffer operation is disabled + Arbitration-lost interrupt request (ALI) is enabled. #1 - BD0 - BD[0]: GTCCR Buffer Operation Disable + TMOIE + Timeout Interrupt Request Enable 0 0 read-write 0 - Buffer operation is enabled + Timeout interrupt request (TMOI) is disabled. #0 1 - Buffer operation is disabled + Timeout interrupt request (TMOI) is enabled. #1 @@ -43571,1295 +57272,941 @@ FMS2,1,0: - GTITC - General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register - 0x44 - 32 + ICSR1 + I2C Bus Status Register 1 + 0x08 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - ADTBL - GTADTRB A/D Converter Start Request Link - 14 - 14 + HOA + Host Address Detection Flag + 7 + 7 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Host address is not detected. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Host address is detected. #1 - ADTAL - GTADTRA A/D Converter Start Request Link - 12 - 12 + DID + Device-ID Address Detection Flag + 5 + 5 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Device-ID command is not detected. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function + Device-ID command is detected. #1 - IVTT - GPT_OVF/GPT_UDF Interrupt Skipping Count Select - 8 - 10 - read-write - - - 000 - No skipping - #000 - - - 001 - Skipping count of 1 - #001 - - - 010 - Skipping count of 2 - #010 - - - 011 - Skipping count of 3 - #011 - - - 100 - Skipping count of 4 - #100 - - - 101 - Skipping count of 5 - #101 - - - 110 - Skipping count of 6 - #110 - - - 111 - Skipping count of 7. - #111 - - - - - IVTC - GPT_OVF/GPT_UDF Interrupt Skipping Function Select - 6 - 7 + GCA + General Call Address Detection Flag + 3 + 3 read-write - 00 - Do not perform skipping - #00 - - - 01 - Count and skip both overflow and underflow for saw waves and crest for triangle waves - #01 - - - 10 - Count and skip both overflow and underflow for saw waves and trough for triangle waves - #10 + 0 + General call address is not detected. + #0 - 11 - Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. - #11 + 1 + General call address is detected. + #1 - ITLF - GTCCRF Compare Match Interrupt Link - 5 - 5 + AAS2 + Slave Address 2 Detection Flag + 2 + 2 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Slave address 2 is not detected. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Slave address 2 is detected #1 - ITLE - GTCCRE Compare Match Interrupt Link - 4 - 4 + AAS1 + Slave Address 1 Detection Flag + 1 + 1 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Slave address 1 is not detected. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Slave address 1 is detected. #1 - ITLD - GTCCRD Compare Match Interrupt Link - 3 - 3 + AAS0 + Slave Address 0 Detection Flag + 0 + 0 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Slave address 0 is not detected. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Slave address 0 is detected. #1 + + + + ICSR2 + I2C Bus Status Register 2 + 0x09 + 8 + read-write + 0x00 + 0xFF + - ITLC - GTCCRC Compare Match Interrupt Link - 2 - 2 - read-write + TDRE + Transmit Data Empty Flag + 7 + 7 + read-only 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + ICDRT contains transmit data. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + ICDRT contains no transmit data. #1 - ITLB - GTCCRB Compare Match/Input Capture Interrupt Link - 1 - 1 + TEND + Transmit End Flag + 6 + 6 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Data is being transmitted. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Data has been transmitted. #1 - ITLA - GTCCRA Compare Match/Input Capture Interrupt Link - 0 - 0 + RDRF + Receive Data Full Flag + 5 + 5 read-write + zeroToClear + modify 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + ICDRR contains no receive data. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + ICDRR contains receive data. #1 - - - - GTCNT - General PWM Timer Counter - 0x48 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GTCNT - Counter - 0 - 31 - read-write - - - - - 6 - 4 - - - A - A - 0 - - - B - B - 1 - - - C - C - 2 - - - E - E - 3 - - - D - D - 4 - - - F - F - 5 - - - GTCCR[%s] - General PWM Timer Compare Capture Register - 0x4C - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTCCR - Compare Capture Register A - 0 - 31 - read-write - - - - - GTPR - General PWM Timer Cycle Setting Register - 0x64 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPR - Cycle Setting Register - 0 - 31 - read-write - - - - - GTPBR - General PWM Timer Cycle Setting Buffer Register - 0x68 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPBR - Cycle Setting Buffer Register - 0 - 31 - read-write - - - - - GTPDBR - General PWM Timer Cycle Setting Double-Buffer Register - 0x6C - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPDBR - Cycle Setting Double-Buffer Register - 0 - 31 - read-write - - - - - GTADTRA - A/D Converter Start Request Timing Register A - 0x70 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTRA - A/D Converter Start Request Timing Register A - 0 - 31 - read-write - - - - - GTADTRB - A/D Converter Start Request Timing Register B - 0x7C - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTRB - A/D Converter Start Request Timing Register B - 0 - 31 - read-write - - - - - GTADTBRA - A/D Converter Start Request Timing Buffer Register A - 0x74 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTBRA - A/D Converter Start Request Timing Buffer Register A - 0 - 31 - read-write - - - - - GTADTBRB - A/D Converter Start Request Timing Buffer Register B - 0x80 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTBRB - A/D Converter Start Request Timing Buffer Register B - 0 - 31 - read-write - - - - - GTADTDBRA - A/D Converter Start Request Timing Double-Buffer Register A - 0x78 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTDBRA - A/D Converter Start Request Timing Double-Buffer Register A - 0 - 31 - read-write - - - - - GTADTDBRB - A/D Converter Start Request Timing Double-Buffer Register B - 0x84 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTDBRB - A/D Converter Start Request Timing Double-Buffer Register B - 0 - 31 - read-write - - - - - GTDTCR - General PWM Timer Dead Time Control Register - 0x88 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - TDFER - GTDVD Setting - 8 - 8 + NACKF + NACK Detection Flag + 4 + 4 read-write + zeroToClear + modify 0 - Set GTDVU and GTDVD separately + NACK is not detected. #0 1 - Automatically set the value written to GTDVU to GTDVD + NACK is detected. #1 - TDBDE - GTDVD Buffer Operation Enable - 5 - 5 + STOP + Stop Condition Detection Flag + 3 + 3 read-write + zeroToClear + modify 0 - Disable GTDVD buffer operation + Stop condition is not detected. #0 1 - Enable GTDVD buffer operation + Stop condition is detected. #1 - TDBUE - GTDVU Buffer Operation Enable - 4 - 4 + START + Start Condition Detection Flag + 2 + 2 read-write + zeroToClear + modify 0 - Disable GTDVU buffer operation + Start condition is not detected. #0 1 - Enable GTDVU buffer operation + Start condition is detected. #1 - TDE - Negative-Phase Waveform Setting - 0 - 0 + AL + Arbitration-Lost Flag + 1 + 1 read-write + zeroToClear + modify 0 - GTCCRB is set without using GTDVU and GTDVD. + Arbitration is not lost. #0 1 - GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. + Arbitration is lost. #1 - - - - GTDVU - General PWM Timer Dead Time Value Register U - 0x8C - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTDVU - Dead Time Value Register U + TMOF + Timeout Detection Flag 0 - 31 + 0 read-write + zeroToClear + modify + + + 0 + Timeout is not detected. + #0 + + + 1 + Timeout is detected. + #1 + + - GTDVD - General PWM Timer Dead Time Value Register D - 0x90 - 32 + ICBRL + I2C Bus Bit Rate Low-Level Register + 0x10 + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF + 0xFF + 0xFF - GTDVD - Dead Time Value Register D + BRL + Bit Rate Low-Level Period(Low-level period of SCL clock) 0 - 31 + 4 read-write - GTDBU - General PWM Timer Dead Time Buffer Register U - 0x94 - 32 + ICBRH + I2C Bus Bit Rate High-Level Register + 0x11 + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF + 0xFF + 0xFF - GTDVU - Dead Time Buffer Register U + BRH + Bit Rate High-Level Period(High-level period of SCL clock) 0 - 31 + 4 read-write - GTDBD - General PWM Timer Dead Time Buffer Register D - 0x98 - 32 + ICDRT + I2C Bus Transmit Data Register + 0x12 + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF + 0xFF + 0xFF - GTDBD - Dead Time Buffer Register D + ICDRT + 8-bit read-write register that stores transmit data. 0 - 31 + 7 read-write - GTSOS - General PWM Timer Output Protection Function Status Register - 0x9C - 32 + ICDRR + I2C Bus Receive Data Register + 0x13 + 8 read-only - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - SOS - Output Protection Function Status + ICDRR + 8-bit register that stores the received data 0 - 1 + 7 read-only - - - 00 - Normal operation - #00 - - - 01 - Protected state (GTCCRA = 0 is set during transfer at trough or crest) - #01 - - - 10 - Protected state (GTCCRA >= GTPR is set during transfer at trough) - #10 - - - 11 - Protected state (GTCCRA >= GTPR is set during transfer at crest) - #11 - - - GTSOTR - General PWM Timer Output Protection Function Temporary Release Register - 0xA0 - 32 + ICWUR + I2C Bus Wake Up Unit Register + 0x16 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x10 + 0xFF - SOTR - Output Protection Function Temporary Release - 0 - 0 + WUE + Wakeup Function Enable + 7 + 7 read-write 0 - Do not release protected state + Wakeup function disabled #0 1 - Release protected state + Wakeup function enabled. #1 - - - - GTICLF - General PWM Timer Inter Channel Logical Operation Function Setting Register - 0xB8 - 32 - read-write - 0x00000000 - 0xffffffff - - - ICLFA - GTIOCnA Output Logical Operation Function Select - 0 - 2 - read-write - - - 000 - A (no delay) - #000 - - - 001 - NOT A (no delay) - #001 - - - 010 - C (1PCLKGPT delay) - #010 - - - 011 - NOT C (1PCLKGPT delay) - #011 - - - 100 - A AND C (1PCLKGPT delay) - #100 - - - 101 - A OR C (1PCLKGPT delay) - #101 - - - 110 - A EXOR C (1PCLKGPT delay) - #110 - - - 111 - A NOR C (1PCLKGPT delay) - #111 - - - - - ICLFSELC - Inter Channel Signal C Select - 4 - 9 - read-write - - - 0x00 - GTIOC0A - 0x00 - - - 0x01 - GTIOC0B - 0x01 - - - 0x02 - GTIOC1A - 0x02 - - - 0x03 - GTIOC1B - 0x03 - - - 0x04 - GTIOC2A - 0x04 - - - 0x05 - GTIOC2B - 0x05 - - - 0x06 - GTIOC3A - 0x06 - - - 0x07 - GTIOC3B - 0x07 - - - 0x08 - GTIOC4A - 0x08 - - - 0x09 - GTIOC4B - 0x09 - - - 0x0A - GTIOC5A - 0x0a - - - 0x0B - GTIOC5B - 0x0b - - - 0x0C - GTIOC6A - 0x0c - - - 0x0D - GTIOC6B - 0x0d - - - 0x0E - GTIOC7A - 0x0e - - - 0x0F - GTIOC7B - 0x0f - - - 0x10 - GTIOC8A - 0x10 - - - 0x11 - GTIOC8B - 0x11 - - - 0x12 - GTIOC9A - 0x12 - - - 0x13 - GTIOC9B - 0x13 - - - Others - Setting prohibited - true - - - - ICLFB - GTIOCnB Output Logical Operation Function Select - 16 - 18 + WUIE + Wakeup Interrupt Request Enable + 6 + 6 read-write - 000 - B (no delay) - #000 - - - 001 - NOT B (no delay) - #001 - - - 010 - D (1PCLKGPT delay) - #010 - - - 011 - NOT D (1PCLKGPT delay) - #011 - - - 100 - B AND D (1PCLKGPT delay) - #100 - - - 101 - B OR D (1PCLKGPTn delay) - #101 - - - 110 - B EXOR D (1PCLKGPT delay) - #110 + 0 + Wakeup Interrupt Request (IIC0_WUI) disabled + #0 - 111 - B NOR D (1PCLKGPT delay) - #111 + 1 + Wakeup Interrupt Request (IIC0_WUI) enabled. + #1 - ICLFSELD - Inter Channel Signal D Select - 20 - 25 + WUF + Wakeup Event Occurrence Flag + 5 + 5 read-write - - - 0x00 - GTIOC0A - 0x00 - - - 0x01 - GTIOC0B - 0x01 - - - 0x02 - GTIOC1A - 0x02 - - - 0x03 - GTIOC1B - 0x03 - - - 0x04 - GTIOC2A - 0x04 - - - 0x05 - GTIOC2B - 0x05 - - - 0x06 - GTIOC3A - 0x06 - - - 0x07 - GTIOC3B - 0x07 - - - 0x08 - GTIOC4A - 0x08 - - - 0x09 - GTIOC4B - 0x09 - - - 0x0A - GTIOC5A - 0x0a - - - 0x0B - GTIOC5B - 0x0b - - - 0x0C - GTIOC6A - 0x0c - - - 0x0D - GTIOC6B - 0x0d - - - 0x0E - GTIOC7A - 0x0e - - - 0x0F - GTIOC7B - 0x0f + + + 0 + Slave address does not match during wakeup function + #0 - 0x10 - GTIOC8A - 0x10 + 1 + Slave address matches during wakeup function. + #1 + + + + WUACK + ACK bit for Wakeup Mode + 4 + 4 + read-write + - 0x11 - GTIOC8B - 0x11 + 0 + State of synchronous operation + #0 - 0x12 - GTIOC9A - 0x12 + 1 + State of asynchronous operation + #1 + + + + WUAFA + Wakeup Analog Filter Additional Selection + 0 + 0 + read-write + - 0x13 - GTIOC9B - 0x13 + 0 + Do not add the wakeup analog filter + #0 - Others - Setting prohibited - true + 1 + Add the wakeup analog filter. + #1 - GTPC - General PWM Timer Period Count Register - 0xBC - 32 + ICWUR2 + I2C Bus Wake up Unit Register 2 + 0x17 + 8 read-write - 0x00000000 - 0xffffffff + 0xFD + 0xFF - PCEN - Period Count Function Enable - 0 - 0 - read-write + WUSYF + Wake-up Function Synchronous Operation Status Flag + 2 + 2 + read-only 0 - Period count function is disabled + IIC asynchronous circuit enable condition #0 1 - Period count function is enabled + IIC synchronous circuit enable condition. #1 - ASTP - Automatic Stop Function Enable - 8 - 8 - read-write + WUASYF + Wake-up Function Asynchronous Operation Status Flag + 1 + 1 + read-only 0 - Automatic stop function is disabled + IIC synchronous circuit enable condition #0 1 - Automatic stop function is enabled + IIC asynchronous circuit enable condition. #1 - PCNT - Period Counter - 16 - 27 - read-write + WUSEN + Wake-up Function Synchronous Enable + 0 + 0 + read-only + + + 0 + IIC asynchronous circuit enable + #0 + + + 1 + IIC synchronous circuit enable + #1 + + + + + + R_IIC1 + 0x40053100 + + + R_IIC2 + 0x40053200 + + + R_IRDA + IrDA Interface + 0x40070F00 + + 0x00000000 + 0x01 + registers + + - GTSECSR - General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register - 0xD0 - 32 + IRCR + IrDA Control Register + 0x00 + 8 read-write - 0x00000000 - 0xffffffff + 0x00 + 0xFF - SECSEL0 - Channel 0 Operation Enable Bit Simultaneous Control Channel Select - 0 - 0 + IRE + IrDA Enable + 7 + 7 read-write 0 - Disable simultaneous control + Serial I/O pins are used for normal serial communication. #0 1 - Enable simultaneous control + Serial I/O pins are used for IrDA data communication. #1 - SECSEL1 - Channel 1 Operation Enable Bit Simultaneous Control Channel Select - 1 - 1 + IRTXINV + IRTXD Polarity Switching + 3 + 3 read-write 0 - Disable simultaneous control + Data to be transmitted is output to IRTXD as is. #0 1 - Enable simultaneous control + Data to be transmitted is output to IRTXD after the polarity is inverted. #1 - SECSEL2 - Channel 2 Operation Enable Bit Simultaneous Control Channel Select + IRRXINV + IRRXD Polarity Switching 2 2 read-write 0 - Disable simultaneous control + IRRXD input is used as received data as is. #0 1 - Enable simultaneous control + IRRXD input is used as received data after the polarity is inverted. #1 + + + + + + R_IWDT + Independent Watchdog Timer + 0x40044400 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x02 + registers + + + + IWDTRR + IWDT Refresh Register + 0x00 + 8 + read-write + 0xFF + 0xFF + + + IWDTRR + The counter is refreshed by writing 0x00 and then writing 0xFF to this register. + 0 + 7 + read-write + + + + + IWDTSR + IWDT Status Register + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + - SECSEL3 - Channel 3 Operation Enable Bit Simultaneous Control Channel Select - 3 - 3 + REFEF + Refresh Error Flag + 15 + 15 read-write + zeroToClear + modify 0 - Disable simultaneous control + Refresh error not occurred #0 1 - Enable simultaneous control + Refresh error occurred #1 - SECSEL4 - Channel 4 Operation Enable Bit Simultaneous Control Channel Select - 4 - 4 + UNDFF + Underflow Flag + 14 + 14 read-write + zeroToClear + modify 0 - Disable simultaneous control + Underflow not occurred #0 1 - Enable simultaneous control + Underflow occurred #1 - SECSEL5 - Channel 5 Operation Enable Bit Simultaneous Control Channel Select - 5 - 5 + CNTVAL + Counter ValueValue counted by the counter + 0 + 13 + read-only + + + + + + + R_JPEG + JPEG Codec + 0x400E6000 + + 0x00000000 + 0x002 + registers + + + 0x00000003 + 0x00F + registers + + + 0x00000040 + 0x014 + registers + + + 0x00000058 + 0x01C + registers + + + 0x0000008C + 0x008 + registers + + + 0x00000100 + 0x11C + registers + + + 0x00000220 + 0x0B2 + registers + + + 0x00000300 + 0x01C + registers + + + 0x00000320 + 0x0B2 + registers + + + + JCMOD + JPEG Code Mode Register + 0x000 + 8 + read-write + 0x00 + 0xFF + + + DSP + Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes. + 3 + 3 read-write 0 - Disable simultaneous control + Compression process #0 1 - Enable simultaneous control + Decompression process #1 - SECSEL6 - Channel 6 Operation Enable Bit Simultaneous Control Channel Select - 6 - 6 + REDU + Pixel FormatNOTE: Read-only in Decompression. + 0 + 2 read-write + + + 001 + YCbCr422(Compression) / YCbCr422(Decompression) + #001 + + + 000 + Setting prohibited(Compression) / YCbCr444(Decompression) + #000 + + + 110 + Setting prohibited(Compression) / YCbCr411/[Decompression] + #110 + + + 010 + Setting prohibited(Compression) / YCbCr420/[Decompression] + #010 + + + others + Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression]) + true + + + + + + + JCCMD + JPEG Code Command Register + 0x001 + 8 + write-only + 0x00 + 0x00 + + + BRST + Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued. + 7 + 7 + write-only 0 - Disable simultaneous control + No effect. #0 1 - Enable simultaneous control + Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers. #1 - SECSEL7 - Channel 7 Operation Enable Bit Simultaneous Control Channel Select - 7 - 7 - read-write + JEND + Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1 + 2 + 2 + write-only 0 - Disable simultaneous control + No effect. #0 1 - Enable simultaneous control + Clear all bits in JINTE0. #1 - SECSEL8 - Channel 8 Operation Enable Bit Simultaneous Control Channel Select - 8 - 8 - read-write + JRST + JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. + 1 + 1 + write-only 0 - Disable simultaneous control + No effect. #0 1 - Enable simultaneous control + Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0). #1 - SECSEL9 - Channel 9 Operation Enable Bit Simultaneous Control Channel Select - 9 - 9 - read-write + JSRT + JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. + 0 + 0 + write-only 0 - Disable simultaneous control + No effect. #0 1 - Enable simultaneous control + Start JPEG core processing #1 @@ -44867,333 +58214,222 @@ FMS2,1,0: - GTSECR - General PWM Timer Operation Enable Bit Simultaneous Control Register - 0xD4 - 32 + JCQTN + JPEG Code Quantization Table Number Register + 0x003 + 8 read-write - 0x00000000 - 0xffffffff + 0x00 + 0xFF - SBDCE - GTCCR Register Buffer Operation Simultaneous Enable - 0 - 0 + QT3 + Quantization table number for the third color component NOTE: Read-only in Decompression. + 4 + 5 read-write - 0 - Disable simultaneous enabling GTCCR buffer operations - #0 + 00 + Use quantization table No.0 (JCQTBL0) as the third color component. + #00 - 1 - Enable GTCCR register buffer operations simultaneously - #1 + 01 + Use quantization table No.1 (JCQTBL1) as the third color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the third color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the third color component. + #11 - SBDPE - GTPR Register Buffer Operation Simultaneous Enable - 1 - 1 + QT2 + Quantization table number for the second color component NOTE: Read-only in Decompression. + 2 + 3 read-write - 0 - Disable simultaneous enabling GTPR buffer operations - #0 + 00 + Use quantization table No.0 (JCQTBL0) as the second color component. + #00 - 1 - Enable GTPR register buffer operations simultaneously - #1 + 01 + Use quantization table No.1 (JCQTBL1) as the second color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the second color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the second color component. + #11 - SBDCD - GTCCR Register Buffer Operation Simultaneous Disable - 8 - 8 + QT1 + Quantization table number for the first color componentNOTE: Read-only in Decompression. + 0 + 1 read-write - 0 - Disable simultaneous disabling GTCCR buffer operations - #0 + 00 + Use quantization table No.0 (JCQTBL0) as the first color component. + #00 - 1 - Disable GTCCR register buffer operations simultaneously - #1 + 01 + Use quantization table No.1 (JCQTBL1) as the first color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the first color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the first color component. + #11 + + + + JCHTN + JPEG Code Huffman Table Number Register + 0x004 + 8 + read-write + 0x00 + 0xFF + - SBDPD - GTPR Register Buffer Operation Simultaneous Disable - 9 - 9 + HTA3 + Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression. + 5 + 5 read-write 0 - Disable simultaneous disabling GTPR buffer operations + AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1) #0 1 - Disable GTPR register buffer operations simultaneously + AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0) #1 - SPCE - Period Count Function Simultaneous Enable - 16 - 16 + HTD3 + Huffman table number (DC) for the third color component NOTE: Read-only in Decompression. + 4 + 4 read-write 0 - Disable simultaneous enabling period count function + DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1) #0 1 - Enable period count function simultaneously + DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0) #1 - SPCD - Period Count Function Simultaneous Disable - 24 - 24 + HTA2 + Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression. + 3 + 3 read-write 0 - Disable simultaneous disabling period count function + AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1) #0 1 - Disable period count function simultaneously + AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0) #1 - - - - - - R_GPT1 - 0x40078100 - - - R_GPT2 - 0x40078200 - - - R_GPT3 - 0x40078300 - - - R_GPT4 - 0x40078400 - - - R_GPT5 - 0x40078500 - - - R_GPT6 - 0x40078600 - - - R_GPT7 - 0x40078700 - - - R_GPT8 - 0x40078800 - - - R_GPT9 - 0x40078900 - - - R_GPT10 - 0x40078A00 - - - R_GPT11 - 0x40078B00 - - - R_GPT12 - 0x40078C00 - - - R_GPT13 - 0x40078D00 - - - R_GPT_ODC - PWM Delay Generation Circuit - 0x4007B000 - - 0x00000000 - 0x004 - registers - - - 0x00000018 - 0x020 - registers - - - - 4 - 4 - GTDLYR[%s] - PWM DELAY RISING - 0x18 - - A - GTIOCA Output Delay Register - 0 - 16 - read-write - 0x0000 - 0xFFFF - - - DLY - GTIOCnA Output Rising Edge Delay Setting - 0 - 4 - read-write - - - 00000 - No delay on rising edges - #00000 - - - others - Delay of DLY/32 times the PCLKD period is applied. - true - - - - - - - B - GTIOCB Output Delay Register - 2 - 16 - read-write - 0x0000 - 0xFFFF - - - DLY - GTIOCnA Output Rising Edge Delay Setting - 0 - 4 - read-write - - - 00000 - No delay on rising edges - #00000 - - - others - Delay of DLY/32 times the PCLKD period is applied. - true - - - - - - - - GTDLYF[%s] - PWM DELAY FALLING - 0x28 - - - GTDLYCR1 - PWM Output Delay Control Register1 - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - DLLMOD - DLL Mode Select - 8 - 8 + HTD2 + Huffman table number (DC) for the second color component NOTE: Read-only in Decompression. + 2 + 2 read-write 0 - 5 bit-mode + DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1) #0 1 - 4 bit-mode + DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0) #1 - DLYRST - PWM Delay Generation Circuit Reset + HTA1 + Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression. 1 1 read-write 0 - Normal operation + AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1) #0 1 - Reset + AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0) #1 - DLLEN - DLL Operation Enable + HTD1 + Huffman table number (DC) for the first color component NOTE: Read-only in Decompression. 0 0 read-write 0 - DLL operation is disabled + DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1) #0 1 - DLL operation is enabled + DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0) #1 @@ -45201,1340 +58437,2005 @@ FMS2,1,0: - GTDLYCR2 - PWM Output Delay Control Register2 - 0x02 - 16 + JCDRIU + JPEG Code DRI Upper Register + 0x005 + 8 read-write - 0x0000 - 0xFFFF + 0x00 + 0xFF - 1 - 1 - DLYDENB%s - PWM Delay Generation Circuit Disenable for GTIOCB - 12 - 12 + DRIU + Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. + 0 + 7 read-write - - - 0 - Delay generation circuit of GTIOCB is based on DLYEN1. - #0 - - - 1 - Delay generation circuit of GTIOCB is disabled. - #1 - - + + + + JCDRID + JPEG Code DRI Lower Register + 0x006 + 8 + read-write + 0x00 + 0xFF + - 1 - 1 - DLYEN%s - PWM Delay Generation Circuit enable - 8 - 8 + DRID + Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. + 0 + 7 read-write - - - 0 - Delay generation circuit of channel is enabled - #0 - - - 1 - Delay generation circuit of channel is disabled. - #1 - - + + + + JCVSZU + JPEG Code Vertical Size Upper Register + 0x007 + 8 + read-write + 0x00 + 0xFF + - 4 - 1 - DLYBS%s - PWM Delay Generation Circuit bypass + VSZU + Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. 0 - 0 + 7 read-write - - - 0 - Delay generation circuit of channel is bypassed. - #0 - - - 1 - Delay generation circuit of channel is not bypassed. - #1 - - - - - - R_GPT_OPS - Output Phase Switching for GPT - 0x40078FF0 - - 0x00000000 - 0x04 - registers - - - OPSCR - Output Phase Switching Control Register - 0x00 - 32 + JCVSZD + JPEG Code Vertical Size Lower Register + 0x008 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - NFCS - External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. - 30 - 31 + VSZD + Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 read-write - - - 00 - PCLK/1 - #00 - - - 01 - PCLK/4 - #01 - - - 10 - PCLK/16 - #10 - - - 11 - PCLK/64 - #11 - - + + + + JCHSZU + JPEG Code Horizontal Size Upper Register + 0x009 + 8 + read-write + 0x00 + 0xFF + - NFEN - External Input Noise Filter Enable - 29 - 29 + HSZU + Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCHSZD + JPEG Coded Horizontal Size Lower Register + 0x00A + 8 + read-write + 0x00 + 0xFF + + + HSZD + Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCDTCU + JPEG Code Data Count Upper Register + 0x00B + 8 + read-only + 0x00 + 0xFF + + + DCU + Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCM + JPEG Code Data Count Middle Register + 0x00C + 8 + read-only + 0x00 + 0xFF + + + DCM + Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCD + JPEG Code Data Count Lower Register + 0x00D + 8 + read-only + 0x00 + 0xFF + + + DCD + Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JINTE0 + JPEG Interrupt Enable Register 0 + 0x00E + 8 + read-write + 0x00 + 0xFF + + + INT7 + This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned. + 7 + 7 read-write 0 - Do not use a noise filter to the external input. + Disabled #0 1 - Use a noise filter to the external input. + Enabled #1 - GODF - Group output disable function - 26 - 26 + INT6 + This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 6 + 6 read-write 0 - This bit function is ignored. + Disabled #0 1 - Group disable will clear OPSCR.EN Bit. + Enabled #1 - GRP - Output disabled source selection - 24 - 25 + INT5 + This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 5 + 5 read-write - 00 - Select Group A output disable source - #00 - - - 01 - Select Group B output disable source - #01 - - - 10 - Select Group C output disable source - #10 + 0 + Disabled + #0 - 11 - Select Group D output disable source - #11 + 1 + Enabled + #1 - ALIGN - Input phase alignment - 21 - 21 + INT3 + This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. + 3 + 3 read-write 0 - Input phase is aligned to PCLK. + Disabled #0 1 - Input phase is aligned PWM. + Enabled #1 + + + + JINTS0 + JPEG Interrupt Status Register 0 + 0x00F + 8 + read-write + 0x00 + 0xFF + + + INS6 + This bit is set to 1 when this module completes compression process normally. + 6 + 6 + read-write + zeroToClear + modify + - RV - Output phase rotation direction reversal - 20 - 20 + INS5 + This bit is set to 1 when a compressed data error occurs. + 5 + 5 + read-write + zeroToClear + modify + + + INS3 + This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. + 3 + 3 + read-write + zeroToClear + modify + + + + + JCDERR + JPEG Code Decode Error Register + 0x010 + 8 + read-write + 0x0A + 0xFF + + + ERR + Error Code (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression. + 0 + 3 read-write - 0 - U/V/W-Phase output - #0 + 0000 + Normal(Decompression error codes)/Normal(Segment error codes) + #0000 - 1 - Output to reverse the V / W-phase - #1 + 0001 + SOI not detected(Decompression error codes) + #0001 + + + 0010 + SOF1 to SOFF detected(Decompression error codes) + #0010 + + + 0011 + Unprovided pixel format detected(Decompression error codes) + #0011 + + + 0100 + SOF accuracy error(Decompression error codes) + #0100 + + + 0101 + DQT accuracy error(Decompression error codes) + #0101 + + + 0110 + Component error 1(Decompression error codes) + #0110 + + + 0111 + Component error 2(Decompression error codes) + #0111 + + + 1000 + SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes) + #1000 + + + 1001 + SOS not detected(Decompression error codes) + #1001 + + + 1010 + EOI not detected (default)(Decompression error codes) + #1010 + + + 1011 + Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes) + #1011 + + + 1100 + Image size error detected(Decompression error codes)/Image size error(Segment error codes) + #1100 + + + 1101 + Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes) + #1101 + + + 1110 + Block data number error detected(Decompression error codes)/Block data number error(Segment error codes) + #1110 + + + others + Setting prohibited + true + + + + JCRST + JPEG Code Reset Register + 0x011 + 8 + read-only + 0x00 + 0xFF + - INV - Invert-Phase Output Control - 19 - 19 - read-write + RST + Operating State + 0 + 0 + read-only 0 - Positive Logic (Active High)output + State other than below #0 1 - Negative Logic (Active Low)output + Suspended state caused by interrupt sources of JINTE0 #1 + + + + JIFECNT + JPEG Interface Compression Control Register + 0x040 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - N - Negative-Phase Output (N) Control - 18 - 18 + JOUTSWAP + Byte/Halfword/Word Swap Output coded data in compression is swapped. + 8 + 10 read-write - 0 - Level signal output - #0 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - 1 - PWM signal output (PWM of GPT0) - #1 + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] + #111 - P - Positive-Phase Output (P) Control - 17 - 17 + DINRINI + Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + 6 + 6 read-write 0 - Level signal output + The transfer address is not initialized when the input of image data lines is restarted #0 1 - PWM signal output (PWM of GPT0) + The transfer address is initialized when the input of image data lines is restarted #1 - FB - External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. - 16 - 16 + DINRCMD + Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. + 5 + 5 + write-only + + + DINLC + Count Mode Setting for Stopping Input Image Data Lines + 4 + 4 read-write 0 - Select the external input. + Count mode for stopping the input of image data lines is off #0 1 - Select the soft setting(OPSCR.UF, VF, WF). + Count mode for stopping the input of image data lines is on #1 - EN - Enable-Phase Output Control - 8 - 8 + DINSWAP + Byte/Halfword Swap + 0 + 2 read-write - 0 - Not Output(Hi-Z external terminals). - #0 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - 1 - Output - #1 + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 + + + + JIFESA + JPEG Interface Compression Source Address Register + 0x044 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - W - Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 6 - 6 - read-only - - - V - Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 5 - 5 - read-only - - - U - Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 4 - 4 - read-only + ESA + Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + JIFESOFST + JPEG Interface Compression Line Offset Register + 0x048 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - WF - Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. - 2 - 2 + ESMW + Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0. + 0 + 14 read-write + + + + JIFEDA + JPEG Interface Compression Destination Address Register + 0x04C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - VF - Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. - 1 - 1 + EDA + Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 read-write + + + + JIFESLC + JPEG Interface Compression Source Line Count Register + 0x050 + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + - UF - Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + LINES + Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. 0 - 0 + 15 read-write - - - - R_GPT_POEG0 - Port Output Enable for GPT - 0x40042000 - - 0x00000000 - 0x04 - registers - - - POEGG - POEG Group Setting Register - 0x00 + JIFDCNT + JPEG Interface Decompression Control Register + 0x058 32 read-write - 0x00000000 + 0x01000000 0xFFFFFFFF - NFCS - Noise Filter Clock Select - 30 - 31 + VINTER + Vertical SubsamplingSubsamples vertical output image data. + 28 + 29 read-write 00 - Sampling GTETRG pin input level for three times in every PCLKB. + No subsampling + #00 + + + 01 + Subsamples output data into 1/2. + #01 + + + 10 + Subsamples output data into 1/4. + #10 + + + 11 + Subsamples output data into 1/8. + #11 + + + + + HINTER + Horizontal Subsampling Subsamples horizontal output image data. + 26 + 27 + read-write + + + 00 + No subsampling #00 01 - Sampling GTETRG pin input level for three times in every PCLKB /8. + Subsamples output data into 1/2. #01 10 - Sampling GTETRG pin input level for three times in every PCLKB /32. + Subsamples output data into 1/4. #10 11 - Sampling GTETRG pin input level for three times in every PCLKB /128. + Subsamples output data into 1/8. #11 - NFEN - Noise Filter Enable - 29 - 29 + OPF + Specifies output image data pixel format. + 24 + 25 read-write - 0 - Filtering noise disabled - #0 + 01 + ARGB8888 + #01 - 1 - Filtering noise enabled - #1 + 10 + RGB565 + #10 + + + others + Setting prohibited + true - INV - GTETRG Input Reverse - 28 - 28 + JINRINI + Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. + 14 + 14 read-write 0 - GTETRG Input + The transfer address is not initialized when the input of coded data is restarted. #0 1 - GTETRG Input Reversed. + The transfer address is initialized when the input of coded data is restarted. #1 - ST - GTETRG Input Status Flag - 16 - 16 - read-only + JINRCMD + Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. + 13 + 13 + write-only + + + JINC + Count Mode Setting for Stopping Input Coded Data + 12 + 12 + read-write 0 - GTETRG input after filtering is 0. + Count mode for stopping the input of coded data is off. #0 1 - GTETRG input after filtering is 1. + Count mode for stopping the input of coded data is on #1 - 6 - 1 - CDRE%s - Comparator Disable Request Enable. Note: Can be modified only once after a reset. + JINSWAP + Byte/Word/Longword Swap Input coded data in decompression is swapped. 8 - 8 + 10 read-write - 0 - A disable request of comparator 0 disabled. - #0 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - 1 - A disable request of comparator 0 enabled. - #1 + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 - OSTPE - Oscillation Stop Detection EnableNote: Can be modified only once after a reset. + DOUTRINI + Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. 6 6 read-write 0 - A output-disable request from the oscillation stop detection disabled. + The transfer address is not initialized when the output of lines of image data is restarted. #0 1 - A output-disable request from the oscillation stop detection enabled. + The transfer address is initialized when the output of lines of image data is restarted #1 - IOCE - Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. + DOUTRCMD + Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. 5 5 + write-only + + + DOUTLC + Count Mode for Stopping Output Image Data Lines + 4 + 4 read-write 0 - Disable output-disable requests from GPT disable request + Count mode for stopping the output of image data lines is off. #0 1 - Enable output-disable requests from GPT disable request + Count mode for stopping the output of image data lines is on #1 - PIDE - Port Input Detection EnableNote: Can be modified only once after a reset. - 4 - 4 + DOUTSWAP + Byte/Word Swap Output image data in decompression is swapped. + 0 + 2 + read-write + + + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 + + + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 + + + + + + + JIFDSA + JPEG Interface Decompression Source Address Register + 0x05C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DSA + Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFDDOFST + JPEG Interface Decompression Line Offset Register + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DDMW + Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + 0 + 14 + read-write + + + + + JIFDDA + JPEG Interface Decompression Destination Address Register + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DDA + Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFDSDC + JPEG Interface Decompression Source Data Count Register + 0x068 + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + + + JDATAS + Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. + 0 + 15 + read-write + + + + + JIFDDLC + JPEG Interface Decompression Destination Line Count Register + 0x06C + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + + + LINES + Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units. + 0 + 15 + read-write + + + + + JIFDADT + JPEG Interface Decompression alpha Set Register + 0x070 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALPHA + Setting of the alpha value for output in ARGB8888 format. + 0 + 7 + read-write + + + + + JINTE1 + JPEG Interrupt Enable Register 1 + 0x08C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. + 6 + 6 read-write 0 - A output-disable request from the GTETRG pins disabled. + Disables an interrupt request. #0 1 - A output-disable request from the GTETRG pins enabled. + Enables an interrupt request. #1 - SSF - Software Stop Flag - 3 - 3 + DINLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. + 5 + 5 read-write 0 - A output-disable request from software has not been generated. + Disables an interrupt request. #0 1 - A output-disable request from software has been generated. + Enables an interrupt request. #1 - OSTPF - Oscillation Stop Detection Flag + DBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. 2 2 read-write - zeroToClear - modify 0 - A output-disable request from the oscillation stop detection has not been generated. + Disables an interrupt request. #0 1 - A output-disable request from the oscillation stop detection has been generated. + Enables an interrupt request. #1 - IOCF - Real Time Overcurrent Detection Flag + JINEN + Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. 1 1 read-write - zeroToClear - modify 0 - A output-disable request from GPT disable request or comparator interrupt has not been generated. + Disables an interrupt request. #0 1 - A output-disable request from GPT disable request or comparator interrupt has been generated. + Enables an interrupt request. #1 - PIDF - Port Input Detection Flag + DOUTLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1 0 0 read-write - zeroToClear - modify 0 - A output-disable request from the GTETRG pin has not been generated. + Disables an interrupt request. #0 1 - A output-disable request from the GTETRG pin has been generated. + Enables an interrupt request. #1 - - - - R_GPT_POEG1 - 0x40042100 - - - R_GPT_POEG2 - 0x40042200 - - - R_GPT_POEG3 - 0x40042300 - - - R_ICU - Interrupt Controller Unit - 0x40006000 - - 0x00000000 - 0x010 - registers - - - 0x00000100 - 0x01 - registers - - - 0x00000120 - 0x02 - registers - - - 0x00000130 - 0x02 - registers - - - 0x00000140 - 0x02 - registers - - - 0x000001A0 - 0x04 - registers - + + JINTS1 + JPEG Interrupt Status Register 1 + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CBTF + This bit is set to 1 when the last output coded data is written in compression. + 6 + 6 + read-write + modify + + + DINLF + This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. + 5 + 5 + read-write + modify + + + DBTF + This bit is set to 1 when the last output image data is written in decompression. + 2 + 2 + read-write + modify + + + JINF + This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. This bit is valid only when the JINC bit in JIFDCNT is set to 1. + 1 + 1 + read-write + modify + + + DOUTLF + In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. + 0 + 0 + read-write + modify + + + + + 64 + 0x1 + JCQTBL0[%s] + Quantization Table 0 + 0x0100 + 8 + write-only + 0x00 + 0x00 + + + JCQTBL1[%s] + Quantization Table 1 + 0x0140 + + + JCQTBL2[%s] + Quantization Table 2 + 0x0180 + + + JCQTBL3[%s] + Quantization Table 3 + 0x01C0 + + + 28 + 0x1 + JCHTBD0[%s] + DC Huffman Table 0 + 0x0200 + 8 + read-write + 0x00 + 0x00 + + + JCHTBD1[%s] + DC Huffman Table 1 + 0x0300 + + + 178 + 0x1 + JCHTBA0[%s] + AC Huffman Table 0 + 0x0220 + 8 + read-write + 0x00 + 0x00 + + + JCHTBA1[%s] + DC Huffman Table 1 + 0x0320 + + + + + R_KINT + Key Interrupt Function + 0x40080000 - 0x00000200 - 0x02 + 0x00000000 + 0x01 registers - 0x00000280 - 0x020 + 0x00000004 + 0x01 registers - 0x00000300 - 0x180 + 0x00000008 + 0x01 registers - 16 - 0x1 - IRQCR[%s] - IRQ Control Register %s - 0x000 + KRCTL + KEY Return Control Register + 0x00 8 read-write 0x00 0xFF - FLTEN - IRQ Digital Filter Enable + KRMD + Usage of Key Interrupt Flags(KR0 to KR7) 7 7 read-write 0 - Digital filter disabled. + Do not use key interrupt flags #0 1 - Digital filter enabled. + Use key interrupt flags. #1 - FCLKSEL - IRQ Digital Filter Sampling Clock Select - 4 - 5 - read-write - - - 00 - PCLKB - #00 - - - 01 - PCLKB/8 - #01 - - - 10 - PCLKB/32 - #10 - - - 11 - PCLKB/64 - #11 - - - - - IRQMD - IRQ Detection Sense Select + KREG + Detection Edge Selection (KRF0 to KRF7) 0 - 1 + 0 read-write - 00 + 0 Falling edge - #00 + #0 - 01 + 1 Rising edge - #01 - - - 10 - Rising and falling edges - #10 - - - 11 - Low level - #11 + #1 - NMISR - Non-Maskable Interrupt Status Register - 0x140 - 16 - read-only - 0x0000 - 0xFFFF + KRF + KEY Return Flag Register + 0x04 + 8 + read-write + 0x00 + 0xFF + zeroToClear + modify - SPEST - CPU Stack pointer monitor Interrupt Status Flag - 12 - 12 - read-only - - - 0 - Interrupt not requested - #0 - - - 1 - Interrupt requested. - #1 - - - - - BUSMST - MPU Bus Master Error Interrupt Status Flag - 11 - 11 - read-only + KRF7 + Key interrupt flag 7 + 7 + 7 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - BUSSST - MPU Bus Slave Error Interrupt Status Flag - 10 - 10 - read-only + KRF6 + Key interrupt flag 6 + 6 + 6 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - RECCST - RAM ECC Error Interrupt Status Flag - 9 - 9 - read-only + KRF5 + Key interrupt flag 5 + 5 + 5 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - RPEST - RAM Parity Error Interrupt Status Flag - 8 - 8 - read-only + KRF4 + Key interrupt flag 4 + 4 + 4 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - NMIST - NMI Status Flag - 7 - 7 - read-only + KRF3 + Key interrupt flag 3 + 3 + 3 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - OSTST - Oscillation Stop Detection Interrupt Status Flag - 6 - 6 - read-only + KRF2 + Key interrupt flag 2 + 2 + 2 + read-write + zeroToClear + modify 0 - Interrupt not requested for main oscillation stop + No interrupt detected #0 1 - Interrupt requested for main oscillation stop. + Interrupt detected. #1 - VBATTST - VBATT monitor Interrupt Status Flag - 4 - 4 - read-only + KRF1 + Key interrupt flag 1 + 1 + 1 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 - LVD2ST - Voltage-Monitoring 2 Interrupt Status Flag - 3 - 3 - read-only + KRF0 + Key interrupt flag 0 + 0 + 0 + read-write + zeroToClear + modify 0 - Interrupt not requested + No interrupt detected #0 1 - Interrupt requested. + Interrupt detected. #1 + + + + KRM + KEY Return Mode Register + 0x08 + 8 + read-write + 0x00 + 0xFF + - LVD1ST - Voltage-Monitoring 1 Interrupt Status Flag - 2 - 2 - read-only + KRM7 + Key interrupt mode control 7 + 7 + 7 + read-write 0 - Interrupt not requested + Does not detect key interrupt signal #0 1 - Interrupt requested. + Detect key interrupt signal. #1 - WDTST - WDT Underflow/Refresh Error Status Flag - 1 - 1 - read-only + KRM6 + Key interrupt mode control 6 + 6 + 6 + read-write 0 - Interrupt not requested + Does not detect key interrupt signal #0 1 - Interrupt requested. + Detect key interrupt signal. #1 - IWDTST - IWDT Underflow/Refresh Error Status Flag - 0 - 0 - read-only + KRM5 + Key interrupt mode control 5 + 5 + 5 + read-write 0 - Interrupt not requested + Does not detect key interrupt signal #0 1 - Interrupt requested. + Detect key interrupt signal. #1 - TZFST - 13 - 13 - read-only + KRM4 + Key interrupt mode control 4 + 4 + 4 + read-write 0 - TRUST Zone Filter Error interrupt is not requested. + Does not detect key interrupt signal #0 1 - TRUST Zone Filter Error interrupt is requested. + Detect key interrupt signal. #1 - CPEST - 15 - 15 - read-only + KRM3 + Key interrupt mode control 3 + 3 + 3 + read-write 0 - Cache RAM Parity Error interrupt is not requested. + Does not detect key interrupt signal #0 1 - Cache RAM Parity Error interrupt is requested. + Detect key interrupt signal. #1 - - - - NMIER - Non-Maskable Interrupt Enable Register - 0x120 - 16 - read-write - 0x0000 - 0xFFFF - - SPEEN - CPU Stack pointer monitor Interrupt Enable - 12 - 12 + KRM2 + Key interrupt mode control 2 + 2 + 2 read-write 0 - Disabled + Does not detect key interrupt signal #0 1 - Enabled. + Detect key interrupt signal. #1 - BUSMEN - MPU Bus Master Error Interrupt Enable - 11 - 11 + KRM1 + Key interrupt mode control 1 + 1 + 1 read-write 0 - Disabled + Does not detect key interrupt signal #0 1 - Enabled. + Detect key interrupt signal. #1 - BUSSEN - MPU Bus Slave Error Interrupt Enable - 10 - 10 + KRM0 + Key interrupt mode control 0 + 0 + 0 read-write 0 - Disabled + Does not detect key interrupt signal #0 1 - Enabled. + Detect key interrupt signal. #1 + + + + + + I3C + I3C Bus Interface + 0x40083000 + + 0x00 + 4 + registers + + + 0x14 + 8 + registers + + + 0x20 + 8 + registers + + + 0x30 + 16 + registers + + + 0x44 + 4 + registers + + + 0x58 + 4 + registers + + + 0x60 + 8 + registers + + + 0x70 + 36 + registers + + + 0xA0 + 8 + registers + + + 0xB0 + 4 + registers + + + 0xC0 + 4 + registers + + + 0x140 + 4 + registers + + + 0x150 + 12 + registers + + + 0x17C + 8 + registers + + + 0x190 + 8 + registers + + + 0x1C0 + 4 + registers + + + 0x1D0 + 32 + registers + + + 0x214 + 4 + registers + + + 0x224 + 32 + registers + + + 0x2A0 + 4 + registers + + + 0x2B0 + 4 + registers + + + 0x2D0 + 16 + registers + + + 0x320 + 12 + registers + + + 0x330 + 4 + registers + + + 0x350 + 40 + registers + + + 0x380 + 4 + registers + + + 0x394 + 8 + registers + + + 0x3C0 + 4 + registers + + + 0x3CC + 8 + registers + + + + PRTS + Protocol Selection Register + 0x000 + 32 + read-write + 0x00000001 + 0xffffffff + - RECCEN - RAM ECC Error Interrupt Enable - 9 - 9 + PRTMD + Protocol Mode + 0 + 0 read-write 0 - Disabled + I3C protocol mode #0 1 - Enabled. + I2C protocol mode #1 + + + + BCTL + Bus Control Register + 0x014 + 32 + read-write + 0x00000000 + 0xffffffff + - RPEEN - RAM Parity Error Interrupt Enable - 8 - 8 + INCBA + Include I3C Broadcast Address + 0 + 0 read-write 0 - Disabled + Do not include I3C broadcast address for private transfers #0 1 - Enabled. + Include I3C broadcast address for private transfers #1 - NMIEN - NMI Pin Interrupt Enable + BMDS + Bus Mode Selection 7 7 read-write 0 - Disabled - #0 - - - 1 - Enabled. - #1 - - - - - OSTEN - Oscillation Stop Detection Interrupt Enable - 6 - 6 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled. - #1 - - - - - VBATTEN - VBATT monitor Interrupt Enable - 4 - 4 - read-write - - - 0 - Disabled + Legacy inclusive Bus mode disabled #0 1 - Enabled. + Legacy inclusive (mix) Bus mode enabled #1 - LVD2EN - Voltage-Monitoring 2 Interrupt Enable - 3 - 3 + HJACKCTL + Hot-Join Acknowledge Control + 8 + 8 read-write 0 - Disabled + ACK the Hot-Join request #0 1 - Enabled. + NACK and send broadcast CCC to disable Hot-Join #1 - LVD1EN - Voltage-Monitoring 1 Interrupt Enable - 2 - 2 + ABT + Abort + 29 + 29 read-write 0 - Disabled + I3C is running. #0 1 - Enabled. + I3C has aborted a transfer. #1 - WDTEN - WDT Underflow/Refresh Error Interrupt Enable - 1 - 1 + RSM + Resume + 30 + 30 read-write 0 - Disabled + I3C is running. #0 1 - Enabled. + I3C is suspended (RW1C). #1 - IWDTEN - IWDT Underflow/Refresh Error Interrupt Enable - 0 - 0 + BUSE + Bus Enable + 31 + 31 read-write 0 - Disabled + I3C bus operation is disabled. #0 1 - Enabled. + I3C bus operation is enabled. #1 + + + + MSDVAD + Master Device Address Register + 0x018 + 32 + read-write + 0x00000000 + 0xffffffff + - TZFEN - 13 - 13 + MDYAD + Master Dynamic Address + 16 + 22 read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - CPEEN - 15 - 15 + MDYADV + Master Dynamic Address Valid + 31 + 31 read-write 0 - Disabled + The master dynamic address field is not valid. #0 1 - Enabled + The master dynamic address field is valid. #1 @@ -46542,274 +60443,296 @@ FMS2,1,0: - NMICLR - Non-Maskable Interrupt Status Clear Register - 0x130 - 16 + RSTCTL + Reset Control Register + 0x020 + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xffffffff - SPECLR - CPU Stack Pointer Monitor Interrupt Clear - 12 - 12 - write-only + RI3CRST + I3C Software Reset + 0 + 0 + read-write 0 - No effect. + Reset of all registers and internal state. #0 1 - Clear the NMISR.SPEST flag. + Releases of all registers and internal state. #1 - BUSMCLR - Bus Master Error Clear - 11 - 11 - write-only + CMDQRST + Command Queue Software Reset + 1 + 1 + read-write 0 - No effect. + The Command Queues in I3C is not flushed. #0 1 - Clear the NMISR.BUSMST flag. + The Command Queues in I3C is flushed. #1 - BUSSCLR - Bus Slave Error Clear - 10 - 10 - write-only + RSPQRST + Response Queue Software Reset + 2 + 2 + read-write 0 - No effect. + The Response Queues in I3C is not flushed. #0 1 - Clear the NMISR.BUSSST flag. + The Response Queues in I3C is flushed. #1 - RECCCLR - SRAM ECC Error Clear - 9 - 9 - write-only + TDBRST + Transmit Data Buffer Software Reset + 3 + 3 + read-write 0 - No effect. + The Transmit Queues in I3C is not flushed. #0 1 - Clear the NMISR.RECCST flag. + The Transmit Queues in I3C is flushed. #1 - RPECLR - SRAM Parity Error Clear - 8 - 8 - write-only + RDBRST + Receive Data Buffer Software Reset + 4 + 4 + read-write 0 - No effect. + The Receive Queues in I3C is not flushed. #0 1 - Clear the NMISR.RPEST flag. + The Receive Queues in I3C is flushed. #1 - NMICLR - NMI Clear - 7 - 7 - write-only + IBIQRST + IBI Queue Software Reset + 5 + 5 + read-write 0 - No effect. + The IBI Queues in I3C is not flushed. #0 1 - Clear the NMISR.NMIST flag. + The IBI Queues in I3C is flushed. #1 - OSTCLR - OST Clear + RSQRST + Receive Status Queue Software Reset 6 6 - write-only - - - 0 - No effect. - #0 - - - 1 - Clear the NMISR.OSTST flag. - #1 - - - - - VBATTCLR - VBATT Clear - 4 - 4 - write-only + read-write 0 - No effect. + The Receive Status Queue in I3C is not flushed. #0 1 - Clear the NMISR.VBATTST flag. + The Receive Status Queue in I3C is flushed. #1 - LVD2CLR - LVD2 Clear - 3 - 3 - write-only + INTLRST + Internal Software Reset + 16 + 16 + read-write 0 - No effect. + BITCNT.BCNT[4:0], SVST, BST (not applicable to BST WUCNDDF) registers + releases, and Internal releases. #0 1 - Clear the NMISR.LVD2ST flag. + BITCNT.BCNT[4:0], SVST, BST (not applicable to BST WUCNDDF) registers resets, and + Internal resets. + #1 + + + + PRSST + Present State Register + 0x024 + 32 + read-write + 0x00000000 + 0xffffffff + - LVD1CLR - LVD1 Clear + CRMS + Current Master 2 2 - write-only + read-write 0 - No effect. + The Master is not the Current Master, and must request and acquire + bus ownership before initiating any transfer. #0 1 - Clear the NMISR.LVD1ST flag. + The Master is the Current Master, and as a result can initiate + transfers. #1 - WDTCLR - WDT Clear - 1 - 1 - write-only + TRMD + Transmit/Receive Mode + 4 + 4 + read-only 0 - No effect. + Receive mode #0 1 - Clear the NMISR.WDTST flag. + Transmit mode #1 - IWDTCLR - IWDT Clear - 0 - 0 + PRSSTWP + Present State Write Protect + 7 + 7 write-only 0 - No effect. + Bit CRMS are protected. #0 1 - Clear the NMISR.IWDTST flag. + Bit CRMS can be written (When writing simultaneously with the value of the + target bit) (This bit is read as 0.) #1 + + + + INST + Internal Status Register + 0x030 + 32 + read-write + 0x00000000 + 0xffffffff + - TZFCLR - 13 - 13 + INEF + Internal Error Flag + 10 + 10 read-write 0 - No effect + I3C Internal Error has not detected. #0 1 - Clear the NMISR.TZFCLR flag + I3C Internal Error has detected. #1 + + + + INSTE + Internal Status Enable Register + 0x034 + 32 + read-write + 0x00000000 + 0xffffffff + - CPECLR - 15 - 15 + INEE + Internal Error Enable + 10 + 10 read-write 0 - No effect + Disable INST.INEF #0 1 - Clear the NMISR.CPECLR flag + Enable INST.INEF #1 @@ -46817,77 +60740,60 @@ FMS2,1,0: - NMICR - NMI Pin Interrupt Control Register - 0x100 - 8 + INIE + Internal Interrupt Enable + Register + 0x038 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - NFLTEN - NMI Digital Filter Enable - 7 - 7 + INEIE + Internal Error Interrupt Enable + 10 + 10 read-write 0 - Digital filter is disabled. + Disables Non-recoverable Internal Error Interrupt Signal. #0 1 - Digital filter is enabled. + Enables Non-recoverable Internal Error Interrupt Signal. #1 + + + + INSTFC + Internal Status Force Register + 0x03C + 32 + read-write + 0x00000000 + 0xffffffff + - NFCLKSEL - NMI Digital Filter Sampling Clock Select - 4 - 5 - read-write - - - 00 - PCLKB - #00 - - - 01 - PCLKB/8 - #01 - - - 10 - PCLKB/32 - #10 - - - 11 - PCLKB/64 - #11 - - - - - NMIMD - NMI Detection Set - 0 - 0 - read-write + INEFC + Internal Error Force + 10 + 10 + write-only 0 - Falling edge + Not force a specific interrupt #0 1 - Rising edge + Force a specific interrupt #1 @@ -46895,780 +60801,960 @@ FMS2,1,0: - 96 - 0x4 - IELSR[%s] - ICU Event Link Setting Register %s - 0x300 + DVCT + Device Characteristic Table + Register + 0x044 + 32 + read-only + 0x00000000 + 0xffffffff + + + IDX + DCT Table Index + 19 + 23 + read-only + + + + + IBINCTL + IBI Notify Control Register + 0x058 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - DTCE - DTC Activation Enable - 24 - 24 + NRHJCTL + Notify Rejected Hot-Join Control + 0 + 0 read-write 0 - DTC activation is disabled + Do not pass rejected IBI Status to IBI Queue, if the incoming + HotJoin request is NACKed and is autodisabled based on field HJACKCTL of + BCTL. #0 1 - DTC activation is enabled + Pass rejected IBI Status to the IBI Queue, if the incoming Hot Join request is + NACKed and is autodisabled based on field HJACKCTL of BCTL. #1 - IR - Interrupt Status Flag - 16 - 16 + NRMRCTL + Notify Rejected Master Request Control + 1 + 1 read-write 0 - No interrupt request is generated + Do not pass rejected IBI Status to IBI Queue/Ring, if the incoming + Master Request is NACKed and is auto-disabled based on DVMRRJ field in relevant DAT + entry. #0 1 - An interrupt request is generated ( 1 write to the IR bit is prohibited. ) + Pass rejected IBI Status to the IBI Queue, if the incoming Master Request is + NACKed and is autodisabled based on DVMRRJ field in relevant DAT entry. #1 - IELS - ICU Event selection to NVICSet the number for the event signal to be linked . - 0 - 8 + NRSIRCTL + Notify Rejected Slave Interrupt Request Control + 3 + 3 read-write - 0x000 - Nothing is selected - 0x000 + 0 + Do not pass rejected IBI Status to the IBI Queue/Rings, if the + incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT + entry. + #0 - others - See Event Table - true + 1 + Pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed + and is auto-disabled based on DVSIRRJ field in relevant DAT entry. + #1 - 8 - 0x4 - DELSR[%s] - DMAC Event Link Setting Register - 0x280 + BFCTL + Bus Function Control Register + 0x060 32 read-write - 0x0000 - 0xFFFF + 0x00000101 + 0xffffffff - IR - Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited. - 16 - 16 + MALE + Master Arbitration-Lost Detection Enable + 0 + 0 read-write - 0x0 - No interrupt request is generated. + 0 + Master arbitration-lost detection disables. +(Disables the arbitration-lost detection function and does not clear the CRMS and + TRMD bits in PRSST automatically when arbitration is lost.) + #0 - 0x1 - An interrupt request is generated. + 1 + Master arbitration-lost detection enables. +(Enables the arbitration-lost detection function and clears the CRMS and TRMD + bits in PRSST automatically when arbitration is lost.) + #1 - DELS - Event selection to DMAC Start request - 0 - 8 + NALE + NACK Transmission Arbitration-Lost Detection Enable + 1 + 1 read-write - 0x000 - Nothing is selected. - 0x000 - - - others - See Event Table - true + 0 + NACK transmission arbitration-lost detection disables. + #0 - - - - - - SELSR0 - Snooze Event Link Setting Register - 0x200 - 16 - read-write - 0x0000 - 0xFFFF - - - SELS - SYS Event Link Select - 0 - 8 - read-write - - 0x000 - Nothing is selected - 0x000 + 1 + NACK transmission arbitration-lost detection enables. + #1 - - - - WUPEN - Wake Up Interrupt Enable Register - 0x1A0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - IIC0WUPEN - IIC0 address match interrupt S/W standby returns enable - 31 - 31 + SALE + Slave Arbitration-Lost Detection Enable + 2 + 2 read-write 0 - S/W standby returns by IIC0 address match interrupt is disabled + Slave arbitration-lost detection disables. #0 1 - S/W standby returns by IIC0 address match interrupt is enabled + Slave arbitration-lost detection enables. #1 - AGT1CBWUPEN - AGT1 compare match B interrupt S/W standby returns enable - 30 - 30 + SCSYNE + SCL Synchronous Circuit Enable + 8 + 8 read-write 0 - S/W standby returns by AGT1 compare match B interrupt is disabled + No SCL synchronous circuit uses. #0 1 - S/W standby returns by AGT1 compare match B interrupt is enabled + An SCL synchronous circuit uses. #1 - AGT1CAWUPEN - AGT1 compare match A interrupt S/W standby returns enable - 29 - 29 + SMBS + SMBus/I2C Bus Selection + 12 + 12 read-write 0 - S/W standby returns by AGT1 compare match A interrupt is disabled + The I2C bus select. #0 1 - S/W standby returns by AGT1 compare match A interrupt is enabled + The SMBus select. #1 - AGT1UDWUPEN - AGT1 underflow interrupt S/W standby returns enable - 28 - 28 + FMPE + Fast-mode Plus Enable + 14 + 14 read-write 0 - S/W standby returns by AGT1 underflow interrupt is disabled + No Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0) #0 1 - S/W standby returns by AGT1 underflow interrupt is enabled + An Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0) #1 - USBFSWUPEN - USBFS interrupt S/W standby returns enable - 27 - 27 + HSME + High Speed Mode Enable + 15 + 15 read-write 0 - S/W standby returns by USBFS interrupt is disabled + Disable High Speed Mode. #0 1 - S/W standby returns by USBFS interrupt is enabled + Enable High Speed Mode. #1 + + + + SVCTL + Slave Control Register + 0x064 + 32 + read-write + 0x00000000 + 0xffffffff + - USBHSWUPEN - USBHS interrupt S/W standby returns enable bit - 26 - 26 + GCAE + General Call Address Enable + 0 + 0 read-write 0 - S/W standby returns by USBHS interrupt is disabled + General call address detection disables. #0 1 - S/W standby returns by USBHS interrupt is enabled + General call address detection enables. #1 - RTCPRDWUPEN - RCT period interrupt S/W standby returns enable - 25 - 25 + HSMCE + Hs-mode Master Code Enable + 5 + 5 read-write 0 - S/W standby returns by RTC period interrupt is disabled + Hs-mode Master Code Detection disables. #0 1 - S/W standby returns by RTC period interrupt is enabled + Hs-mode Master Code Detection enables. #1 - RTCALMWUPEN - RTC alarm interrupt S/W standby returns enable - 24 - 24 + DVIDE + Device-ID Address Enable + 6 + 6 read-write 0 - S/W standby returns by RTC alarm interrupt is disabled + Device-ID address detection disables. #0 1 - S/W standby returns by RTC alarm interrupt is enabled + Device-ID address detection enables. #1 - ACMPLP0WUPEN - ACMPLP0 interrupt S/W standby returns enable - 23 - 23 + HOAE + Host Address Enable + 15 + 15 read-write 0 - S/W standby returns by ACMPLP0 interrupt is disabled + Host address detection disables. #0 1 - S/W standby returns by ACMPLP0 interrupt is enabled + Host address detection enables. #1 - ACMPHS0WUPEN - ACMPHS0 interrupt S/W standby returns enable bit - 22 - 22 + SVAEn + Slave Address Enable n (n = 0) + 16 + 16 read-write 0 - S/W standby returns by ACMPHS0 interrupt is disabled + Slave n disables #0 1 - S/W standby returns by ACMPHS0 interrupt is enabled + Slave n enables #1 + + + + REFCKCTL + Reference Clock Control + Register + 0x070 + 32 + read-write + 0x00000000 + 0xffffffff + - VBATTWUPEN - VBATT monitor interrupt S/W standby returns enable - 20 - 20 + IREFCKS + Internal Reference Clock Selection + 0 + 2 read-write - 0 - S/W standby returns by VBATT monitor interrupt is disabled - #0 + 000 + PCLKD/1 clock + #000 - 1 - S/W standby returns by VBATT monitor interrupt is enabled - #1 + 001 + PCLKD/2 clock + #001 + + + 010 + PCLKD/4 clock + #010 + + + 011 + PCLKD/8 clock + #011 + + + 100 + PCLKD/16 clock + #100 + + + 101 + PCLKD/32 clock + #101 + + + 110 + PCLKD/64 clock + #110 + + + 111 + PCLKD/128 clock + #111 + + + + STDBR + Standard Bit Rate Register + 0x074 + 32 + read-write + 0x3f3fffff + 0xffffffff + + + SBRLO + Count value of the Low-level period of SCL clock + 0 + 7 + read-write + - LVD2WUPEN - LVD2 interrupt S/W standby returns enable - 19 - 19 + SBRHO + Count value of the High-level period of SCL clock + 8 + 15 + read-write + + + SBRLP + Standard Bit Rate Low-level Period Push-Pull + 16 + 21 + read-write + + + SBRHP + Standard Bit Rate High-Level Period Push-Pull + 24 + 29 + read-write + + + DSBRPO + Double the Standard Bit Rate Period for Open-Drain + 31 + 31 read-write 0 - S/W standby returns by LVD2 interrupt is disabled + The time period set for SBRHO[7:0] and SBRLO[7:0] is + not doubled. + #0 1 - S/W standby returns by LVD2 interrupt is enabled + The time period set for SBRHO[7:0] and SBRLO[7:0] is + doubled. + #1 + + + + EXTBR + Extended Bit Rate Register + 0x078 + 32 + read-write + 0x1f3ffffe + 0xffffffff + - LVD1WUPEN - LVD1 interrupt S/W standby returns enable - 18 - 18 + EBRLO + Extended Bit Rate Low-Level Period Open-Drain + 0 + 7 + read-write + + + EBRHO + Extended Bit Rate High-Level Period Open-Drain + 8 + 15 + read-write + + + EBRLP + Extended Bit Rate Low-Level Period Push-Pull + 16 + 21 + read-write + + + EBRHP + Extended Bit Rate Low-Level Period Push-Pull + 24 + 29 + read-write + + + + + BFRECDT + Bus Free Condition Detection Time + Register + 0x07C + 32 + read-write + 0x00000000 + 0xffffffff + + + FRECYC + Bus Free Condition Detection Cycle + 0 + 8 + read-write + + + + + BAVLCDT + Bus Available Condition Detection Time + Register + 0x080 + 32 + read-write + 0x00000000 + 0xffffffff + + + AVLCYC + Bus Available Condition Detection Cycle + 0 + 8 + read-write + + + + + BIDLCDT + Bus Idle Condition Detection Time + Register + 0x084 + 32 + read-write + 0x00000000 + 0xffffffff + + + IDLCYC + Bus Idle Condition Detection Cycle + 0 + 17 + read-write + + + + + OUTCTL + Output Control Register + 0x088 + 32 + read-write + 0x00000003 + 0xffffffff + + + SDOC + SDA Output Control + 0 + 0 read-write 0 - S/W standby returns by LVD1 interrupt is disabled + I3C drives the SDAn pin low. #0 1 - S/W standby returns by LVD1 interrupt is enabled + I3C releases the SDAn pin. #1 - KEYWUPEN - Key interrupt S/W standby returns enable - 17 - 17 + SCOC + SCL Output Control + 1 + 1 read-write 0 - S/W standby returns by KEY interrupt is disabled + I3C drives the SCLn pin low. #0 1 - S/W standby returns by KEY interrupt is enabled + I3C releases the SCLn pin. #1 - IWDTWUPEN - IWDT interrupt S/W standby returns enable - 16 - 16 - read-write + SOCWP + SCL/SDA Output Control Write Protect + 2 + 2 + write-only 0 - S/W standby returns by IWDT interrupt is disabled + Bits SCOC and SDOC are protected. #0 1 - S/W standby returns by IWDT interrupt is enabled + Bits SCOC and SDOC can be written (When writing simultaneously with the value of + the target bit). +This bit is read as 0. + #1 - 16 - 0x01 - IRQWUPEN%s - IRQ interrupt S/W standby returns enable - 0 - 0 + EXCYC + Extra SCL Clock Cycle Output + 4 + 4 read-write 0 - S/W standby returns by IRQ interrupt is disabled + Does not output an extra SCL clock cycle (default). #0 1 - S/W standby returns by IRQ interrupt is enabled + Outputs an extra SCL clock cycle. #1 - - - - WUPEN1 - Wake Up interrupt enable register 1 - 0x1A4 - 32 - read-write - 0x00000000 - 0xffffffff - - AGT3UDWUPEN - AGT3 underflow interrupt S/W standby returns enable bit - 0 - 0 + SDOD + SDA Output Delay + 8 + 10 read-write - 0 - S/W standby returns by AGT3 underflow interrupt is disabled - #0 + 000 + No output delay + #000 - 1 - S/W standby returns by AGT3 underflow interrupt is enabled - #1 + 001 + 1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) +1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #001 + + + 010 + 2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #010 + + + 011 + 3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #011 + + + 100 + 4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #100 + + + 101 + 5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #101 + + + 110 + 6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #110 + + + 111 + 7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) +13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) + + #111 - AGT3CAWUPEN - AGT3 compare match A interrupt S/W standby returns enable bit - 1 - 1 + SDODCS + SDA Output Delay Clock Source Selection + 15 + 15 read-write 0 - S/W standby returns by AGT3 compare match A interrupt is disabled + The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter. #0 1 - S/W standby returns by AGT3 compare match A interrupt is enabled + The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter. #1 + + + + INCTL + Input Control Register + 0x08C + 32 + read-write + 0x000000d0 + 0xffffffff + + + DNFS + Digital Noise Filter Stage Selection + 0 + 3 + read-write + - AGT3CBWUPEN - AGT3 compare match B interrupt S/W standby returns enable bit - 2 - 2 + DNFE + Digital Noise Filter Circuit Enable + 4 + 4 read-write 0 - S/W standby returns by AGT3 compare match B interrupt is disabled + No digital noise filter circuit is used. #0 1 - S/W standby returns by AGT3 compare match B interrupt is enabled + A digital noise filter circuit is used. #1 - - - - R_IIC0 - I2C Bus Interface - 0x40053000 - - 0x00000000 - 0x014 - registers - - - 0x00000016 - 0x002 - registers - - - - 3 - 0x2 - SAR[%s] - Slave Address Registers - 0x0A - 16 - - L - Slave Address Register L - 0x0 - 8 - read-write - 0x00 - 0xFF - - - SVA - A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } - 0 - 7 - read-write - - - - - U - Slave Address Register U - 0x01 - 8 - read-write - 0x00 - 0xFF - - - SVA9 - 10-Bit Address(bit9) - 2 - 2 - read-write - - - SVA8 - 10-Bit Address(bit8) - 1 - 1 - read-write - - - FS - 7-Bit/10-Bit Address Format Selection - 0 - 0 - read-write - - - 0 - The 7-bit address format is selected. - #0 - - - 1 - The 10-bit address format is selected. - #1 - - - - - - - ICCR1 - I2C Bus Control Register 1 - 0x00 - 8 + TMOCTL + Timeout Control Register + 0x090 + 32 read-write - 0x1F - 0xFF + 0x00000030 + 0xffffffff - ICE - I2C Bus Interface Enable - 7 - 7 + TODTS + Timeout Detection Time Selection + 0 + 1 read-write - 0 - Disable (SCLn and SDAn pins in inactive state) - #0 + 00 + 16bit-timeout + #00 - 1 - Enable (SCLn and SDAn pins in active state) - #1 + 01 + 14bit-timeout + #01 + + + 10 + 8bit-timeout + #10 + + + 11 + 6bit-timeout + #11 - - IICRST - I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). - 6 - 6 + + TOLCTL + Timeout L Count Control + 4 + 4 read-write 0 - Releases the RIIC reset or internal reset. + Count is disabled while the SCLn line is at a low level. #0 1 - Initiates the RIIC reset or internal reset. + Count is enabled while the SCLn line is at a low level. #1 - CLO - Extra SCL Clock Cycle Output + TOHCTL + Timeout H Count Control 5 5 read-write 0 - Does not output an extra SCL clock cycle. + Count is disabled while the SCLn line is at a high level. #0 1 - Outputs an extra SCL clock cycle. + Count is enabled while the SCLn line is at a high level. #1 - SOWP - SCLO/SDAO Write Protect - 4 - 4 + TOMDS + Timeout Operation Mode Selection + 6 + 7 read-write - 0 - Bits SCLO and SDAO can be written - #0 + 00 + Timeout is detected during the following conditions: +The bus is busy (BCST.BFREF = 0) in master mode.I3C’s own slave address is detected and the bus is busy in slave + mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is + requested (CNDCTL.STCND = 1). + #00 - 1 - Bits SCLO and SDAO are protected. - #1 + 01 + Timeout is detected while the bus is busy. + #01 - - - - SCLO - SCL Output Control/Monitor - 3 - 3 - read-write - - 0 - (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. - #0 + 10 + Timeout is detected while the bus is free. + #10 - 1 - (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. - #1 + 11 + Setting prohibited + #11 + + + + ACKCTL + Acknowledge Control Register + 0x0A0 + 32 + read-write + 0x00000000 + 0xffffffff + - SDAO - SDA Output Control/Monitor - 2 - 2 - read-write + ACKR + Acknowledge Reception + 0 + 0 + read-only 0 - (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. + A 0 is received as the acknowledge bit (ACK reception). #0 1 - (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. + A 1 is received as the acknowledge bit (NACK reception). #1 - SCLI - SCL Line Monitor + ACKT + Acknowledge Transmission 1 1 - read-only + read-write 0 - SCLn line is low. + A 0 is sent as the acknowledge bit (ACK transmission). #0 1 - SCLn line is high. + A 1 is sent as the acknowledge bit (NACK transmission). #1 - SDAI - SDA Line Monitor - 0 - 0 - read-only + ACKTWP + ACKT Write Protect + 2 + 2 + write-only 0 - SDAn line is low. + The ACKT bit are protected. #0 1 - SDAn line is high. + The ACKT bit can be written (when writing simultaneously with the + value of the target bit). +This bit is read as 0. + #1 @@ -47676,124 +61762,153 @@ FMS2,1,0: - ICCR2 - I2C Bus Control Register 2 - 0x01 - 8 + SCSTRCTL + SCL Stretch Control Register + 0x0A4 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - BBSY - Bus Busy Detection Flag - 7 - 7 - read-only + ACKTWE + Acknowledge Transmission Wait Enable + 0 + 0 + read-write 0 - The I2C bus is released (bus free state). + NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. + (The SCLn line is not held low at the falling edge of the eighth clock + cycle.) #0 1 - The I2C bus is occupied (bus busy state). + NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The SCLn + line is held low at the falling edge of the eighth clock cycle.) +Low-hold is released by writing a value to the ACKCTL.ACKT bit. + #1 - MST - Master/Slave Mode - 6 - 6 + RWE + Receive Wait Enable + 1 + 1 read-write 0 - Slave mode + No WAIT (The period between ninth clock cycle and first clock cycle + is not held low.) #0 1 - Master mode + WAIT (The period between ninth clock cycle and first clock cycle is held + low.) +Low-hold is released by reading NTDTBPn (n = 0) + #1 + + + + SCSTLCTL + SCL Stalling Control Register + 0x0B0 + 32 + read-write + 0x00000000 + 0xffffffff + + + STLCYC + Stalling Cycle + 0 + 15 + read-write + - TRS - Transmit/Receive Mode - 5 - 5 + AAPE + Assigend Address Phase Enable + 28 + 28 read-write 0 - Receive mode + Does not stall the SCL clock during the address assignment + phase. #0 1 - Transmit mode + Stall the SCL clock during address assignment phase. #1 - SP - Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. - 3 - 3 + TRAPE + Transition Phase Enable + 29 + 29 read-write 0 - Does not request to issue a stop condition. + Does not stall the SCL clock during the transition bit in read + transfer. #0 1 - Requests to issue a stop condition. + Stall the SCL clock during the transition bit in read transfer. #1 - RS - Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. - 2 - 2 + PARPE + Parity Phase Enable + 30 + 30 read-write 0 - Does not request to issue a restart condition. + Does not stall the SCL clock during the parity bit period. #0 1 - Requests to issue a restart condition. + Stall the SCL clock during the parity bit period. #1 - ST - Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). - 1 - 1 + ACKPE + ACK phase Enable + 31 + 31 read-write 0 - Does not request to issue a start condition. + Does not stall the SCL clock during the ACK/NACK phase. #0 1 - Requests to issue a start condition. + Stall the SCL clock during the ACK/NACK phase. #1 @@ -47801,599 +61916,605 @@ FMS2,1,0: - ICMR1 - I2C Bus Mode Register 1 - 0x02 - 8 + SVTDLG0 + Slave Transfer Data Length Register 0 + 0x0C0 + 32 read-write - 0x08 - 0xFF + 0x00000000 + 0xffffffff - MTWP - MST/TRS Write Protect - 7 - 7 + STDLG + Slave Transfer Data Length + 16 + 31 + read-write + + + + + CNDCTL + Condition Control Register + 0x140 + 32 + read-write + 0x00000000 + 0xffffffff + + + STCND + START (S) Condition Issuance + 0 + 0 read-write 0 - Disables writing to the MST and TRS bits in ICCR2. + Does not request to issue a START condition. #0 1 - Enables writing to the MST and TRS bits in ICCR2. + Requests to issue a START condition. #1 - CKS - Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) - 4 - 6 + SRCND + Repeated START (Sr) Condition Issuance + 1 + 1 read-write - 000 - PCLKB/1 clock - #000 - - - 001 - PCLKB/2 clock - #001 - - - 010 - PCLKB/4 clock - #010 - - - 011 - PCLKB/8 clock - #011 - - - 100 - PCLKB/16 clock - #100 - - - 101 - PCLKB/32 clock - #101 - - - 110 - PCLKB/64 clock - #110 + 0 + Does not request to issue a Repeated START condition. + #0 - 111 - PCLKB/128 clock - #111 + 1 + Requests to issue a Repeated START condition. + #1 - BCWP - BC Write Protect(This bit is read as 1.) - 3 - 3 - write-only + SPCND + STOP (P) Condition Issuance + 2 + 2 + read-write 0 - Enables a value to be written in the BC[2:0] bits. + Does not request to issue a STOP condition. #0 1 - Disables a value to be written in the BC[2:0] bits. + Requests to issue a STOP condition. #1 + + + + NCMDQP + Normal Command Queue Port + Register + 0x150 + 32 + write-only + 0x00000000 + 0xffffffff + + + NRSPQP + Normal Response Queue Port + Register + 0x154 + 32 + read-only + 0x00000000 + 0xffffffff + + + NTDTBP0 + Normal Transfer Data Buffer Port Register + 0 + 0x158 + 32 + read-write + 0x00000000 + 0xffffffff + + + NIBIQP + Normal IBI Queue Port Register + 0x17C + 32 + read-write + 0x00000000 + 0xffffffff + + + NRSQP + Normal Receive Status Queue Port + Register + 0x180 + 32 + read-only + 0x00000000 + 0xffffffff + + + NQTHCTL + Normal Queue Threshold Control + Register + 0x190 + 32 + read-write + 0x01010101 + 0xffffffff + - BC - Bit Counter + CMDQTH + Normal Command Ready Queue Threshold 0 - 2 + 7 read-write - 000 - 9 bits - #000 - - - 001 - 2 bits - #001 - - - 010 - 3 bits - #010 - - - 011 - 4 bits - #011 - - - 100 - 5 bits - #100 + 0 + Interrupt is issued when Command Queue is completely empty. + #0 - 101 - 6 bits - #101 + Others + Interrupt is issued when Command Queue contains N empties. (N = CMDQTH[7:0]) + true + + + + RSPQTH + Normal Response Queue Threshold + 8 + 15 + read-write + - 110 - 7 bits - #110 + 0 + Interrupt is issued when Response Queue contains 1 entry + (DWORD). + #0 - 111 - 8 bits - #111 + Others + Interrupt is triggered when Response Queue contains N+1 entries (DWORD). (N = + CMDQTH[7:0]) + true - - - - ICMR2 - I2C Bus Mode Register 2 - 0x03 - 8 - read-write - 0x06 - 0xFF - - DLCS - SDA Output Delay Clock Source Select - 7 - 7 + IBIDSSZ + Normal IBI Data Segment Size + 16 + 23 + read-write + + + IBIQTH + Normal IBI Queue Threshold + 24 + 31 read-write 0 - The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. + I3C Protocol mode (Master): +Interrupt is generated when the Outstanding IBI Status count is >= 1. +I3C Protocol mode (Slave): +Interrupt is issued when IBI Data Buffer is completely empty. + #0 - 1 - The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. - #1 + Others + I3C Protocol mode (Master): +Interrupt is generated when the Outstanding IBI Status is >= N + 1. (N = CMDQTH[7:0]) +I3C Protocol mode (Slave): +Interrupt is issued when IBI Data Buffer contains N empties. + + true + + + + NTBTHCTL0 + Normal Transfer Data Buffer Threshold + Control Register 0 + 0x194 + 32 + read-write + 0x01010101 + 0xffffffff + - SDDL - SDA Output Delay Counter - 4 - 6 + TXDBTH + Normal Transmit Data Buffer Threshold + 0 + 2 read-write - 000 - No output delay - #000 + 0x0 + Interrupt triggers at 2 Tx Buffer empties, DWORDs + 0x0 - 001 - 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) - #001 + 0x1 + Interrupt triggers at 4 Tx Buffer empties, DWORDs + 0x1 - 010 - 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) - #010 + 0x2 + Interrupt triggers at 8 Tx Buffer empties, DWORDs + 0x2 - 011 - 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) - #011 + 0x3 + Interrupt triggers at 16 Tx Buffer empties, DWORDs + 0x3 - 100 - 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) - #100 + 0x4 + Interrupt triggers at 32 Tx Buffer empties, DWORDs + 0x4 - 101 - 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) - #101 + 0x5 + Interrupt triggers at 64 Tx Buffer empties, DWORDs + 0x5 - 110 - 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) - #110 + 0x6 + Interrupt triggers at 128 Tx Buffer empties, DWORDs + 0x6 - 111 - 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) - #111 + 0x7 + Interrupt triggers at 256 Tx Buffer empties, DWORDs + 0x7 - TMOH - Timeout H Count Control - 2 - 2 + RXDBTH + Normal Receive Data Buffer Threshold + 8 + 10 read-write - 0 - Count is disabled while the SCLn line is at a high level. - #0 + 0x0 + Interrupt triggers at 2 Rx Buffer entries, DWORDs + 0x0 - 1 - Count is enabled while the SCLn line is at a high level. - #1 + 0x1 + Interrupt triggers at 4 Rx Buffer entries, DWORDs + 0x1 - - - - TMOL - Timeout L Count Control - 1 - 1 - read-write - - 0 - Count is disabled while the SCLn line is at a low level. - #0 + 0x2 + Interrupt triggers at 8 Rx Buffer entries, DWORDs + 0x2 - 1 - Count is enabled while the SCLn line is at a low level. - #1 + 0x3 + Interrupt triggers at 16 Rx Buffer entries, DWORDs + 0x3 - - - - TMOS - Timeout Detection Time Select - 0 - 0 - read-write - - 0 - Long mode is selected. - #0 + 0x4 + Interrupt triggers at 32 Rx Buffer entries, DWORDs + 0x4 - 1 - Short mode is selected. - #1 + 0x5 + Interrupt triggers at 64 Rx Buffer entries, DWORDs + 0x5 - - - - - - ICMR3 - I2C Bus Mode Register 3 - 0x04 - 8 - read-write - 0x00 - 0xFF - - - SMBS - SMBus/I2C Bus Selection - 7 - 7 - read-write - - 0 - The I2C bus is selected. - #0 + 0x6 + Interrupt triggers at 128 Rx Buffer entries, DWORDs + 0x6 - 1 - The SMBus is selected. - #1 + 0x7 + Interrupt triggers at 256 Rx Buffer entries, DWORDs + 0x7 - WAIT - WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. - 6 - 6 + TXSTTH + Normal Tx Start Threshold + 16 + 18 read-write - 0 - No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) - #0 + 0x0 + Wait for 2 DWORDs + 0x0 - 1 - WAIT (The period between ninth clock cycle and first clock cycle is held low.) - #1 + 0x1 + Wait for 4 DWORDs + 0x1 - - - - RDRFS - RDRF Flag Set Timing Selection - 5 - 5 - read-write - - 0 - The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) - #0 + 0x2 + Wait for 8 DWORDs + 0x2 - 1 - The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) - #1 + 0x3 + Wait for 16 DWORDs + 0x3 - - - - ACKWP - ACKBT Write Protect - 4 - 4 - read-write - - 0 - Modification of the ACKBT bit is disabled. - #0 + 0x4 + Wait for 32 DWORDs + 0x4 - 1 - Modification of the ACKBT bit is enabled. - #1 + 0x5 + Wait for 64 DWORDs + 0x5 + + + 0x6 + Wait for 128 DWORDs + 0x6 + + + 0x7 + Wait for 256 DWORDs + 0x7 - ACKBT - Transmit Acknowledge - 3 - 3 + RXSTTH + Normal Rx Start Threshold + 24 + 26 read-write - 0 - A 0 is sent as the acknowledge bit (ACK transmission). - #0 + 0x0 + Wait for 2 empty DWORDs + 0x0 - 1 - A 1 is sent as the acknowledge bit (NACK transmission). - #1 + 0x1 + Wait for 4 empty DWORDs + 0x1 - - - - ACKBR - Receive Acknowledge - 2 - 2 - read-only - - 0 - A 0 is received as the acknowledge bit (ACK reception). - #0 + 0x2 + Wait for 8 empty DWORDs + 0x2 - 1 - A 1 is received as the acknowledge bit (NACK reception). - #1 + 0x3 + Wait for 16 empty DWORDs + 0x3 - - - - NF - Noise Filter Stage Selection - 0 - 1 - read-write - - 00 - Noise of up to one fIIC cycle is filtered out (single-stage filter). - #00 + 0x4 + Wait for 32 empty DWORDs + 0x4 - 01 - Noise of up to two fIIC cycles is filtered out (2-stage filter). - #01 + 0x5 + Wait for 64 empty DWORDs + 0x5 - 10 - Noise of up to three fIIC cycles is filtered out (3-stage filter). - #10 + 0x6 + Wait for 128 empty DWORDs + 0x6 - 11 - Noise of up to four fIIC cycles is filtered out (4-stage filter) - #11 + 0x7 + Wait for 256 empty DWORDs + 0x7 - ICFER - I2C Bus Function Enable Register - 0x05 - 8 + NRQTHCTL + Normal Receive Status Queue Threshold + Control Register + 0x1C0 + 32 read-write - 0x72 - 0xFF + 0x00000001 + 0xffffffff - FMPE - Fast-mode Plus Enable - 7 + RSQTH + Normal Receive Status Queue Threshold + 0 7 read-write 0 - No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. + Interrupt is issued when Receive Status Queue contains 1 entry + (DWORD). #0 - 1 - An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. - #1 + Others + Interrupt is triggered when Receive Status Queue contains N+1 entries (DWORD). + (N = RSQTH[7:0]) + true + + + + BST + Bus Status Register + 0x1D0 + 32 + read-write + 0x00000000 + 0xffffffff + - SCLE - SCL Synchronous Circuit Enable - 6 - 6 + STCNDDF + START condition Detection Flag + 0 + 0 read-write 0 - No SCL synchronous circuit is used. + START condition Detection Interrupt does not occur. #0 1 - An SCL synchronous circuit is used. + START condition Detection Interrupt occurs. #1 - NFE - Digital Noise Filter Circuit Enable - 5 - 5 + SPCNDDF + STOP condition Detection Flag + 1 + 1 read-write 0 - No digital noise filter circuit is used. + STOP condition Detection Interrupt does not occur. #0 1 - A digital noise filter circuit is used. + STOP condition Detection Interrupt occurs. #1 - NACKE - NACK Reception Transfer Suspension Enable - 4 - 4 + HDREXDF + HDR Exit Pattern Detection Flag + 2 + 2 read-write 0 - Transfer operation is not suspended during NACK reception (transfer suspension disabled). + HDR Exit Pattern Detection Interrupt does not occur. #0 1 - Transfer operation is suspended during NACK reception (transfer suspension enabled). + HDR Exit Pattern Detection Interrupt occurs. #1 - SALE - Slave Arbitration-Lost Detection Enable - 3 - 3 + NACKDF + NACK Detection Flag + 4 + 4 read-write 0 - Slave arbitration-lost detection is disabled. + NACK Detection Interrupt does not occur. #0 1 - Slave arbitration-lost detection is enabled. + NACK Detection Interrupt occurs. #1 - NALE - NACK Transmission Arbitration-Lost Detection Enable - 2 - 2 + TENDF + Transmit End Flag + 8 + 8 read-write 0 - NACK transmission arbitration-lost detection is disabled. + Transmit End Interrupt does not occur. #0 1 - NACK transmission arbitration-lost detection is enabled. + Transmit End Interrupt occurs. #1 - MALE - Master Arbitration-Lost Detection Enable - 1 - 1 + ALF + Arbitration Lost Flag + 16 + 16 read-write 0 - Master arbitration-lost detection is disabled. + Arbitration Lost Interrupt does not occur. #0 1 - Master arbitration-lost detection is enabled. + Arbitration Lost Interrupt occurs. #1 - TMOE - Timeout Function Enable - 0 - 0 + TODF + Timeout Detection Flag + 20 + 20 read-write 0 - The timeout function is disabled. + Timeout Detection Interrupt does not occur. #0 1 - The timeout function is enabled. + Timeout Detection Interrupt occurs. #1 @@ -48401,287 +62522,287 @@ FMS2,1,0: - ICSER - I2C Bus Status Enable Register - 0x06 - 8 + BSTE + Bus Status Enable Register + 0x1D4 + 32 read-write - 0x09 - 0xFF + 0x00000000 + 0xffffffff - HOAE - Host Address Enable - 7 - 7 + STCNDDE + START condition Detection Enable + 0 + 0 read-write 0 - Host address detection is disabled. + Disables START condition Detection Interrupt Status logging. #0 1 - Host address detection is enabled. + Enables START condition Detection Interrupt Status logging. #1 - DIDE - Device-ID Address Detection Enable - 5 - 5 + SPCNDDE + STOP condition Detection Enable + 1 + 1 read-write 0 - Device-ID address detection is disabled. + Disables STOP condition Detection Interrupt Status logging. #0 1 - Device-ID address detection is enabled. + Enables STOP condition Detection Interrupt Status logging. #1 - GCAE - General Call Address Enable - 3 - 3 + HDREXDE + HDR Exit Pattern Detection Enable + 2 + 2 read-write 0 - General call address detection is disabled. + Disables HDR Exit Pattern Detection Interrupt Status logging. #0 1 - General call address detection is enabled. + Enables HDR Exit Pattern Detection Interrupt Status logging. #1 - SAR2E - Slave Address Register 2 Enable - 2 - 2 + NACKDE + NACK Detection Enable + 4 + 4 read-write 0 - Slave address in SARL2 and SARU2 is disabled. + Disables NACK Detection Interrupt Status logging. #0 1 - Slave address in SARL2 and SARU2 is enabled + Enables NACK Detection Interrupt Status logging. #1 - SAR1E - Slave Address Register 1 Enable - 1 - 1 + TENDE + Transmit End Enable + 8 + 8 read-write 0 - Slave address in SARL1 and SARU1 is disabled. + Disables Transmit End Interrupt Status logging. #0 1 - Slave address in SARL1 and SARU1 is enabled. + Enables Transmit End Interrupt Status logging. #1 - SAR0E - Slave Address Register 0 Enable - 0 - 0 + ALE + Arbitration Lost Enable + 16 + 16 read-write 0 - Slave address in SARL0 and SARU0 is disabled. + Disables Arbitration Lost Interrupt Status logging. #0 1 - Slave address in SARL0 and SARU0 is enabled. + Enables Arbitration Lost Interrupt Status logging. #1 - - - - ICIER - I2C Bus Interrupt Enable Register - 0x07 - 8 - read-write - 0x00 - 0xFF - - TIE - Transmit Data Empty Interrupt Request Enable - 7 - 7 + TODE + Timeout Detection Enable + 20 + 20 read-write 0 - Transmit data empty interrupt request (IIC_TXI) is disabled. + Disables Timeout Detection Interrupt Status logging. #0 1 - Transmit data empty interrupt request (IIC_TXI) is enabled. + Enables Timeout Detection Interrupt Status logging. #1 + + + + BIE + Bus Interrupt Enable Register + 0x1D8 + 32 + read-write + 0x00000000 + 0xffffffff + - TEIE - Transmit End Interrupt Request Enable - 6 - 6 + STCNDDIE + START condition Detection Interrupt Enable + 0 + 0 read-write 0 - Transmit end interrupt request (IIC_TEI) is disabled. + Disables START condition Detection Interrupt Signal. #0 1 - Transmit end interrupt request (IIC_TEI) is enabled. + Enables START condition Detection Interrupt Signal. #1 - RIE - Receive Data Full Interrupt Request Enable - 5 - 5 + SPCNDDIE + STOP condition Detection Interrupt Enable + 1 + 1 read-write 0 - Receive data full interrupt request (IIC_RXI) is disabled. + Disables STOP condition Detection Interrupt Signal. #0 1 - Receive data full interrupt request (IIC_RXI) is enabled. + Enables STOP condition Detection Interrupt Signal. #1 - NAKIE - NACK Reception Interrupt Request Enable - 4 - 4 + HDREXDIE + HDR Exit Pattern Detection Interrupt Enable + 2 + 2 read-write 0 - NACK reception interrupt request (NAKI) is disabled. + Disables HDR Exit Pattern Detection Interrupt Signal. #0 1 - NACK reception interrupt request (NAKI) is enabled. + Enables HDR Exit Pattern Detection Interrupt Signal. #1 - SPIE - Stop Condition Detection Interrupt Request Enable - 3 - 3 + NACKDIE + NACK Detection Interrupt Enable + 4 + 4 read-write 0 - Stop condition detection interrupt request (SPI) is disabled. + Disables NACK Detection Interrupt Signal. #0 1 - Stop condition detection interrupt request (SPI) is enabled. + Enables NACK Detection Interrupt Signal. #1 - STIE - Start Condition Detection Interrupt Request Enable - 2 - 2 + TENDIE + Transmit End Interrupt Enable + 8 + 8 read-write 0 - Start condition detection interrupt request (STI) is disabled. + Disables Transmit End Interrupt Signal. #0 1 - Start condition detection interrupt request (STI) is enabled. + Enables Transmit End Interrupt Signal. #1 ALIE - Arbitration-Lost Interrupt Request Enable - 1 - 1 + Arbitration Lost Interrupt Enable + 16 + 16 read-write 0 - Arbitration-lost interrupt request (ALI) is disabled. + Disables Arbitration Lost Interrupt Signal. #0 1 - Arbitration-lost interrupt request (ALI) is enabled. + Enables Arbitration Lost Interrupt Signal. #1 - TMOIE - Timeout Interrupt Request Enable - 0 - 0 + TODIE + Timeout Detection Interrupt Enable + 20 + 20 read-write 0 - Timeout interrupt request (TMOI) is disabled. + Disables Timeout Detection Interrupt Signal. #0 1 - Timeout interrupt request (TMOI) is enabled. + Enables Timeout Detection Interrupt Signal. #1 @@ -48689,487 +62810,354 @@ FMS2,1,0: - ICSR1 - I2C Bus Status Register 1 - 0x08 - 8 + BSTFC + Bus Status Force Register + 0x1DC + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - HOA - Host Address Detection Flag - 7 - 7 - read-write - zeroToClear - modify - - - 0 - Host address is not detected. - #0 - - - 1 - Host address is detected. - #1 - - - - - DID - Device-ID Address Detection Flag - 5 - 5 - read-write - - - 0 - Device-ID command is not detected. - #0 - - - 1 - Device-ID command is detected. - #1 - - - - - GCA - General Call Address Detection Flag - 3 - 3 - read-write - - - 0 - General call address is not detected. - #0 - - - 1 - General call address is detected. - #1 - - - - - AAS2 - Slave Address 2 Detection Flag - 2 - 2 - read-write - zeroToClear - modify + STCNDDFC + START condition Detection Force + 0 + 0 + write-only 0 - Slave address 2 is not detected. + Not Force START condition Detection Interrupt for software + testing. #0 1 - Slave address 2 is detected + Force START condition Detection Interrupt for software testing. #1 - AAS1 - Slave Address 1 Detection Flag + SPCNDDFC + STOP condition Detection Force 1 1 - read-write - zeroToClear - modify - - - 0 - Slave address 1 is not detected. - #0 - - - 1 - Slave address 1 is detected. - #1 - - - - - AAS0 - Slave Address 0 Detection Flag - 0 - 0 - read-write - zeroToClear - modify + write-only 0 - Slave address 0 is not detected. + Not Force STOP condition Detection Interrupt for software + testing. #0 1 - Slave address 0 is detected. + Force STOP condition Detection Interrupt for software testing. #1 - - - - ICSR2 - I2C Bus Status Register 2 - 0x09 - 8 - read-write - 0x00 - 0xFF - - TDRE - Transmit Data Empty Flag - 7 - 7 - read-only + HDREXDFC + HDR Exit Pattern Detection Force + 2 + 2 + write-only 0 - ICDRT contains transmit data. + Not Force HDR Exit Pattern Detection Interrupt for software testing. #0 1 - ICDRT contains no transmit data. + Force HDR Exit Pattern Detection Interrupt for software testing. #1 - TEND - Transmit End Flag - 6 - 6 - read-write - zeroToClear - modify + NACKDFC + NACK Detection Force + 4 + 4 + write-only 0 - Data is being transmitted. + Not Force NACK Detection Interrupt for software testing. #0 1 - Data has been transmitted. + Force NACK Detection Interrupt for software testing. #1 - RDRF - Receive Data Full Flag - 5 - 5 - read-write - zeroToClear - modify + TENDFC + Transmit End Force + 8 + 8 + write-only 0 - ICDRR contains no receive data. + Not Force Transmit End Interrupt for software testing. #0 1 - ICDRR contains receive data. + Force Transmit End Interrupt for software testing. #1 - NACKF - NACK Detection Flag - 4 - 4 - read-write - zeroToClear - modify + ALFC + Arbitration Lost Force + 16 + 16 + write-only 0 - NACK is not detected. + Not Force Arbitration Lost Interrupt for software testing. #0 1 - NACK is detected. + Force Arbitration Lost Interrupt for software testing. #1 - STOP - Stop Condition Detection Flag - 3 - 3 - read-write - zeroToClear - modify + TODFC + Timeout Detection Force + 20 + 20 + write-only 0 - Stop condition is not detected. + Not Force Timeout Detection Interrupt for software testing. #0 1 - Stop condition is detected. + Force Timeout Detection Interrupt for software testing. #1 + + + + NTST + Normal Transfer Status Register + 0x1E0 + 32 + read-write + 0x00000000 + 0xffffffff + - START - Start Condition Detection Flag - 2 - 2 + TDBEF0 + Normal Transmit Data Buffer Empty Flag 0 + 0 + 0 read-write - zeroToClear - modify 0 - Start condition is not detected. + For I2C protocol mode: PRTS.PRTMD bit = 1. +Normal Transmit Data Buffer 0 contains transmit data. +For I3C protocol mode: PRTS.PRTMD bit = 0. +The number of empties in the Normal Transmit Data +Buffer 0 is < the NTBTHCTL0.TXDBTH[2:0] threshold. + #0 1 - Start condition is detected. + For I2C protocol mode: PRTS.PRTMD bit = 1. +Normal Transmit Data Buffer 0 contains no transmit data. +For I3C protocol mode: PRTS.PRTMD bit = 0. +The number of empties in the Normal Transmit Data +Buffer 0 is >= the NTBTHCTL0.TXDBTH[2:0] threshold. + #1 - AL - Arbitration-Lost Flag + RDBFF0 + Normal Receive Data Buffer Full Flag 0 1 1 read-write - zeroToClear - modify 0 - Arbitration is not lost. + For I2C protocol mode: PRTS.PRTMD bit = 1. +Normal Receive Data Buffer0 contains no receive data. +For I3C Protocol mode: PRTS.PRTMD bit = 0. +The number of entries in the Normal Receive Data +Buffer 0 is < the NTBTHCTL0.RXDBTH[2:0] threshold. + #0 1 - Arbitration is lost. + For I2C protocol mode: PRTS.PRTMD bit = 1. +Normal Receive Data Buffer0 contains receive data. +For I3C Protocol mode: PRTS.PRTMD bit = 0. +The number of entries in the Normal Receive Data +Buffer 0 is >= the NTBTHCTL0.RXDBTH[2:0] threshold. + #1 - TMOF - Timeout Detection Flag - 0 - 0 + IBIQEFF + Normal IBI Queue Empty/Full Flag + 2 + 2 read-write - zeroToClear - modify 0 - Timeout is not detected. + For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. +The number of IBI Status Queue entries is <= the NQTHCTL.IBIQTH threshold. +For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. +If the NQTHCTL.IBIQTH = 0: +The number of IBI Data Buffer empties is < the IBI Data Buffer size. +If the NQTHCTL.IBIQTH is other than 0: +The number of IBI Data Buffer empties is < the NQTHCTL.IBIQTH threshold. + #0 1 - Timeout is detected. + For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. +The number of IBI Status Queue entries is > the NQTHCTL.IBIQTH threshold. +For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. +If the NQTHCTL.IBIQTH = 0: +The number of IBI Data Buffer empties is the IBI Data Buffer size. +If the NQTHCTL.IBIQTH is other than 0: +The number of IBI Data Buffer empties is >= the NQTHCTL.IBIQTH threshold. + #1 - - - - ICBRL - I2C Bus Bit Rate Low-Level Register - 0x10 - 8 - read-write - 0xFF - 0xFF - - - BRL - Bit Rate Low-Level Period(Low-level period of SCL clock) - 0 - 4 - read-write - - - - - ICBRH - I2C Bus Bit Rate High-Level Register - 0x11 - 8 - read-write - 0xFF - 0xFF - - - BRH - Bit Rate High-Level Period(High-level period of SCL clock) - 0 - 4 - read-write - - - - - ICDRT - I2C Bus Transmit Data Register - 0x12 - 8 - read-write - 0xFF - 0xFF - - - ICDRT - 8-bit read-write register that stores transmit data. - 0 - 7 - read-write - - - - - ICDRR - I2C Bus Receive Data Register - 0x13 - 8 - read-only - 0x00 - 0xFF - - - ICDRR - 8-bit register that stores the received data - 0 - 7 - read-only - - - - - ICWUR - I2C Bus Wake Up Unit Register - 0x16 - 8 - read-write - 0x10 - 0xFF - - WUE - Wakeup Function Enable - 7 - 7 + CMDQEF + Normal Command Queue Empty Flag + 3 + 3 read-write 0 - Wakeup function disabled + If the NQTHCTL.CMDQTH = 0: +The number of Command Queue empties is < the Command Queue size. +If the NQTHCTL.CMDQTH is other than 0: +The number of Command Queue empties is < the NQTHCTL.CMDQTH threshold. + #0 1 - Wakeup function enabled. + If the NQTHCTL.CMDQTH = 0: +The number of Command Queue empties is the Command Queue size. +If the NQTHCTL.CMDQTH is other than 0: +1: The number of Command Queue empties is >= the NQTHCTL.CMDQTH threshold. + #1 - WUIE - Wakeup Interrupt Request Enable - 6 - 6 + RSPQFF + Normal Response Queue Full Flag + 4 + 4 read-write 0 - Wakeup Interrupt Request (IIC0_WUI) disabled + The number of Response Queue entries is <= the NQTHCTL.RSPQTH threshold. #0 1 - Wakeup Interrupt Request (IIC0_WUI) enabled. + The number of Response Queue entries is > the NQTHCTL.RSPQTH threshold. #1 - WUF - Wakeup Event Occurrence Flag + TABTF + Normal Transfer Abort Flag 5 5 read-write 0 - Slave address does not match during wakeup function + Transfer Abort does not occur. #0 1 - Slave address matches during wakeup function. + Transfer Abort occur. +To clear, write 0 to this bit after 1 state is read. + #1 - WUACK - ACK bit for Wakeup Mode - 4 - 4 + TEF + Normal Transfer Error Flag + 9 + 9 read-write 0 - State of synchronous operation + Transfer Error does not occur. #0 1 - State of asynchronous operation + Transfer Error occurs. +To clear, write 0 to this bit after 1 state is read. + #1 - WUAFA - Wakeup Analog Filter Additional Selection - 0 - 0 + RSQFF + Normal Receive Status Queue Full Flag + 20 + 20 read-write 0 - Do not add the wakeup analog filter + The number of Receive Status Queue entries is <= the NRQTHCTL.RSQTH threshold. #0 1 - Add the wakeup analog filter. + The number of Receive Status Queue entries is > the NRQTHCTL.RSQTH threshold. #1 @@ -49177,453 +63165,327 @@ FMS2,1,0: - ICWUR2 - I2C Bus Wake up Unit Register 2 - 0x17 - 8 + NTSTE + Normal Transfer Status Enable + Register + 0x1E4 + 32 read-write - 0xFD - 0xFF + 0x00000000 + 0xffffffff - WUSYF - Wake-up Function Synchronous Operation Status Flag - 2 - 2 - read-only + TDBEE0 + Normal Transmit Data Buffer Empty Enable 0 + 0 + 0 + read-write 0 - IIC asynchronous circuit enable condition + Disables Tx0 Data Buffer Empty Interrupt Status logging. #0 1 - IIC synchronous circuit enable condition. + Enables Tx0 Data Buffer Empty Interrupt Status logging. #1 - WUASYF - Wake-up Function Asynchronous Operation Status Flag + RDBFE0 + Normal Receive Data Buffer Full Enable 0 1 1 - read-only + read-write 0 - IIC synchronous circuit enable condition + Disables Rx0 Data Buffer Full Interrupt Status logging. #0 1 - IIC asynchronous circuit enable condition. + Enables Rx0 Data Buffer Full Interrupt Status logging. #1 - WUSEN - Wake-up Function Synchronous Enable - 0 - 0 - read-only + IBIQEFE + Normal IBI Queue Empty/Full Enable + 2 + 2 + read-write 0 - IIC asynchronous circuit enable + Disables IBI Status Buffer Full Interrupt Status logging. #0 1 - IIC synchronous circuit enable + Enables IBI Status Buffer Full Interrupt Status logging. #1 - - - - - - R_IIC1 - 0x40053100 - - - R_IIC2 - 0x40053200 - - - R_IRDA - IrDA Interface - 0x40070F00 - - 0x00000000 - 0x01 - registers - - - - IRCR - IrDA Control Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - IRE - IrDA Enable - 7 - 7 + CMDQEE + Normal Command Queue Empty Enable + 3 + 3 read-write 0 - Serial I/O pins are used for normal serial communication. + Disables Command Buffer Empty Interrupt Status logging. #0 1 - Serial I/O pins are used for IrDA data communication. + Enables Command Buffer Empty Interrupt Status logging. #1 - IRTXINV - IRTXD Polarity Switching - 3 - 3 + RSPQFE + Normal Response Queue Full Enable + 4 + 4 read-write 0 - Data to be transmitted is output to IRTXD as is. + Disables Response Buffer Full Interrupt Status logging. #0 1 - Data to be transmitted is output to IRTXD after the polarity is inverted. + Enables Response Buffer Full Interrupt Status logging. #1 - IRRXINV - IRRXD Polarity Switching - 2 - 2 + TABTE + Normal Transfer Abort Enable + 5 + 5 read-write 0 - IRRXD input is used as received data as is. + Disables Transfer Abort Interrupt Status logging. #0 1 - IRRXD input is used as received data after the polarity is inverted. + Enables Transfer Abort Interrupt Status logging. #1 - - - - - - R_IWDT - Independent Watchdog Timer - 0x40044400 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x02 - registers - - - - IWDTRR - IWDT Refresh Register - 0x00 - 8 - read-write - 0xFF - 0xFF - - - IWDTRR - The counter is refreshed by writing 0x00 and then writing 0xFF to this register. - 0 - 7 - read-write - - - - - IWDTSR - IWDT Status Register - 0x04 - 16 - read-write - 0x0000 - 0xFFFF - - REFEF - Refresh Error Flag - 15 - 15 + TEE + Normal Transfer Error Enable + 9 + 9 read-write - zeroToClear - modify 0 - Refresh error not occurred + Disables Transfer Error Interrupt Status logging. #0 1 - Refresh error occurred + Enables Transfer Error Interrupt Status logging. #1 - UNDFF - Underflow Flag - 14 - 14 + RSQFE + Normal Receive Status Queue Full Enable + 20 + 20 read-write - zeroToClear - modify 0 - Underflow not occurred + Disables Receive Status Buffer Full Interrupt Status logging. #0 1 - Underflow occurred + Enables Receive Status Buffer Full Interrupt Status logging. #1 - - CNTVAL - Counter ValueValue counted by the counter - 0 - 13 - read-only - - - - - R_JPEG - JPEG Codec - 0x400E6000 - - 0x00000000 - 0x002 - registers - - - 0x00000003 - 0x00F - registers - - - 0x00000040 - 0x014 - registers - - - 0x00000058 - 0x01C - registers - - - 0x0000008C - 0x008 - registers - - - 0x00000100 - 0x11C - registers - - - 0x00000220 - 0x0B2 - registers - - - 0x00000300 - 0x01C - registers - - - 0x00000320 - 0x0B2 - registers - - - JCMOD - JPEG Code Mode Register - 0x000 - 8 + NTIE + Normal Transfer Interrupt Enable + Register + 0x1E8 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - DSP - Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes. - 3 - 3 + TDBEIE0 + Normal Transmit Data Buffer Empty Interrupt Enable 0 + 0 + 0 read-write 0 - Compression process + Disables Tx0 Data Buffer Empty Interrupt Signal. #0 1 - Decompression process + Enables Tx0 Data Buffer Empty Interrupt Signal. #1 - REDU - Pixel FormatNOTE: Read-only in Decompression. - 0 - 2 + RDBFIE0 + Normal Receive Data Buffer Full Interrupt Enable 0 + 1 + 1 read-write - 001 - YCbCr422(Compression) / YCbCr422(Decompression) - #001 + 0 + Disables Rx0 Data Buffer Full Interrupt Signal. + #0 - 000 - Setting prohibited(Compression) / YCbCr444(Decompression) - #000 + 1 + Enables Rx0 Data Buffer Full Interrupt Signal. + #1 + + + + IBIQEFIE + Normal IBI Queue Empty/Full Interrupt Enable + 2 + 2 + read-write + - 110 - Setting prohibited(Compression) / YCbCr411/[Decompression] - #110 + 0 + Disables IBI Status Buffer Full Interrupt Signal. + #0 - 010 - Setting prohibited(Compression) / YCbCr420/[Decompression] - #010 + 1 + Enables IBI Status Buffer Full Interrupt Signal. + #1 + + + + CMDQEIE + Normal Command Queue Empty Interrupt Enable + 3 + 3 + read-write + - others - Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression]) - true + 0 + Disables Command Buffer Empty Interrupt Signal. + #0 + + + 1 + Enables Command Buffer Empty Interrupt Signal. + #1 - - - - JCCMD - JPEG Code Command Register - 0x001 - 8 - write-only - 0x00 - 0x00 - - BRST - Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued. - 7 - 7 - write-only + RSPQFIE + Normal Response Queue Full Interrupt Enable + 4 + 4 + read-write 0 - No effect. + Disables Response Buffer Full Interrupt Signal. #0 1 - Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers. + Enables Response Buffer Full Interrupt Signal. #1 - JEND - Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1 - 2 - 2 - write-only + TABTIE + Normal Transfer Abort Interrupt Enable + 5 + 5 + read-write 0 - No effect. + Disables Transfer Abort Interrupt Signal. #0 1 - Clear all bits in JINTE0. + Enables Transfer Abort Interrupt Signal. #1 - JRST - JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. - 1 - 1 - write-only + TEIE + Normal Transfer Error Interrupt Enable + 9 + 9 + read-write 0 - No effect. + Disables Transfer Error Interrupt Signal. #0 1 - Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0). + Enables Transfer Error Interrupt Signal. #1 - JSRT - JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. - 0 - 0 - write-only + RSQFIE + Normal Receive Status Queue Full Interrupt Enable + 20 + 20 + read-write 0 - No effect. + Disables Receive Status Buffer Full Interrupt Signal. #0 1 - Start JPEG core processing + Enables Receive Status Buffer Full Interrupt Signal. #1 @@ -49631,471 +63493,275 @@ FMS2,1,0: - JCQTN - JPEG Code Quantization Table Number Register - 0x003 - 8 + NTSTFC + Normal Transfer Status Force + Register + 0x1EC + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - QT3 - Quantization table number for the third color component NOTE: Read-only in Decompression. - 4 - 5 - read-write + TDBEFC0 + Normal Transmit Data Buffer Empty Force 0 + 0 + 0 + write-only - 00 - Use quantization table No.0 (JCQTBL0) as the third color component. - #00 - - - 01 - Use quantization table No.1 (JCQTBL1) as the third color component. - #01 - - - 10 - Use quantization table No.2 (JCQTBL2) as the third color component. - #10 + 0 + Not Force Tx0 Data Buffer Empty Interrupt for software + testing. + #0 - 11 - Use quantization table No.3 (JCQTBL3) as the third color component. - #11 + 1 + Force Tx0 Data Buffer Empty Interrupt for software testing. + #1 - QT2 - Quantization table number for the second color component NOTE: Read-only in Decompression. - 2 - 3 - read-write + RDBFFC0 + Normal Receive Data Buffer Full Force 0 + 1 + 1 + write-only - 00 - Use quantization table No.0 (JCQTBL0) as the second color component. - #00 - - - 01 - Use quantization table No.1 (JCQTBL1) as the second color component. - #01 - - - 10 - Use quantization table No.2 (JCQTBL2) as the second color component. - #10 + 0 + Not Force Rx0 Data Buffer Full Interrupt for software + testing. + #0 - 11 - Use quantization table No.3 (JCQTBL3) as the second color component. - #11 + 1 + Force Rx0 Data Buffer Full Interrupt for software testing. + #1 - QT1 - Quantization table number for the first color componentNOTE: Read-only in Decompression. - 0 - 1 - read-write + IBIQEFFC + Normal IBI Queue Empty/Full Force + 2 + 2 + write-only - 00 - Use quantization table No.0 (JCQTBL0) as the first color component. - #00 - - - 01 - Use quantization table No.1 (JCQTBL1) as the first color component. - #01 - - - 10 - Use quantization table No.2 (JCQTBL2) as the first color component. - #10 + 0 + Not Force IBI Status Buffer Full Interrupt for software testing. + #0 - 11 - Use quantization table No.3 (JCQTBL3) as the first color component. - #11 + 1 + Force IBI Status Buffer Full Interrupt for software testing. + #1 - - - - JCHTN - JPEG Code Huffman Table Number Register - 0x004 - 8 - read-write - 0x00 - 0xFF - - HTA3 - Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression. - 5 - 5 - read-write + CMDQEFC + Normal Command Queue Empty Force + 3 + 3 + write-only 0 - AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1) + Not Force Command Buffer Empty Interrupt for software testing. #0 1 - AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0) + Force Command Buffer Empty Interrupt for software testing. #1 - HTD3 - Huffman table number (DC) for the third color component NOTE: Read-only in Decompression. + RSPQFFC + Normal Response Queue Full Force 4 4 - read-write + write-only 0 - DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1) + Not Force Response Buffer Full Interrupt for software testing. #0 1 - DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0) + Force Response Buffer Full Interrupt for software testing. #1 - HTA2 - Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression. - 3 - 3 - read-write + TABTFC + Normal Transfer Abort Force + 5 + 5 + write-only 0 - AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1) + Not Force Transfer Abort Interrupt for software testing. #0 1 - AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0) + Force Transfer Abort Interrupt for software testing. #1 - HTD2 - Huffman table number (DC) for the second color component NOTE: Read-only in Decompression. - 2 - 2 - read-write + TEFC + Normal Transfer Error Force + 9 + 9 + write-only 0 - DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1) + Not Force Transfer Error Interrupt for software testing. #0 1 - DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0) + Force Transfer Error Interrupt for software testing. #1 - HTA1 - Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression. - 1 - 1 - read-write + RSQFFC + Normal Receive Status Queue Full Force + 20 + 20 + write-only 0 - AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1) + Not Force Receive Status Buffer Full Interrupt for software testing. #0 1 - AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0) + Force Receive Status Buffer Full Interrupt for software testing. #1 + + + + SVST + Slave Status Register + 0x214 + 32 + read-write + 0x00000000 + 0xffffffff + - HTD1 - Huffman table number (DC) for the first color component NOTE: Read-only in Decompression. + GCAF + General Call Address Detection Flag 0 0 read-write 0 - DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1) + General call address does not detect. #0 1 - DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0) + General call address detects. #1 - - - - JCDRIU - JPEG Code DRI Upper Register - 0x005 - 8 - read-write - 0x00 - 0xFF - - - DRIU - Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCDRID - JPEG Code DRI Lower Register - 0x006 - 8 - read-write - 0x00 - 0xFF - - - DRID - Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCVSZU - JPEG Code Vertical Size Upper Register - 0x007 - 8 - read-write - 0x00 - 0xFF - - - VSZU - Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCVSZD - JPEG Code Vertical Size Lower Register - 0x008 - 8 - read-write - 0x00 - 0xFF - - - VSZD - Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCHSZU - JPEG Code Horizontal Size Upper Register - 0x009 - 8 - read-write - 0x00 - 0xFF - - - HSZU - Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCHSZD - JPEG Coded Horizontal Size Lower Register - 0x00A - 8 - read-write - 0x00 - 0xFF - - - HSZD - Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write - - - - - JCDTCU - JPEG Code Data Count Upper Register - 0x00B - 8 - read-only - 0x00 - 0xFF - - - DCU - Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression. - 0 - 7 - read-only - - - - - JCDTCM - JPEG Code Data Count Middle Register - 0x00C - 8 - read-only - 0x00 - 0xFF - - - DCM - Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression. - 0 - 7 - read-only - - - - - JCDTCD - JPEG Code Data Count Lower Register - 0x00D - 8 - read-only - 0x00 - 0xFF - - - DCD - Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression. - 0 - 7 - read-only - - - - - JINTE0 - JPEG Interrupt Enable Register 0 - 0x00E - 8 - read-write - 0x00 - 0xFF - - INT7 - This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned. - 7 - 7 + HSMCF + Hs-mode Master Code Detection Flag + 5 + 5 read-write 0 - Disabled + Hs-mode Master Code does not detect. #0 1 - Enabled + Hs-mode Master Code detects. #1 - INT6 - This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + DVIDF + Device-ID Address Detection Flag 6 6 read-write 0 - Disabled + Device-ID command does not detect. #0 1 - Enabled + Device-ID command detects. +This bit set to 1 when the first frame received immediately after a START + condition is detected matches a value of (device ID (1111 100) + 0[W]). #1 - INT5 - This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. - 5 - 5 + HOAF + Host Address Detection Flag + 15 + 15 read-write 0 - Disabled + Host address does not detect. #0 1 - Enabled + Host address detects. +This bit set to 1 when the received slave address matches the host address + (0001 000). #1 - INT3 - This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. - 3 - 3 + SVAFn + Slave Address Detection Flag n (n = 0) + 16 + 16 read-write 0 - Disabled + Slave n does not detect #0 1 - Enabled + Slave n detect #1 @@ -50103,167 +63769,184 @@ FMS2,1,0: - JINTS0 - JPEG Interrupt Status Register 0 - 0x00F - 8 + 4 + 0x08 + 0-3 + DATBAS%s + Device Address Table Basic Register %s + 0x224 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - INS6 - This bit is set to 1 when this module completes compression process normally. - 6 + DVSTAD + Device Static Address + 0 6 read-write - zeroToClear - modify - - - INS5 - This bit is set to 1 when a compressed data error occurs. - 5 - 5 - read-write - zeroToClear - modify - - - INS3 - This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. - 3 - 3 - read-write - zeroToClear - modify - - - - JCDERR - JPEG Code Decode Error Register - 0x010 - 8 - read-write - 0x0A - 0xFF - - ERR - Error Code (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression. - 0 - 3 + DVIBIPL + Device IBI Payload + 12 + 12 read-write - 0000 - Normal(Decompression error codes)/Normal(Segment error codes) - #0000 - - - 0001 - SOI not detected(Decompression error codes) - #0001 - - - 0010 - SOF1 to SOFF detected(Decompression error codes) - #0010 - - - 0011 - Unprovided pixel format detected(Decompression error codes) - #0011 - - - 0100 - SOF accuracy error(Decompression error codes) - #0100 - - - 0101 - DQT accuracy error(Decompression error codes) - #0101 - - - 0110 - Component error 1(Decompression error codes) - #0110 + 0 + IBIs from this Device do not carry a Data Payload. + #0 - 0111 - Component error 2(Decompression error codes) - #0111 + 1 + IBIs from this Device do carry a Data Payload. + #1 + + + + DVSIRRJ + Device In-Band Slave Interrupt Request Reject + 13 + 13 + read-write + - 1000 - SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes) - #1000 + 0 + This Device shall ACK the SIR. + #0 - 1001 - SOS not detected(Decompression error codes) - #1001 + 1 + This Device shall NACK the SIR and send the auto-disable CCC. + #1 + + + + DVMRRJ + Device In-Band Master Request Reject + 14 + 14 + read-write + - 1010 - EOI not detected (default)(Decompression error codes) - #1010 + 0 + This Device shall ACK Master Requests. + #0 - 1011 - Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes) - #1011 + 1 + This Device shall NACK Master Requests and send the auto-disable + command. + #1 - - 1100 - Image size error detected(Decompression error codes)/Image size error(Segment error codes) - #1100 + + + + DVIBITS + Device IBI Time-stamp + 15 + 15 + read-write + + + 0 + The Master shall not time-stamp IBIs from this Device with Master + Time-stamps. + #0 - 1101 - Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes) - #1101 + 1 + The Master shall time-stamp IBIs for this Device with Master + Time-stamps. + #1 + + + + DVDYAD + Device I3C Dynamic Address + 16 + 23 + read-write + + + DVNACK + Device NACK Retry Count + 29 + 30 + read-write + + + DVTYP + Device Type + 31 + 31 + read-write + - 1110 - Block data number error detected(Decompression error codes)/Block data number error(Segment error codes) - #1110 + 0 + I3C Device + #0 - others - Setting prohibited - true + 1 + I2C Device + #1 - JCRST - JPEG Code Reset Register - 0x011 - 8 - read-only - 0x00 - 0xFF + EXDATBAS + Extended Device Address Table Basic + Register + 0x2A0 + 32 + read-write + 0x00000000 + 0xffffffff - RST - Operating State + EDSTAD + Extended Device Static Address 0 - 0 - read-only + 6 + read-write + + + EDDYAD + Extended Device I3C Dynamic Address + 16 + 23 + read-write + + + EDNACK + Extended Device NACK Retry Count + 29 + 30 + read-write + + + EDTYP + Extended Device Type + 31 + 31 + read-write 0 - State other than below + I3C Device #0 1 - Suspended state caused by interrupt sources of JINTE0 + I2C Device #1 @@ -50271,900 +63954,830 @@ FMS2,1,0: - JIFECNT - JPEG Interface Compression Control Register - 0x040 + SDATBAS0 + Slave Device Address Table Basic Register 0 (n = 0) + 0x2B0 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - JOUTSWAP - Byte/Halfword/Word Swap Output coded data in compression is swapped. - 8 + SDSTAD + Slave Device Static Address + 0 + 9 + read-write + + + SDADLS + Slave Device Address Length Selection + 10 10 read-write - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 - - - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 - - - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 0 + Slave Device address length 7 bits selected. + #0 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 1 + Slave Device address length 10 bits selected. (I2C device only) + + #1 + + + + SDIBIPL + Slave Device IBI Payload + 12 + 12 + read-write + - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 + 0 + IBIs from this Device do not carry a Data Payload. + #0 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] - #111 + 1 + IBIs from this Device do carry a Data Payload. + #1 - DINRINI - Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. - 6 - 6 + SDDYAD + Slave Device I3C Dynamic Address + 16 + 22 + read-write + + + + + 4 + 0x04 + 0-3 + MSDCT%s + Master Device Characteristic Table Register %s + 0x2D0 + 32 + read-write + 0x00000000 + 0xffffffff + + + RBCR0 + Max Data Speed Limitation + 8 + 8 read-write 0 - The transfer address is not initialized when the input of image data lines is restarted + No Limitation #0 1 - The transfer address is initialized when the input of image data lines is restarted + Limitation #1 - DINRCMD - Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. - 5 - 5 - write-only - - - DINLC - Count Mode Setting for Stopping Input Image Data Lines - 4 - 4 + RBCR1 + IBI Request Capable + 9 + 9 read-write 0 - Count mode for stopping the input of image data lines is off + Not Capable #0 1 - Count mode for stopping the input of image data lines is on + Capable #1 - DINSWAP - Byte/Halfword Swap - 0 - 2 + RBCR2 + IBI Payload + 10 + 10 read-write - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 + 0 + No data byte follows the accepted IBI. + #0 - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 + 1 + Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. + #1 + + + + RBCR3 + Offline Capable + 11 + 11 + read-write + - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 + 0 + Device will always respond to I3C bus commands. + #0 - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 + 1 + Device will not always respond to I3C bus commands. + #1 + + + + RBCR76 + Device Role + 14 + 15 + read-write + - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 00 + I3C Slave + #00 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 01 + I3C Master + #01 - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 + 10 + Reserved for future definition by MIPI Sensor WG + #10 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 + 11 + Reserved for future definition by MIPI Sensor WG + #11 - JIFESA - JPEG Interface Compression Source Address Register - 0x044 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ESA - Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 - read-write - - - - - JIFESOFST - JPEG Interface Compression Line Offset Register - 0x048 + SVDCT + Slave Device Characteristic Table + Register + 0x320 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - ESMW - Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0. + TDCR + Transfar Device Characteristic Register 0 - 14 + 7 read-write - - - - JIFEDA - JPEG Interface Compression Destination Address Register - 0x04C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - EDA - Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 + TBCR0 + Max Data Speed Limitation + 8 + 8 read-write + + + 0 + No Limitation + #0 + + + 1 + Limitation + #1 + + - - - - JIFESLC - JPEG Interface Compression Source Line Count Register - 0x050 - 32 - read-write - 0xFFF8FFF8 - 0xFFFFFFFF - - LINES - Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. - 0 - 15 + TBCR1 + IBI Request Capable + 9 + 9 read-write + + + 0 + Not Capable + #0 + + + 1 + Capable + #1 + + - - - - JIFDCNT - JPEG Interface Decompression Control Register - 0x058 - 32 - read-write - 0x01000000 - 0xFFFFFFFF - - VINTER - Vertical SubsamplingSubsamples vertical output image data. - 28 - 29 + TBCR2 + IBI Payload + 10 + 10 read-write - 00 - No subsampling - #00 + 0 + No data byte follows the accepted IBI. + #0 - 01 - Subsamples output data into 1/2. - #01 + 1 + Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. + #1 + + + + TBCR3 + Offline Capable + 11 + 11 + read-write + - 10 - Subsamples output data into 1/4. - #10 + 0 + Device will always respond to I3C bus commands. + #0 - 11 - Subsamples output data into 1/8. - #11 + 1 + Device will not always respond to I3C bus commands. + #1 - HINTER - Horizontal Subsampling Subsamples horizontal output image data. - 26 - 27 + TBCR76 + Device Role + 14 + 15 read-write 00 - No subsampling + I3C Slave #00 01 - Subsamples output data into 1/2. + I3C Master #01 10 - Subsamples output data into 1/4. + Reserved for future definition by MIPI Sensor WG #10 11 - Subsamples output data into 1/8. + Reserved for future definition by MIPI Sensor WG #11 + + + + SDCTPIDL + Slave Device Characteristic Table + Provisional ID Low Register + 0x324 + 32 + read-write + 0x00000000 + 0xffffffff + + + SDCTPIDH + Slave Device Characteristic Table + Provisional ID High Register + 0x328 + 32 + read-write + 0x00000000 + 0xffffffff + + + 1 + 0x04 + 0 + SVDVAD%s + Slave Device Address Register %s + 0x330 + 32 + read-only + 0x00000000 + 0xffffffff + - OPF - Specifies output image data pixel format. - 24 + SVAD + Slave Address + 16 25 - read-write + read-only + + + SADLG + Slave Address Length + 27 + 27 + read-only - 01 - ARGB8888 - #01 - - - 10 - RGB565 - #10 + 0 + The 7-bit address format is selected. + #0 - others - Setting prohibited - true + 1 + The 10-bit address format is selected. + #1 - JINRINI - Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. - 14 - 14 - read-write + SSTADV + Slave Static Address Valid + 30 + 30 + read-only 0 - The transfer address is not initialized when the input of coded data is restarted. + Slave address is disabled. #0 1 - The transfer address is initialized when the input of coded data is restarted. + Slave address is enabled. #1 - JINRCMD - Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. - 13 - 13 - write-only - - - JINC - Count Mode Setting for Stopping Input Coded Data - 12 - 12 - read-write + SDYADV + Slave Dynamic Address Valid + 31 + 31 + read-only 0 - Count mode for stopping the input of coded data is off. + Dynamic Address is disabled. #0 1 - Count mode for stopping the input of coded data is on + Dynamic Address is enabled. #1 + + + + CSECMD + CCC Slave Events Command + Register + 0x350 + 32 + read-write + 0x00000000 + 0xffffffff + - JINSWAP - Byte/Word/Longword Swap Input coded data in decompression is swapped. - 8 - 10 + SVIRQE + Slave Interrupt Requests Enable + 0 + 0 read-write - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 - - - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 - - - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 - - - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 - - - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] - #110 + 0 + DISABLED: Slave-initiated Interrupts is Disabled by the + Master to control. + #0 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 + 1 + ENABLED: Slave-initiated Interrupts is Enabled by the Master + to control. + #1 - DOUTRINI - Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. - 6 - 6 + MSRQE + Mastership Requests Enable + 1 + 1 read-write 0 - The transfer address is not initialized when the output of lines of image data is restarted. + DISABLED: Mastership requests from Secondary Masters is + Disabled by the Current Master to control. #0 1 - The transfer address is initialized when the output of lines of image data is restarted + ENABLED: Mastership requests from Secondary Masters is + Enabled by the Current Master to control. #1 - DOUTRCMD - Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. - 5 - 5 - write-only - - - DOUTLC - Count Mode for Stopping Output Image Data Lines - 4 - 4 + HJEVE + Hot-Join Event Enable + 3 + 3 read-write 0 - Count mode for stopping the output of image data lines is off. + DISABLED: Slave-initiated Hot-Join is Disabled by the Master + to control. #0 1 - Count mode for stopping the output of image data lines is on + ENABLED: Slave-initiated Hot-Join is Enabled by the Master + to control. #1 + + + + CEACTST + CCC Enter Activity State + Register + 0x354 + 32 + read-write + 0x00000000 + 0xffffffff + - DOUTSWAP - Byte/Word Swap Output image data in decompression is swapped. + ACTST + Activity State 0 - 2 + 3 read-write - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 - - - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 + 0x1 + ENTAS0 (1µs: Latency-free operation) + 0x1 - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 0x2 + ENTAS1 (100 µs) + 0x2 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 0x4 + ENTAS2 (2 ms) + 0x4 - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 + 0x8 + ENTAS3 (50 ms: Lowest-activity operation) + 0x8 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 + Others + Setting prohibited + true - JIFDSA - JPEG Interface Decompression Source Address Register - 0x05C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DSA - Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 - read-write - - - - - JIFDDOFST - JPEG Interface Decompression Line Offset Register - 0x060 + CMWLG + CCC Max Write Length Register + 0x358 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - DDMW - Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + MWLG + Max Write Length 0 - 14 + 15 read-write - JIFDDA - JPEG Interface Decompression Destination Address Register - 0x064 + CMRLG + CCC Max Read Length Register + 0x35C 32 read-write 0x00000000 - 0xFFFFFFFF - - - DDA - Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 - read-write - - - - - JIFDSDC - JPEG Interface Decompression Source Data Count Register - 0x068 - 32 - read-write - 0xFFF8FFF8 - 0xFFFFFFFF + 0xffffffff - JDATAS - Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. + MRLG + Max Read Length 0 15 read-write - - - - JIFDDLC - JPEG Interface Decompression Destination Line Count Register - 0x06C - 32 - read-write - 0xFFF8FFF8 - 0xFFFFFFFF - - LINES - Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units. - 0 - 15 + IBIPSZ + IBI Payload Size + 16 + 23 read-write - JIFDADT - JPEG Interface Decompression alpha Set Register - 0x070 + CETSTMD + CCC Enter Test Mode Register + 0x360 32 - read-write + read-only 0x00000000 - 0xFFFFFFFF + 0xffffffff - ALPHA - Setting of the alpha value for output in ARGB8888 format. + TSTMD + Test Mode 0 7 - read-write + read-only + + + 0x00 + Exit Test Mode +This value removes all I3C devices from Test Mode. + + 0x00 + + + 0x01 + Vendor Test Mode +This value indicates that I3C devices shall return a random 32bit value in the provisional ID + during the Dynamic Address Assignment procedure. + + 0x01 + + + Others + MIPI reserved +Reserved for future use by the MIPI Alliance + + true + + - JINTE1 - JPEG Interrupt Enable Register 1 - 0x08C + CGDVST + CCC Get Device Status Register + 0x364 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - CBTEN - Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. - 6 - 6 + PNDINT + Pending Interrupt + 0 + 3 read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - - DINLEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. + PRTE + Protocol Error 5 5 read-write 0 - Disables an interrupt request. + The Slave has not detected a protocol error since the last + Status read. #0 1 - Enables an interrupt request. + The Slave has detected a protocol error since the last + Status read. #1 - DBTEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. - 2 - 2 + ACTMD + Slave Device’s current Activity Mode + 6 + 7 read-write - 0 - Disables an interrupt request. - #0 + 00 + Activity Mode 0 + #00 - 1 - Enables an interrupt request. - #1 + 01 + Activity Mode 1 + #01 - - - - JINEN - Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. - 1 - 1 - read-write - - 0 - Disables an interrupt request. - #0 + 10 + Activity Mode 2 + #10 - 1 - Enables an interrupt request. - #1 + 11 + Activity Mode 3 + #11 - DOUTLEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1 - 0 - 0 + VDRSV + Vendor Reserved + 8 + 15 read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - - JINTS1 - JPEG Interrupt Status Register 1 - 0x090 + CMDSPW + CCC Max Data Speed W (Write) + Register + 0x368 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - CBTF - This bit is set to 1 when the last output coded data is written in compression. - 6 - 6 - read-write - modify - - - DINLF - This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. - 5 - 5 - read-write - modify - - - DBTF - This bit is set to 1 when the last output image data is written in decompression. - 2 - 2 - read-write - modify - - - JINF - This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. This bit is valid only when the JINC bit in JIFDCNT is set to 1. - 1 - 1 - read-write - modify - - - DOUTLF - In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. + MSWDR + Maximum Sustained Write Data Rate 0 - 0 + 2 read-write - modify + + + 000 + fscl Max (default value) + #000 + + + 001 + 8MHz + #001 + + + 010 + 6MHz + #010 + + + 011 + 4MHz + #011 + + + 100 + 2MHz + #100 + + + Others + Setting prohibited + true + + - 64 - 0x1 - JCQTBL0[%s] - Quantization Table 0 - 0x0100 - 8 - write-only - 0x00 - 0x00 - - - JCQTBL1[%s] - Quantization Table 1 - 0x0140 - - - JCQTBL2[%s] - Quantization Table 2 - 0x0180 - - - JCQTBL3[%s] - Quantization Table 3 - 0x01C0 - - - 28 - 0x1 - JCHTBD0[%s] - DC Huffman Table 0 - 0x0200 - 8 - read-write - 0x00 - 0x00 - - - JCHTBD1[%s] - DC Huffman Table 1 - 0x0300 - - - 178 - 0x1 - JCHTBA0[%s] - AC Huffman Table 0 - 0x0220 - 8 - read-write - 0x00 - 0x00 - - - JCHTBA1[%s] - DC Huffman Table 1 - 0x0320 - - - - - R_KINT - Key Interrupt Function - 0x40080000 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x01 - registers - - - 0x00000008 - 0x01 - registers - - - - KRCTL - KEY Return Control Register - 0x00 - 8 + CMDSPR + CCC Max Data Speed R (Read) Register + 0x36C + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - KRMD - Usage of Key Interrupt Flags(KR0 to KR7) - 7 - 7 + MSRDR + Maximum Sustained Read Data Rate + 0 + 2 read-write - 0 - Do not use key interrupt flags - #0 + 000 + fscl Max (default value) + #000 - 1 - Use key interrupt flags. - #1 + 001 + Setting prohibited + #001 + + + 010 + Setting prohibited + #010 + + + 011 + 4MHz + #011 + + + 100 + 2MHz + #100 + + + Others + Setting prohibited + true + + + + CMDSPT + CCC Max Data Speed T (Turnaround) + Register + 0x370 + 32 + read-write + 0x00000000 + 0xffffffff + - KREG - Detection Edge Selection (KRF0 to KRF7) + MRTTIM + Maximum Read Turnaround Time 0 - 0 + 23 + read-write + + + MRTE + Maximum Read Turnaround Time Enable + 31 + 31 read-write 0 - Falling edge + Disables transmission of the Maximum Read + Turnaround Time. +(GETMXDS Format 1: Without Turnaround) + #0 1 - Rising edge + Enables transmission of the Maximum Read + Turnaround Time. +(GETMXDS Format 2: With Turnaround) + #1 @@ -51172,349 +64785,478 @@ FMS2,1,0: - KRF - KEY Return Flag Register - 0x04 - 8 + CETSM + CCC Exchange Timing Support Information M + (Mode) Register + 0x374 + 32 read-write - 0x00 - 0xFF - zeroToClear - modify + 0x00000000 + 0xffffffff - KRF7 - Key interrupt flag 7 - 7 - 7 + FREQ + Frequency Byte + 8 + 15 read-write - zeroToClear - modify - 0 - No interrupt detected - #0 + 0x00 + 32.0 KHz + 0x00 + + + 0x0F + 7.5 MHz + 0x0f + + + 0x1F + 15.5 MHz + 0x1f + + + 0x2F + 23.5 MHz + 0x2f + + + 0x3F + 31.5 MHz + 0x3f + + + 0x4F + 39.5 MHz + 0x4f + + + 0x5F + 47.5 MHz + 0x5f + + + 0x6F + 55.5 MHz + 0x6f + + + 0x7F + 63.5 MHz + 0x7f + + + 0x8F + Setting prohibited + 0x8f + + + 0x9F + Setting prohibited + 0x9f + + + 0xAF + Setting prohibited + 0xaf + + + 0xBF + Setting prohibited + 0xbf + + + 0xCF + Setting prohibited + 0xcf + + + 0xDF + Setting prohibited + 0xdf + + + 0xEF + Setting prohibited + 0xef - 1 - Interrupt detected. - #1 + 0xFF + Setting prohibited + 0xff + + + Others + Setting prohibited + true - KRF6 - Key interrupt flag 6 - 6 - 6 + INAC + Inaccuracy Byte + 16 + 23 read-write - zeroToClear - modify - 0 - No interrupt detected - #0 + 0x00 + 0.0% + 0x00 - 1 - Interrupt detected. - #1 + 0x0F + 1.5% + 0x0f - - - - KRF5 - Key interrupt flag 5 - 5 - 5 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x1F + 3.1% + 0x1f - 1 - Interrupt detected. - #1 + 0x2F + 4.7% + 0x2f - - - - KRF4 - Key interrupt flag 4 - 4 - 4 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x3F + 6.3% + 0x3f - 1 - Interrupt detected. - #1 + 0x4F + 7.9% + 0x4f - - - - KRF3 - Key interrupt flag 3 - 3 - 3 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x5F + 9.5% + 0x5f - 1 - Interrupt detected. - #1 + 0x6F + 11.1% + 0x6f - - - - KRF2 - Key interrupt flag 2 - 2 - 2 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x7F + 12.7% + 0x7f - 1 - Interrupt detected. - #1 + 0x8F + 14.3% + 0x8f - - - - KRF1 - Key interrupt flag 1 - 1 - 1 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x9F + 15.9% + 0x9f - 1 - Interrupt detected. - #1 + 0xAF + 17.5% + 0xaf - - - - KRF0 - Key interrupt flag 0 - 0 - 0 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0xBF + 19.1% + 0xbf - 1 - Interrupt detected. - #1 + 0xCF + 20.7% + 0xcf + + + 0xDF + 22.3% + 0xdf + + + 0xEF + 23.9% + 0xef + + + 0xFF + 25.5% + 0xff - KRM - KEY Return Mode Register - 0x08 - 8 + BITCNT + Bit Count Register + 0x380 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - KRM7 - Key interrupt mode control 7 - 7 - 7 + BCNT + Bit Counter + 0 + 4 read-write - 0 - Does not detect key interrupt signal - #0 + 0x00 + 9 bits (SDR/Legacy I2C Message) + + 0x00 - 1 - Detect key interrupt signal. - #1 + 0x01 + 1 bit (SDR/Legacy I2C Message) + + 0x01 - - - - KRM6 - Key interrupt mode control 6 - 6 - 6 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x02 + 2 bits (SDR/Legacy I2C Message) + + 0x02 - 1 - Detect key interrupt signal. - #1 + 0x03 + 3 bits (SDR/Legacy I2C Message) + + 0x03 - - - - KRM5 - Key interrupt mode control 5 - 5 - 5 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x04 + 4 bits (SDR/Legacy I2C Message) + + 0x04 - 1 - Detect key interrupt signal. - #1 + 0x05 + 5 bits (SDR/Legacy I2C Message) + + 0x05 - - - - KRM4 - Key interrupt mode control 4 - 4 - 4 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x06 + 6 bits (SDR/Legacy I2C Message) + + 0x06 - 1 - Detect key interrupt signal. - #1 + 0x07 + 7 bits (SDR/Legacy I2C Message) + + 0x07 - - - - KRM3 - Key interrupt mode control 3 - 3 - 3 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x08 + 8 bits (SDR/Legacy I2C Message) + + 0x08 - 1 - Detect key interrupt signal. - #1 + Others + setting prohibited + true - KRM2 - Key interrupt mode control 2 - 2 - 2 - read-write + BCNTWP + BCNT Write Protect + 7 + 7 + write-only 0 - Does not detect key interrupt signal + The BCNT[4:0] bits are protected. #0 1 - Detect key interrupt signal. + The BCNT[4:0] bits can be written (when writing simultaneously with the value of + the target bit). +This bit is read as 0. + #1 + + + + NQSTLV + Normal Queue Status Level + Register + 0x394 + 32 + read-only + 0x00000002 + 0xffffffff + + + CMDQFLV + Normal Command Queue Free Level + 0 + 7 + read-only + - KRM1 - Key interrupt mode control 1 + RSPQLV + Normal Response Queue Level + 8 + 15 + read-only + + + IBIQLV + Normal IBI Queue Level + 16 + 23 + read-only + + + IBISCNT + Normal IBI Status Count + 24 + 28 + read-only + + + + + NDBSTLV0 + Normal Data Buffer Status Level + Register + 0x398 + 32 + read-only + 0x00000001 + 0xffffffff + + + TDBFLV + Normal Transmit Data Buffer Free Level + 0 + 7 + read-only + + + RDBLV + Normal Receive Data Buffer Level + 8 + 15 + read-only + + + + + NRSQSTLV + Normal Receive Status Queue Status Level + Register + 0x3C0 + 32 + read-only + 0x00000000 + 0xffffffff + + + RSQLV + Normal Receive Status Queue Level + 0 + 7 + read-only + + + + + PRSTDBG + Present State Debug Register + 0x3CC + 32 + read-only + 0x00000000 + 0xffffffff + + + SCILV + SCL Line Signal Level + 0 + 0 + read-only + + + SDILV + SDA Line Signal Level 1 1 - read-write + read-only + + + SCOLV + SCL Output Level + 2 + 2 + read-only 0 - Does not detect key interrupt signal + I3C has driven the SCL pin low. #0 1 - Detect key interrupt signal. + I3C has released the SCL pin. #1 - KRM0 - Key interrupt mode control 0 - 0 - 0 - read-write + SDOLV + SDA Output Level + 3 + 3 + read-only 0 - Does not detect key interrupt signal + I3C has driven the SDA pin low. #0 1 - Detect key interrupt signal. + I3C has released the SDA pin. #1 + + MSERRCNT + Master Error Counters + Register + 0x3D0 + 32 + read-only + 0x00000000 + 0xffffffff + + + M2ECNT + M2 Error Counter + 0 + 7 + read-only + + + @@ -53855,7 +67597,7 @@ FMS2,1,0: MSTPB9 - I2C Bus Interface 0 Module Stop + IIC/I3C Bus Interface 0 Module Stop 9 9 read-write @@ -54049,6 +67791,25 @@ FMS2,1,0: + + MSTPC27 + CANFD Module Stop + 27 + 27 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state. + #1 + + + MSTPC14 Event Link Controller Module Stop @@ -56982,7 +70743,7 @@ FMS2,1,0: - 9 + 12 0x2 PMSAR[%s] Port Security Attribution Register @@ -71825,6 +85586,16 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang 0x002 registers + + 0x0000006C + 0x005 + registers + + + 0x00000074 + 0x005 + registers + 0x00000092 0x01 @@ -77728,6 +91499,51 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang + + CANFDCKDIVCR + CANFD Clock Division Control Register + 0x06E + 8 + read-write + 0x00 + 0xff + + + CANFDCKDIV + CANFD Clock (CANFDCLK) Division Select + 0 + 2 + read-write + + + 000 + ∕ 1 (value after reset) + #000 + + + 001 + ∕ 2 + #001 + + + 010 + ∕ 4 + #010 + + + 011 + ∕ 6 + #011 + + + Others + Setting prohibited. + true + + + + + USBCKCR USB Clock Control Register @@ -77899,6 +91715,79 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang + + CANFDCKCR + CANFD Clock Control Register + 0x076 + 8 + read-write + 0x01 + 0xff + + + CANFDCKSEL + CANFD Clock (CANFDCLK) Source Select + 0 + 2 + read-write + + + 101 + PLL + #101 + + + 110 + PLL2 + #110 + + + Others + Setting prohibited. + true + + + + + CANFDCKSREQ + CANFD Clock (CANFDCLK) Switching Request + 6 + 6 + read-write + + + 0 + No request + #0 + + + 1 + Request switching. + #1 + + + + + CANFDCKSRDY + CANFD Clock (CANFDCLK) Switching Ready state flag + 7 + 7 + read-only + + + 0 + Switching not possible + #0 + + + 1 + Switching possible. + #1 + + + + + SNZREQCR1 Snooze Request Control Register 1 diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index 1ee1604e8..76963ef5d 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -154,8 +154,8 @@ void SystemInit (void) /* Seal the main stack for secure projects. Reference: * https://developer.arm.com/documentation/100720/0300 * https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */ - uint32_t * p_main_stack = (uint32_t *) __Vectors[0]; - p_main_stack[BSP_CFG_STACK_MAIN_BYTES / sizeof(uint32_t)] = BSP_TZ_STACK_SEAL_VALUE; + uint32_t * p_main_stack_top = (uint32_t *) __Vectors[0]; + *p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE; #endif #if !BSP_TZ_NONSECURE_BUILD diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index fbf5e9235..6c3907233 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -1109,6 +1109,28 @@ void bsp_clock_init (void) R_BSP_OctaclkUpdate(&octaclk_settings); #endif /* BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTASPI_CLOCK_ENABLE */ + /* Set the CANFD clock if it exists on the MCU */ +#if BSP_FEATURE_BSP_HAS_CANFD_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + + /* Request to stop the CANFD clock. */ + R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 1; + + /* Wait for the CANFD clock to stop. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 1U); + + /* Select the CANFD clock divisor and source. */ + R_SYSTEM->CANFDCKDIVCR = BSP_CFG_CANFDCLK_DIV; + R_SYSTEM->CANFDCKCR = BSP_CFG_CANFDCLK_SOURCE | R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk | + R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk; + + /* Request to start the CANFD clock. */ + R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 0; + + /* Wait for the CANFD clock to start. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 0U); +#endif + /* Lock CGC and LPM protection registers. */ R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; @@ -1302,8 +1324,8 @@ void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting) R_SYSTEM->OCTACKDIVCR = (uint8_t) p_octaclk_setting->divider; R_SYSTEM->OCTACKCR = (uint8_t) (p_octaclk_setting->source_clock | R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk); - /* Start the OCTASPI Clock. */ - R_SYSTEM->OCTACKCR = BSP_CLOCKS_SOURCE_CLOCK_PLL2; + /* Start the OCTASPI Clock by setting OCTACKSREQ to zero. */ + R_SYSTEM->OCTACKCR = (uint8_t) p_octaclk_setting->source_clock; /* Wait for the OCTASPI Clock to be started. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index dabda61ce..489a57962 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -142,6 +142,12 @@ FSP_HEADER #define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 #define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 +/* CANFD clock divider options. */ +#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 + /* PLL divider options. */ #define BSP_CLOCKS_PLL_DIV_1 (0) #define BSP_CLOCKS_PLL_DIV_2 (1) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index 668d099b6..9ed33f1e8 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -125,6 +125,8 @@ FSP_HEADER #define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); #define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U)); #define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); #define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index fc6dff4b3..6fe75ae8d 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0xFF01FF) // 0 to 8, 16 to 23 in unit 0 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -84,6 +85,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -118,6 +120,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (1U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -174,7 +178,8 @@ #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) -#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (0U) @@ -256,6 +261,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x203U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) @@ -275,7 +282,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -287,4 +293,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index 6265c4c71..bddd2a976 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -57,6 +57,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x7E07FF) // 0 to 10, 17 to 22 in unit 0 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -66,6 +67,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -99,6 +101,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) // Feature not available on this MCU #define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) @@ -145,17 +149,18 @@ #define BSP_FEATURE_CTSU_HAS_TXVSEL (1) #define BSP_FEATURE_CTSU_VERSION (2) -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) // Feature not available on this MCU -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) // Feature not available on this MCU -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) // Feature not available on this MCU -#define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (0U) @@ -237,6 +242,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) // Feature not available on this MCU #define BSP_FEATURE_SCI_CHANNELS (0x207U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) @@ -256,7 +263,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) @@ -268,4 +274,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index 17b066ec4..1d364344c 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F7FFF) // 0 to 14, 16 (ADCTDR) 17 to 20 in unit 0 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -84,6 +85,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -117,6 +119,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (1U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) @@ -173,7 +177,8 @@ #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) -#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (0U) @@ -255,6 +260,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x20FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) @@ -274,7 +281,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -286,4 +292,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index 135fac9d8..2c5689c04 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x3FF7FFF) // 0 to 14, 16 to 25 in unit 0 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -84,6 +85,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (1) #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -118,6 +120,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -175,6 +179,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register @@ -256,6 +261,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x207U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -275,7 +282,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -287,4 +293,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index 29687d010..fda0c5dbd 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x139FF) // 0 to 8, 11 to 13, 16 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) @@ -87,6 +88,7 @@ #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU @@ -120,6 +122,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -178,6 +182,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M2 has Data Watchpoint Cycle Count Register @@ -259,6 +264,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -278,7 +285,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) @@ -290,4 +296,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_BSP_NUM_PMSAR (8U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index 98f43fc36..c73b32bab 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) @@ -88,6 +89,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) @@ -120,6 +122,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -179,6 +183,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M3 has Data Watchpoint Cycle Count Register @@ -260,6 +265,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -279,7 +286,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) @@ -291,4 +297,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_BSP_NUM_PMSAR (9U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index ece243e23..a9651ac74 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1A0670) // 4 to 6, 9, 10, 17, 19, 20 in unit 0 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -84,6 +85,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (1) #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -118,6 +120,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -175,6 +179,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register @@ -256,6 +261,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x213U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -275,7 +282,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -287,4 +293,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index b06f5d329..f9a4f1790 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -73,12 +73,13 @@ #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_SLOPE (4000) #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1700EF) // 0 to 3, 5 to 7, 16 to 18, and 20 in unit 0 and 0 to 2, 5 to 7, 16 to 17 in unit 1 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x300E7) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -88,6 +89,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -122,6 +124,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -179,6 +183,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register @@ -260,6 +265,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -279,7 +286,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -291,4 +297,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index 475094a94..0130d9101 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -73,12 +73,13 @@ #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_SLOPE (4000) #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 2, 5 to 7, 16 to 18 in unit 1 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x700E7) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -88,6 +89,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -122,6 +124,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -179,6 +183,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register @@ -260,6 +265,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -279,7 +286,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -291,4 +297,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index 56579f9e8..e8bc0da02 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -73,12 +73,13 @@ #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) #define BSP_FEATURE_ADC_TSN_SLOPE (4000) #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 3, 5 to 7, 16 to 19 in unit 1 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0xF00EF) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -88,6 +89,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) @@ -122,6 +124,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -179,6 +183,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register @@ -260,6 +265,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -279,7 +286,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -291,4 +297,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index dce2f7807..172e54a4f 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -61,6 +61,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) @@ -69,6 +70,7 @@ #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU @@ -102,6 +104,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -161,6 +165,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register @@ -242,6 +247,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -261,7 +268,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -273,4 +279,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_BSP_NUM_PMSAR (9U) + #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h new file mode 100644 index 000000000..79c55969d --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h @@ -0,0 +1,329 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/******************************************************************************************************************* + * @addtogroup BSP_MCU_RA6M5 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra6m5 +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC transfer end 0 + ELC_EVENT_DMAC1_INT = (0x021), // DMAC transfer end 1 + ELC_EVENT_DMAC2_INT = (0x022), // DMAC transfer end 2 + ELC_EVENT_DMAC3_INT = (0x023), // DMAC transfer end 3 + ELC_EVENT_DMAC4_INT = (0x024), // DMAC transfer end 4 + ELC_EVENT_DMAC5_INT = (0x025), // DMAC transfer end 5 + ELC_EVENT_DMAC6_INT = (0x026), // DMAC transfer end 6 + ELC_EVENT_DMAC7_INT = (0x027), // DMAC transfer end 7 + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x02B), // DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // DMA 0 request + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // DMA 1 request + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // DMA 2 request + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // DMA 3 request + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // DMA 4 request + ELC_EVENT_CAN_DMAREQ5 = (0x060), // DMA 5 request + ELC_EVENT_CAN_DMAREQ6 = (0x061), // DMA 6 request + ELC_EVENT_CAN_DMAREQ7 = (0x062), // DMA 7 request + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO recieve interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO recieve + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Slave address match + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable interrupt B + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable interrupt C + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable interrupt D + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // A/D scan end interrupt + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x186), // Received data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Received data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Received data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Received data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Received data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Received data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Received data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Received data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Received data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_CAN_MRAM_ERI = (0x1D0), // ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA6M5) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h new file mode 100644 index 000000000..25708fc4b --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -0,0 +1,284 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (19999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x01U) +#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x02U) +#else + #define CGC_MAINCLOCK_DRIVE (0x03U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) +#define BSP_FEATURE_BSP_HAS_SP_MON (0U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD + +#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_SPCR3 (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + +#define BSP_FEATURE_BSP_NUM_PMSAR (12U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h new file mode 100644 index 000000000..26a8a93bb --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h @@ -0,0 +1,40 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA6M5 RA6M5 + * @includedoc config_bsp_ra6m5_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA6M5) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index 6033cf64b..f6e38c363 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1700EF) // 0 to 3, 5 to 7, 16 to 18, and 20 in unit 0 and 0 to 2, 5 to 7, 16 to 17 in unit 1 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x300E7) #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) @@ -88,6 +89,7 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) @@ -121,6 +123,8 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU + #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) @@ -178,6 +182,7 @@ #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register @@ -259,6 +264,8 @@ #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -278,7 +285,6 @@ #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) @@ -290,4 +296,6 @@ #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) + #endif diff --git a/ra/fsp/src/r_adc/r_adc.c b/ra/fsp/src/r_adc/r_adc.c index ebf5c719b..3ea254b71 100644 --- a/ra/fsp/src/r_adc/r_adc.c +++ b/ra/fsp/src/r_adc/r_adc.c @@ -78,6 +78,8 @@ #define ADC_PRV_TSCR_TSN_ENABLE (R_TSN_CTRL_TSCR_TSEN_Msk | R_TSN_CTRL_TSCR_TSOE_Msk) +#define ADC_PRV_ADBUF_ENABLED (1U) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -479,6 +481,10 @@ fsp_err_t R_ADC_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t (reg_id == ADC_CHANNEL_DUPLEX) || (reg_id == ADC_CHANNEL_DUPLEX_A) || (reg_id == ADC_CHANNEL_DUPLEX_B)); } + + /* Data is not available to be read from ADDRn registers when ADBUF is enabled. Read API cannot be used with ADBUF enabled. */ + adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + FSP_ASSERT(1U != p_extend->enable_adbuf); #endif /* Read the data from the requested ADC conversion register and return it */ @@ -1181,6 +1187,15 @@ static void r_adc_open_sub (adc_instance_ctrl_t * const p_instance_ctrl, adc_cfg p_instance_ctrl->p_reg->VREFAMPCNT = (uint8_t) (p_cfg_extend->adc_vref_control); } #endif + +#if BSP_FEATURE_ADC_HAS_ADBUF + uint8_t adbuf = 0; + if (1U == p_cfg_extend->enable_adbuf) + { + adbuf = R_ADC0_ADBUFEN_BUFEN_Msk; + } + p_instance_ctrl->p_reg->ADBUFEN = adbuf; +#endif } /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c index 72c6d6813..b9f4e3f60 100644 --- a/ra/fsp/src/r_agt/r_agt.c +++ b/ra/fsp/src/r_agt/r_agt.c @@ -923,6 +923,7 @@ void agt_int_isr (void) /* Stop timer */ p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP; agtcr &= AGT_PRV_AGTCR_STATUS_FLAGS; + p_instance_ctrl->p_reg->AGTCR = (uint8_t) agtcr; /* Set counter to period minus one. */ r_agt_period_register_set(p_instance_ctrl, p_instance_ctrl->period); @@ -1010,6 +1011,9 @@ void agt_int_isr (void) /* Restore callback memory in case this is a nested interrupt. */ *p_instance_ctrl->p_callback_memory = callback_args; } + + /* Retreive AGTCR in case it was modified in the callback. */ + agtcr = p_instance_ctrl->p_reg->AGTCR; } /* Clear flags in AGTCR. */ diff --git a/ra/fsp/src/r_can/r_can.c b/ra/fsp/src/r_can/r_can.c index 6296466c6..edf4df897 100644 --- a/ra/fsp/src/r_can/r_can.c +++ b/ra/fsp/src/r_can/r_can.c @@ -33,7 +33,7 @@ #define CAN_TEST_LISTEN_ONLY (3U) #define CAN_TEST_LOOPBACK_EXTERNAL (5U) #define CAN_TEST_LOOPBACK_INTERNAL (7U) -#define CAN_MAX_DATA_LENGTH (8U) +#define CAN_MAX_DATA_LENGTH (8) #define CAN_MAX_NO_MAILBOXES (32U) #define CAN_BAUD_RATE_PRESCALER_MIN (1U) @@ -68,7 +68,7 @@ #define CAN_TX_RX_INTERRUPTS_ENABLE (0xFFFFFFFFU) #define CAN_TX_RX_INTERRUPTS_DISABLE (0x00000000U) -#define CAN_BAUD_RATE_PRESCALER_MASK (0x3FU) +#define CAN_BAUD_RATE_PRESCALER_MASK (0x3FFU) #define CAN_TIMESTAMP_PRESCALER_8BITTIME (0x3U) @@ -148,6 +148,7 @@ const can_api_t g_can_on_can = .open = R_CAN_Open, .close = R_CAN_Close, .write = R_CAN_Write, + .read = R_CAN_Read, .modeTransition = R_CAN_ModeTransition, .infoGet = R_CAN_InfoGet, .callbackSet = R_CAN_CallbackSet, @@ -317,8 +318,8 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c p_ctrl->p_reg->BCR = (uint32_t) (((p_cfg->p_bit_timing->baud_rate_prescaler - 1) & CAN_BAUD_RATE_PRESCALER_MASK) << R_CAN0_BCR_BRP_Pos) | - (uint32_t) (p_cfg->p_bit_timing->time_segment_1 << R_CAN0_BCR_TSEG1_Pos) | - (uint32_t) (p_cfg->p_bit_timing->time_segment_2 << R_CAN0_BCR_TSEG2_Pos) | + ((p_cfg->p_bit_timing->time_segment_1 - 1U) << R_CAN0_BCR_TSEG1_Pos) | + ((p_cfg->p_bit_timing->time_segment_2 - 1U) << R_CAN0_BCR_TSEG2_Pos) | (uint32_t) ((p_cfg->p_bit_timing->synchronization_jump_width - 1U) << R_CAN0_BCR_SJW_Pos) | (uint32_t) (p_ctrl->clock_source << R_CAN0_BCR_CCLKS_Pos); @@ -346,10 +347,11 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c if (CAN_MAILBOX_RECEIVE == (p_cfg->p_mailbox[i].mailbox_type)) { /* The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). - * Mixed ID mode is currently unsupported by this driver. * When the IDFM[1:0] bits are not 10b, only write 0 to IDE. It reads as 0. */ - if (CAN_ID_MODE_STANDARD == p_cfg->id_mode) + if ((CAN_GLOBAL_ID_MODE_STANDARD == p_cfg->id_mode) || + ((p_cfg->id_mode == CAN_GLOBAL_ID_MODE_MIXED) && + (p_cfg->p_mailbox[i].id_mode == CAN_ID_MODE_STANDARD))) { p_ctrl->p_reg->MB[i].ID = ((uint32_t) (0U << R_CAN0_MB_ID_IDE_Pos) | (uint32_t) (p_cfg->p_mailbox[i].frame_type << R_CAN0_MB_ID_RTR_Pos) | @@ -358,7 +360,9 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c } else { - p_ctrl->p_reg->MB[i].ID = ((uint32_t) (0U << R_CAN0_MB_ID_IDE_Pos) | + uint32_t ide = ((p_cfg->id_mode == CAN_GLOBAL_ID_MODE_MIXED) && + p_cfg->p_mailbox[i].id_mode) ? 1U : 0U; + p_ctrl->p_reg->MB[i].ID = ((ide << R_CAN0_MB_ID_IDE_Pos) | (uint32_t) (p_cfg->p_mailbox[i].frame_type << R_CAN0_MB_ID_RTR_Pos) | (uint32_t) ((p_cfg->p_mailbox[i].mailbox_id & CAN_XID_MASK) << R_CAN0_MB_ID_EID_Pos)); @@ -382,7 +386,8 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c /* If the user has defined a mask */ if (extended_cfg->p_mailbox_mask[i] < CAN_DEFAULT_MASK) { - if (CAN_ID_MODE_STANDARD == p_cfg->id_mode) + /* In Mixed ID mode the Standard ID mask (SID) is the upper 11 bits of the full Extended ID (SID+XID) */ + if (CAN_GLOBAL_ID_MODE_STANDARD == p_cfg->id_mode) { /* Set standard ID mask. Set unused bits high */ p_ctrl->p_reg->MKR[i] = CAN_DEFAULT_MASK & @@ -406,9 +411,6 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c /* Set the Mask as invalid for mailboxes that do not use the mask. */ p_ctrl->p_reg->MKIVLR = ~(mask_enabled); - /* Transition to requested test mode */ - p_ctrl->p_reg->TCR = (uint8_t) p_cfg->test_mode; - /* Go to normal operation. */ r_can_mode_transition(p_ctrl, CAN_OPERATION_MODE_NORMAL, CAN_TEST_MODE_DISABLED); @@ -419,13 +421,6 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c p_ctrl->p_reg->CTLR_b.TSRC = CAN_TIMESTAMP_RESET; /* Set Timestamp counter reset command */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CTLR_b.TSRC, !CAN_TIMESTAMP_RESET); - /* Transition to user defined mode - * Since the driver is already in the requested test mode this helper function - * will not go through halt mode again. - * Test mode transition will be ignored. - */ - r_can_mode_transition(p_ctrl, p_cfg->operation_mode, p_cfg->test_mode); - /* If successful, Lookup and store IRQ numbers. Enable interrupts. */ r_can_bsp_irq_cfg_enable(p_ctrl, p_cfg->error_irq); r_can_bsp_irq_cfg_enable(p_ctrl, p_cfg->mailbox_rx_irq); @@ -491,19 +486,23 @@ fsp_err_t R_CAN_Write (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_fram FSP_ASSERT(NULL != p_ctrl); FSP_ASSERT(NULL != p_frame); FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mailbox < p_ctrl->p_cfg->mailbox_count, FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(1U != p_ctrl->p_reg->MCTL_TX_b[mailbox].RECREQ, FSP_ERR_CAN_RECEIVE_MAILBOX); FSP_ERROR_RETURN((p_frame->data_length_code <= CAN_MAX_DATA_LENGTH), FSP_ERR_INVALID_ARGUMENT); #endif + uint32_t i; FSP_ERROR_RETURN(0U == p_ctrl->p_reg->MCTL_TX_b[mailbox].TRMREQ, FSP_ERR_CAN_TRANSMIT_NOT_READY); /* Setup the frame to be transmitted. */ /* Set the ID based on the ID mode */ - if (CAN_ID_MODE_STANDARD == p_ctrl->p_cfg->id_mode) + if ((CAN_GLOBAL_ID_MODE_STANDARD == p_ctrl->p_cfg->id_mode) || + ((p_ctrl->p_cfg->id_mode == CAN_GLOBAL_ID_MODE_MIXED) && + (p_frame->id_mode == CAN_ID_MODE_STANDARD))) { p_ctrl->p_reg->MB[mailbox].ID = ((uint32_t) (0U << R_CAN0_MB_ID_IDE_Pos) | (uint32_t) (p_frame->type << R_CAN0_MB_ID_RTR_Pos) | @@ -511,7 +510,8 @@ fsp_err_t R_CAN_Write (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_fram } else { - p_ctrl->p_reg->MB[mailbox].ID = ((uint32_t) (0U << R_CAN0_MB_ID_IDE_Pos) | + uint32_t ide = ((p_ctrl->p_cfg->id_mode == CAN_GLOBAL_ID_MODE_MIXED) && p_frame->id_mode) ? 1U : 0U; + p_ctrl->p_reg->MB[mailbox].ID = ((ide << R_CAN0_MB_ID_IDE_Pos) | (uint32_t) (p_frame->type << R_CAN0_MB_ID_RTR_Pos) | (uint32_t) ((p_frame->id & CAN_XID_MASK) << R_CAN0_MB_ID_EID_Pos)); } @@ -531,6 +531,20 @@ fsp_err_t R_CAN_Write (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_fram return FSP_SUCCESS; } +/***************************************************************************************************************//** + * @ref can_api_t::read is not supported on CAN. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + *****************************************************************************************************************/ +fsp_err_t R_CAN_Read (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_frame_t * const p_frame) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(mailbox); + FSP_PARAMETER_NOT_USED(p_frame); + + return FSP_ERR_UNSUPPORTED; +} + /***************************************************************************************************************//** * CAN Mode Transition is used to change CAN driver state. * @@ -577,10 +591,10 @@ fsp_err_t R_CAN_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_inf FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); #endif - p_info->status = (can_status_t) p_ctrl->p_reg->STR; // Status register value - p_info->error_count_receive = p_ctrl->p_reg->RECR; // Report receive error count - p_info->error_count_transmit = p_ctrl->p_reg->TECR; // Report transmit error count - p_info->error_code = (can_error_t) p_ctrl->p_reg->ECSR; // Report error code + p_info->status = (can_status_t) p_ctrl->p_reg->STR; // Status register value + p_info->error_count_receive = p_ctrl->p_reg->RECR; // Report receive error count + p_info->error_count_transmit = p_ctrl->p_reg->TECR; // Report transmit error count + p_info->error_code = (can_error_t) p_ctrl->p_reg->ECSR & CAN_ERROR_MASK; // Report error code /* Since the error flags were read, we clear them to ensure that we won't read them again * Because register is volatile, we clear only the flags that we already read. Preserve the value @@ -803,41 +817,43 @@ void can_mailbox_rx_isr (void) p_ctrl->p_reg->MSMR = CAN_RECEIVE_SEARCH; // search for lowest numbered &mailbox with message received mailbox = p_ctrl->p_reg->MSSR_b.MBNST; // get mailbox number p_ctrl->p_reg->MSMR = saved_msmr; // Restore the previous MSMR value - can_frame_t frame; /* Get frame data. */ uint32_t i; uint32_t mbox_id = p_ctrl->p_reg->MB[mailbox].ID; /* Get the frame type */ - frame.type = (can_frame_type_t) ((mbox_id & R_CAN0_MB_ID_RTR_Msk) >> R_CAN0_MB_ID_RTR_Pos); + args.frame.type = (can_frame_type_t) ((mbox_id & R_CAN0_MB_ID_RTR_Msk) >> R_CAN0_MB_ID_RTR_Pos); + + /* Get the ID mode */ + args.frame.id_mode = (can_id_mode_t) ((p_ctrl->p_cfg->id_mode | p_ctrl->p_reg->MB[mailbox].ID_b.IDE) & 1); - /* Get the frame id */ - if (CAN_ID_MODE_STANDARD == p_ctrl->p_cfg->id_mode) + /* Get the ID based on the mode */ + if (CAN_ID_MODE_STANDARD == args.frame.id_mode) { - frame.id = (mbox_id & R_CAN0_MB_ID_SID_Msk) >> R_CAN0_MB_ID_SID_Pos; + args.frame.id = (mbox_id & R_CAN0_MB_ID_SID_Msk) >> R_CAN0_MB_ID_SID_Pos; } else { - frame.id = mbox_id; + args.frame.id = mbox_id & (R_CAN0_MB_ID_SID_Msk | R_CAN0_MB_ID_EID_Msk); } /* Get the frame data length code */ - frame.data_length_code = p_ctrl->p_reg->MB[mailbox].DL_b.DLC; + args.frame.data_length_code = p_ctrl->p_reg->MB[mailbox].DL_b.DLC; /* Refer Note 1 about DLC[3:0] under Section 37.2.6 * 'Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31; m = 0 to 7)' * of RA6M3 manual R01UH0886EJ010. */ - if (frame.data_length_code > CAN_MAX_DATA_LENGTH) + if (args.frame.data_length_code > CAN_MAX_DATA_LENGTH) { - frame.data_length_code = CAN_MAX_DATA_LENGTH; + args.frame.data_length_code = CAN_MAX_DATA_LENGTH; } /* Be sure to check data_length_code in calling function */ - for (i = 0U; i < frame.data_length_code; i++) + for (i = 0U; i < args.frame.data_length_code; i++) { - frame.data[i] = p_ctrl->p_reg->MB[mailbox].D[i]; // Copy receive data to buffer + args.frame.data[i] = p_ctrl->p_reg->MB[mailbox].D[i]; // Copy receive data to buffer } /* Clear rx data flag. Do not modify message-lost flag as this keeps track of @@ -850,7 +866,7 @@ void can_mailbox_rx_isr (void) */ p_ctrl->p_reg->MCTL_RX[mailbox] = CAN_MAILBOX_RX_MASK_MSGLOST; - args.p_frame = &frame; + args.p_frame = &args.frame; args.event = CAN_EVENT_RX_COMPLETE; /* Save the receive mailbox number. */ diff --git a/ra/fsp/src/r_canfd/r_canfd.c b/ra/fsp/src/r_canfd/r_canfd.c new file mode 100644 index 000000000..d4db8da4d --- /dev/null +++ b/ra/fsp/src/r_canfd/r_canfd.c @@ -0,0 +1,1140 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_canfd.h" +#include "r_canfd_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define CANFD_OPEN (0x52434644U) // "RCFD" in ASCII + +#define CANFD_BAUD_RATE_PRESCALER_MIN (1U) +#define CANFD_BAUD_RATE_PRESCALER_MAX (1024U) + +#define CANFD_PRV_CTR_MODE_MASK (R_CANFD_CFDGCTR_GSLPR_Msk + R_CANFD_CFDGCTR_GMDC_Msk) +#define CANFD_PRV_CTR_RESET_BIT (1U) +#define CANFD_PRV_RX_FIFO_MAX (8U) +#define CANFD_PRV_RX_BUFFER_RAM_LIMIT_BYTES (4864U) +#define CANFD_PRV_RXMB_MAX (32U) +#define CANFD_PRV_TXMB_OFFSET (32U) +#define CANFD_PRV_TXMB_CHANNEL_OFFSET (64U) +#define CANFD_PRV_STANDARD_ID_MAX (0x7FFU) + +/*********************************************************************************************************************** + * Const data + **********************************************************************************************************************/ + +/* LUT to convert DLC values to payload size in bytes */ +static const uint8_t dlc_to_bytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + +/* LUT to determine the hierarchy of can_operation_mode_t modes. */ +static const uint8_t g_mode_order[] = {0, 2, 1, 0, 0, 3}; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * canfd_prv_ns_callback)(can_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile canfd_prv_ns_callback)(can_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if CANFD_CFG_PARAM_CHECKING_ENABLE +static bool r_canfd_bit_timing_parameter_check(can_bit_timing_cfg_t * p_bit_timing); + +#endif + +static void r_canfd_mb_read(uint32_t buffer, can_frame_t * const frame); +static void r_canfd_call_callback(canfd_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args); +static void r_canfd_mode_transition(canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode); +static void r_canfd_mode_ctr_set(volatile uint32_t * p_ctr_reg, can_operation_mode_t operation_mode); +static uint8_t r_canfd_bytes_to_dlc(uint8_t bytes); +void canfd_error_isr(void); +void canfd_rx_fifo_isr(void); +void canfd_channel_tx_isr(void); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Version data structure used by error logger macro. */ +static const fsp_version_t g_canfd_version = +{ + .api_version_minor = CAN_API_VERSION_MINOR, + .api_version_major = CAN_API_VERSION_MAJOR, + .code_version_major = CANFD_CODE_VERSION_MAJOR, + .code_version_minor = CANFD_CODE_VERSION_MINOR +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Channel control struct array */ +static canfd_instance_ctrl_t * gp_ctrl[BSP_FEATURE_CANFD_NUM_CHANNELS] = {NULL}; + +/* CAN function pointers */ +const can_api_t g_canfd_on_canfd = +{ + .open = R_CANFD_Open, + .close = R_CANFD_Close, + .write = R_CANFD_Write, + .read = R_CANFD_Read, + .modeTransition = R_CANFD_ModeTransition, + .infoGet = R_CANFD_InfoGet, + .callbackSet = R_CANFD_CallbackSet, + .versionGet = R_CANFD_VersionGet +}; + +/*******************************************************************************************************************//** + * @addtogroup CANFD + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/***************************************************************************************************************//** + * Open and configure the CANFD channel for operation. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_Open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Driver already open. + * @retval FSP_ERR_IN_USE Channel is already in use. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel does not exist on this MCU. + * @retval FSP_ERR_ASSERTION A required pointer was NULL. + * @retval FSP_ERR_CAN_INIT_FAILED The provided nominal or data bitrate is invalid. + * @retval FSP_ERR_CLOCK_INACTIVE CANFD source clock is disabled (PLL or PLL2). + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(p_cfg->p_callback); + FSP_ASSERT(p_cfg->p_bit_timing); + + /* Check that the module is not open, the channel is present and that it is not in use */ + FSP_ERROR_RETURN(CANFD_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(p_cfg->channel < 2, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(NULL == gp_ctrl[p_cfg->channel], FSP_ERR_IN_USE); + + /* Check that mandatory interrupts are enabled */ + FSP_ERROR_RETURN(VECTOR_NUMBER_CAN_RXF >= 0, FSP_ERR_CAN_INIT_FAILED); + FSP_ERROR_RETURN(VECTOR_NUMBER_CAN_GLERR >= 0, FSP_ERR_CAN_INIT_FAILED); + + /* Check that the global config is present */ + canfd_extended_cfg_t * p_extend = (canfd_extended_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(p_extend->p_global_cfg); + + #if BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC + + /* Check that PLL/PLL2 is running when it is selected as the DLL source clock */ + FSP_ERROR_RETURN(0U == (R_SYSTEM->CANFDCKCR == BSP_CLOCKS_SOURCE_CLOCK_PLL ? R_SYSTEM->PLLCR : R_SYSTEM->PLL2CR), + FSP_ERR_CLOCK_INACTIVE); + #endif + + /* Check nominal bit timing parameters for correctness */ + FSP_ERROR_RETURN(r_canfd_bit_timing_parameter_check(p_cfg->p_bit_timing), FSP_ERR_CAN_INIT_FAILED); + + /* Check that bit timing for FD bitrate switching is present and correct */ + can_bit_timing_cfg_t * p_data_timing = p_extend->p_data_timing; + FSP_ASSERT(p_data_timing); + FSP_ERROR_RETURN(r_canfd_bit_timing_parameter_check(p_data_timing), FSP_ERR_CAN_INIT_FAILED); + + can_bit_timing_cfg_t * p_bit_timing = p_cfg->p_bit_timing; + + /* Check that data rate > nominal rate */ + uint32_t data_rate_clocks = p_data_timing->baud_rate_prescaler * + (p_data_timing->time_segment_1 + p_data_timing->time_segment_2 + 1U); + uint32_t nominal_rate_clocks = p_bit_timing->baud_rate_prescaler * + (p_bit_timing->time_segment_1 + p_bit_timing->time_segment_2 + 1U); + FSP_ERROR_RETURN(data_rate_clocks <= nominal_rate_clocks, FSP_ERR_CAN_INIT_FAILED); +#else + + /* Get extended config */ + canfd_extended_cfg_t * p_extend = (canfd_extended_cfg_t *) p_cfg->p_extend; +#endif + + fsp_err_t err = FSP_SUCCESS; + + /* Initialize the control block */ + p_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Get global config */ + canfd_global_cfg_t * p_global_cfg = p_extend->p_global_cfg; + + /* Start module */ + R_BSP_MODULE_START(FSP_IP_CANFD, 0); + + /* Perform global config only if the module is in Global Sleep or Global Reset */ + if (R_CANFD->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) + { + /* Wait for RAM initialization (see RA6M5 User's Manual (R01UH0891EJ0100) section 32.3.4.1 Note 2) */ + FSP_HARDWARE_REGISTER_WAIT((R_CANFD->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); + + /* Cancel Global Sleep and wait for transition to Global Reset */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); + + /* Configure global TX priority, DLC check/replace functions, external/internal clock select and payload + * overflow behavior */ + R_CANFD->CFDGCFG = p_global_cfg->global_config; + + /* Configure rule count for both channels */ + R_CANFD->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos) | + CANFD_CFG_AFL_CH1_RULE_NUM; + + /* Set CAN FD Protocol Exception response (ISO exception state or send error frame) */ + R_CANFD->CFDGFDCFG = CANFD_CFG_FD_PROTOCOL_EXCEPTION; + + /* Set CAN FD standard (ISO or Bosch) */ + R_CANFD->CFDGCRCCFG = CANFD_CFG_FD_STANDARD; + + /* Set number and size of RX message buffers */ + R_CANFD->CFDRMNB = p_global_cfg->rx_mb_config; + + /* Configure RX FIFOs and interrupt */ + for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) + { + R_CANFD->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; + } + + R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_RXF, p_global_cfg->rx_fifo_ipl, NULL); + + /* Set global error interrupts */ + R_CANFD->CFDGCTR = p_global_cfg->global_interrupts; + } + + if (CANFD_CFG_GLOBAL_ERROR_CH == p_cfg->channel) + { + /* Configure global error interrupt */ + R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_GLERR, p_global_cfg->global_err_ipl, NULL); + } + + /* Track ctrl struct */ + gp_ctrl[p_cfg->channel] = p_ctrl; + + /* Get AFL entry and limit */ + uint32_t afl_entry = 0; + uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; + if (1U == p_cfg->channel) + { + afl_entry += CANFD_CFG_AFL_CH0_RULE_NUM; + afl_max += CANFD_CFG_AFL_CH1_RULE_NUM; + } + + /* Unlock AFL */ + R_CANFD->CFDGAFLECTR = R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + + /* Write all configured AFL entries */ + R_CANFD_CFDGAFL_Type * p_afl = (R_CANFD_CFDGAFL_Type *) p_extend->p_afl; + for ( ; afl_entry < afl_max; afl_entry++) + { + /* AFL register access is performed through a page window comprised of 16 entries. See Section 32.5.4 "Entering + * Entries in the AFL" in the RA6M5 User's Manual (R01UH0891EJ010) for more details. */ + + /* Set AFL page */ + R_CANFD->CFDGAFLECTR = (afl_entry >> 4) | R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + + /* Get pointer to current AFL rule and set it to the rule pointed to by p_afl */ + volatile R_CANFD_CFDGAFL_Type * cfdgafl = &R_CANFD->CFDGAFL[afl_entry & 0xF]; + *cfdgafl = *p_afl++; + + /* Set Information Label 0 to the channel being configured */ + cfdgafl->P0_b.GAFLIFL0 = p_cfg->channel & 1U; + } + + /* Lock AFL */ + R_CANFD->CFDGAFLECTR = 0; + + /* Cancel Channel Sleep and wait for transition to Channel Reset */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_RESET); + + /* Configure bitrate */ + R_CANFD->CFDC[p_cfg->channel].NCFG = + (uint32_t) (((p_cfg->p_bit_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC_NCFG_NBRP_Msk) << + R_CANFD_CFDC_NCFG_NBRP_Pos) | + ((p_cfg->p_bit_timing->time_segment_1 - 1U) << R_CANFD_CFDC_NCFG_NTSEG1_Pos) | + ((p_cfg->p_bit_timing->time_segment_2 - 1U) << R_CANFD_CFDC_NCFG_NTSEG2_Pos) | + ((p_cfg->p_bit_timing->synchronization_jump_width - 1U) << R_CANFD_CFDC_NCFG_NSJW_Pos); + + /* Configure data bitrate for rate switching on FD frames */ + R_CANFD->CFDC2[p_cfg->channel].DCFG = + (uint32_t) (((p_extend->p_data_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC2_DCFG_DBRP_Msk) << + R_CANFD_CFDC2_DCFG_DBRP_Pos) | + ((p_extend->p_data_timing->time_segment_1 - 1U) << R_CANFD_CFDC2_DCFG_DTSEG1_Pos) | + ((p_extend->p_data_timing->time_segment_2 - 1U) << R_CANFD_CFDC2_DCFG_DTSEG2_Pos) | + ((p_extend->p_data_timing->synchronization_jump_width - 1U) << R_CANFD_CFDC2_DCFG_DSJW_Pos); + + /* Ensure transceiver delay offset is not larger than 8 bits */ + uint32_t tdco = p_extend->p_data_timing->time_segment_1; + if (tdco > UINT8_MAX) + { + tdco = UINT8_MAX; + } + + /* Configure transceiver delay compensation; allow user to set ESI bit manually */ + R_CANFD->CFDC2[p_cfg->channel].FDCFG = + (tdco << R_CANFD_CFDC2_FDCFG_TDCO_Pos) | + (uint32_t) (p_extend->delay_compensation << R_CANFD_CFDC2_FDCFG_TDCE_Pos) | + R_CANFD_CFDC2_FDCFG_ESIC_Msk | 1U; + + /* Write TX message buffer interrupt enable bits */ + memcpy((void *) &R_CANFD->CFDTMIEC[p_cfg->channel * 2], &p_extend->txmb_txi_enable, 2 * sizeof(uint32_t)); + + /* Configure channel error interrupts */ + R_CANFD->CFDC[p_cfg->channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; + + /* Enable channel interrupts */ + + if (p_cfg->error_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->error_irq, p_cfg->ipl, p_ctrl); + } + + if (p_cfg->mailbox_tx_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->mailbox_tx_irq, p_cfg->ipl, p_ctrl); + } + + /* Set global mode to Operation and wait for transition */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_OPERATION); + + /* Transition to Channel Operation */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_NORMAL); + + /* Set current operation modes */ + p_ctrl->operation_mode = CAN_OPERATION_MODE_NORMAL; + p_ctrl->test_mode = CAN_TEST_MODE_DISABLED; + + /* Set driver to open */ + p_ctrl->open = CANFD_OPEN; + + return err; +} + +/***************************************************************************************************************//** + * Close the CANFD channel. + * + * @retval FSP_SUCCESS Channel closed successfully. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Close (can_ctrl_t * const p_api_ctrl) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Set driver to closed */ + p_ctrl->open = 0U; + + /* Get config struct */ + can_cfg_t * p_cfg = (can_cfg_t *) p_ctrl->p_cfg; + + /* Disable channel interrupts */ + + if (p_cfg->error_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->error_irq); + } + + if (p_cfg->mailbox_tx_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->mailbox_tx_irq); + } + + /* Disable Global Error interrupt if the handler channel is being closed */ + if (CANFD_CFG_GLOBAL_ERROR_CH == p_cfg->channel) + { + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_GLERR); + } + + /* Set channel to Sleep if other is open, otherwise reset/stop CANFD module */ + if (gp_ctrl[!p_cfg->channel]) + { + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_SLEEP); + } + else + { + /* Disable RX FIFO interrupt */ + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_RXF); + + /* Transition to Global Sleep */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_SLEEP); + + /* Stop CANFD module */ + R_BSP_MODULE_STOP(FSP_IP_CANFD, 0); + } + + /* Reset global control struct pointer */ + gp_ctrl[p_cfg->channel] = NULL; + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Write data to the CANFD channel. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_Write + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_CAN_TRANSMIT_NOT_READY Transmit in progress, cannot write data at this time. + * @retval FSP_ERR_INVALID_ARGUMENT Data length or buffer number invalid. + * @retval FSP_ERR_INVALID_MODE An FD option was set on a non-FD frame. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Write (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_frame_t * const p_frame) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_frame); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + + /* CANFD channels have 16 TX message buffers each (0-7, 32-39) */ + FSP_ERROR_RETURN((buffer <= 7U) || (buffer - 32U <= 7U), FSP_ERR_INVALID_ARGUMENT); + + /* Check DLC field */ + if (!(p_frame->options & CANFD_FRAME_OPTION_FD)) + { + FSP_ERROR_RETURN(p_frame->data_length_code <= 8, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_frame->options == 0, FSP_ERR_INVALID_MODE); + } + else if (p_frame->data_length_code > 0) + { + /* Make sure the supplied data size corresponds to a valid DLC value */ + FSP_ERROR_RETURN(0U != r_canfd_bytes_to_dlc(p_frame->data_length_code), FSP_ERR_INVALID_ARGUMENT); + } + else + { + /* Do nothing. */ + } +#endif + + /* Calculate global TX message buffer number */ + uint32_t txmb = buffer + (p_ctrl->p_cfg->channel * CANFD_PRV_TXMB_CHANNEL_OFFSET); + + /* Ensure MB is ready */ + FSP_ERROR_RETURN(0U == R_CANFD->CFDTMSTS_b[txmb].TMTSTS, FSP_ERR_CAN_TRANSMIT_NOT_READY); + + /* Set TX message buffer registers */ + R_CANFD->CFDTM[txmb].ID = p_frame->id | ((uint32_t) p_frame->type << R_CANFD_CFDTM_ID_TMRTR_Pos) | + ((uint32_t) p_frame->id_mode << R_CANFD_CFDTM_ID_TMIDE_Pos); + R_CANFD->CFDTM[txmb].PTR = (uint32_t) r_canfd_bytes_to_dlc(p_frame->data_length_code) << + R_CANFD_CFDTM_PTR_TMDLC_Pos; + + /* Set FD bits (ESI, BRS and FDF) */ + R_CANFD->CFDTM[txmb].FDCTR = p_frame->options & 7U; + + /* Copy data to register buffer */ + memcpy((void *) R_CANFD->CFDTM[txmb].DF, p_frame->data, p_frame->data_length_code); + + /* Request transmission */ + R_CANFD->CFDTMC[txmb] = 1; + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Read data from a CANFD Message Buffer or FIFO. + * + * Example: + * snippet r_canfd_example.c R_CANFD_Read + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_ARGUMENT Buffer number invalid. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_frame is NULL. + * @retval FSP_ERR_BUFFER_EMPTY Buffer or FIFO is empty. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Read (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_frame_t * const p_frame) +{ +#if CANFD_CFG_PARAM_CHECKING_ENABLE + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_frame); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(buffer < CANFD_PRV_RXMB_MAX + CANFD_PRV_RX_FIFO_MAX, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + uint32_t not_empty; + + /* Return an error if the buffer or FIFO is empty */ + if (buffer < CANFD_PRV_RXMB_MAX) + { + not_empty = R_CANFD->CFDRMND0 & (1U << buffer); + } + else + { + not_empty = !(R_CANFD->CFDFESTS & (1U << (buffer - CANFD_PRV_RXMB_MAX))); + } + + FSP_ERROR_RETURN(not_empty, FSP_ERR_BUFFER_EMPTY); + + /* Retrieve message from buffer */ + r_canfd_mb_read(buffer, p_frame); + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Switch to a different channel, global or test mode. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_ModeTransition + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + * @retval FSP_ERR_INVALID_MODE Cannot change to the requested mode from the current global mode. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + + /* Get Global Status */ + uint32_t cfdgsts = R_CANFD->CFDGSTS; + + /* Check to ensure the current mode is Global Halt when transitioning into or out of Internal Bus mode */ + FSP_ERROR_RETURN((cfdgsts & R_CANFD_CFDGSTS_GHLTSTS_Msk) || !((p_ctrl->test_mode != test_mode) && + ((CAN_TEST_MODE_INTERNAL_BUS == p_ctrl->test_mode) || + (CAN_TEST_MODE_INTERNAL_BUS == test_mode))), + FSP_ERR_INVALID_MODE); + + /* Check to ensure the current mode is Global Reset when transitioning into or out of Global Sleep (see Section + * 32.3.2 "Global Modes" in the RA6M5 User's Manual (R01UH0891EJ0100) for details) */ + FSP_ERROR_RETURN(((cfdgsts & R_CANFD_CFDGSTS_GRSTSTS_Msk) && (CAN_OPERATION_MODE_RESET & operation_mode)) || + (!(cfdgsts & R_CANFD_CFDGSTS_GSLPSTS_Msk) && (CAN_OPERATION_MODE_GLOBAL_SLEEP != operation_mode)), + FSP_ERR_INVALID_MODE); + + /* Check to ensure the current Global mode supports the requested Channel mode, if applicable. The requested mode + * and the current global mode are converted into a number 0-3 corresponding to Operation, Halt, Reset and Sleep + * respectively. The channel mode cannot be switched to a mode with an index lower than the current global mode. */ + if (operation_mode < CAN_OPERATION_MODE_GLOBAL_OPERATION) + { + FSP_ERROR_RETURN(g_mode_order[operation_mode] >= g_mode_order[cfdgsts & CANFD_PRV_CTR_MODE_MASK], + FSP_ERR_INVALID_MODE); + } +#endif + + if (p_ctrl->test_mode != test_mode) + { + /* Follow the procedure for switching to Internal Bus mode given in Section 32.9.2.2 "Internal CAN Bus + * Communication Test Mode" of the RA6M5 User's Manual (R01UH0891EJ0100) */ + if (CAN_TEST_MODE_INTERNAL_BUS == test_mode) + { + /* Disable channel test mode */ + R_CANFD->CFDC[p_ctrl->p_cfg->channel].CTR_b.CTME = 0; + + /* Link channel to internal bus */ + R_CANFD->CFDGTSTCFG |= 1U << p_ctrl->p_cfg->channel; + + /* Enable internal bus test mode */ + R_CANFD->CFDGTSTCTR = 1; + } + else + { + if (p_ctrl->test_mode == CAN_TEST_MODE_INTERNAL_BUS) + { + /* Unlink channel from internal bus */ + R_CANFD->CFDGTSTCFG &= ~(1U << p_ctrl->p_cfg->channel); + + /* Disable global test mode if no channels are linked */ + if (!R_CANFD->CFDGTSTCFG) + { + R_CANFD->CFDGTSTCTR = 0; + } + } + + /* Transition to Channel Halt when changing test modes */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_HALT); + + /* Set channel test mode */ + uint32_t cfdcnctr = R_CANFD->CFDC[p_ctrl->p_cfg->channel].CTR; + cfdcnctr &= ~(R_CANFD_CFDC_CTR_CTME_Msk | R_CANFD_CFDC_CTR_CTMS_Msk); + R_CANFD->CFDC[p_ctrl->p_cfg->channel].CTR = cfdcnctr | ((uint32_t) test_mode << R_CANFD_CFDC_CTR_CTME_Pos); + } + + p_ctrl->test_mode = test_mode; + } + + if (p_ctrl->operation_mode != operation_mode) + { + r_canfd_mode_transition(p_ctrl, operation_mode); + } + + return err; +} + +/***************************************************************************************************************//** + * Get CANFD state and status information for the channel. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CANFD_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_info) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + + /* Check pointers for NULL values */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_info); + + /* If channel is not open, return an error */ + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); +#endif + + uint32_t cfdcnsts = R_CANFD->CFDC[p_ctrl->p_cfg->channel].STS; + p_info->status = cfdcnsts & UINT16_MAX; + p_info->error_count_receive = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_REC_Msk) >> R_CANFD_CFDC_STS_REC_Pos); + p_info->error_count_transmit = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_TEC_Msk) >> R_CANFD_CFDC_STS_TEC_Pos); + p_info->error_code = R_CANFD->CFDC[p_ctrl->p_cfg->channel].ERFL & UINT16_MAX; + p_info->rx_mb_status = R_CANFD->CFDRMND0; + p_info->rx_fifo_status = (~R_CANFD->CFDFESTS) & R_CANFD_CFDFESTS_RFXEMP_Msk; + + /* Clear error flags */ + R_CANFD->CFDC[p_ctrl->p_cfg->channel].ERFL &= ~((uint32_t) UINT16_MAX); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref can_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CANFD_CallbackSet (can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void const * const p_context, + can_callback_args_t * const p_callback_memory) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CANFD_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CANFD_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + can_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(can_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * DEPRECATED Get CAN module code and API versions. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION Null pointer presented + **********************************************************************************************************************/ +fsp_err_t R_CANFD_VersionGet (fsp_version_t * const p_version) +{ +#if CANFD_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value */ + FSP_ASSERT(NULL != p_version); +#endif + + /* Return module version information. */ + p_version->version_id = g_canfd_version.version_id; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CAN) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ +#if CANFD_CFG_PARAM_CHECKING_ENABLE +static bool r_canfd_bit_timing_parameter_check (can_bit_timing_cfg_t * const p_bit_timing) +{ + /* Check that prescaler is in range */ + FSP_ERROR_RETURN((p_bit_timing->baud_rate_prescaler <= CANFD_BAUD_RATE_PRESCALER_MAX) && + (p_bit_timing->baud_rate_prescaler >= CANFD_BAUD_RATE_PRESCALER_MIN), + false); + + /* Check that TSEG1 > TSEG2 >= SJW for nominal bitrate per section 32.4.1.1 "Bit Timing Conditions" in the RA6M5 + * User's Manual (R01UH0891EJ0100). */ + + /* Check Time Segment 1 is greater than Time Segment 2 */ + FSP_ERROR_RETURN((uint32_t) p_bit_timing->time_segment_1 > (uint32_t) p_bit_timing->time_segment_2, false); + + /* Check Time Segment 2 is greater than or equal to the synchronization jump width */ + FSP_ERROR_RETURN((uint32_t) p_bit_timing->time_segment_2 >= (uint32_t) p_bit_timing->synchronization_jump_width, + false); + + return true; +} + +#endif + +/*******************************************************************************************************************//** + * Read from a Message Buffer or FIFO. + * + * NOTE: Does not index FIFOs. + * + * @param[in] buffer Index of buffer to read from (MBs 0-31, FIFOs 32+) + * @param[in] frame Pointer to CAN frame to write to + **********************************************************************************************************************/ +static void r_canfd_mb_read (uint32_t buffer, can_frame_t * const frame) +{ + bool is_mb = buffer < CANFD_PRV_RXMB_MAX; + + /* Get pointer to message buffer (FIFOs use the same buffer structure) */ + volatile R_CANFD_CFDRM_Type * mb_regs = + (is_mb) ? &(R_CANFD->CFDRM[buffer]) : + (volatile R_CANFD_CFDRM_Type *) &(R_CANFD->CFDRF[buffer - CANFD_PRV_RXMB_MAX]); + + /* Get frame data. */ + uint32_t id = mb_regs->ID; + + /* Get the frame type */ + frame->type = (can_frame_type_t) ((id & R_CANFD_CFDRM_ID_RMRTR_Msk) >> R_CANFD_CFDRM_ID_RMRTR_Pos); + + /* Get FD status bits (ESI, BRS and FDF) */ + frame->options = mb_regs->FDSTS & 7U; + + /* Get the frame ID */ + frame->id = id & R_CANFD_CFDRM_ID_RMID_Msk; + + /* Get the frame ID mode (IDE bit) */ + frame->id_mode = (can_id_mode_t) (id >> R_CANFD_CFDRM_ID_RMIDE_Pos); + + /* Get the frame data length code */ + frame->data_length_code = dlc_to_bytes[mb_regs->PTR >> R_CANFD_CFDRM_PTR_RMDLC_Pos]; + + /* Copy data to frame */ + memcpy(frame->data, (void *) mb_regs->DF, frame->data_length_code); + + if (is_mb) + { + /* Clear RXMB New Data bit */ + R_CANFD->CFDRMND0 &= ~(1U << buffer); + } + else + { + /* Increment RX FIFO pointer */ + R_CANFD->CFDRFPCTR[buffer - CANFD_PRV_RXMB_MAX] = UINT8_MAX; + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to CAN instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_canfd_call_callback (canfd_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args) +{ + can_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + can_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + canfd_prv_ns_callback p_callback = (canfd_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Error ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common error function, and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_error_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Get IRQ and context */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args = {0U}; + canfd_instance_ctrl_t * p_callback_ctrl; + + if (VECTOR_NUMBER_CAN_GLERR == irq) + { + args.event = CAN_EVENT_ERR_GLOBAL; + + /* Read global error flags. */ + uint32_t cfdgerfl = R_CANFD->CFDGERFL; + + /* Global errors are in the top halfword of canfd_error_t; move and preserve ECC error flags. */ + args.error = ((cfdgerfl & UINT16_MAX) << 16) + ((cfdgerfl >> 16) << 28); + + /* Clear global error flags. */ + R_CANFD->CFDGERFL = 0; + + if (args.error & CANFD_ERROR_GLOBAL_MESSAGE_LOST) + { + /* Get lowest RX FIFO with Message Lost condition and clear the flag */ + args.buffer = __CLZ(__RBIT(R_CANFD->CFDFMSTS)); + R_CANFD->CFDRFSTS[args.buffer] &= ~R_CANFD_CFDRFSTS_RFMLT_Msk; + } + + /* Choose ctrl block for the selected global error handler channel. */ + p_callback_ctrl = gp_ctrl[CANFD_CFG_GLOBAL_ERROR_CH]; + + /* Set channel and context based on selected global error handler channel. */ + args.channel = CANFD_CFG_GLOBAL_ERROR_CH; + args.p_context = p_callback_ctrl->p_context; + } + else + { + args.event = CAN_EVENT_ERR_CHANNEL; + + /* Read and clear channel error flags. */ + args.error = R_CANFD->CFDC[p_ctrl->p_cfg->channel].ERFL & UINT16_MAX; // Upper halfword contains latest CRC + R_CANFD->CFDC[p_ctrl->p_cfg->channel].ERFL = 0; + + /* Choose the channel provided by the interrupt context. */ + p_callback_ctrl = p_ctrl; + + args.channel = p_ctrl->p_cfg->channel; + args.p_context = p_ctrl->p_context; + args.buffer = 0U; + } + + /* Set remaining arguments and call callback */ + args.p_frame = NULL; + r_canfd_call_callback(p_callback_ctrl, &args); + + /* Clear IRQ */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Receive ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common receive function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_rx_fifo_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + can_callback_args_t args; + + /* Get lowest FIFO requesting interrupt */ + uint32_t fifo = __CLZ(__RBIT(R_CANFD->CFDRFISTS)); + + /* Only perform ISR duties if a FIFO has requested it */ + if (fifo < CANFD_PRV_RX_FIFO_MAX) + { + /* Set static arguments */ + args.p_frame = &args.frame; + args.event = CAN_EVENT_RX_COMPLETE; + args.buffer = fifo + CANFD_PRV_RXMB_MAX; + + /* Read from the FIFO until it is empty */ + while (!(R_CANFD->CFDFESTS & (1U << fifo))) + { + /* Get channel associated with the AFL entry */ + args.channel = R_CANFD->CFDRF[fifo].FDSTS_b.RFIFL; + + /* Read and index FIFO */ + r_canfd_mb_read(fifo + CANFD_PRV_RXMB_MAX, &args.frame); + + /* Set the remaining callback arguments */ + args.p_context = gp_ctrl[args.channel]->p_context; + r_canfd_call_callback(gp_ctrl[args.channel], &args); + } + + /* Clear RX FIFO Interrupt Flag */ + R_CANFD->CFDRFSTS[fifo] &= ~R_CANFD_CFDRFSTS_RFIF_Msk; + } + + if (!R_CANFD->CFDRFISTS) + { + /* Clear interrupt in NVIC if there are no pending RX FIFO IRQs */ + R_BSP_IrqStatusClear(VECTOR_NUMBER_CAN_RXF); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common transmit function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_channel_tx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + uint32_t channel = p_ctrl->p_cfg->channel; + + /* Set static arguments */ + can_callback_args_t args; + args.channel = channel; + args.p_context = p_ctrl->p_context; + args.p_frame = NULL; + + /* Check the byte of CFDGTINTSTS0 that corresponds to the interrupting channel */ + uint32_t cfdgtintsts = *((uint8_t *) (&R_CANFD->CFDGTINTSTS0) + channel); + while (cfdgtintsts) + { + uint32_t txmb; + volatile uint32_t * cfdtm_sts; + + channel <<= 1; + + /* Get relevant TX status register bank */ + if (cfdgtintsts & R_CANFD_CFDGTINTSTS0_TSIF0_Msk) + { + cfdtm_sts = (volatile uint32_t *) &R_CANFD->CFDTMTCSTS[channel]; + args.event = CAN_EVENT_TX_COMPLETE; + } + else + { + cfdtm_sts = (volatile uint32_t *) &R_CANFD->CFDTMTASTS[channel]; + args.event = CAN_EVENT_TX_ABORTED; + } + + channel >>= 1; + + /* Calculate lowest TXMB with the specified event */ + txmb = __CLZ(__RBIT(*cfdtm_sts)); + txmb = (txmb < 8) ? txmb : __CLZ(__RBIT(*(cfdtm_sts + 1))) + CANFD_PRV_TXMB_OFFSET; + + /* Clear TX complete/abort flags */ + R_CANFD->CFDTMSTS_b[txmb + (CANFD_PRV_TXMB_CHANNEL_OFFSET * channel)].TMTRF = 0; + + /* Set the callback arguments */ + args.buffer = txmb; + r_canfd_call_callback(p_ctrl, &args); + + /* Check for more interrupts on this channel */ + cfdgtintsts = *((uint8_t *) (&R_CANFD->CFDGTINTSTS0) + channel); + } + + /* Clear interrupt */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is used to switch the CANFD peripheral operation mode. + * @param[in] p_ctrl - pointer to control structure + * @param[in] operation_mode - destination operation mode + **********************************************************************************************************************/ +static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode) +{ + uint32_t channel = p_ctrl->p_cfg->channel; + + /* Get bit 7 from operation_mode to determine if this is a global mode change request */ + bool global_mode = (bool) (operation_mode >> 7); + operation_mode &= 0xF; + + if (global_mode) + { + uint32_t cfdgctr = R_CANFD->CFDGCTR; + + r_canfd_mode_ctr_set(&R_CANFD->CFDGCTR, operation_mode); + + /* If CANFD is transitioning out of Reset the FIFOs need to be enabled. */ + if ((cfdgctr & R_CANFD_CFDGSTS_GRSTSTS_Msk) && !(operation_mode & CAN_OPERATION_MODE_RESET)) + { + /* Get global config */ + canfd_global_cfg_t * p_global_cfg = + ((canfd_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_global_cfg; + + /* Enable RX FIFOs */ + for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) + { + R_CANFD->CFDRFCC_b[i].RFE = p_global_cfg->rx_fifo_config[i] & 1U; + } + } + } + else + { + uint32_t cfdcnctr = R_CANFD->CFDC[channel].CTR; + + if (((cfdcnctr & R_CANFD_CFDC_CTR_CSLPR_Msk) && (!(CAN_OPERATION_MODE_RESET & operation_mode))) || + ((!(cfdcnctr & CANFD_PRV_CTR_RESET_BIT)) && (CAN_OPERATION_MODE_SLEEP == operation_mode))) + { + /* Transition channel to Reset if a transition to/from Sleep is requested (see Section 32.3.3 "Channel + * Modes" in the RA6M5 User's Manual (R01UH0891EJ0100) for details) */ + r_canfd_mode_ctr_set(&R_CANFD->CFDC[channel].CTR, CAN_OPERATION_MODE_RESET); + } + + /* Request transition to selected mode */ + r_canfd_mode_ctr_set(&R_CANFD->CFDC[channel].CTR, operation_mode); + } + + p_ctrl->operation_mode = (can_operation_mode_t) (R_CANFD->CFDC[channel].CTR & CANFD_PRV_CTR_MODE_MASK); +} + +/*******************************************************************************************************************//** + * Sets the provided CTR register to the requested mode and waits for the associated STS register to reflect the change + * @param[in] p_ctr_reg - pointer to control register + * @param[in] operation_mode - requested mode (not including global bits) + **********************************************************************************************************************/ +static void r_canfd_mode_ctr_set (volatile uint32_t * p_ctr_reg, can_operation_mode_t operation_mode) +{ + volatile uint32_t * p_sts_reg = p_ctr_reg + 1; + + /* See definitions for CFDCnCTR, CFDCnSTS, CFDGCTR and CFDGSTS in the RA6M5 User's Manual (R01UH0891EJ0100) */ + *p_ctr_reg = (*p_ctr_reg & ~CANFD_PRV_CTR_MODE_MASK) | operation_mode; + FSP_HARDWARE_REGISTER_WAIT((*p_sts_reg & CANFD_PRV_CTR_MODE_MASK), operation_mode); +} + +/*******************************************************************************************************************//** + * Converts bytes into a DLC value + * @param[in] bytes Number of payload bytes + **********************************************************************************************************************/ +static uint8_t r_canfd_bytes_to_dlc (uint8_t bytes) +{ + if (bytes <= 8) + { + return bytes; + } + + if (bytes <= 24) + { + return (uint8_t) (8U + ((bytes - 8U) / 4U)); + } + + return (uint8_t) (0xDU + ((bytes / 16U) - 2U)); +} diff --git a/ra/fsp/src/r_ctsu/r_ctsu.c b/ra/fsp/src/r_ctsu/r_ctsu.c index 448bbabde..bf491f753 100644 --- a/ra/fsp/src/r_ctsu/r_ctsu.c +++ b/ra/fsp/src/r_ctsu/r_ctsu.c @@ -76,10 +76,12 @@ #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) #define CTSU_CORRECTION_STD_VAL (19200) // 20UC standard value #define CTSU_CORRECTION_STD_UNIT (1920) // 2UC value + #define CTSU_CORRECTION_STD_EXREG (14400) // External registance standard value #define CTSU_CORRECTION_OFFSET_UNIT (120) // (7680 / 64) #else #define CTSU_CORRECTION_STD_VAL (15360) // 20UC standard value * 0.8 #define CTSU_CORRECTION_STD_UNIT (1536) // 2UC value * 0.8 + #define CTSU_CORRECTION_STD_EXREG (11520) // External registance standard value #define CTSU_CORRECTION_OFFSET_UNIT (96) // (7680 / 64) * 0.8 #endif #define CTSU_CORRECTION_SUMULTI (0x20) // SUMULTI step @@ -89,13 +91,13 @@ #define CTSU_CORRECTION_RTRIM_THRESHOLD2 (0x50) #define CTSU_CORRECTION_TRIMB_THRESHOLD1 (0xC0) #define CTSU_CORRECTION_TRIMB_THRESHOLD2 (0x3F) + #define CTSU_CORRECTION_BIT16 (0x10000) #define CTSU_CORRECTION_BIT10 (0x0400) #define CTSU_CORRECTION_BIT9 (0x0200) #define CTSU_CORRECTION_BIT8 (0x0100) #define CTSU_CORRECTION_BIT7 (0x0080) #if (CTSU_CFG_NUM_CFC != 0) - #define CTSU_CORRCFC_POINT_NUM (5) // number of table #define CTSU_CORRCFC_CENTER_POINT ((CTSU_CORRCFC_POINT_NUM - 1) / 2) // number of center point #define CTSU_CORRCFC_TS_MAX (36) // Maximum number of TS terminal #define CTSU_CORRCFC_SHIFT8 (8) // Definition of 8bit shift @@ -197,11 +199,10 @@ static void ctsu_correction_multi(ctsu_correction_multi_t * p_multi, uint16_t * #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) static void ctsu_correction_scan_start(void); -static void ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) -static void ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl); -static void ctsu_correction_offset_adjust(uint16_t * p_adj_data, uint16_t raw_data, int32_t offset_error); +static void ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); #endif #endif @@ -569,12 +570,6 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) if (CTSU_MODE_CORRECTION_SCAN == p_cfg->md) { - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - p_cfg->p_adc_instance->p_api->open(p_cfg->p_adc_instance->p_ctrl, p_cfg->p_adc_instance->p_cfg); - p_cfg->p_adc_instance->p_api->scanCfg(p_cfg->p_adc_instance->p_ctrl, p_cfg->p_adc_instance->p_channel_cfg); - R_ADC0->ADSSTRL = CTSU_CALIB_ADSSTRL; - ctsu_correction_calib_rtrim(p_instance_ctrl); - #endif g_ctsu_correction_info.scan_index = CTSU_CORRECTION_POINT_NUM; } #endif @@ -827,7 +822,7 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - ctsu_correction_data_get(p_instance_ctrl); + ctsu_correction_data_get(p_instance_ctrl, p_data); p_instance_ctrl->state = CTSU_STATE_IDLE; return err; @@ -1764,6 +1759,12 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) uint32_t trimb; uint8_t trimb_byte; uint8_t rtrim; + uint16_t base_value; + uint16_t base_conv_dac; + uint32_t ref_include_error; + int32_t x0; + int32_t x1; + int32_t y0; g_ctsu_correction_info.status = CTSU_CORRECTION_RUN; @@ -1877,27 +1878,41 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) /* Step4 : Calculate the coefficient between step2 and step3. */ for (i = 0; i < CTSU_RANGE_NUM; i++) { - g_ctsu_correction_info.error_rate[i] = - (uint16_t) (((uint32_t) g_ctsu_correction_info.base_value[i] * (uint32_t) error_registance[i]) / - g_ctsu_correction_info.dac_value[9]); + /* Linear interpolation calculation */ + base_value = g_ctsu_correction_info.base_value[i]; + j = 1; + while (1) + { + if ((base_value < g_ctsu_correction_info.dac_value[j]) || ((CTSU_CORRECTION_POINT_NUM - 1) == j)) + { + y0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * (j + 1)); + x0 = g_ctsu_correction_info.dac_value[j]; + x1 = g_ctsu_correction_info.dac_value[j - 1]; + break; + } + + j++; + } + + base_conv_dac = (uint16_t) (y0 - ((CTSU_CORRECTION_STD_UNIT * (x0 - base_value)) / (x0 - x1))); + + /* Error rate calculation */ + ref_include_error = (uint32_t) (CTSU_CORRECTION_STD_VAL * (CTSU_CORRECTION_BIT16 - error_registance[i])); + g_ctsu_correction_info.error_rate[i] = (uint16_t) (ref_include_error / base_conv_dac); for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) { - g_ctsu_correction_info.real_value[j] = - (uint16_t) (((uint32_t) g_ctsu_correction_info.dac_value[j] * - (uint32_t) g_ctsu_correction_info.error_rate[i]) >> + g_ctsu_correction_info.ref_value[i][j] = + (uint16_t) ((CTSU_CORRECTION_STD_UNIT * (j + 1) * g_ctsu_correction_info.error_rate[i]) >> CTSU_SHIFT_AMOUNT); - g_ctsu_correction_info.coefficient[i][j] = - (uint16_t) ((uint32_t) ((CTSU_CORRECTION_STD_UNIT * (j + 1)) << CTSU_SHIFT_AMOUNT) / - g_ctsu_correction_info.real_value[j]); } } for (i = 0; i < CTSU_RANGE_NUM - 1; i++) { g_ctsu_correction_info.range_ratio[i] = - (uint16_t) (((uint32_t) g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA] << CTSU_SHIFT_AMOUNT) / - g_ctsu_correction_info.error_rate[i]); + (uint16_t) (((uint32_t) g_ctsu_correction_info.error_rate[i] << CTSU_SHIFT_AMOUNT) / + g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA]); } g_ctsu_correction_info.status = CTSU_CORRECTION_COMPLETE; #endif @@ -2110,10 +2125,15 @@ void ctsu_correction_scan_start (void) /*********************************************************************************************************************** * ctsu_correction_data_get ***********************************************************************************************************************/ -void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl) +void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) { uint32_t i; uint32_t j; + uint16_t base_value; + uint16_t base_conv_dac; + int32_t x0; + int32_t x1; + int32_t y0; if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM) { @@ -2141,30 +2161,51 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl) /* Step4 : Calculate the coefficient between step2 and step3. */ if (g_ctsu_correction_info.update_counter > CTSU_CFG_TEMP_CORRECTION_TIME) { + /* Linear interpolation calculation */ + base_value = g_ctsu_correction_info.ex_base_value; + j = 1; + while (1) + { + if ((base_value < g_ctsu_correction_info.dac_value[j]) || ((CTSU_CORRECTION_POINT_NUM - 1) == j)) + { + y0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * (j + 1)); + x0 = g_ctsu_correction_info.dac_value[j]; + x1 = g_ctsu_correction_info.dac_value[j - 1]; + break; + } + + j++; + } + + base_conv_dac = (uint16_t) (y0 - ((CTSU_CORRECTION_STD_UNIT * (x0 - base_value)) / (x0 - x1))); + + /* Error rate calculation */ g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA] = - (uint16_t) ((g_ctsu_correction_info.ex_base_value << CTSU_SHIFT_AMOUNT) / - ((g_ctsu_correction_info.dac_value[7] + g_ctsu_correction_info.dac_value[6]) / 2)); + (uint16_t) ((CTSU_CORRECTION_STD_EXREG << CTSU_SHIFT_AMOUNT) / base_conv_dac); + for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) { - g_ctsu_correction_info.real_value[j] = - (uint16_t) ((g_ctsu_correction_info.dac_value[j] * + g_ctsu_correction_info.ref_value[CTSU_RANGE_160UA][j] = + (uint16_t) ((CTSU_CORRECTION_STD_UNIT * (j + 1) * g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA]) >> CTSU_SHIFT_AMOUNT); - g_ctsu_correction_info.coefficient[CTSU_RANGE_160UA][j] = - (uint16_t) (((CTSU_CORRECTION_STD_UNIT * (j + 1)) << CTSU_SHIFT_AMOUNT) / - g_ctsu_correction_info.real_value[j]); for (i = 0; i < CTSU_RANGE_NUM - 1; i++) { - g_ctsu_correction_info.coefficient[i][j] = - (uint16_t) ((g_ctsu_correction_info.coefficient[CTSU_RANGE_160UA][j] * + g_ctsu_correction_info.ref_value[i][j] = + (uint16_t) ((g_ctsu_correction_info.ref_value[CTSU_RANGE_160UA][j] * g_ctsu_correction_info.range_ratio[i]) >> CTSU_SHIFT_AMOUNT); } } g_ctsu_correction_info.update_counter = 0; #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - ctsu_correction_calib_rtrim(p_instance_ctrl); + ctsu_correction_calib_rtrim(p_instance_ctrl, p_data); #endif } + else + { + /* Indicates that ADC measurement was not performed. */ + *p_data = CTSU_COUNT_MAX; + } } #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) @@ -2172,7 +2213,7 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl) /*********************************************************************************************************************** * ctsu_correction_calib_rtrim ***********************************************************************************************************************/ -void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) +void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) { adc_status_t status; adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; @@ -2184,23 +2225,10 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) int16_t dir = 0; uint16_t comp = 0; - adctdr_sum = 0; - for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) - { - p_adc->p_api->scanStart(p_adc->p_ctrl); - - /* Wait for conversion to complete. */ - status.state = ADC_STATE_SCAN_IN_PROGRESS; - while (ADC_STATE_SCAN_IN_PROGRESS == status.state) - { - p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); - } - - p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); - adctdr_sum += adctdr_result; - } - - g_ctsu_correction_info.tscap_voltage = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); + /* Initialize ADC for CTSU TSCAP */ + p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); + p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + R_ADC0->ADSSTRL = CTSU_CALIB_ADSSTRL; /* Self single scan mode */ R_CTSU->CTSUCRA_b.LOAD = 1; @@ -2278,43 +2306,17 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) } } + /* Restore register settings */ R_CTSU->CTSUCALIB_b.DRV = 0; R_CTSU->CTSUCRA_b.CSW = 1; R_CTSU->CTSUCRA_b.DCMODE = 0; R_CTSU->CTSUCRA_b.DCBACK = 0; -} -/*********************************************************************************************************************** - * ctsu_correction_offset_adjust - ***********************************************************************************************************************/ -void ctsu_correction_offset_adjust (uint16_t * p_adj_data, uint16_t raw_data, int32_t offset_error) -{ - int32_t diff; - - diff = (int32_t) ((int32_t) raw_data - offset_error); + /* Indicates that ADC measurement was performed */ + *p_data = R_CTSUTRIM->CTSUTRIMA_b.RTRIM; - if (offset_error > 0) - { - if (0 < diff) - { - *p_adj_data = (uint16_t) diff; - } - else - { - *p_adj_data = 0; - } - } - else - { - if (CTSU_COUNT_MAX < diff) - { - *p_adj_data = CTSU_COUNT_MAX; - } - else - { - *p_adj_data = (uint16_t) diff; - } - } + /* Close ADC for CTSU TSCAP */ + p_adc->p_api->close(p_adc->p_ctrl); } #endif @@ -2327,7 +2329,6 @@ void ctsu_correction_offset_adjust (uint16_t * p_adj_data, uint16_t raw_data, in void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_correction_calc_t * p_calc) { uint32_t answer; - uint16_t coefficient; int32_t cmp_data; uint8_t calc_flag = 0; #if (BSP_FEATURE_CTSU_VERSION == 1) @@ -2335,6 +2336,7 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c int32_t diff_coefficient; int32_t mul_diffcoff_diff1valsval; uint32_t mul_coff1val_diffcorr; + uint16_t coefficient; #endif #if (BSP_FEATURE_CTSU_VERSION == 2) int32_t y0 = 0; @@ -2394,53 +2396,87 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c /* Get correction coefficient of scan data */ coefficient = (uint16_t) (((int32_t) mul_coff1val_diffcorr - mul_diffcoff_diff1valsval) / diff_val); + + /* Get output count data */ + answer = (uint32_t) (((uint32_t) raw_data * (uint32_t) coefficient) >> CTSU_SHIFT_AMOUNT); #endif #if (BSP_FEATURE_CTSU_VERSION == 2) /* Since the correction coefficient table is created with the recommended measurement time, */ /* If the measurement time is different, adjust the value level. */ - cmp_data = (int32_t) (((int32_t) raw_data * (CTSU_SNUM_RECOMMEND + 1)) / (p_calc->snum + 1)); + if (CTSU_SNUM_RECOMMEND == p_calc->snum) + { + cmp_data = raw_data; + } + else + { + cmp_data = (int32_t) (((int32_t) raw_data * (CTSU_SNUM_RECOMMEND + 1)) / (p_calc->snum + 1)); + } /* y = y0 + (y1 - y0) * (x - x0) / (x1 - x0); [y=coefficient, x=value] */ if (CTSU_MODE_MUTUAL_CFC_SCAN != p_calc->md) { - for (i = 1; i < CTSU_CORRECTION_POINT_NUM; i++) + i = 0; + while (1) { - if (((CTSU_CORRECTION_POINT_NUM - 1) == i) || - (cmp_data < g_ctsu_correction_info.real_value[i])) + if ((cmp_data < g_ctsu_correction_info.dac_value[i]) || ((CTSU_CORRECTION_POINT_NUM - 1) == i)) { - y0 = g_ctsu_correction_info.coefficient[p_calc->range][i]; - y1 = g_ctsu_correction_info.coefficient[p_calc->range][i - 1]; - x0 = g_ctsu_correction_info.real_value[i]; - x1 = g_ctsu_correction_info.real_value[i - 1]; + y0 = g_ctsu_correction_info.ref_value[p_calc->range][i]; + x0 = g_ctsu_correction_info.dac_value[i]; + if (0 == i) + { + x1 = 0; + y1 = 0; + } + else + { + x1 = g_ctsu_correction_info.dac_value[i - 1]; + y1 = g_ctsu_correction_info.ref_value[p_calc->range][i - 1]; + } + break; } + + i++; } } #if (CTSU_CFG_NUM_CFC != 0) else { - for (i = 1; i < CTSU_CORRCFC_POINT_NUM; i++) + i = 0; + while (1) { - if (((CTSU_CORRCFC_POINT_NUM - 1) == i) || - (cmp_data < g_ctsu_corrcfc_info.value[p_calc->cfc][i])) + if ((cmp_data < g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i]) || ((CTSU_CORRCFC_POINT_NUM - 1) == i)) { - y0 = g_ctsu_corrcfc_info.coefficient[p_calc->cfc][i]; - y1 = g_ctsu_corrcfc_info.coefficient[p_calc->cfc][i - 1]; - x0 = g_ctsu_corrcfc_info.value[p_calc->cfc][i]; - x1 = g_ctsu_corrcfc_info.value[p_calc->cfc][i - 1]; + y0 = g_ctsu_corrcfc_info.ref_value[p_calc->cfc][i]; + x0 = g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i]; + if (0 == i) + { + x1 = 0; + y1 = 0; + } + else + { + x1 = g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i - 1]; + y1 = g_ctsu_corrcfc_info.ref_value[p_calc->cfc][i - 1]; + } + break; } + + i++; } } #endif - coefficient = (uint16_t) (y0 - (((y0 - y1) * (x0 - cmp_data)) / (x0 - x1))); -#endif + answer = (uint32_t) (y0 - (((y0 - y1) * (x0 - cmp_data)) / (x0 - x1))); - /* Get output count data */ - answer = (uint32_t) (((uint32_t) raw_data * (uint32_t) coefficient) >> CTSU_SHIFT_AMOUNT); + if (CTSU_SNUM_RECOMMEND != p_calc->snum) + { + answer = (uint32_t) ((answer * (uint32_t) (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + } +#endif /* Value Overflow Check */ if (CTSU_COUNT_MAX < answer) @@ -2567,25 +2603,6 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) ctsuso = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI) + i].ctsuso & CTSU_TUNING_MAX); multi.offset[i] = (ctsuso * (uint32_t) (CTSU_CORRECTION_OFFSET_UNIT >> calc.range)); - #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - - /* Correction offset current by TSCAP voltage error */ - if (0 == g_ctsu_correction_info.tscap_voltage) - { - multi.offset_error[i] = 0; - } - else - { - multi.offset_error[i] = - (int32_t) (((uint32_t) g_ctsu_correction_info.tscap_voltage << CTSU_SHIFT_AMOUNT) / CTSU_CALIB_REF); - multi.offset_error[i] = - (int32_t) (((multi.offset[i] * (uint32_t) multi.offset_error[i]) >> CTSU_SHIFT_AMOUNT) - - multi.offset[i]); - } - multi.offset[i] = (multi.offset[i] + (uint32_t) multi.offset_error[i]); - #endif - #endif } if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_cfg->md) @@ -2593,16 +2610,10 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { - multi.pri[i] = p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i]; - #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - ctsu_correction_offset_adjust(&multi.pri[i], - p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i], - multi.offset_error[i]); - #endif - #endif + ctsu_correction_calc(&multi.pri[i], + p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i], + &calc); multi.snd[i] = 0; - ctsu_correction_calc(&multi.pri[i], multi.pri[i], &calc); } p_self_data = (p_instance_ctrl->p_self_data + (element_id * CTSU_CFG_NUM_SUMULTI)); @@ -2636,21 +2647,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) } else if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - p_self_data = (p_instance_ctrl->p_self_data + (element_id * CTSU_CFG_NUM_SUMULTI)); - multi.pri[0] = p_instance_ctrl->p_self_raw[element_id]; - #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - ctsu_correction_offset_adjust(&multi.pri[0], - p_instance_ctrl->p_self_raw[element_id], - multi.offset_error[0]); - #endif - #endif + p_self_data = (p_instance_ctrl->p_self_data + (element_id * CTSU_CFG_NUM_SUMULTI)); /* Store last moving averaged data */ average_self[0] = p_self_data[0]; /* Correction */ - ctsu_correction_calc(p_self_data, multi.pri[0], &calc); + ctsu_correction_calc(p_self_data, p_instance_ctrl->p_self_raw[element_id], &calc); /* Update moving averaged data */ if (1 < p_instance_ctrl->average) @@ -2665,22 +2668,12 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { - multi.pri[i] = p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)]; - multi.snd[i] = p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1]; - #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) - #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - ctsu_correction_offset_adjust(&multi.pri[i], - p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + - (i * 2)], - multi.offset_error[i]); - ctsu_correction_offset_adjust(&multi.snd[i], - p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + - (i * 2) + 1], - multi.offset_error[i]); - #endif - #endif - ctsu_correction_calc(&multi.pri[i], multi.pri[i], &calc); - ctsu_correction_calc(&multi.snd[i], multi.snd[i], &calc); + ctsu_correction_calc(&multi.pri[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)], + &calc); + ctsu_correction_calc(&multi.snd[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1], + &calc); } p_pri_data = (p_instance_ctrl->p_mutual_pri_data + (element_id * CTSU_CFG_NUM_SUMULTI)); @@ -2742,10 +2735,12 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { - multi.pri[i] = p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2)]; - multi.snd[i] = p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2) + num_rx]; - ctsu_correction_calc(&multi.pri[i], multi.pri[i], &calc); - ctsu_correction_calc(&multi.snd[i], multi.snd[i], &calc); + ctsu_correction_calc(&multi.pri[i], + p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2)], + &calc); + ctsu_correction_calc(&multi.snd[i], + p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2) + num_rx], + &calc); } p_pri_data = (p_instance_ctrl->p_mutual_pri_data + (element_id * CTSU_CFG_NUM_SUMULTI)); @@ -2932,9 +2927,13 @@ void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) uint8_t j; uint8_t ts_id; uint8_t index; - uint32_t ref_temp; uint64_t new_bitmap; ctsu_cfg_t const * p_cfg; + uint16_t base_value; + uint16_t base_conv_dac; + int32_t x0; + int32_t x1; + int32_t y0; g_ctsu_corrcfc_info.status = CTSU_CORRECTION_RUN; @@ -3001,7 +3000,7 @@ void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) R_CTSU->CTSUSUCLK0 = (uint16_t) (((j + CTSU_CORRCFC_CENTER_POINT) * CTSU_CORRECTION_SUMULTI) - 1); R_CTSU->CTSUCRA_b.SDPSEL = 1; - ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.value[index][j], CTSU_CORRCFC_POINT_NUM); + ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.dac_value[index][j], CTSU_CORRCFC_POINT_NUM); } /* Reset register */ @@ -3011,18 +3010,33 @@ void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) /* Step3 : Calculate the error between step1 and step2. */ for (i = index; i < (index + g_ctsu_corrcfc_info.num_ts); i++) { + /* Linear interpolation calculation */ + base_value = g_ctsu_corrcfc_info.base_value[i]; + j = 1; + while (1) + { + if ((base_value < g_ctsu_corrcfc_info.dac_value[index][j]) || ((CTSU_CORRCFC_POINT_NUM - 1) == j)) + { + y0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * (j + CTSU_CORRCFC_CENTER_POINT)); + x0 = g_ctsu_corrcfc_info.dac_value[index][j]; + x1 = g_ctsu_corrcfc_info.dac_value[index][j - 1]; + break; + } + + j++; + } + + base_conv_dac = (uint16_t) (y0 - ((CTSU_CORRECTION_STD_UNIT * (x0 - base_value)) / (x0 - x1))); + + /* Error rate calculation */ g_ctsu_corrcfc_info.error_rate[i] = - (uint16_t) ((g_ctsu_corrcfc_info.base_value[i] << CTSU_SHIFT_AMOUNT) / - g_ctsu_corrcfc_info.value[i][CTSU_CORRCFC_CENTER_POINT]); + (uint16_t) (((CTSU_CORRECTION_STD_UNIT * 4) << CTSU_SHIFT_AMOUNT) / base_conv_dac); for (j = 0; j < CTSU_CORRCFC_POINT_NUM; j++) { - ref_temp = (uint32_t) ((CTSU_CORRECTION_STD_UNIT * (j + CTSU_CORRCFC_CENTER_POINT)) << CTSU_SHIFT_AMOUNT); - - g_ctsu_corrcfc_info.value[i][j] = - (uint16_t) ((g_ctsu_corrcfc_info.value[i][j] * g_ctsu_corrcfc_info.error_rate[i]) >> CTSU_SHIFT_AMOUNT); - - g_ctsu_corrcfc_info.coefficient[i][j] = (uint16_t) (ref_temp / g_ctsu_corrcfc_info.value[i][j]); + g_ctsu_corrcfc_info.ref_value[i][j] = + (uint16_t) ((CTSU_CORRECTION_STD_UNIT * (j + CTSU_CORRCFC_CENTER_POINT) * + g_ctsu_corrcfc_info.error_rate[i]) >> CTSU_SHIFT_AMOUNT); } } diff --git a/ra/fsp/src/r_dmac/r_dmac.c b/ra/fsp/src/r_dmac/r_dmac.c index 52db940cf..93a7a124d 100644 --- a/ra/fsp/src/r_dmac/r_dmac.c +++ b/ra/fsp/src/r_dmac/r_dmac.c @@ -530,7 +530,8 @@ static void r_dmac_config_transfer_info (dmac_instance_ctrl_t * p_ctrl, transfer /* Configure the transfer count. */ dmcra = p_info->length; - if ((TRANSFER_MODE_BLOCK == p_info->mode) || (TRANSFER_MODE_REPEAT == p_info->mode)) + if ((TRANSFER_MODE_BLOCK == p_info->mode) || (TRANSFER_MODE_REPEAT == p_info->mode) || + (TRANSFER_MODE_REPEAT_BLOCK == p_info->mode)) { /* Configure the reload count. */ dmcra |= dmcra << DMAC_PRV_DMCRA_HIGH_OFFSET; @@ -539,8 +540,11 @@ static void r_dmac_config_transfer_info (dmac_instance_ctrl_t * p_ctrl, transfer /* Configure the block count. */ dmcrb = p_info->num_blocks; - /* Configure the repeat area */ - dmtmd |= (uint32_t) (p_info->repeat_area << DMAC_PRV_DMTMD_DTS_OFFSET); + if ((TRANSFER_MODE_BLOCK == p_info->mode) || (TRANSFER_MODE_REPEAT == p_info->mode)) + { + /* Configure the repeat area */ + dmtmd |= (uint32_t) (p_info->repeat_area << DMAC_PRV_DMTMD_DTS_OFFSET); + } } else /* TRANSFER_MODE_NORMAL */ { @@ -561,15 +565,71 @@ static void r_dmac_config_transfer_info (dmac_instance_ctrl_t * p_ctrl, transfer if (TRANSFER_IRQ_EACH == p_info->irq) { - /* Enable the transfer end escape interrupt requests - * (Repeat size end and Extended Repeat area overflow requests). */ - dmint |= (DMAC_PRV_DMINT_RPTIE_MASK | DMAC_PRV_DMINT_ESIE_MASK); + if (TRANSFER_MODE_REPEAT_BLOCK == p_info->mode) + { + /* Enable the transfer end escape interrupt requests. + * Repeat size end and Extended Repeat area overflow requests are not + * used with Repeat-Block mode. Reference section 16.2.9 "DMINT : DMA Interrupt Setting Register" + * of RA6M4 hardware manual R01UH0890EJ0110. */ + dmint |= DMAC_PRV_DMINT_ESIE_MASK; + } + else + { + /* Enable the transfer end escape interrupt requests + * (Repeat size end and Extended Repeat area overflow requests). */ + dmint |= (DMAC_PRV_DMINT_RPTIE_MASK | DMAC_PRV_DMINT_ESIE_MASK); + } } /* Enable the IRQ in the NVIC. */ R_BSP_IrqCfgEnable(p_extend->irq, p_extend->ipl, p_ctrl); } +#if BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE + uint32_t dmsbs = 0; + uint32_t dmdbs = 0; + + if (TRANSFER_MODE_REPEAT_BLOCK == p_info->mode) + { + uint16_t num_of_blocks = p_info->num_blocks; + uint16_t size_of_block; + size_of_block = p_info->length; + uint16_t src_buffer_size; + uint16_t dest_buffer_size; + if (TRANSFER_ADDR_MODE_OFFSET == p_info->src_addr_mode) + { + src_buffer_size = num_of_blocks; + dmamd |= R_DMAC0_DMAMD_SADR_Msk; + } + else + { + src_buffer_size = p_extend->src_buffer_size; + } + + if (TRANSFER_ADDR_MODE_OFFSET == p_info->dest_addr_mode) + { + dest_buffer_size = num_of_blocks; + dmamd |= R_DMAC0_DMAMD_DADR_Msk; + } + else + { + dest_buffer_size = (uint16_t) (num_of_blocks * size_of_block); + } + + dmsbs = src_buffer_size; + dmsbs |= dmsbs << R_DMAC0_DMSBS_DMSBSH_Pos; + + dmdbs = dest_buffer_size; + dmdbs |= dmdbs << R_DMAC0_DMDBS_DMDBSH_Pos; + + p_ctrl->p_reg->DMSRR = (uint32_t) p_info->p_src; + p_ctrl->p_reg->DMDRR = (uint32_t) p_info->p_dest; + } + + p_ctrl->p_reg->DMSBS = dmsbs; + p_ctrl->p_reg->DMDBS = dmdbs; +#endif + /* Write register settings. */ p_ctrl->p_reg->DMAMD = (uint16_t) dmamd; p_ctrl->p_reg->DMTMD = (uint16_t) dmtmd; diff --git a/ra/fsp/src/r_ether/r_ether.c b/ra/fsp/src/r_ether/r_ether.c index 38783db3d..103742852 100644 --- a/ra/fsp/src/r_ether/r_ether.c +++ b/ra/fsp/src/r_ether/r_ether.c @@ -1109,7 +1109,7 @@ static fsp_err_t ether_open_param_check (ether_instance_ctrl_t const * const p_i ETHER_ERROR_RETURN((NULL != p_cfg->p_mac_address), FSP_ERR_INVALID_POINTER); ETHER_ERROR_RETURN((BSP_FEATURE_ETHER_MAX_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); ETHER_ERROR_RETURN((0 <= p_cfg->irq), FSP_ERR_INVALID_ARGUMENT); - ETHER_ERROR_RETURN((p_cfg->padding <= ETEHR_PADDING_3BYTE), FSP_ERR_INVALID_ARGUMENT); + ETHER_ERROR_RETURN((p_cfg->padding <= ETHER_PADDING_3BYTE), FSP_ERR_INVALID_ARGUMENT); if (p_cfg->padding != ETHER_PADDING_DISABLE) { diff --git a/ra/fsp/src/r_gpt/r_gpt.c b/ra/fsp/src/r_gpt/r_gpt.c index 4e0866a56..103a41f88 100644 --- a/ra/fsp/src/r_gpt/r_gpt.c +++ b/ra/fsp/src/r_gpt/r_gpt.c @@ -500,7 +500,11 @@ fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_c r_gpt_write_protect_disable(p_instance_ctrl); - p_instance_ctrl->p_reg->GTCCR[pin + 2] = duty_regs.gtccr_buffer; + /* Only update GTCCR if 0% or 100% duty is not requested */ + if (!duty_regs.omdty) + { + p_instance_ctrl->p_reg->GTCCR[pin + 2] = duty_regs.gtccr_buffer; + } /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the * other pin. */ diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index ee9beb335..679b52fd0 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -478,7 +478,7 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) snzcr |= (uint32_t) (p_cfg->dtc_state_in_snooze << R_SYSTEM_SNZCR_SNZDTCEN_Pos); /* Set the source that can cause an exit from snooze to normal mode */ - R_ICU->SELSR0_b.SELS = (uint8_t) p_cfg->snooze_cancel_sources; + R_ICU->SELSR0_b.SELS = R_ICU_SELSR0_SELS_Msk & p_cfg->snooze_cancel_sources; /* Set all sources that can cause an exit from snooze mode to software standby. */ R_SYSTEM->SNZEDCR = (uint8_t) p_cfg->snooze_end_sources & UINT8_MAX; diff --git a/ra/fsp/src/r_ospi/r_ospi.c b/ra/fsp/src/r_ospi/r_ospi.c index f69e549dd..18057cbd6 100644 --- a/ra/fsp/src/r_ospi/r_ospi.c +++ b/ra/fsp/src/r_ospi/r_ospi.c @@ -169,11 +169,12 @@ fsp_err_t R_OSPI_Open (spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_instance_ctrl->channel); /* Max = 256 bytes, i.e., Page size */ - R_OSPI->DWSCTSR = OSPI_PRV_SHIFT(OSPI_PRV_PAGE_SIZE_BYTES << R_OSPI_DWSCTSR_CTSN0_Pos, p_instance_ctrl->channel); + R_OSPI->DWSCTSR = OSPI_PRV_SHIFT(p_instance_ctrl->p_cfg->page_size_bytes << R_OSPI_DWSCTSR_CTSN0_Pos, + p_instance_ctrl->channel); /* Read back to ensure value has been written */ FSP_HARDWARE_REGISTER_WAIT(R_OSPI->DWSCTSR, - OSPI_PRV_SHIFT(OSPI_PRV_PAGE_SIZE_BYTES << R_OSPI_DWSCTSR_CTSN0_Pos, + OSPI_PRV_SHIFT(p_instance_ctrl->p_cfg->page_size_bytes << R_OSPI_DWSCTSR_CTSN0_Pos, p_instance_ctrl->channel)); /* Setup SPI protocol specific registers */ @@ -312,6 +313,7 @@ fsp_err_t R_OSPI_XipExit (spi_flash_ctrl_t * p_ctrl) * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. * @retval FSP_ERR_NOT_OPEN Driver is not opened. * @retval FSP_ERR_DEVICE_BUSY Another Write/Erase transaction is in progress. + * @retval FSP_ERR_INVALID_SIZE Write operation crosses page-boundary. **********************************************************************************************************************/ fsp_err_t R_OSPI_Write (spi_flash_ctrl_t * p_ctrl, uint8_t const * const p_src, @@ -323,9 +325,13 @@ fsp_err_t R_OSPI_Write (spi_flash_ctrl_t * p_ctrl, FSP_ASSERT(NULL != p_instance_ctrl); FSP_ASSERT(NULL != p_src); FSP_ASSERT(NULL != p_dest); - FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ASSERT(OSPI_PRV_PAGE_SIZE_BYTES >= byte_count); FSP_ASSERT(0 != byte_count); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check that space remaining in page is sufficient for requested write size */ + uint32_t page_size = p_instance_ctrl->p_cfg->page_size_bytes; + uint32_t page_offset = (uint32_t) p_dest & (page_size - 1); + FSP_ERROR_RETURN((page_size - page_offset) >= byte_count, FSP_ERR_INVALID_SIZE); #endif FSP_ERROR_RETURN(false == r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_status_bit), diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c index 16055b858..c786250f9 100644 --- a/ra/fsp/src/r_rtc/r_rtc.c +++ b/ra/fsp/src/r_rtc/r_rtc.c @@ -1360,7 +1360,7 @@ void rtc_alarm_periodic_isr (void) rtc_instance_ctrl_t * p_ctrl = (rtc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); /* Call the callback routine if one is available */ - if (NULL != p_ctrl->p_cfg->p_callback) + if (NULL != p_ctrl->p_callback) { /* Set data to identify callback to user, then call user callback. */ rtc_event_t event; diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c index c0f018d20..d12ba57fc 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c @@ -25,7 +25,7 @@ fsp_err_t HW_SCE_SHA256_UpdateHash (const uint32_t * p_source, uint32_t num_word { uint32_t out_data[8] = {0}; fsp_err_t err = HW_SCE_Sha224256GenerateMessageDigestSub(p_digest, p_source, num_words, out_data); - memcpy(p_digest, out_data, (4U * num_words)); + memcpy(p_digest, out_data, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); return err; } diff --git a/ra/fsp/src/r_sdhi/r_sdhi_private.h b/ra/fsp/src/r_sdhi/r_sdhi_private.h index c43400c6b..6b4f714d5 100644 --- a/ra/fsp/src/r_sdhi/r_sdhi_private.h +++ b/ra/fsp/src/r_sdhi/r_sdhi_private.h @@ -101,7 +101,7 @@ FSP_HEADER /* Commands */ #define SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE (3U) -#define SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT (1U) +#define SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT (2U) #define SDHI_PRV_EMMC_HIGH_SPEED_MODE (((SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE << 24U) | \ (SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET << 16U)) | \ (SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT << 8U)) diff --git a/ra/fsp/src/r_spi/r_spi.c b/ra/fsp/src/r_spi/r_spi.c index 174aabd6a..4c3d5ec85 100644 --- a/ra/fsp/src/r_spi/r_spi.c +++ b/ra/fsp/src/r_spi/r_spi.c @@ -201,7 +201,7 @@ fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) FSP_ERROR_RETURN(SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase, FSP_ERR_UNSUPPORTED); } - #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 || BSP_FEATURE_SPI_HAS_BYTE_SWAP == 0 || SPI_TRANSMIT_FROM_RXI_ISR == 1 + #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 || SPI_TRANSMIT_FROM_RXI_ISR == 1 spi_extended_cfg_t * p_extend = (spi_extended_cfg_t *) p_cfg->p_extend; #endif #if SPI_TRANSMIT_FROM_RXI_ISR == 1 @@ -217,9 +217,6 @@ fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) } #endif - #if BSP_FEATURE_SPI_HAS_BYTE_SWAP == 0 - FSP_ERROR_RETURN(SPI_BYTE_SWAP_DISABLE == p_extend->byte_swap, FSP_ERR_UNSUPPORTED); - #endif #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 if ((SPI_MODE_MASTER == p_cfg->operating_mode)) { diff --git a/ra/fsp/src/r_usb_basic/r_usb_basic.c b/ra/fsp/src/r_usb_basic/r_usb_basic.c index 167d6d39a..b12bad0cb 100644 --- a/ra/fsp/src/r_usb_basic/r_usb_basic.c +++ b/ra/fsp/src/r_usb_basic/r_usb_basic.c @@ -257,12 +257,12 @@ fsp_err_t R_USB_EventGet (usb_ctrl_t * const p_api_ctrl, usb_status_t * event) g_usb_cstd_event.read_pointer = 0; } } - #else /* (BSP_CFG_RTOS == 0) */ FSP_PARAMETER_NOT_USED(p_api_ctrl); FSP_PARAMETER_NOT_USED(*event); result = FSP_ERR_USB_FAILED; #endif /* (BSP_CFG_RTOS == 0) */ + return result; } /* End of function R_USB_EventGet() */ @@ -291,6 +291,7 @@ fsp_err_t R_USB_Callback (usb_callback_t * p_callback) FSP_PARAMETER_NOT_USED(*p_callback); err = FSP_ERR_USB_FAILED; #endif /* (BSP_CFG_RTOS == 2) */ + return err; } /* End of function R_USB_Callback() */ @@ -339,7 +340,6 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c #endif #if USB_CFG_PARAM_CHECKING_ENABLE - /* Argument Checking */ FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) @@ -369,7 +369,6 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c { FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) } - #else /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ @@ -450,7 +449,6 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c if (USB_MODE_HOST == p_cfg->usb_mode) { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - /* Be sure set USB_MODE_HOST to g_usb_usbmode variable before calling usb_rtos_configuration function. */ g_usb_usbmode[p_ctrl->module_number] = USB_MODE_HOST; #endif @@ -458,7 +456,6 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c else { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - /* Be sure set USB_MODE_PERI to g_usb_usbmode variable before calling usb_rtos_configuration function. */ g_usb_usbmode[p_ctrl->module_number] = USB_MODE_PERI; #endif @@ -475,7 +472,6 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c return FSP_ERR_USB_FAILED; } } - #else /* (USB_NUM_USBIP == 2) */ os_err = usb_rtos_configuration(p_cfg->usb_mode); if (UsbRtos_Success != os_err) @@ -754,7 +750,6 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) { usb_rtos_delete(p_ctrl->module_number); } - #else /* (USB_NUM_USBIP == 2) */ usb_rtos_delete(p_ctrl->module_number); #endif /* (USB_NUM_USBIP == 2) */ @@ -896,7 +891,7 @@ fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t s * Set the device class type in usb_ctrl_t structure member (type). * Confirm after data write is completed by checking the return value (USB_STATUS_WRITE_COMPLETE) * of the R_USB_GetEvent function. - * To request the transmission of a NULL packet, assign USB_NULL(0) to the third argument (size). + * For sending a zero-length packet, please refer the following Note. * * 2. Control data transfer * @@ -909,9 +904,13 @@ fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t s * USB device with same device address. * @retval FSP_ERR_ASSERTION Parameter is NULL error. * @retval FSP_ERR_USB_PARAMETER Parameter error. - * @note Do not call this API in the following function. - * @note (1). Interrupt function. - * @note (2). Callback function ( for RTOS ). + * @note 1.The user needs to send the zero-length packet(ZLP) since this USB driver does not send the ZLP automatically. + * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_Write function as follow. + * @note e.g) + * @note R_USB_Write (&g_basic0_ctrl, &g_buf, USB_NULL); + * @note 2.Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). ******************************************************************************/ fsp_err_t R_USB_Write (usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination) { @@ -1171,7 +1170,6 @@ fsp_err_t R_USB_Suspend (usb_ctrl_t * const p_api_ctrl) { ret_code = FSP_ERR_USB_FAILED; } - #else /* (BSP_CFG_RTOS == 0) */ if (USB_YES == gs_usb_suspend_ing[p_ctrl->module_number]) { @@ -1271,7 +1269,6 @@ fsp_err_t R_USB_Resume (usb_ctrl_t * const p_api_ctrl) { ret_code = FSP_ERR_USB_FAILED; } - #else /* (BSP_CFG_RTOS == 0) */ if (USB_YES == g_usb_resume_ing[p_ctrl->module_number]) { @@ -1298,6 +1295,7 @@ fsp_err_t R_USB_Resume (usb_ctrl_t * const p_api_ctrl) g_usb_resume_ing[p_ctrl->module_number] = USB_NO; #endif /* (BSP_CFG_RTOS == 0) */ #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + return ret_code; #endif /* USB_CFG_MODE == USB_CFG_PERI */ } @@ -1545,7 +1543,6 @@ fsp_err_t R_USB_InfoGet (usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uin { p_info->bcport = USB_BCPORT_SDP; /* USB_SDP/USB_CDP/USB_DCP */ } - #else /* #if USB_CFG_BC == USB_CFG_ENABLE */ p_info->bcport = USB_BCPORT_SDP; /* USB_SDP/USB_CDP/USB_DCP */ #endif /* #if USB_CFG_BC == USB_CFG_ENABLE */ @@ -1824,16 +1821,20 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 * The write data is stored in the area specified in the argument (p_buf). * After data write is completed, confirm the operation with the return value * (USB_STATUS_WRITE_COMPLETE) of the EventGet function. - * To request the transmission of a NULL packet, assign USB_NULL (0) to the third argument (size). + * For sending a zero-length packet, please refer the following Note. * * @retval FSP_SUCCESS Successfully completed. * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. * @retval FSP_ERR_ASSERTION Parameter is NULL error. * @retval FSP_ERR_USB_PARAMETER Parameter error. - * @note Do not call this API in the following function. - * @note (1). Interrupt function. - * @note (2). Callback function ( for RTOS ). + * @note 1.The user needs to send the zero-length packet(ZLP) since this USB driver does not send the ZLP automatically. + * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_PipeWrite function as follow. + * @note e.g) + * @note R_USB_PipeWrite (&g_basic0_ctrl, &g_buf, USB_NULL, pipe_number); + * @note 2.Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). ******************************************************************************/ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number) { @@ -1862,7 +1863,6 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 p_ctrl->pipe = pipe_number; #if USB_CFG_PARAM_CHECKING_ENABLE - /* Argument Checking */ FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) @@ -2038,7 +2038,6 @@ fsp_err_t R_USB_PipeStop (usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number) p_ctrl->pipe = pipe_number; #if USB_CFG_PARAM_CHECKING_ENABLE - /* Argument Checking */ FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) @@ -2193,7 +2192,6 @@ fsp_err_t R_USB_PipeInfoGet (usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, p_ctrl->pipe = pipe_number; #if USB_CFG_PARAM_CHECKING_ENABLE - /* Argument Checking */ FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) @@ -2260,7 +2258,6 @@ fsp_err_t R_USB_PipeInfoGet (usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, else { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - /* Get PIPE Number from Endpoint address */ p_info->endpoint = (uint8_t) (g_usb_pipe_table[p_ctrl->module_number][p_ctrl->pipe].pipe_cfg & USB_EPNUMFIELD); /* Set EP num. */ if (USB_DIR_P_IN == (g_usb_pipe_table[p_ctrl->module_number][p_ctrl->pipe].pipe_cfg & USB_DIRFIELD)) /* Check dir */ @@ -2363,8 +2360,9 @@ fsp_err_t R_USB_HostControlTransfer (usb_ctrl_t * const p_api_ctrl, { usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; - usb_er_t err = USB_ERROR; - fsp_err_t result = FSP_ERR_USB_FAILED; + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) @@ -2375,6 +2373,19 @@ fsp_err_t R_USB_HostControlTransfer (usb_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(USB_MAXDEVADDR >= device_address, FSP_ERR_USB_PARAMETER) #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS == result) + { + if (USB_STATUS_CONFIGURED != info.device_status) + { + return FSP_ERR_USB_FAILED; + } + } + else + { + return FSP_ERR_USB_FAILED; + } + p_ctrl->device_address = device_address; p_ctrl->setup.request_type = p_setup->request_type; p_ctrl->setup.request_value = p_setup->request_value; @@ -2413,6 +2424,7 @@ fsp_err_t R_USB_HostControlTransfer (usb_ctrl_t * const p_api_ctrl, * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. * @retval FSP_ERR_ASSERTION Parameter is NULL error. * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_PARAMETER Parameter error. * @note Do not call this API in the following function. * @note (1). Interrupt function. * @note (2). Callback function ( for RTOS ). @@ -2421,13 +2433,27 @@ fsp_err_t R_USB_PeriControlDataGet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_b { usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; - usb_er_t err = USB_ERROR; - fsp_err_t result = FSP_ERR_USB_FAILED; + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) FSP_ASSERT(p_buf) -#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS == result) + { + if (USB_STATUS_CONFIGURED != info.device_status) + { + return FSP_ERR_USB_FAILED; + } + } + else + { + return FSP_ERR_USB_FAILED; + } err = usb_ctrl_read(p_ctrl, p_buf, size); /* Request Control transfer */ if (err == USB_QOVR) @@ -2453,6 +2479,7 @@ fsp_err_t R_USB_PeriControlDataGet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_b * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. * @retval FSP_ERR_ASSERTION Parameter is NULL error. * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_PARAMETER Parameter error. * @note Do not call this API in the following function. * @note (1). Interrupt function. * @note (2). Callback function ( for RTOS ). @@ -2461,13 +2488,27 @@ fsp_err_t R_USB_PeriControlDataSet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_b { usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; - usb_er_t err = USB_ERROR; - fsp_err_t result = FSP_ERR_USB_FAILED; + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) FSP_ASSERT(p_buf) -#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS == result) + { + if (USB_STATUS_CONFIGURED != info.device_status) + { + return FSP_ERR_USB_FAILED; + } + } + else + { + return FSP_ERR_USB_FAILED; + } err = usb_ctrl_write(p_ctrl, p_buf, size); /* Request Control transfer */ if (err == USB_QOVR) @@ -2492,6 +2533,7 @@ fsp_err_t R_USB_PeriControlDataSet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_b * @retval FSP_SUCCESS Successful completion. * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. * @note Do not call this API in the following function. * @note (1). Interrupt function. * @note (2). Callback function ( for RTOS ). @@ -2506,9 +2548,25 @@ fsp_err_t R_USB_PeriControlStatusSet (usb_ctrl_t * const p_api_ctrl, usb_setup_s return FSP_ERR_USB_FAILED; #else /* USB_CFG_MODE == USB_CFG_HOST */ + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; + #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) - #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS == result) + { + if (USB_STATUS_CONFIGURED != info.device_status) + { + return FSP_ERR_USB_FAILED; + } + } + else + { + return FSP_ERR_USB_FAILED; + } p_ctrl->status = (uint16_t) status; @@ -2567,7 +2625,6 @@ fsp_err_t R_USB_RemoteWakeup (usb_ctrl_t * const p_api_ctrl) break; } } - #else /* (BSP_CFG_RTOS == 0) */ if (USB_YES == g_usb_resume_ing[p_ctrl->module_number]) { diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c index 7e6864db0..9eec4915f 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c @@ -56,26 +56,20 @@ ******************************************************************************/ /** Declare a task handler for the created tasks. **/ - #if (USB_UT_MODE == 0) - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) static TaskHandle_t g_hcd_tsk_hdl; static TaskHandle_t g_mgr_tsk_hdl; - #if USB_CFG_HUB == USB_CFG_ENABLE + #if USB_CFG_HUB == USB_CFG_ENABLE static TaskHandle_t g_hub_tsk_hdl; - #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ - #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ - #endif /* #if (USB_UT_MODE == 0) */ + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - #if (USB_UT_MODE == 0) static TaskHandle_t g_pcd_tsk_hdl; - #endif #endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ #if defined(USB_CFG_PMSC_USE) - #if (USB_UT_MODE == 0) static TaskHandle_t g_pmsc_tsk_hdl; - #endif /* (USB_UT_MODE == 0) */ #endif /* defined(USB_CFG_PMSC_USE) */ #if defined(USB_CFG_HMSC_USE) @@ -124,24 +118,22 @@ static QueueHandle_t g_hcdc_mpl_hdl; static QueueHandle_t g_hhid_mpl_hdl; static QueueHandle_t g_pmsc_mpl_hdl; - #if (USB_UT_MODE == 0) - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) static void * g_p_hcd_mpl[QUEUE_SIZE]; static void * g_p_mgr_mpl[QUEUE_SIZE]; static void * g_p_hub_mpl[QUEUE_SIZE]; static void * g_p_cls_mpl[QUEUE_SIZE]; - #if defined(USB_CFG_HMSC_USE) + #if defined(USB_CFG_HMSC_USE) static void * g_p_hmsc_mpl[QUEUE_SIZE]; static void * g_p_hmsc_req_mpl[QUEUE_SIZE]; - #endif /* defined(USB_CFG_HMSC_USE) */ - #if defined(USB_CFG_HCDC_USE) + #endif /* defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HCDC_USE) static void * g_p_hcdc_mpl[QUEUE_SIZE]; - #endif /* defined(USB_CFG_HCDC_USE) */ - #if defined(USB_CFG_HHID_USE) + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) static void * g_p_hhid_mpl[QUEUE_SIZE]; - #endif /* defined(USB_CFG_HHID_USE) */ - #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ - #endif /* (USB_UT_MODE == 0) */ + #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ /** Declare an array of memory pool handlers. **/ QueueHandle_t * g_mpl_table[] = @@ -159,8 +151,6 @@ QueueHandle_t * g_mpl_table[] = &g_pmsc_mpl_hdl, /* A memory pool handler of USB PMSC task */ }; - #if (USB_UT_MODE == 0) - /****************************************************************************** * Function Name: usb_rtos_configuration * Description : Create mailboxes, memory pool using for the created tasks @@ -183,7 +173,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (USB_MODE_HOST == usb_mode) { - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) uint16_t i; void * tmptr = NULL; @@ -224,7 +214,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #if defined(USB_CFG_HMSC_USE) + #if defined(USB_CFG_HMSC_USE) vSemaphoreCreateBinary(SemaphoreHandleRead); /** USB Host MSC **/ @@ -244,9 +234,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_HMSC_USE) */ - #if defined(USB_CFG_HCDC_USE) + #if defined(USB_CFG_HCDC_USE) /** USB Host CDC **/ g_hcdc_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); @@ -256,9 +246,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* defined(USB_CFG_HCDC_USE) */ + #endif /* defined(USB_CFG_HCDC_USE) */ - #if defined(USB_CFG_HHID_USE) + #if defined(USB_CFG_HHID_USE) /** USB Host HID **/ g_hhid_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); @@ -268,7 +258,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* defined(USB_CFG_HHID_USE) */ /** Create memory pool using for each task **/ /** USB HCD task **/ @@ -282,16 +272,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_hcd_mpl[i] = tmptr; - xQueueSend(g_hcd_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_hcd_mpl[i] = tmptr; + xQueueSend(g_hcd_mpl_hdl, &tmptr, 0); } } else @@ -317,16 +303,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_mgr_mpl[i] = tmptr; - xQueueSend(g_mgr_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_mgr_mpl[i] = tmptr; + xQueueSend(g_mgr_mpl_hdl, &tmptr, 0); } } else @@ -352,16 +334,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_hub_mpl[i] = tmptr; - xQueueSend(g_hub_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_hub_mpl[i] = tmptr; + xQueueSend(g_hub_mpl_hdl, &tmptr, 0); } } else @@ -387,16 +365,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_cls_mpl[i] = tmptr; - xQueueSend(g_cls_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_cls_mpl[i] = tmptr; + xQueueSend(g_cls_mpl_hdl, &tmptr, 0); } } else @@ -411,7 +385,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #if defined(USB_CFG_HMSC_USE) + #if defined(USB_CFG_HMSC_USE) /** USB Host MSC **/ g_hmsc_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); @@ -424,16 +398,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_hmsc_mpl[i] = tmptr; - xQueueSend(g_hmsc_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_hmsc_mpl[i] = tmptr; + xQueueSend(g_hmsc_mpl_hdl, &tmptr, 0); } } else @@ -459,16 +429,12 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) if (NULL == tmptr) { err = UsbRtos_Err_Init_Mpl; + + return err; } - else if (UsbRtos_Success == err) - { - g_p_hmsc_req_mpl[i] = tmptr; - xQueueSend(g_hmsc_req_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_hmsc_req_mpl[i] = tmptr; + xQueueSend(g_hmsc_req_mpl_hdl, &tmptr, 0); } } else @@ -482,9 +448,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) { return err; } - #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_HMSC_USE) */ - #if defined(USB_CFG_HCDC_USE) + #if defined(USB_CFG_HCDC_USE) /** USB Host CDC **/ g_hcdc_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); @@ -500,15 +466,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - else if (UsbRtos_Success == err) - { - g_p_hcdc_mpl[i] = tmptr; - xQueueSend(g_hcdc_mpl_hdl, &tmptr, 0); - } - else - { - /* None */ - } + + g_p_hcdc_mpl[i] = tmptr; + xQueueSend(g_hcdc_mpl_hdl, &tmptr, 0); } } else @@ -522,9 +482,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) { return err; } - #endif /* defined(USB_CFG_HCDC_USE) */ + #endif /* defined(USB_CFG_HCDC_USE) */ - #if defined(USB_CFG_HHID_USE) + #if defined(USB_CFG_HHID_USE) /** USB Host HID **/ g_hhid_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); @@ -540,11 +500,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - else - { - g_p_hhid_mpl[i] = tmptr; - xQueueSend(g_hhid_mpl_hdl, &tmptr, 0); - } + + g_p_hhid_mpl[i] = tmptr; + xQueueSend(g_hhid_mpl_hdl, &tmptr, 0); } } else @@ -553,7 +511,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* defined(USB_CFG_HHID_USE) */ /** USB Tasks Creation **/ ret = xTaskCreate((TaskFunction_t) usb_hstd_hcd_task, /** Entry function of USB HCD task **/ @@ -569,7 +527,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #if USB_CFG_HUB == USB_CFG_ENABLE + #if USB_CFG_HUB == USB_CFG_ENABLE ret = xTaskCreate((TaskFunction_t) usb_hhub_task, /** Entry function of USB HUB task **/ "HUB_TSK", /** Name of USB HUB task **/ HUB_STACK_SIZE, /** Stack size in words **/ @@ -582,7 +540,7 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ ret = xTaskCreate((TaskFunction_t) usb_hstd_mgr_task, /** Entry function of USB MGR task **/ "MGR_TSK", /** Name of USB MGR task **/ @@ -596,11 +554,11 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ } else { - #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) /** Create mailbox **/ /** USB PCD task **/ @@ -625,9 +583,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ - #if defined(USB_CFG_PMSC_USE) + #if defined(USB_CFG_PMSC_USE) /** Create mailbox **/ /** USB PMSC task **/ @@ -652,13 +610,13 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) return err; } - #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /* defined(USB_CFG_PMSC_USE) */ } - #if (USB_NUM_USBIP == 2) + #if (USB_NUM_USBIP == 2) if ((g_usb_usbmode[0] == 0) || (g_usb_usbmode[1] == 0)) { - #endif /* (USB_NUM_USBIP == 2) */ + #endif /* (USB_NUM_USBIP == 2) */ /* WAIT_LOOP */ for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) { @@ -688,9 +646,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode) } } - #if (USB_NUM_USBIP == 2) + #if (USB_NUM_USBIP == 2) } - #endif /* (USB_NUM_USBIP == 2) */ + #endif /* (USB_NUM_USBIP == 2) */ return err; } /* End of function usb_rtos_configuration() */ @@ -712,13 +670,13 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) uint16_t ip_loop; uint16_t pipe_loop; uint16_t addr_loop; - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) uint16_t i; - #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ if (USB_MODE_HOST == g_usb_usbmode[module_number]) { - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) /** Create mailbox for each task. **/ /** USB HCD task **/ @@ -733,7 +691,7 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) /** USB Internal Communication mailbox **/ vQueueDelete(g_cls_mbx_hdl); - #if defined(USB_CFG_HMSC_USE) + #if defined(USB_CFG_HMSC_USE) vSemaphoreDelete(SemaphoreHandleRead); /** USB Host MSC **/ @@ -741,19 +699,19 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) /** USB Host MSC (for class request) **/ vQueueDelete(g_hmsc_req_mbx_hdl); - #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_HMSC_USE) */ - #if defined(USB_CFG_HCDC_USE) + #if defined(USB_CFG_HCDC_USE) /** USB Host CDC **/ vQueueDelete(g_hcdc_mbx_hdl); - #endif /* defined(USB_CFG_HCDC_USE) */ + #endif /* defined(USB_CFG_HCDC_USE) */ - #if defined(USB_CFG_HHID_USE) + #if defined(USB_CFG_HHID_USE) /** USB Host HID **/ vQueueDelete(g_hhid_mbx_hdl); - #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* defined(USB_CFG_HHID_USE) */ /** Create memory pool using for each task **/ /** USB HCD task **/ @@ -784,7 +742,7 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) vPortFree(g_p_cls_mpl[i]); } - #if defined(USB_CFG_HMSC_USE) + #if defined(USB_CFG_HMSC_USE) /** USB Host MSC **/ vQueueDelete(g_hmsc_mpl_hdl); @@ -799,9 +757,9 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) { vPortFree(g_p_hmsc_req_mpl[i]); } - #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_HMSC_USE) */ - #if defined(USB_CFG_HCDC_USE) + #if defined(USB_CFG_HCDC_USE) /** USB Host CDC **/ vQueueDelete(g_hcdc_mpl_hdl); @@ -809,9 +767,9 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) { vPortFree(g_p_hcdc_mpl[i]); } - #endif /* defined(USB_CFG_HCDC_USE) */ + #endif /* defined(USB_CFG_HCDC_USE) */ - #if defined(USB_CFG_HHID_USE) + #if defined(USB_CFG_HHID_USE) /** USB Host HID **/ vQueueDelete(g_hhid_mpl_hdl); @@ -819,20 +777,20 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) { vPortFree(g_p_hhid_mpl[i]); } - #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* defined(USB_CFG_HHID_USE) */ /** USB Tasks Creation **/ vTaskDelete(g_hcd_tsk_hdl); - #if USB_CFG_HUB == USB_CFG_ENABLE + #if USB_CFG_HUB == USB_CFG_ENABLE vTaskDelete(g_hub_tsk_hdl); - #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ vTaskDelete(g_mgr_tsk_hdl); - #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ } else { - #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) /** USB Tasks Creation **/ vTaskDelete(g_pcd_tsk_hdl); @@ -841,7 +799,7 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) /** USB PCD task **/ vQueueDelete(g_pcd_mbx_hdl); - #if defined(USB_CFG_PMSC_USE) + #if defined(USB_CFG_PMSC_USE) /** USB Tasks Creation **/ vTaskDelete(g_pmsc_tsk_hdl); @@ -849,14 +807,14 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) /** Create mailbox **/ /** USB PMSC task **/ vQueueDelete(g_pmsc_mbx_hdl); - #endif /* defined(USB_CFG_PMSC_USE) */ - #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ } - #if (USB_NUM_USBIP == 2) + #if (USB_NUM_USBIP == 2) if ((g_usb_usbmode[0] == 0) || (g_usb_usbmode[1] == 0)) { - #endif /* (USB_NUM_USBIP == 2) */ + #endif /* (USB_NUM_USBIP == 2) */ /* WAIT_LOOP */ for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) { @@ -874,14 +832,12 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number) } } - #if (USB_NUM_USBIP == 2) + #if (USB_NUM_USBIP == 2) } - #endif /* (USB_NUM_USBIP == 2) */ + #endif /* (USB_NUM_USBIP == 2) */ return err; } /* End of function usb_rtos_delete() */ - #endif /* #if (USB_UT_MODE == 0) */ - /****************************************************************************** * Function Name : usb_cstd_rec_msg * Description : Receive a message to the specified id (mailbox). diff --git a/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c b/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c new file mode 100644 index 000000000..a85203304 --- /dev/null +++ b/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c @@ -0,0 +1,599 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +#include "r_spi_flash_api.h" +#include "rm_block_media_api.h" +#include "rm_block_media_spi.h" +#include "rm_block_media_spi_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "SPI" in ASCII, used to identify general RM_BLOCK_MEDIA_SPI control block */ +#define RM_BLOCK_MEDIA_SPI_OPEN (0x51535049U) +#define SPI_BANK_SIZE (64UL * 1024UL * 1024UL) + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/* Block Media SPI function pointers */ +const rm_block_media_api_t g_rm_block_media_on_spi = +{ + .open = RM_BLOCK_MEDIA_SPI_Open, + .mediaInit = RM_BLOCK_MEDIA_SPI_MediaInit, + .read = RM_BLOCK_MEDIA_SPI_Read, + .write = RM_BLOCK_MEDIA_SPI_Write, + .erase = RM_BLOCK_MEDIA_SPI_Erase, + .callbackSet = RM_BLOCK_MEDIA_SPI_CallbackSet, + .statusGet = RM_BLOCK_MEDIA_SPI_StatusGet, + .infoGet = RM_BLOCK_MEDIA_SPI_InfoGet, + .close = RM_BLOCK_MEDIA_SPI_Close, + .versionGet = RM_BLOCK_MEDIA_SPI_VersionGet +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Version data structure used by error logger macro. -- DEPRECATED */ +static const fsp_version_t g_block_media_spi_version = +{ + .api_version_minor = RM_BLOCK_MEDIA_API_VERSION_MINOR, + .api_version_major = RM_BLOCK_MEDIA_API_VERSION_MAJOR, + .code_version_major = RM_BLOCK_MEDIA_SPI_CODE_VERSION_MAJOR, + .code_version_minor = RM_BLOCK_MEDIA_SPI_CODE_VERSION_MINOR +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t rm_block_media_spi_program(rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + uint8_t * p_device_address, + uint8_t const * p_buffer, + uint32_t const num_blocks); + +static fsp_err_t rm_block_media_spi_rom_read(rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + uint8_t * const p_dest, + uint32_t const start_block, + uint32_t const num_blocks); + +static void rm_block_media_call_callback(rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + rm_block_media_event_t event); + +/*******************************************************************************************************************//** + * @addtogroup RM_BLOCK_MEDIA_SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Parameter checking and Acquires mutex, then handles driver initialization at the HAL SPI layer and marking the + * open flag in control block. + * + * Implements @ref rm_block_media_api_t::open. + * + * @retval FSP_SUCCESS Block media for SPI framework is successfully opened. + * @retval FSP_ERR_ASSERTION One of the input parameters or their data references may be null. + * @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. See HAL driver for other possible causes. + * @return See @ref RENESAS_ERROR_CODES or HAL driver for other possible return codes or causes. + * This function calls + * * @ref spi_flash_api_t::open + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Open (rm_block_media_ctrl_t * const p_ctrl, rm_block_media_cfg_t const * const p_cfg) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != ((rm_block_media_spi_extended_cfg_t *) p_cfg->p_extend)->p_spi); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + rm_block_media_spi_extended_cfg_t * p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_cfg->p_extend; + spi_flash_instance_t * p_spi_flash = (spi_flash_instance_t *) p_extended_cfg->p_spi; + + /* Open the underlying driver. */ + fsp_err_t err = p_spi_flash->p_api->open(p_spi_flash->p_ctrl, p_spi_flash->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Populate the control structure */ + p_instance_ctrl->p_spi_flash = p_spi_flash; + p_instance_ctrl->p_cfg = p_cfg; + + /* Module is now open */ + p_instance_ctrl->open = RM_BLOCK_MEDIA_SPI_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Retrieves module information. + * + * Implements @ref rm_block_media_api_t::infoGet. + * + * @retval FSP_SUCCESS Erase operation requested. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_NOT_INITIALIZED Module has not been initialized. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_InfoGet (rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + p_info->num_sectors = p_extended_cfg->block_count_total; + p_info->sector_size_bytes = p_extended_cfg->block_size_bytes; + p_info->write_protected = false; + p_info->reentrant = false; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initializes the Block Media SPI Flash device. + * + * Implements @ref rm_block_media_api_t::mediaInit. + * + * @retval FSP_SUCCESS Module is initialized and ready to access the memory device. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_MediaInit (rm_block_media_ctrl_t * const p_ctrl) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->initialized = true; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Reads a number of blocks from spi flash memory. By default, this is a function is blocking. Non-blocking operation + * may be achieved by yielding control within the optional callback function. + * + * Implements @ref rm_block_media_api_t::read. + * + * @retval FSP_SUCCESS SPI data read successfully + * @retval FSP_ERR_ASSERTION p_ctrl or p_dest is NULL, or num_blocks is zero + * @retval FSP_ERR_NOT_OPEN Block Media SPI module is not yet open + * @retval FSP_ERR_INVALID_ADDRESS Invalid address range for read operation + * @retval FSP_ERR_NOT_INITIALIZED Block Media SPI module is not yet initialized + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Read (rm_block_media_ctrl_t * const p_ctrl, + uint8_t * const p_dest, + uint32_t const start_block, + uint32_t const num_blocks) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(num_blocks > 0U); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint32_t base_address = p_extended_cfg->base_address; + uint32_t block_size = p_extended_cfg->block_size_bytes; + uint32_t read_bytes_remain = num_blocks * block_size; + uint32_t rom_address = (base_address + (block_size * start_block)); + + /* Check if the address is within flash size */ + if ((rom_address + read_bytes_remain) > (p_extended_cfg->block_count_total * block_size) + base_address) + { + return FSP_ERR_INVALID_ADDRESS; + } +#endif + + fsp_err_t err = rm_block_media_spi_rom_read(p_instance_ctrl, p_dest, start_block, num_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * Implements @ref rm_block_media_api_t::statusGet. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * + * @return See @ref RENESAS_ERROR_CODES or HAL driver for other possible return codes or causes. + * This function calls + * * @ref spi_flash_api_t::statusGet + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_StatusGet (rm_block_media_ctrl_t * const p_ctrl, rm_block_media_status_t * const p_status) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Call the underlying driver. */ + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + spi_flash_instance_t * p_spi_flash; + + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + p_spi_flash = (spi_flash_instance_t *) p_extended_cfg->p_spi; + + spi_flash_status_t status; + fsp_err_t err = p_spi_flash->p_api->statusGet(p_spi_flash->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + bool spi_driver_busy = status.write_in_progress; + bool block_driver_busy = p_instance_ctrl->read_in_progress || p_instance_ctrl->write_in_progress || + p_instance_ctrl->erase_in_progress; + + p_status->media_inserted = true; + p_status->initialized = p_instance_ctrl->initialized; + p_status->busy = spi_driver_busy || block_driver_busy; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Writes provided data to a number of blocks of spi flash memory. By default, this is a function is blocking. + * Non-blocking operation may be achieved by yielding control within the optional callback function. + * + * Implements @ref rm_block_media_api_t::write. + * + * @retval FSP_SUCCESS Flash write finished successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_src is NULL. Or num_blocks is zero. + * @retval FSP_ERR_NOT_OPEN Block media SPI Framework module is not yet initialized. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address range + * @retval FSP_ERR_NOT_INITIALIZED Block Media SPI module is not yet initialized + * + * @return See @ref RENESAS_ERROR_CODES or HAL driver for other possible return codes or causes. + * This function calls + * * @ref spi_flash_api_t::write + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Write (rm_block_media_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const start_block, + uint32_t const num_blocks) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(num_blocks > 0U); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Calculate the address of flash */ + ; + uint32_t base_address = p_extended_cfg->base_address; + uint32_t rom_address = base_address + (p_extended_cfg->block_size_bytes * start_block); + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + + /* Check if the address of flash is within flash size*/ + if (((rom_address + (num_blocks * p_extended_cfg->block_size_bytes))) > + ((p_extended_cfg->block_count_total * p_extended_cfg->block_size_bytes) + base_address)) + { + return FSP_ERR_INVALID_ADDRESS; + } +#endif + + fsp_err_t err = FSP_SUCCESS; + err = RM_BLOCK_MEDIA_SPI_Erase(p_instance_ctrl, start_block, num_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Write data into the block media SPI flash */ + err = rm_block_media_spi_program(p_instance_ctrl, (uint8_t *) rom_address, p_src, num_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. API not supported. + * + * Implements @ref rm_block_media_api_t::callbackSet. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by RM_BLOCK_MEDIA_SPI. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_CallbackSet (rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); + + return FSP_ERR_UNSUPPORTED; +} + +/******************************************************************************************************************//** + * Closes the Block Media SPI device. Implements @ref rm_block_media_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION One of the following parameters may be null: p_ctrl. + * @retval FSP_ERR_NOT_OPEN Block media SPI Framework module is not yet initialized. + * @return See @ref RENESAS_ERROR_CODES or HAL driver for other possible return codes or causes. + * This function calls + * * @ref spi_flash_api_t::close + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Close (rm_block_media_ctrl_t * const p_ctrl) +{ + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Call lower level API. The error code is not checked here, since module close functions should never fail */ + p_instance_ctrl->p_spi_flash->p_api->close(p_instance_ctrl->p_spi_flash->p_ctrl); + p_instance_ctrl->open = 0U; + p_instance_ctrl->initialized = 0U; + + return FSP_SUCCESS; +} + +/********************************************************************************************************************** + * DEPRECATED Provides API and code version in the user provided pointer. Implements @ref rm_block_media_api_t::versionGet. + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION Null Pointer. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_VersionGet (fsp_version_t * const p_version) +{ +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_version); +#endif + + p_version->version_id = g_block_media_spi_version.version_id; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function erases blocks of the SPI device. By default, this is a function is blocking. Non-blocking operation + * may be achieved by yielding control within the optional callback function. + * + * Implements @ref rm_block_media_api_t::erase. + * + * @retval FSP_SUCCESS Erase operation requested. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_NOT_INITIALIZED Module has not been initialized. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address range + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + * This function calls: + * * @ref spi_flash_api_t::erase + * * @ref spi_flash_api_t::statusGet + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SPI_Erase (rm_block_media_ctrl_t * const p_ctrl, + uint32_t const start_block, + uint32_t const num_blocks) +{ + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + spi_flash_instance_t * p_spi_flash; + uint8_t * rom_address; + + rm_block_media_spi_instance_ctrl_t * p_instance_ctrl = (rm_block_media_spi_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SPI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint32_t block_size = p_extended_cfg->block_size_bytes; + +#if RM_BLOCK_MEDIA_SPI_CFG_PARAM_CHECKING_ENABLE + + /* Confirm start and end blocks are within range */ + uint32_t block_count = p_extended_cfg->block_count_total; + FSP_ERROR_RETURN((block_size * block_count) >= (block_size * (start_block + num_blocks)), FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + p_spi_flash = (spi_flash_instance_t *) p_extended_cfg->p_spi; + rom_address = (uint8_t *) p_extended_cfg->base_address + (start_block * block_size); + + /* Erase the blocks, one at a time */ + fsp_err_t err = FSP_SUCCESS; + uint32_t iteration = num_blocks; + spi_flash_status_t status; + p_instance_ctrl->erase_in_progress = true; + while ((iteration > 0U) && (FSP_SUCCESS == err)) + { + err = p_spi_flash->p_api->erase(p_spi_flash->p_ctrl, rom_address, block_size); + FSP_ERROR_LOG(err); + + /* Wait until operation is in complete */ + while ((FSP_SUCCESS == err) && + (FSP_SUCCESS == p_spi_flash->p_api->statusGet(p_spi_flash->p_ctrl, &status)) && + (true == status.write_in_progress)) + { + /* Notify application of erase in progress */ + rm_block_media_call_callback(p_instance_ctrl, RM_BLOCK_MEDIA_EVENT_POLL_STATUS); + } + + /* Calculate next block address */ + rom_address = rom_address + block_size; + iteration--; + } + + /* Notify appication of completion */ + p_instance_ctrl->erase_in_progress = false; + rm_block_media_event_t event = + (FSP_SUCCESS == err ? RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE : RM_BLOCK_MEDIA_EVENT_ERROR); + rm_block_media_call_callback(p_instance_ctrl, event); + + return err; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This is the subroutine for the RM_BLOCK_MEDIA_SPI_Write API. + * + * @retval FSP_SUCCESS No parameter error found + * @return See @ref RENESAS_ERROR_CODES or HAL driver for other possible return codes or causes. + * This function calls + * * @ref spi_flash_api_t::write + * * @ref spi_flash_api_t::statusGet + **********************************************************************************************************************/ +static fsp_err_t rm_block_media_spi_program (rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + uint8_t * p_device_address, + uint8_t const * p_buffer, + uint32_t const num_blocks) +{ + /* Instance and error data */ + fsp_err_t err = FSP_SUCCESS; + spi_flash_instance_t * p_spi_flash = p_instance_ctrl->p_spi_flash; + uint32_t page_size = p_spi_flash->p_cfg->page_size_bytes; + + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint32_t byte_req = num_blocks * (p_extended_cfg->block_size_bytes); + uint32_t iteration = byte_req / page_size; + spi_flash_status_t status; + + /* Write data into the block media SPI flash */ + p_instance_ctrl->write_in_progress = true; + while ((iteration > 0U) && (FSP_SUCCESS == err)) + { + err = p_spi_flash->p_api->write(p_spi_flash->p_ctrl, p_buffer, p_device_address, page_size); + FSP_ERROR_LOG(err); + + while ((FSP_SUCCESS == err) && + (FSP_SUCCESS == p_spi_flash->p_api->statusGet(p_spi_flash->p_ctrl, &status)) && + (true == status.write_in_progress)) + { + /* Notify application of read in progress */ + rm_block_media_call_callback(p_instance_ctrl, RM_BLOCK_MEDIA_EVENT_POLL_STATUS); + } + + p_device_address = p_device_address + page_size; + p_buffer = p_buffer + page_size; + iteration--; + } + + /* Notify appication of completion */ + p_instance_ctrl->write_in_progress = false; + rm_block_media_event_t event = + (FSP_SUCCESS == err ? RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE : RM_BLOCK_MEDIA_EVENT_ERROR); + rm_block_media_call_callback(p_instance_ctrl, event); + + return err; +} + +/*******************************************************************************************************************//** + * This is the subroutine for the RM_BLOCK_MEDIA_SPI_READ API to read data from banks using ROM area. + * + * @retval FSP_SUCCESS No parameter error found + **********************************************************************************************************************/ +static fsp_err_t rm_block_media_spi_rom_read (rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + uint8_t * const p_dest, + uint32_t const start_block, + uint32_t const num_blocks) +{ + /* Calculate read address and size */ + rm_block_media_spi_extended_cfg_t * p_extended_cfg; + p_extended_cfg = (rm_block_media_spi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint32_t block_size = p_extended_cfg->block_size_bytes; + uint32_t base_address = p_extended_cfg->base_address; + uint32_t read_bytes = num_blocks * block_size; + uint32_t rom_address = base_address + (block_size * start_block); + + /* Read data from block media SPI flash */ + p_instance_ctrl->read_in_progress = true; + memcpy(p_dest, (uint8_t *) rom_address, read_bytes); + + /* Notify appication of completion */ + p_instance_ctrl->read_in_progress = false; + rm_block_media_call_callback(p_instance_ctrl, RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This is the subroutine for validating and calling the application configured callback. + **********************************************************************************************************************/ +static void rm_block_media_call_callback (rm_block_media_spi_instance_ctrl_t * p_instance_ctrl, + rm_block_media_event_t event) +{ + void (* p_callback)(rm_block_media_callback_args_t *) = p_instance_ctrl->p_cfg->p_callback; + + if (NULL != p_callback) + { + rm_block_media_callback_args_t args = + { + .event = event, + .p_context = p_instance_ctrl->p_cfg->p_context + }; + + p_callback(&args); + } +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_BLOCK_MEDIA_SPI) + **********************************************************************************************************************/ diff --git a/ra/fsp/src/rm_emwin_port/LCDConf.c b/ra/fsp/src/rm_emwin_port/LCDConf.c index 8083cba32..08502efda 100644 --- a/ra/fsp/src/rm_emwin_port/LCDConf.c +++ b/ra/fsp/src/rm_emwin_port/LCDConf.c @@ -1048,23 +1048,55 @@ static int _DrawArcAA (int x0, int y0, int rx, int ry, long a0, long a1) d2_color Color; const GUI_RECT * pRect; uint16_t PenSize; + U32 Flag; GUI_USE_PARA(ry); - PenSize = GUI_GetPenSize(); - Mode = _GetD2Mode(); - while (a1 < a0) + + // + // If both angles are equal (e.g. 0 and 0 or 180 and 180) nothing has to be done + // + if (a0 == a1) + { + return 0; // Nothing to do, no angle - no arc + } + + if (a1 < a0) + { + return 0; // Nothing to do, emWin doesn't support this one + } + + // + // If the angles not equal, but meet at the same position + // we don't draw an arc but a circle instead. + // + if (a1 > (a0 + 360000)) { - a1 += 360000; + return _DrawCircleAA(x0, y0, rx); // a1 meets a0 after one round so we have a circle } - nx0 = GUI__SinHQ(a0); - ny0 = GUI__CosHQ(a0); + if ((a0 % 360000) == (a1 % 360000)) + { + return _DrawCircleAA(x0, y0, rx); // Both angles are at the same position but not equal, so we have a circle + } + + PenSize = GUI_GetPenSize(); + Mode = _GetD2Mode(); + + nx0 = -GUI__SinHQ(a0); + ny0 = -GUI__CosHQ(a0); nx1 = GUI__SinHQ(a1); ny1 = GUI__CosHQ(a1); - if ((a1 - a0) <= 180000) + + // + // If the difference between both is larger than 180 degrees we must use the concave flag + // + if (((a1 - a0) % 360000) <= 180000) + { + Flag = 0; + } + else { - nx0 *= -1; - ny0 *= -1; + Flag = d2_wf_concave; } // @@ -1090,7 +1122,7 @@ static int _DrawArcAA (int x0, int y0, int rx, int ry, long a0, long a1) ny0, nx1, ny1, - 0); + Flag); // // Execute render operations diff --git a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c index a4b6e246b..132d5002f 100644 --- a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c +++ b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c @@ -27,6 +27,8 @@ #if defined(MBEDTLS_PSA_CRYPTO_ACCEL_DRV_C) #include "asymmetric_vendor.h" +#if defined(MBEDTLS_ECP_C) + #if (defined(MBEDTLS_ECP_ALT)) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) /* Generate an ECP keypair in vendor defined format. */ @@ -127,4 +129,6 @@ psa_status_t psa_import_ec_private_key_vendor (psa_ecc_curve_t curve, #endif /* (defined(MBEDTLS_ECP_ALT)) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) */ +#endif /* MBEDTLS_ECP_C */ + #endif /* MBEDTLS_PSA_CRYPTO_ACCEL_DRV_C */ diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt.c b/ra/fsp/src/rm_psa_crypto/gcm_alt.c index 629c8cfe4..7126946c7 100644 --- a/ra/fsp/src/rm_psa_crypto/gcm_alt.c +++ b/ra/fsp/src/rm_psa_crypto/gcm_alt.c @@ -505,8 +505,6 @@ int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - unsigned char check_tag[16]; size_t i; int diff; @@ -517,24 +515,9 @@ int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, GCM_VALIDATE_RET( length == 0 || input != NULL ); GCM_VALIDATE_RET( length == 0 || output != NULL ); - if( ( ret = mbedtls_gcm_crypt_and_tag( ctx, MBEDTLS_GCM_DECRYPT, length, + return ( mbedtls_gcm_crypt_and_tag( ctx, MBEDTLS_GCM_DECRYPT, length, iv, iv_len, add, add_len, - input, output, tag_len, check_tag ) ) != 0 ) - { - return( ret ); - } - - /* Check tag in "constant-time" */ - for( diff = 0, i = 0; i < tag_len; i++ ) - diff |= tag[i] ^ check_tag[i]; - - if( diff != 0 ) - { - mbedtls_platform_zeroize( output, length ); - return( MBEDTLS_ERR_GCM_AUTH_FAILED ); - } - - return( 0 ); + input, output, tag_len, (unsigned char *)tag ) ); } void mbedtls_gcm_free( mbedtls_gcm_context *ctx ) diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c index 78b33ac6f..c3e76a0e6 100644 --- a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c @@ -344,14 +344,11 @@ int sce_gcm_crypt_and_tag (mbedtls_gcm_context * ctx, tag_bit_size[0] = change_endian_long(tag_len); /* Zero pad the tag if tag length is less than 16 bytes */ - memcpy(padded_tag, &input[length], tag_len); + memcpy(padded_tag, tag, tag_len); err = g_sce_aes_gcm_decrypt_final[key_len_idx]((uint32_t *) gcm_buffer, (uint32_t *) padded_tag, aad_bit_size, data_bit_size, tag_bit_size, (uint32_t *) &output[input_length]); - - /* tag buffer value is validated by the caller (mbedcrypto). Copy the tag from the input buffer */ - memcpy(tag, &input[length], tag_len); } } diff --git a/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h b/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h index 2a54a7ea5..bf8a98cf4 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h @@ -44,19 +44,18 @@ extern "C" { */ typedef struct mbedtls_sha256_context { - uint32_t total[2]; /*!< The number of Bytes processed. */ - uint32_t state[8]; /*!< The intermediate digest state. */ - unsigned char buffer[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES]; /*!< The data block being processed. */ - int is224; /*!< Determines which function to use: - 0: Use SHA-256, or 1: Use SHA-224. */ -} -mbedtls_sha256_context; - - + uint32_t total[2]; /*!< The number of Bytes processed. */ + uint32_t state[8]; /*!< The intermediate digest state. */ + unsigned char buffer[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES]; /*!< The data block being processed. */ + int is224; /*!< Determines which function to use: + * 0: Use SHA-256, or 1: Use SHA-224. */ +} mbedtls_sha256_context; +int mbedtls_internal_sha256_process_ext(mbedtls_sha256_context * ctx, + const unsigned char data[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES], uint32_t len); -#ifdef __cplusplus + #ifdef __cplusplus } -#endif + #endif -#endif /* mbedtls_sha256.h */ +#endif /* mbedtls_sha256.h */ diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c index 3ae0d6319..4d1501b78 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c @@ -390,12 +390,12 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, /* Write N into the buffer in reverse */ if (0 != mbedtls_mpi_write_binary(&ctx->N, (uint8_t *) p_calloc_temp_buff_N, ctx->len)) { - ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } /* Write D into the buffer in reverse */ else if (0 != mbedtls_mpi_write_binary(&ctx->D, (uint8_t *) p_calloc_temp_buff_D, private_key_size_bytes)) { - ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } else { diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt.c b/ra/fsp/src/rm_psa_crypto/sha256_alt.c index cfa5c2797..53d0a795a 100644 --- a/ra/fsp/src/rm_psa_crypto/sha256_alt.c +++ b/ra/fsp/src/rm_psa_crypto/sha256_alt.c @@ -21,6 +21,7 @@ * * This file is part of mbed TLS (https://tls.mbed.org) */ + /* * The SHA-256 Secure Hash Standard was published by NIST in 2002. * @@ -306,6 +307,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; + uint32_t sha256_block_aligned_size; SHA256_VALIDATE_RET( ctx != NULL ); SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); @@ -325,22 +327,21 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); - - if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + if( ( ret = mbedtls_internal_sha256_process_ext( ctx, ctx->buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0 ) return( ret ); input += fill; ilen -= fill; left = 0; } - - while( ilen >= 64 ) + if (ilen >= SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES) { - if( ( ret = mbedtls_internal_sha256_process( ctx, input ) ) != 0 ) + sha256_block_aligned_size = ilen / SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES; + ilen = ilen - (sha256_block_aligned_size * SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES); + if( ( ret = mbedtls_internal_sha256_process_ext( ctx, input, sha256_block_aligned_size * SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES) ) != 0 ) return( ret ); - input += 64; - ilen -= 64; + input += (sha256_block_aligned_size * SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES); } if( ilen > 0 ) @@ -387,8 +388,7 @@ int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, { /* We'll need an extra block */ memset( ctx->buffer + used, 0, 64 - used ); - - if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + if( ( ret = mbedtls_internal_sha256_process_ext( ctx, ctx->buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0 ) return( ret ); memset( ctx->buffer, 0, 56 ); @@ -404,9 +404,8 @@ int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, PUT_UINT32_BE( high, ctx->buffer, 56 ); PUT_UINT32_BE( low, ctx->buffer, 60 ); - if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + if( ( ret = mbedtls_internal_sha256_process_ext( ctx, ctx->buffer, SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES ) ) != 0 ) return( ret ); - /* * Output final state */ diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c index 8edb0bbd4..9b1d7d59f 100644 --- a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c @@ -54,12 +54,36 @@ **********************************************************************************************************************/ /*******************************************************************************************************************//** - * Uses the SCE to process the hash and returns the result. + * Uses the SCE to process the hash for len size of data and returns the result. * * * @retval 0 Hash calculation was successful. * @retval MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED Hash calculation with the SCE failed **********************************************************************************************************************/ +int mbedtls_internal_sha256_process_ext (mbedtls_sha256_context * ctx, + const unsigned char data[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES], + uint32_t len) +{ + SHA256_VALIDATE_RET(ctx != NULL); + SHA256_VALIDATE_RET((const unsigned char *) data != NULL); + + if (FSP_SUCCESS != + HW_SCE_SHA256_UpdateHash((const uint32_t *) &data[0], BYTES_TO_WORDS(len), &ctx->state[0])) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; +} + +/*******************************************************************************************************************//** + * Uses the SCE to process the hash for SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES bytes of data and returns the result. + * + * + * @retval 0 Hash calculation was successful. + * @retval MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED Hash calculation with the SCE failed + **********************************************************************************************************************/ + int mbedtls_internal_sha256_process (mbedtls_sha256_context * ctx, const unsigned char data[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES]) { @@ -68,7 +92,7 @@ int mbedtls_internal_sha256_process (mbedtls_sha256_context * ctx, if (FSP_SUCCESS != HW_SCE_SHA256_UpdateHash((const uint32_t *) &data[0], BYTES_TO_WORDS(SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES), - (uint32_t *) &ctx->state[0])) // NOLINT(rea-tp-casting) + &ctx->state[0])) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; } diff --git a/ra/fsp/src/rm_psa_crypto/vendor.c b/ra/fsp/src/rm_psa_crypto/vendor.c index 03b8b7c4d..edd4cc844 100644 --- a/ra/fsp/src/rm_psa_crypto/vendor.c +++ b/ra/fsp/src/rm_psa_crypto/vendor.c @@ -136,7 +136,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, } else #endif /* defined(MBEDTLS_AES_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_AES_FORMAT))) */ -#if defined(MBEDTLS_RSA_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) +#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_RSA_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) if (slot->attr.type == PSA_KEY_TYPE_RSA_KEY_PAIR) { mbedtls_rsa_context * rsa; @@ -187,7 +187,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, else #endif /* defined(MBEDTLS_RSA_C) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) */ -#if defined(MBEDTLS_ECP_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) +#if defined(MBEDTLS_ECP_C) && defined(MBEDTLS_ECP_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) if (PSA_KEY_TYPE_IS_ECC(slot->attr.type) && PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { psa_ecc_curve_t curve = PSA_KEY_TYPE_GET_CURVE(slot->attr.type); @@ -238,7 +238,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, status = PSA_SUCCESS; } else -#endif /* MBEDTLS_ECP_C && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) */ +#endif /* MBEDTLS_ECP_C && MBEDTLS_ECP_ALT && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) */ { status = PSA_ERROR_NOT_SUPPORTED; } @@ -289,7 +289,7 @@ psa_status_t psa_import_key_into_slot_vendor (psa_key_slot_t * slot, } else #endif /* defined(MBEDTLS_AES_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_AES_FORMAT))) */ -#if defined(MBEDTLS_ECP_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) +#if defined(MBEDTLS_ECP_C) && defined(MBEDTLS_ECP_ALT) && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(slot->attr.type)) { status = psa_import_ec_private_key_vendor(PSA_KEY_TYPE_GET_CURVE(slot->attr.type), @@ -304,7 +304,7 @@ psa_status_t psa_import_key_into_slot_vendor (psa_key_slot_t * slot, else #endif /* MBEDTLS_ECP_C && ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT))) */ -#if defined(MBEDTLS_RSA_ALT) && defined(MBEDTLS_PK_PARSE_C) && \ +#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_RSA_ALT) && defined(MBEDTLS_PK_PARSE_C) && \ ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT))) if (PSA_KEY_TYPE_IS_RSA(slot->attr.type)) { diff --git a/ra/fsp/src/rm_touch/rm_touch.c b/ra/fsp/src/rm_touch/rm_touch.c index 16de20cc9..119458509 100644 --- a/ra/fsp/src/rm_touch/rm_touch.c +++ b/ra/fsp/src/rm_touch/rm_touch.c @@ -38,8 +38,6 @@ /** "TOUC" in ASCII, used to determine if device is open. */ #define TOUCH_OPEN (0x544F5543ULL) -#define TOUCH_COUNT_MAX (0xFFFF) -#define TOUCH_OFF_VALUE (0xFFFF) #define TOUCH_SLIDER_ELEMENTS_MIN (3) #define TOUCH_SLIDER_ELEMENTS_MAX (10) #define TOUCH_WHEEL_ELEMENTS_SMALL (4) diff --git a/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c b/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c index 6400b67ec..a0b3afa2f 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c @@ -121,11 +121,6 @@ static BaseType_t prvNetworkRecv (void * pvContext, unsigned char * pucReceiveBu return receive_byte; } -/*******************************************************************************************************************//** - * @addtogroup WIFI_ONCHIP_SILEX WIFI_ONCHIP_SILEX - * @{ - **********************************************************************************************************************/ - /** * Creates a TCP socket. * @@ -747,7 +742,3 @@ BaseType_t SOCKETS_Init (void) return pdPASS; } - -/*******************************************************************************************************************//** - * @} (end addtogroup WIFI_ONCHIP_SILEX) - **********************************************************************************************************************/ diff --git a/ra/fsp/src/rm_wifi_onchip_silex/aws_wifi.c b/ra/fsp/src/rm_wifi_onchip_silex/aws_wifi.c index a61a499a2..037093796 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/aws_wifi.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/aws_wifi.c @@ -40,11 +40,6 @@ extern const wifi_onchip_silex_cfg_t g_wifi_onchip_silex_cfg; static uint32_t prvConvertSecurityFromSilexAT(WIFISecurity_t xSecurity); -/*******************************************************************************************************************//** - * @addtogroup WIFI_ONCHIP_SILEX WIFI_ONCHIP_SILEX - * @{ - **********************************************************************************************************************/ - /** * Turns on Wi-Fi. * @@ -421,10 +416,6 @@ BaseType_t WIFI_IsConnected (void) { return xIsConnected; } -/*******************************************************************************************************************//** - * @} (end addtogroup WIFI_ONCHIP_SILEX) - **********************************************************************************************************************/ - static uint32_t prvConvertSecurityFromSilexAT (WIFISecurity_t xSecurity) { uint32_t xConvertedSecurityType = WIFI_ONCHIP_SILEX_SECURITY_UNDEFINED; diff --git a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c index a0f2142ba..101425311 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c @@ -35,6 +35,8 @@ #include "r_ioport.h" #include "rm_wifi_onchip_silex.h" +/*! \cond PRIVATE */ + /* Version data structure used by error logger macro. */ static const fsp_version_t g_wifi_onchip_version = { @@ -44,7 +46,12 @@ static const fsp_version_t g_wifi_onchip_version = .code_version_minor = WIFI_ONCHIP_SILEX_CODE_VERSION_MINOR }; +/*********************************************************************************************************************** + * Externs + **********************************************************************************************************************/ + extern char * g_wifi_onchip_silex_uart_cmd_baud; +extern const ioport_instance_t g_ioport; /*********************************************************************************************************************** * Enumerations @@ -76,101 +83,104 @@ typedef enum **********************************************************************************************************************/ /* Max number of AT command return types supported by the modem */ -#define WIFI_ONCHIP_SILEX_MAX_AT_COMMAND_TYPES 2 +#define WIFI_ONCHIP_SILEX_MAX_AT_COMMAND_TYPES 2 /* Silex uart port defines */ -#define WIFI_ONCHIP_SILEX_UART_INITIAL_PORT (0) -#define WIFI_ONCHIP_SILEX_UART_SECOND_PORT (1) +#define WIFI_ONCHIP_SILEX_UART_INITIAL_PORT (0) +#define WIFI_ONCHIP_SILEX_UART_SECOND_PORT (1) /* Mutex give/take defines */ -#define WIFI_ONCHIP_SILEX_MUTEX_TX (1 << 0) -#define WIFI_ONCHIP_SILEX_MUTEX_RX (1 << 1) +#define WIFI_ONCHIP_SILEX_MUTEX_TX (1 << 0) +#define WIFI_ONCHIP_SILEX_MUTEX_RX (1 << 1) /* Text full versions of AT command returns */ -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_OK "OK\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_CONNECT "CONNECT\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_RING "RING\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_CARRIER "NO_CARRIER\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_ERROR "ERROR\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_DIALTONE "NO_DIALTONE\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_BUSY "BUSY\r\n" -#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_ANSWER "NO_ANSWER\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_OK "OK\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_CONNECT "CONNECT\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_RING "RING\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_CARRIER "NO_CARRIER\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_ERROR "ERROR\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_DIALTONE "NO_DIALTONE\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_BUSY "BUSY\r\n" +#define WIFI_ONCHIP_SILEX_RETURN_TEXT_NO_ANSWER "NO_ANSWER\r\n" /* Text numeric versions of AT command returns */ -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_OK "0\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_CONNECT "1\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_RING "2\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_CARRIER "3\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_ERROR "4\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_DIALTONE "6\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_BUSY "7\r" -#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_ANSWER "8\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_OK "0\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_CONNECT "1\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_RING "2\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_CARRIER "3\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_ERROR "4\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_DIALTONE "6\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_BUSY "7\r" +#define WIFI_ONCHIP_SILEX_RETURN_NUMERIC_NO_ANSWER "8\r" /* Socket status return values */ -#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_CLOSED "CLOSED" -#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_SOCKET "SOCKET" -#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_BOUND "BOUND" -#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_LISTEN "LISTEN" -#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_CONNECTED "CONNECTED" +#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_CLOSED "CLOSED" +#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_SOCKET "SOCKET" +#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_BOUND "BOUND" +#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_LISTEN "LISTEN" +#define WIFI_ONCHIP_SILEX_SOCKET_STATUS_TEXT_CONNECTED "CONNECTED" /* Error type defines */ -#define WIFI_ONCHIP_SILEX_ERR_BUSY (4) -#define WIFI_ONCHIP_SILEX_ERR_NO_SUPPORT (7) -#define WIFI_ONCHIP_SILEX_ERR_UNKNOWN (-3) -#define WIFI_ONCHIP_SILEX_ERR_COMMS (-2) -#define WIFI_ONCHIP_SILEX_ERR_ERROR (-1) -#define WIFI_ONCHIP_SILEX_ERR_BUSY_CHAR ('4') -#define WIFI_ONCHIP_SILEX_ERR_NO_SUPPORT_CHAR ('7') -#define WIFI_ONCHIP_SILEX_ERR_NONE_CHAR ('0') +#define WIFI_ONCHIP_SILEX_ERR_BUSY (4) +#define WIFI_ONCHIP_SILEX_ERR_NO_SUPPORT (7) +#define WIFI_ONCHIP_SILEX_ERR_UNKNOWN (-3) +#define WIFI_ONCHIP_SILEX_ERR_COMMS (-2) +#define WIFI_ONCHIP_SILEX_ERR_ERROR (-1) +#define WIFI_ONCHIP_SILEX_ERR_BUSY_CHAR ('4') +#define WIFI_ONCHIP_SILEX_ERR_NO_SUPPORT_CHAR ('7') +#define WIFI_ONCHIP_SILEX_ERR_NONE_CHAR ('0') /* Predefined timeout values */ -#define WIFI_ONCHIP_SILEX_TIMEOUT_1MS (1) -#define WIFI_ONCHIP_SILEX_TIMEOUT_3MS (3) -#define WIFI_ONCHIP_SILEX_TIMEOUT_5MS (5) -#define WIFI_ONCHIP_SILEX_TIMEOUT_10MS (10) -#define WIFI_ONCHIP_SILEX_TIMEOUT_25MS (25) -#define WIFI_ONCHIP_SILEX_TIMEOUT_30MS (30) -#define WIFI_ONCHIP_SILEX_TIMEOUT_100MS (100) -#define WIFI_ONCHIP_SILEX_TIMEOUT_200MS (200) -#define WIFI_ONCHIP_SILEX_TIMEOUT_300MS (300) -#define WIFI_ONCHIP_SILEX_TIMEOUT_400MS (400) -#define WIFI_ONCHIP_SILEX_TIMEOUT_500MS (500) -#define WIFI_ONCHIP_SILEX_TIMEOUT_1SEC (1000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_2SEC (2000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_3SEC (3000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_4SEC (4000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_5SEC (5000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_8SEC (8000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_15SEC (15000) -#define WIFI_ONCHIP_SILEX_TIMEOUT_20SEC (20000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_1MS (1) +#define WIFI_ONCHIP_SILEX_TIMEOUT_3MS (3) +#define WIFI_ONCHIP_SILEX_TIMEOUT_5MS (5) +#define WIFI_ONCHIP_SILEX_TIMEOUT_10MS (10) +#define WIFI_ONCHIP_SILEX_TIMEOUT_25MS (25) +#define WIFI_ONCHIP_SILEX_TIMEOUT_30MS (30) +#define WIFI_ONCHIP_SILEX_TIMEOUT_100MS (100) +#define WIFI_ONCHIP_SILEX_TIMEOUT_200MS (200) +#define WIFI_ONCHIP_SILEX_TIMEOUT_300MS (300) +#define WIFI_ONCHIP_SILEX_TIMEOUT_400MS (400) +#define WIFI_ONCHIP_SILEX_TIMEOUT_500MS (500) +#define WIFI_ONCHIP_SILEX_TIMEOUT_1SEC (1000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_2SEC (2000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_3SEC (3000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_4SEC (4000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_5SEC (5000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_8SEC (8000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_15SEC (15000) +#define WIFI_ONCHIP_SILEX_TIMEOUT_20SEC (20000) /* Max IP packet size */ -#define WIFI_ONCHIP_SILEX_CFG_MAX_PACKET_SIZE (1420) -#define WIFI_ONCHIP_SILEX_MAX_IP_FRAME_SIZE (5000) +#define WIFI_ONCHIP_SILEX_CFG_MAX_PACKET_SIZE (1420) +#define WIFI_ONCHIP_SILEX_MAX_IP_FRAME_SIZE (5000) /* Max retry attempts for socket index change */ -#define WIFI_ONCHIP_SILEX_MAX_SOCKET_INDEX_RETRIES (10) +#define WIFI_ONCHIP_SILEX_MAX_SOCKET_INDEX_RETRIES (10) /* Flag definitions for TCP Timeout */ -#define WIFI_ONCHIP_SILEX_TCP_TIMEOUT_FLAG_SEND (0) -#define WIFI_ONCHIP_SILEX_TCP_TIMEOUT_FLAG_RECV (1) +#define WIFI_ONCHIP_SILEX_TCP_TIMEOUT_FLAG_SEND (0) +#define WIFI_ONCHIP_SILEX_TCP_TIMEOUT_FLAG_RECV (1) /* Pulse timing for reset pin CHIP_PWD_L of the Silex module */ -#define WIFI_ONCHIP_SILEX_RESET_PIN_PULSE (WIFI_ONCHIP_SILEX_TIMEOUT_25MS) +#define WIFI_ONCHIP_SILEX_RESET_PIN_PULSE (WIFI_ONCHIP_SILEX_TIMEOUT_25MS) + +/* Pin or port invalid definition */ +#define WIFI_ONCHIP_SILEX_BSP_PIN_PORT_INVALID (UINT16_MAX) -/* pin or port invalid definition */ -#define WIFI_ONCHIP_SILEX_BSP_PIN_PORT_INVALID (UINT16_MAX) +/* Minimum string size for getting local time string */ +#define RM_WIFI_ONCHIP_SILEX_MIN_LOCAL_TIME_STRING_SIZE 25 -/* initial Silex Wifi module UART settings */ -#define WIFI_ONCHIP_SILEX_DEFAULT_BAUDRATE 115200 -#define WIFI_ONCHIP_SILEX_DEFAULT_MODULATION false -#define WIFI_ONCHIP_SILEX_DEFAULT_ERROR 9000 +/* Initial Silex Wifi module UART settings */ +#define WIFI_ONCHIP_SILEX_DEFAULT_BAUDRATE 115200 +#define WIFI_ONCHIP_SILEX_DEFAULT_MODULATION false +#define WIFI_ONCHIP_SILEX_DEFAULT_ERROR 9000 /* Unique number for WIFI Open status */ -#define WIFI_OPEN (0x57495749ULL) // Is "WIFI" in ASCII +#define WIFI_OPEN (0x57495749ULL) // Is "WIFI" in ASCII /* Unique number for SCI Open Status */ -#define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII +#define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII /*********************************************************************************************************************** * Constants @@ -213,7 +223,7 @@ static const TickType_t wifi_sx_wifi_onchip_silex_sem_block_timeout = pdMS_TO_TI /* Result code array used for AT command return parsing */ const uint8_t * const g_wifi_onchip_silex_result_code[][WIFI_ONCHIP_SILEX_MAX_AT_COMMAND_TYPES] = { - /* text mode*/ /* numeric mode */ + /* Text mode*/ /* Numeric mode */ {g_wifi_onchip_silex_return_text_ok, g_wifi_onchip_silex_return_numeric_ok}, {g_wifi_onchip_silex_return_text_connect, @@ -278,9 +288,6 @@ void rm_wifi_onchip_silex_send_basic_give_mutex(wifi_onchip_silex_instance_ctrl_ static fsp_err_t rm_wifi_onchip_silex_change_socket_index(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl, uint32_t socket_no); -static fsp_err_t rm_wifi_onchip_silex_uart_close(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl, - uint32_t uart_port); - static fsp_err_t rm_wifi_onchip_silex_socket_init(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl); static fsp_err_t rm_wifi_onchip_silex_get_ipaddress(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl); @@ -289,6 +296,11 @@ static void rm_wifi_onchip_silex_wifi_module_reset(wifi_onchip_silex_instance_ct static void rm_wifi_onchip_silex_cleanup_open(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl); +#if (1 == WIFI_ONCHIP_SILEX_CFG_SNTP_ENABLE) +static fsp_err_t rm_wifi_onchip_silex_sntp_service_init(wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl); + +#endif + size_t xStreamBufferReceiveAlternate(StreamBufferHandle_t xStreamBuffer, void * pvRxData, size_t xBufferLengthBytes, @@ -300,11 +312,6 @@ static fsp_err_t rm_wifi_onchip_silex_send_scan(wifi_onchip_silex_instance_ctrl_ uint32_t byte_timeout, uint32_t timeout_ms); -/*******************************************************************************************************************//** - * @addtogroup WIFI_ONCHIP_SILEX WIFI_ONCHIP_SILEX - * @{ - **********************************************************************************************************************/ - /*********************************************************************************************************************** * Public Functions Implementation **********************************************************************************************************************/ @@ -315,10 +322,12 @@ static fsp_err_t rm_wifi_onchip_silex_send_scan(wifi_onchip_silex_instance_ctrl_ * @param[in] p_cfg Pointer to pin configuration structure. * * @retval FSP_SUCCESS WIFI_ONCHIP_SILEX successfully configured. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_cfg or p_instance_ctrl is NULL. * @retval FSP_ERR_OUT_OF_MEMORY There is no more heap memory available. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_ARGUMENT Parameter passed into function was invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg) { @@ -330,27 +339,26 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) FSP_ASSERT(NULL != p_cfg); - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(WIFI_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); #endif - /* clear the control structure*/ + /* Clear the control structure*/ memset(p_instance_ctrl, 0, sizeof(wifi_onchip_silex_instance_ctrl_t)); - /* update control structure from configuration values */ + /* Update control structure from configuration values */ p_instance_ctrl->p_wifi_onchip_silex_cfg = p_cfg; p_instance_ctrl->num_uarts = p_cfg->num_uarts; for (uint32_t i = 0; i < p_instance_ctrl->num_uarts; i++) { - p_instance_ctrl->uart_instance_objects[i] = (uart_instance_t *) p_cfg->uart_instances[i]; - p_instance_ctrl->uart_state_info[i].uart_tei_sem = xSemaphoreCreateBinaryStatic(&g_uart_tei_mutexes[i]); - if (NULL == p_instance_ctrl->uart_state_info[i].uart_tei_sem) + p_instance_ctrl->uart_instance_objects[i] = (uart_instance_t *) p_cfg->uart_instances[i]; + p_instance_ctrl->uart_tei_sem[i] = xSemaphoreCreateBinaryStatic(&g_uart_tei_mutexes[i]); + if (NULL == p_instance_ctrl->uart_tei_sem[i]) { rm_wifi_onchip_silex_cleanup_open(p_instance_ctrl); } - FSP_ERROR_RETURN(NULL != p_instance_ctrl->uart_state_info[i].uart_tei_sem, FSP_ERR_OUT_OF_MEMORY); - xSemaphoreTake(p_instance_ctrl->uart_state_info[i].uart_tei_sem, 0); + FSP_ERROR_RETURN(NULL != p_instance_ctrl->uart_tei_sem[i], FSP_ERR_OUT_OF_MEMORY); + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[i], 0); } p_instance_ctrl->reset_pin = p_cfg->reset_pin; @@ -422,7 +430,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg uart0_cfg_115200.p_extend = (void *) &uart0_cfg_extended_115200; - /* call uart open() */ + /* Open uart 1 with module default values for baud. 115200 and no hardware flow control. */ p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg_115200); @@ -435,8 +443,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_SILEX_TIMEOUT_100MS)); - p_instance_ctrl->at_cmd_mode = 0; - + p_instance_ctrl->at_cmd_mode = 0; p_instance_ctrl->curr_socket_index = 0; /* Test basic communications with an AT command. */ @@ -454,8 +461,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); - /* create string for wifi modem baud rate change. - * using currently unused socket RX buffer for temp string. */ + /* Create string for wifi modem baud rate change. using currently unused socket RX buffer for temp string. */ memset(p_instance_ctrl->sockets[0].socket_recv_buff, 0, sizeof(p_instance_ctrl->sockets[0].socket_recv_buff)); strncat((char *) p_instance_ctrl->sockets[0].socket_recv_buff, "ATB=", 5); strncat((char *) p_instance_ctrl->sockets[0].socket_recv_buff, g_wifi_onchip_silex_uart_cmd_baud, 10); @@ -472,6 +478,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg strncat((char *) p_instance_ctrl->sockets[0].socket_recv_buff, "h\r", 3); } + /* Send reconfiguration AT command to wifi module */ err = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, p_instance_ctrl->curr_cmd_port, (char *) p_instance_ctrl->sockets[0].socket_recv_buff, @@ -485,7 +492,11 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); - err = rm_wifi_onchip_silex_uart_close(p_instance_ctrl, WIFI_ONCHIP_SILEX_UART_INITIAL_PORT); + /* Close initial uart port */ + err = + p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]->p_api->close( + p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]->p_ctrl); + if (FSP_SUCCESS != err) { rm_wifi_onchip_silex_cleanup_open(p_instance_ctrl); @@ -493,12 +504,13 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + /* Delay after close */ vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_SILEX_TIMEOUT_100MS)); + /* Open first uart port with config values from the configurator */ p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; err = p_uart->p_api->open(p_uart->p_ctrl, p_uart->p_cfg); - /* Set uart enabled value */ if (FSP_SUCCESS != err) { rm_wifi_onchip_silex_cleanup_open(p_instance_ctrl); @@ -506,9 +518,10 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + /* Delay after open */ vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_SILEX_TIMEOUT_1SEC)); - /* flush the uart channel */ + /* Flush the uart channel */ rm_wifi_onchip_silex_send_basic(p_instance_ctrl, p_instance_ctrl->curr_cmd_port, "AT\r", @@ -530,6 +543,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + /* Change to numeric command mode */ p_instance_ctrl->at_cmd_mode = 1; /* Result code format = numeric */ @@ -696,6 +710,15 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg WIFI_ONCHIP_SILEX_RETURN_OK); } +#if (1 == WIFI_ONCHIP_SILEX_CFG_SNTP_ENABLE) + if ((FSP_SUCCESS == err) && p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_enabled) + { + p_instance_ctrl->open = WIFI_OPEN; // Allows interface calls to complete for SNTP init. + err = rm_wifi_onchip_silex_sntp_service_init(p_instance_ctrl); + p_instance_ctrl->open = 0; // Reset open since this will be determined later + } +#endif + if (FSP_SUCCESS != err) { rm_wifi_onchip_silex_cleanup_open(p_instance_ctrl); @@ -714,7 +737,7 @@ fsp_err_t rm_wifi_onchip_silex_open (wifi_onchip_silex_cfg_t const * const p_cfg * Disables WIFI_ONCHIP_SILEX. * * @retval FSP_SUCCESS WIFI_ONCHIP_SILEX closed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl is NULL. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. * @retval FSP_ERR_NOT_OPEN Module is not open. **********************************************************************************************************************/ @@ -725,7 +748,6 @@ fsp_err_t rm_wifi_onchip_silex_close () wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif @@ -772,7 +794,7 @@ fsp_err_t rm_wifi_onchip_silex_close () * Disconnects from connected AP. * * @retval FSP_SUCCESS WIFI_ONCHIP_SILEX disconnected successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl is NULL. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. * @retval FSP_ERR_NOT_OPEN Module is not open. **********************************************************************************************************************/ @@ -782,7 +804,6 @@ fsp_err_t rm_wifi_onchip_silex_disconnect () wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif @@ -824,7 +845,7 @@ fsp_err_t rm_wifi_onchip_silex_disconnect () * @param[out] p_version Memory address to return version information to. * * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_version_get (fsp_version_t * const p_version) { @@ -843,7 +864,7 @@ fsp_err_t rm_wifi_onchip_silex_version_get (fsp_version_t * const p_version) * @param[out] p_status Pointer to integer holding the socket connection status. * * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_status is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. **********************************************************************************************************************/ @@ -878,7 +899,7 @@ fsp_err_t rm_wifi_onchip_silex_socket_connected (fsp_err_t * p_status) * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_ssid or p_passphrase is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_INVALID_ARGUMENT No commas are accepted in the SSID or Passphrase. **********************************************************************************************************************/ @@ -931,7 +952,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, return FSP_ERR_WIFI_FAILED; } - /* connect to an OPEN security AP */ + /* Connect to an OPEN security AP */ if (WIFI_ONCHIP_SILEX_SECURITY_OPEN == security) { strncpy((char *) p_instance_ctrl->cmd_tx_buff, "ATWA=", 6); @@ -940,7 +961,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, } else if ((WIFI_ONCHIP_SILEX_SECURITY_WPA == security) || (WIFI_ONCHIP_SILEX_SECURITY_WPA2 == security)) { - /* connect to an WPA security AP */ + /* Connect to an WPA security AP */ strncpy((char *) p_instance_ctrl->cmd_tx_buff, "ATWAWPA=", 9); strncat((char *) p_instance_ctrl->cmd_tx_buff, p_ssid, wificonfigMAX_SSID_LEN); @@ -969,7 +990,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, } else { - /* return with error for unsupported secuirty types */ + /* Return with error for unsupported secuirty types */ rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); return FSP_ERR_WIFI_FAILED; @@ -996,7 +1017,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, { ret = (fsp_err_t) WIFI_ONCHIP_SILEX_ERR_ERROR; - /* test that connection was made to ssid passed in parameter */ + /* Test that connection was made to ssid passed in parameter */ pstr = strstr((char *) p_instance_ctrl->cmd_rx_buff, "ssid = "); if (NULL != pstr) { @@ -1034,7 +1055,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, } else { - /* disconnect the current connection if we are already connected */ + /* Disconnect the current connection if we are already connected */ rm_wifi_onchip_silex_send_basic(p_instance_ctrl, p_instance_ctrl->curr_cmd_port, "ATWD\r", @@ -1063,7 +1084,7 @@ fsp_err_t rm_wifi_onchip_silex_connect (const char * p_ssid, uint32_t security, * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_macaddr is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_mac_addr_get (uint8_t * p_macaddr) @@ -1150,10 +1171,10 @@ fsp_err_t rm_wifi_onchip_silex_mac_addr_get (uint8_t * p_macaddr) * @param[out] p_results Pointer to a structure array holding scanned Access Points. * @param[in] maxNetworks Size of the structure array for holding APs. * - * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. - * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The parameter p_results or p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_WIFI_SCAN_COMPLETE Wifi scan has completed. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxNetworks) @@ -1168,7 +1189,6 @@ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxN wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ASSERT(NULL != p_results); FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif @@ -1206,7 +1226,7 @@ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxN do { - /* test for end of list */ + /* Test for end of list */ p_results[idx].cSSID[0] = '\0'; int32_t test_ssid = strncmp(ptr, "ssid =", 6); if (0 != test_ssid) @@ -1261,7 +1281,7 @@ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxN break; } - /* copy the bssid data into result */ + /* Copy the bssid data into result */ for (int i = 0; i < wificonfigMAX_BSSID_LEN; i++) { bssid[i] = (uint8_t) bssid2[i]; @@ -1426,7 +1446,7 @@ fsp_err_t rm_wifi_onchip_silex_scan (WIFIScanResult_t * p_results, uint32_t maxN * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_ip_addr is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_ping (uint8_t * p_ip_addr, uint32_t count, uint32_t interval_ms) @@ -1497,7 +1517,7 @@ fsp_err_t rm_wifi_onchip_silex_ping (uint8_t * p_ip_addr, uint32_t count, uint32 * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_ip_addr is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_ip_addr_get (uint8_t * p_ip_addr) @@ -1521,13 +1541,6 @@ fsp_err_t rm_wifi_onchip_silex_ip_addr_get (uint8_t * p_ip_addr) FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), FSP_ERR_WIFI_FAILED); - if (NULL == p_ip_addr) - { - rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); - - return FSP_ERR_WIFI_FAILED; - } - /* Return an error if a socket is connected */ if ((1 == p_instance_ctrl->num_uarts) && (p_instance_ctrl->sockets[0].socket_status == WIFI_ONCHIP_SILEX_SOCKET_STATUS_CONNECTED)) @@ -1591,7 +1604,7 @@ fsp_err_t rm_wifi_onchip_silex_ip_addr_get (uint8_t * p_ip_addr) * @param[out] p_socket_id Pointer to an integer to hold the socket ID. * * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_socket_id is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_WIFI_FAILED Error occured in the execution of this function **********************************************************************************************************************/ @@ -1626,7 +1639,8 @@ fsp_err_t rm_wifi_onchip_silex_avail_socket_get (uint32_t * p_socket_id) * @param[out] p_socket_status Pointer to an integer to hold the socket status * * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl or p_socket_status is NULL. The value of socket_no + * is greater than/equal num_creatable_sockets. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_socket_status_get (uint32_t socket_no, uint32_t * p_socket_status) @@ -1634,7 +1648,6 @@ fsp_err_t rm_wifi_onchip_silex_socket_status_get (uint32_t socket_no, uint32_t * wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ASSERT(NULL != p_socket_status); FSP_ASSERT(socket_no < p_instance_ctrl->num_creatable_sockets); FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); @@ -1652,7 +1665,8 @@ fsp_err_t rm_wifi_onchip_silex_socket_status_get (uint32_t socket_no, uint32_t * * @param[in] shutdown_channels Specify if read or write channel is shutdown for socket * * @retval FSP_SUCCESS Function completed successfully. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl is NULL. The value of socket_no + * is greater than/equal num_creatable_sockets. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ int32_t rm_wifi_onchip_silex_tcp_shutdown (uint32_t socket_no, uint32_t shutdown_channels) @@ -1660,7 +1674,6 @@ int32_t rm_wifi_onchip_silex_tcp_shutdown (uint32_t socket_no, uint32_t shutdown wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; #if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) - FSP_ASSERT(NULL != p_instance_ctrl); FSP_ASSERT(socket_no < p_instance_ctrl->num_creatable_sockets); FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif @@ -1687,7 +1700,7 @@ int32_t rm_wifi_onchip_silex_tcp_shutdown (uint32_t socket_no, uint32_t shutdown * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_socket_create (uint32_t socket_no, uint32_t type, uint32_t ipversion) @@ -1770,7 +1783,7 @@ fsp_err_t rm_wifi_onchip_silex_socket_create (uint32_t socket_no, uint32_t type, * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ fsp_err_t rm_wifi_onchip_silex_tcp_connect (uint32_t socket_no, uint32_t ipaddr, uint32_t port) @@ -1849,7 +1862,7 @@ fsp_err_t rm_wifi_onchip_silex_tcp_connect (uint32_t socket_no, uint32_t ipaddr, * @param[in] timeout_ms Timeout to wait for transmit end event * * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl or parameter p_data is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. **********************************************************************************************************************/ int32_t rm_wifi_onchip_silex_tcp_send (uint32_t socket_no, const uint8_t * p_data, uint32_t length, uint32_t timeout_ms) @@ -1867,7 +1880,7 @@ int32_t rm_wifi_onchip_silex_tcp_send (uint32_t socket_no, const uint8_t * p_dat FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* if socket write has been disabled by shutdown call then return 0 bytes sent. */ + /* If socket write has been disabled by shutdown call then return 0 bytes sent. */ if (!(p_instance_ctrl->sockets[socket_no].socket_read_write_flag & WIFI_ONCHIP_SILEX_SOCKET_WRITE)) { return 0; @@ -1932,8 +1945,7 @@ int32_t rm_wifi_onchip_silex_tcp_send (uint32_t socket_no, const uint8_t * p_dat } if (pdFALSE == - xSemaphoreTake(p_instance_ctrl->uart_state_info[p_instance_ctrl->curr_data_port].uart_tei_sem, - pdMS_TO_TICKS(timeout_ms))) + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[p_instance_ctrl->curr_data_port], pdMS_TO_TICKS(timeout_ms))) { rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); @@ -1959,6 +1971,7 @@ int32_t rm_wifi_onchip_silex_tcp_send (uint32_t socket_no, const uint8_t * p_dat * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl or parameter p_data is NULL. **********************************************************************************************************************/ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uint32_t length, uint32_t timeout_ms) { @@ -1974,7 +1987,7 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* if socket read has been disabled by shutdown call then return 0 bytes received. */ + /* If socket read has been disabled by shutdown call then return 0 bytes received. */ if (!(p_instance_ctrl->sockets[socket_no].socket_read_write_flag & WIFI_ONCHIP_SILEX_SOCKET_READ)) { return 0; @@ -1997,7 +2010,7 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin return WIFI_ONCHIP_SILEX_ERR_ERROR; } - /* change socket index if needed */ + /* Change socket index if needed */ if (socket_no != p_instance_ctrl->curr_socket_index) { rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); @@ -2056,7 +2069,7 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin ret = (int32_t) recvcnt; break; } - } /* for */ + } /* For */ } else { @@ -2066,7 +2079,7 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin /* Reset the trigger level for socket stream buffer */ xStreamBufferSetTriggerLevel(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl, 1); } - else /* num uarts = 1 */ + else /* Num uarts = 1 */ { if (0 == p_instance_ctrl->sockets[socket_no].socket_create_flag) { @@ -2109,11 +2122,11 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin ret = (int32_t) recvcnt; break; } - } /* for */ + } /* For */ } else { - ret = 0; // timeout occurred + ret = 0; // Timeout occurred } /* Reset the trigger level for socket stream buffer */ @@ -2132,7 +2145,7 @@ int32_t rm_wifi_onchip_silex_tcp_recv (uint32_t socket_no, uint8_t * p_data, uin * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_INVALID_ARGUMENT Bad parameter value was passed into function. **********************************************************************************************************************/ @@ -2226,7 +2239,7 @@ fsp_err_t rm_wifi_onchip_silex_socket_disconnect (uint32_t socket_no) * * @retval FSP_SUCCESS Function completed successfully. * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. - * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl, p_textstring, p_ip_addr is NULL. * @retval FSP_ERR_NOT_OPEN The instance has not been opened. * @retval FSP_ERR_INVALID_ARGUMENT The URL passed in is to long. **********************************************************************************************************************/ @@ -2317,10 +2330,6 @@ fsp_err_t rm_wifi_onchip_silex_dns_query (const char * p_textstring, uint8_t * p return FSP_SUCCESS; } -/*******************************************************************************************************************//** - * @} (end addtogroup WIFI_ONCHIP_SILEX) - **********************************************************************************************************************/ - /*********************************************************************************************************************** * Private Functions Implementation **********************************************************************************************************************/ @@ -2347,16 +2356,16 @@ static void rm_wifi_onchip_silex_cleanup_open (wifi_onchip_silex_instance_ctrl_t p_instance_ctrl->socket_byteq_hdl = NULL; } - if (NULL != p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT].uart_tei_sem) + if (NULL != p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]) { - vSemaphoreDelete(p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT].uart_tei_sem); - p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT].uart_tei_sem = NULL; + vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]); + p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT] = NULL; } - if (NULL != p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_SECOND_PORT].uart_tei_sem) + if (NULL != p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_SECOND_PORT]) { - vSemaphoreDelete(p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_SECOND_PORT].uart_tei_sem); - p_instance_ctrl->uart_state_info[WIFI_ONCHIP_SILEX_UART_SECOND_PORT].uart_tei_sem = NULL; + vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_SECOND_PORT]); + p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_SILEX_UART_SECOND_PORT] = NULL; } uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; @@ -2371,7 +2380,7 @@ static void rm_wifi_onchip_silex_cleanup_open (wifi_onchip_silex_instance_ctrl_t p_uart->p_api->close(p_uart->p_ctrl); } - /* clean up the stream buffers that were allocated */ + /* Clean up the stream buffers that were allocated */ for (int i = 0; i < WIFI_ONCHIP_SILEX_CFG_NUM_CREATEABLE_SOCKETS; i++) { if (p_instance_ctrl->sockets[i].socket_byteq_hdl) @@ -2546,7 +2555,7 @@ fsp_err_t rm_wifi_onchip_silex_send_basic (wifi_onchip_silex_instance_ctrl_t * p { recvcnt = 0; - if (uxQueueMessagesWaiting((QueueHandle_t) p_instance_ctrl->uart_state_info[serial_ch_id].uart_tei_sem) != + if (uxQueueMessagesWaiting((QueueHandle_t) p_instance_ctrl->uart_tei_sem[serial_ch_id]) != 0) { return FSP_ERR_WIFI_FAILED; @@ -2560,7 +2569,7 @@ fsp_err_t rm_wifi_onchip_silex_send_basic (wifi_onchip_silex_instance_ctrl_t * p FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); FSP_ERROR_RETURN(pdTRUE == - xSemaphoreTake(p_instance_ctrl->uart_state_info[serial_ch_id].uart_tei_sem, + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[serial_ch_id], (timeout_ms / portTICK_PERIOD_MS)), FSP_ERR_WIFI_FAILED); } @@ -2659,7 +2668,7 @@ fsp_err_t rm_wifi_onchip_silex_send_basic (wifi_onchip_silex_instance_ctrl_t * p p_instance_ctrl->at_cmd_mode]))) { - /* busy */ + /* Busy */ return (fsp_err_t) WIFI_ONCHIP_SILEX_RETURN_BUSY; } @@ -2705,7 +2714,7 @@ static fsp_err_t rm_wifi_onchip_silex_send_scan (wifi_onchip_silex_instance_ctrl { recvcnt = 0; - if (uxQueueMessagesWaiting((QueueHandle_t) p_instance_ctrl->uart_state_info[serial_ch_id].uart_tei_sem) != + if (uxQueueMessagesWaiting((QueueHandle_t) p_instance_ctrl->uart_tei_sem[serial_ch_id]) != 0) { return FSP_ERR_WIFI_FAILED; @@ -2720,8 +2729,7 @@ static fsp_err_t rm_wifi_onchip_silex_send_scan (wifi_onchip_silex_instance_ctrl FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); FSP_ERROR_RETURN(pdTRUE == - xSemaphoreTake(p_instance_ctrl->uart_state_info[serial_ch_id].uart_tei_sem, - (timeout_ms / portTICK_PERIOD_MS)), + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[serial_ch_id], (timeout_ms / portTICK_PERIOD_MS)), FSP_ERR_WIFI_FAILED); } @@ -2790,9 +2798,9 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins if (p_instance_ctrl->num_uarts == 2) { - if (socket_no != p_instance_ctrl->curr_socket_index) // only attempt change if socket number is different than current. + if (socket_no != p_instance_ctrl->curr_socket_index) // Only attempt change if socket number is different than current. { - for (int i = 0; i < WIFI_ONCHIP_SILEX_MAX_SOCKET_INDEX_RETRIES; i++) // retry to change socket index number max 10 times. + for (int i = 0; i < WIFI_ONCHIP_SILEX_MAX_SOCKET_INDEX_RETRIES; i++) // Retry to change socket index number max 10 times. { sprintf((char *) p_instance_ctrl->cmd_tx_buff, "ATNSOCKINDEX=%d\r", (int) socket_no); ret = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, @@ -2854,7 +2862,7 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins return (fsp_err_t) WIFI_ONCHIP_SILEX_ERR_UNKNOWN; } } - else // module comms error. + else // Module comms error. { return (fsp_err_t) WIFI_ONCHIP_SILEX_ERR_COMMS; } @@ -2869,23 +2877,6 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins return ret; } -/*******************************************************************************************************************//** - * Close the UART. - * - * @param[in] p_instance_ctrl Pointer to control instance. - * @param[in] uart_port UART port number. - * - * @retval FSP_SUCCESS Function completed successfully. - **********************************************************************************************************************/ -static fsp_err_t rm_wifi_onchip_silex_uart_close (wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl, - uint32_t uart_port) -{ - p_instance_ctrl->uart_instance_objects[uart_port]->p_api->close( - p_instance_ctrl->uart_instance_objects[uart_port]->p_ctrl); - - return FSP_SUCCESS; -} - /*******************************************************************************************************************//** * Initialize the sockets interface. * @@ -2982,11 +2973,9 @@ void rm_wifi_onchip_silex_uart_callback (uart_callback_args_t * p_args) case UART_EVENT_TX_DATA_EMPTY: { if ((0 == - uxQueueMessagesWaitingFromISR((QueueHandle_t) p_instance_ctrl->uart_state_info[uart_context_index]. - uart_tei_sem))) + uxQueueMessagesWaitingFromISR((QueueHandle_t) p_instance_ctrl->uart_tei_sem[uart_context_index]))) { - xSemaphoreGiveFromISR(p_instance_ctrl->uart_state_info[uart_context_index].uart_tei_sem, - &xHigherPriorityTaskWoken); + xSemaphoreGiveFromISR(p_instance_ctrl->uart_tei_sem[uart_context_index], &xHigherPriorityTaskWoken); } portYIELD_FROM_ISR(xHigherPriorityTaskWoken); @@ -3001,6 +2990,320 @@ void rm_wifi_onchip_silex_uart_callback (uart_callback_args_t * p_args) } } +/*******************************************************************************************************************//** + * Initialize silex module SNTP client service. + * + * @param[in] p_instance_ctrl Pointer to array holding URL to query from DNS. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_INVALID_ARGUMENT Parameter passed into function was invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +#if (1 == WIFI_ONCHIP_SILEX_CFG_SNTP_ENABLE) +static fsp_err_t rm_wifi_onchip_silex_sntp_service_init (wifi_onchip_silex_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + uint8_t ip_address_sntp_server[4] = {0, 0, 0, 0}; + int32_t err_scan; + + /* Enable/disable the SNTP clinet */ + err = RM_WIFI_ONCHIP_SILEX_SntpEnableSet(p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_enabled); + + /* Set the SNTP server IP address */ + if ((FSP_SUCCESS == err) && (1 == p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_enabled)) + { + err_scan = + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + sscanf((const char *) p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_server_ip, + "%u.%u.%u.%u,", + (unsigned int *) &ip_address_sntp_server[0], + (unsigned int *) &ip_address_sntp_server[1], + (unsigned int *) &ip_address_sntp_server[2], + (unsigned int *) &ip_address_sntp_server[3]); + + if (4 == err_scan) + { + err = RM_WIFI_ONCHIP_SILEX_SntpServerIpAddressSet((uint8_t *) ip_address_sntp_server); + } + } + + /* Set the SNTP Timezone configuration string */ + if ((FSP_SUCCESS == err) && (1 == p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_enabled)) + { + err = RM_WIFI_ONCHIP_SILEX_SntpTimeZoneSet( + p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_timezone_offset_from_utc_hours, + p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_timezone_offset_from_utc_minutes, + p_instance_ctrl->p_wifi_onchip_silex_cfg->sntp_timezone_use_daylight_savings); + } + + return err; +} + +#endif + +/*! \endcond */ + +/*******************************************************************************************************************//** + * @addtogroup WIFI_ONCHIP_SILEX WIFI_ONCHIP_SILEX + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This will retrieve time info from an NTP server at the address entered via an during configuration. If the server + * isn’t set or the client isn’t enabled, then it will return an error. The date/time is retrieved as the number of + * seconds since 00:00:00 UTC January 1, 1970 + * + * @param[out] p_utc_time Returns the epoch time in seconds. + * + * @retval FSP_SUCCESS Successfully retrieved the system time from module. + * @retval FSP_ERR_ASSERTION The parameter utc_time or p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_EpochTimeGet (time_t * p_utc_time) +{ + uint32_t mutex_flag; + fsp_err_t ret; + wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; + +#if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_utc_time); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_SILEX_MUTEX_TX | WIFI_ONCHIP_SILEX_MUTEX_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + ret = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "ATNTPTIMESEC=?\r", + WIFI_ONCHIP_SILEX_TIMEOUT_100MS, + WIFI_ONCHIP_SILEX_TIMEOUT_500MS, + WIFI_ONCHIP_SILEX_RETURN_OK); + + if (FSP_SUCCESS == ret) + { + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + sscanf((const char *) p_instance_ctrl->cmd_rx_buff, "%u", (unsigned int *) p_utc_time); + } + + rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return ret; +} + +/*******************************************************************************************************************//** + * Get the current local time based on current timezone in a string . Exp: Wed Oct 15 1975 07:06:00 + * + * @param[out] p_local_time Returns local time in string format. + * @param[in] size_string Size of p_local_time string buffer.The size of this string needs to be at least 25 bytes + * + * @retval FSP_SUCCESS Successfully returned the local time string. + * @retval FSP_ERR_ASSERTION The parameter local_time or p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE String size value passed in exceeds maximum. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_LocalTimeGet (uint8_t * p_local_time, uint32_t size_string) +{ + uint32_t mutex_flag; + fsp_err_t ret; + wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; + +#if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_local_time); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(RM_WIFI_ONCHIP_SILEX_MIN_LOCAL_TIME_STRING_SIZE <= size_string, FSP_ERR_INVALID_SIZE); +#endif + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_SILEX_MUTEX_TX | WIFI_ONCHIP_SILEX_MUTEX_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + memset(p_local_time, 0, size_string); + + ret = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "ATNTPTIME=?\r", + WIFI_ONCHIP_SILEX_TIMEOUT_100MS, + WIFI_ONCHIP_SILEX_TIMEOUT_500MS, + WIFI_ONCHIP_SILEX_RETURN_OK); + + if (FSP_SUCCESS == ret) + { + /* Copy local time and crop out only the date/time string */ + strncpy((char *) p_local_time, (const char *) p_instance_ctrl->cmd_rx_buff, size_string); + char * cr_loc = strchr((char *) p_local_time, '\r'); + cr_loc[0] = '\0'; + } + + rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return ret; +} + +/*******************************************************************************************************************//** + * Set the SNTP Client to Enable or Disable + * + * @param[in] enable Can be set to enable/disable for SNTP support. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpEnableSet (wifi_onchip_silex_sntp_enable_t enable) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; + +#if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mutex_flag = (WIFI_ONCHIP_SILEX_MUTEX_TX | WIFI_ONCHIP_SILEX_MUTEX_RX); + + FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + snprintf((char *) p_instance_ctrl->sockets[0].socket_recv_buff, + sizeof(p_instance_ctrl->sockets[0].socket_recv_buff), + "ATNTPCLIENT=%u\r", + (unsigned int) enable); + + err = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (const char *) p_instance_ctrl->sockets[0].socket_recv_buff, + WIFI_ONCHIP_SILEX_TIMEOUT_3MS, + WIFI_ONCHIP_SILEX_TIMEOUT_500MS, + WIFI_ONCHIP_SILEX_RETURN_OK); + + rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * Set the SNTP Client Server IP Address + * + * @param[in] p_ip_address Pointer to IP address of SNTP server in byte array format. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_ASSERTION The parameter p_ip_address or p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpServerIpAddressSet (uint8_t * p_ip_address) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; + +#if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_ip_address); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mutex_flag = (WIFI_ONCHIP_SILEX_MUTEX_TX | WIFI_ONCHIP_SILEX_MUTEX_RX); + + FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + snprintf((char *) p_instance_ctrl->sockets[0].socket_recv_buff, + sizeof(p_instance_ctrl->sockets[0].socket_recv_buff), + "ATNTPSRVR=%u.%u.%u.%u\r", + p_ip_address[0], + p_ip_address[1], + p_ip_address[2], + p_ip_address[3]); + + err = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (const char *) p_instance_ctrl->sockets[0].socket_recv_buff, + WIFI_ONCHIP_SILEX_TIMEOUT_3MS, + WIFI_ONCHIP_SILEX_TIMEOUT_500MS, + WIFI_ONCHIP_SILEX_RETURN_OK); + + rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * Set the SNTP Client Timezone + * + * @param[in] hours Number of hours (+/-) used for timezone offset from GMT. + * @param[in] minutes Number of minutes used for timezone offset from GMT. + * @param[in] daylightSavingsEnable Enable/Disable daylight saving in the timezone calculation. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_ARGUMENT Parameter passed into function was invalid. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_SILEX_SntpTimeZoneSet (int32_t hours, + uint32_t minutes, + wifi_onchip_silex_sntp_daylight_savings_enable_t daylightSavingsEnable) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_silex_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_silex_instance; + +#if (WIFI_ONCHIP_SILEX_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(((hours >= -12) && (hours <= 12)), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((minutes <= 59), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(!(((hours == -12) || (hours == 12)) && (minutes > 0)), FSP_ERR_INVALID_ARGUMENT); +#endif + + mutex_flag = (WIFI_ONCHIP_SILEX_MUTEX_TX | WIFI_ONCHIP_SILEX_MUTEX_RX); + + FSP_ERROR_RETURN(FSP_SUCCESS == rm_wifi_onchip_silex_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + uint32_t is_positive = 0; + + if (0 <= hours) + { + is_positive = 1; + } + else + { + hours = -hours; + } + + snprintf((char *) p_instance_ctrl->sockets[0].socket_recv_buff, + sizeof(p_instance_ctrl->sockets[0].socket_recv_buff), + "ATNTPZONE=%d,%u,%u,%u\r", + (int) hours, + (unsigned int) minutes, + (unsigned int) is_positive, + (unsigned int) daylightSavingsEnable); + + err = rm_wifi_onchip_silex_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (const char *) p_instance_ctrl->sockets[0].socket_recv_buff, + WIFI_ONCHIP_SILEX_TIMEOUT_3MS, + WIFI_ONCHIP_SILEX_TIMEOUT_500MS, + WIFI_ONCHIP_SILEX_RETURN_OK); + + rm_wifi_onchip_silex_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_ONCHIP_SILEX) + **********************************************************************************************************************/ + +/*! \cond PRIVATE */ + /////////////////////////////////////////////////////////////////////////////// /* @@ -3311,3 +3614,5 @@ bool IotClock_GetTimestring (char * pBuffer, size_t bufferSize, size_t * pTimest } #endif + +/*! \endcond */