diff --git a/README.md b/README.md index 2f95ccc73..10348b24d 100644 --- a/README.md +++ b/README.md @@ -8,18 +8,23 @@ The e² studio ISDE provides support with intuitive configurators and intelligen FSP uses an open software ecosystem and provides flexibility in using your preferred RTOS, legacy code, and third-party ecosystem solutions. -Download the latest FSP version from the [Releases page](https://github.com/renesas/fsp/releases). +### Current Release + +[FSP v2.2.0](https://github.com/renesas/fsp/releases/tag/v2.2.0) ### Supported RA MCU Kits - EK-RA2A1 +- EK-RA2L1 - EK-RA4M1 - EK-RA4W1 +- EK-RA4M3 - EK-RA6M1 - EK-RA6M2 - EK-RA6M3 - EK-RA6M3G - EK-RA6M4 +- RSSK-RA2L1 - RSSK-RA6T1 ### Setup Instructions @@ -32,7 +37,7 @@ If you have already installed a previous FSP release that included e² studio th #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [latest release](https://github.com/renesas/fsp/releases). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v2.2.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/ra/board/ra2l1_ek/board.h b/ra/board/ra2l1_ek/board.h new file mode 100644 index 000000000..915859343 --- /dev/null +++ b/ra/board/ra2l1_ek/board.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA2L1_EK for the RA2L1-EK board + * @brief BSP for the RA2L1-EK Board + * + * The RA2L1_EK is a development kit for the Renesas R7FA2L1AB2DFP microcontroller in a LQFP100 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA2L1_EK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA2L1_EK) */ + +#endif diff --git a/ra/board/ra2l1_ek/board_init.c b/ra/board/ra2l1_ek/board_init.c new file mode 100644 index 000000000..2ef1d5558 --- /dev/null +++ b/ra/board/ra2l1_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_EK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2L1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2L1_EK) */ diff --git a/ra/board/ra2l1_ek/board_init.h b/ra/board/ra2l1_ek/board_init.h new file mode 100644 index 000000000..0fcf9f321 --- /dev/null +++ b/ra/board/ra2l1_ek/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_EK + * @brief Board specific code for the RA2L1-EK Board + * + * This include file is specific to the RA2L1-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA2L1_EK) */ diff --git a/ra/board/ra2l1_ek/board_leds.c b/ra/board/ra2l1_ek/board_leds.c new file mode 100644 index 000000000..7e6ca56bc --- /dev/null +++ b/ra/board/ra2l1_ek/board_leds.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_EK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA2L1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_05_PIN_03, ///< LED1 + (uint16_t) BSP_IO_PORT_05_PIN_04, ///< LED2 + (uint16_t) BSP_IO_PORT_05_PIN_05, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA2L1_EK_LEDS) */ diff --git a/ra/board/ra2l1_ek/board_leds.h b/ra/board/ra2l1_ek/board_leds.h new file mode 100644 index 000000000..ff2496636 --- /dev/null +++ b/ra/board/ra2l1_ek/board_leds.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA2L1_EK + * @defgroup BOARD_A1L1_EK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EEK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA2L1_EK_LEDS) */ diff --git a/ra/board/ra2l1_rssk/board.h b/ra/board/ra2l1_rssk/board.h new file mode 100644 index 000000000..370ffc97a --- /dev/null +++ b/ra/board/ra2l1_rssk/board.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA2L1_RSSK + * @brief BSP for the RA2L1-RSSK Board + * + * The RA2L1-RSSK is a development kit for the Renesas R7FA2L1AB2DFP microcontroller in a LQFP100 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA2L1_RSSK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA2L1_RSSK) */ + +#endif diff --git a/ra/board/ra2l1_rssk/board_init.c b/ra/board/ra2l1_rssk/board_init.c new file mode 100644 index 000000000..7096d58e9 --- /dev/null +++ b/ra/board/ra2l1_rssk/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_RSSK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2L1_RSSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2L1_RSSK) */ diff --git a/ra/board/ra2l1_rssk/board_init.h b/ra/board/ra2l1_rssk/board_init.h new file mode 100644 index 000000000..32deebbb3 --- /dev/null +++ b/ra/board/ra2l1_rssk/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_RSSK + * @brief Board specific code for the RA2L1-RSSK Board + * + * This include file is specific to the RA2L1-RSSK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA2L1_RSSK) */ diff --git a/ra/board/ra2l1_rssk/board_leds.c b/ra/board/ra2l1_rssk/board_leds.c new file mode 100644 index 000000000..f553ecc9b --- /dev/null +++ b/ra/board/ra2l1_rssk/board_leds.c @@ -0,0 +1,70 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_RSSK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA2L1_RSSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_03_PIN_05, ///< LED2 + (uint16_t) BSP_IO_PORT_03_PIN_04, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA2L1_RSSK_LEDS) */ diff --git a/ra/board/ra2l1_rssk/board_leds.h b/ra/board/ra2l1_rssk/board_leds.h new file mode 100644 index 000000000..20acb86ec --- /dev/null +++ b/ra/board/ra2l1_rssk/board_leds.h @@ -0,0 +1,73 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA2L1_RSSK + * @defgroup BOARD_RA2L1_RSSK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the RA2L1 RSSK board. It includes info on the number of LEDs and which pins are they are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA2L1_RSSK_LEDS) */ diff --git a/ra/board/ra4m3_ek/board.h b/ra/board/ra4m3_ek/board.h new file mode 100644 index 000000000..23118006b --- /dev/null +++ b/ra/board/ra4m3_ek/board.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA4M3_EK for the RA4M3-EK board + * @brief BSP for the RA4M3-EK Board + * + * The RA4M3_EK is a development kit for the Renesas R7FA4M3AF3CFB microcontroller in a LQFP144 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA4M3_EK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA4M3_EK) */ + +#endif diff --git a/ra/board/ra4m3_ek/board_init.c b/ra/board/ra4m3_ek/board_init.c new file mode 100644 index 000000000..325205ac9 --- /dev/null +++ b/ra/board/ra4m3_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4M3_EK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA4M3_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA4M3_EK) */ diff --git a/ra/board/ra4m3_ek/board_init.h b/ra/board/ra4m3_ek/board_init.h new file mode 100644 index 000000000..09024f7a9 --- /dev/null +++ b/ra/board/ra4m3_ek/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4M3_EK + * @brief Board specific code for the RA4M3-EK Board + * + * This include file is specific to the RA4M3-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA4M3_EK) */ diff --git a/ra/board/ra4m3_ek/board_leds.c b/ra/board/ra4m3_ek/board_leds.c new file mode 100644 index 000000000..961f8b8aa --- /dev/null +++ b/ra/board/ra4m3_ek/board_leds.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4M3_EK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA4M3_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_04_PIN_15, ///< LED1 + (uint16_t) BSP_IO_PORT_04_PIN_04, ///< LED2 + (uint16_t) BSP_IO_PORT_04_PIN_00, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA4M3_EK_LEDS) */ diff --git a/ra/board/ra4m3_ek/board_leds.h b/ra/board/ra4m3_ek/board_leds.h new file mode 100644 index 000000000..f0e715040 --- /dev/null +++ b/ra/board/ra4m3_ek/board_leds.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA4M3_EK + * @defgroup BOARD_RA4M3_EK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA4M3_EK_LEDS) */ diff --git a/ra/fsp/inc/api/r_usb_basic_api.h b/ra/fsp/inc/api/r_usb_basic_api.h index 74d00975a..7a7d8a45f 100644 --- a/ra/fsp/inc/api/r_usb_basic_api.h +++ b/ra/fsp/inc/api/r_usb_basic_api.h @@ -128,6 +128,11 @@ FSP_HEADER #define USB_EP14 (0xEU) ///< End Point Number14 #define USB_EP15 (0xFU) ///< End Point Number15 +/* Endpoint Direction */ +#define USB_EP_DIR (0x0080U) ///< b7: Endpoint Direction +#define USB_EP_DIR_IN (0x0080U) ///< b7: Endpoint Direction In +#define USB_EP_DIR_OUT (0x0000U) ///< b7: Endpoint Direction Out + /* Descriptor type Define */ #define USB_DT_DEVICE (0x01U) ///< Device Descriptor #define USB_DT_CONFIGURATION (0x02U) ///< Configuration Descriptor diff --git a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h index a20e69bde..545dbdce0 100644 --- a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h +++ b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h @@ -117,11 +117,18 @@ typedef struct st_rm_freertos_plus_fat_cfg typedef struct st_rm_freertos_plus_fat_disk_cfg { - uint32_t num_sectors; ///< Number of sectors in this partition - uint32_t sector_size_bytes; ///< Block size - uint32_t cache_size_bytes; ///< Chache memory size - uint8_t * p_cache; ///< Pointer to cache memory - uint8_t partition_number; ///< Partition number for this disk + union + { + rm_freertos_plus_fat_device_t device; ///< Device sector data + struct + { + uint32_t num_sectors; // DEPRECATED + uint32_t sector_size_bytes; // DEPRECATED + }; + }; + uint32_t cache_size_bytes; ///< Chache memory size + uint8_t * p_cache; ///< Pointer to cache memory + uint8_t partition_number; ///< Partition number for this disk } rm_freertos_plus_fat_disk_cfg_t; typedef void rm_freertos_plus_fat_ctrl_t; diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 5ee754f69..e6b18ea3f 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -41,19 +41,19 @@ #define FSP_VERSION_MAJOR (2U) /** FSP pack minor version. */ -#define FSP_VERSION_MINOR (1U) +#define FSP_VERSION_MINOR (2U) /** FSP pack patch version. */ -#define FSP_VERSION_PATCH (1U) +#define FSP_VERSION_PATCH (0U) /** FSP pack version build number (currently unused). */ #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ -#define FSP_VERSION_STRING ("2.1.1") +#define FSP_VERSION_STRING ("2.2.0") /** Unique FSP version ID. */ -#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.1.1") +#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.2.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc.h b/ra/fsp/inc/instances/r_adc.h index c75f6b61b..02253bab4 100644 --- a/ra/fsp/inc/instances/r_adc.h +++ b/ra/fsp/inc/instances/r_adc.h @@ -221,9 +221,6 @@ typedef struct uint32_t scan_mask; // Scan mask used for Normal scan. uint16_t scan_start_adcsr; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs. adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h index 74d5885a3..4870a6254 100644 --- a/ra/fsp/inc/instances/r_agt.h +++ b/ra/fsp/inc/instances/r_agt.h @@ -125,9 +125,6 @@ typedef struct st_agt_instance_ctrl R_AGT0_Type * p_reg; // Base register for this channel uint32_t period; // Current timer period (counts) -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/inc/instances/r_cac.h b/ra/fsp/inc/instances/r_cac.h index 1519e3761..102be355a 100644 --- a/ra/fsp/inc/instances/r_cac.h +++ b/ra/fsp/inc/instances/r_cac.h @@ -52,10 +52,6 @@ typedef struct st_cac_instance_ctrl uint32_t open; // Set to "CAC" once API has been successfully opened. cac_cfg_t const * p_cfg; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(cac_callback_args_t *); cac_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_can.h b/ra/fsp/inc/instances/r_can.h index ff608f753..7a33a6eae 100644 --- a/ra/fsp/inc/instances/r_can.h +++ b/ra/fsp/inc/instances/r_can.h @@ -61,9 +61,6 @@ typedef struct st_can_instance_ctrl can_message_mode_t message_mode; // Overwrite message or overrun. can_clock_source_t clock_source; // Clock source. CANMCLK or PCLKB. -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(can_callback_args_t *); // Pointer to callback can_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/inc/instances/r_cgc.h b/ra/fsp/inc/instances/r_cgc.h index 53ec66214..630de3745 100644 --- a/ra/fsp/inc/instances/r_cgc.h +++ b/ra/fsp/inc/instances/r_cgc.h @@ -51,9 +51,6 @@ typedef struct st_cgc_instance_ctrl { uint32_t open; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif cgc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. void (* p_callback)(cgc_callback_args_t * p_args); // Pointer to callback that is called when a cgc_event_t occurs. diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h index 759f782b2..91d2b6a4c 100644 --- a/ra/fsp/inc/instances/r_ctsu.h +++ b/ra/fsp/inc/instances/r_ctsu.h @@ -203,9 +203,6 @@ typedef struct st_ctsu_instance_ctrl IRQn_Type write_irq; ///< Copy from config by Open API. CTSU_CTSUWR interrupt vector IRQn_Type read_irq; ///< Copy from config by Open API. CTSU_CTSURD interrupt vector IRQn_Type end_irq; ///< Copy from config by Open API. CTSU_CTSUFN interrupt vector -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; ///< If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(ctsu_callback_args_t *); ///< Callback provided when a CTSUFN occurs. ctsu_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. void const * p_context; ///< Placeholder for user data. diff --git a/ra/fsp/inc/instances/r_doc.h b/ra/fsp/inc/instances/r_doc.h index 8ff4da957..11c3d8374 100644 --- a/ra/fsp/inc/instances/r_doc.h +++ b/ra/fsp/inc/instances/r_doc.h @@ -47,10 +47,6 @@ typedef struct st_doc_instance_ctrl doc_cfg_t const * p_cfg; // Pointer to the configuration structure uint32_t open; ///< Used by driver to check if the control structure is valid -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(doc_callback_args_t *); doc_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_flash_hp.h b/ra/fsp/inc/instances/r_flash_hp.h index 2dccaf80b..257f96b15 100644 --- a/ra/fsp/inc/instances/r_flash_hp.h +++ b/ra/fsp/inc/instances/r_flash_hp.h @@ -88,9 +88,7 @@ typedef struct st_flash_hp_instance_ctrl uint32_t dest_end_address; uint32_t operations_remaining; flash_bgo_operation_t current_operation; ///< Operation in progress, for example, FLASH_OPERATION_CF_ERASE -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif + void (* p_callback)(flash_callback_args_t *); // Pointer to callback flash_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/inc/instances/r_gpt.h b/ra/fsp/inc/instances/r_gpt.h index 073b67ea1..ff6c2d902 100644 --- a/ra/fsp/inc/instances/r_gpt.h +++ b/ra/fsp/inc/instances/r_gpt.h @@ -260,9 +260,6 @@ typedef struct st_gpt_instance_ctrl uint32_t channel_mask; // Channel bitmask timer_variant_t variant; // Timer variant -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(timer_callback_args_t *); // Pointer to callback timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/inc/instances/r_icu.h b/ra/fsp/inc/instances/r_icu.h index 016bd207f..e2defdac8 100644 --- a/ra/fsp/inc/instances/r_icu.h +++ b/ra/fsp/inc/instances/r_icu.h @@ -53,7 +53,6 @@ typedef struct st_icu_instance_ctrl uint8_t channel; ///< Channel #if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. #endif void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. diff --git a/ra/fsp/inc/instances/r_iic_master.h b/ra/fsp/inc/instances/r_iic_master.h index af53ed0a6..9197d2a03 100644 --- a/ra/fsp/inc/instances/r_iic_master.h +++ b/ra/fsp/inc/instances/r_iic_master.h @@ -90,10 +90,6 @@ typedef struct st_iic_master_instance_ctrl volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read iic_master_timeout_mode_t timeout_mode; // Holds the timeout mode value. i.e short mode or long mode -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(i2c_master_callback_args_t *); i2c_master_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_iic_slave.h b/ra/fsp/inc/instances/r_iic_slave.h index cd87a209b..3edcf3e39 100644 --- a/ra/fsp/inc/instances/r_iic_slave.h +++ b/ra/fsp/inc/instances/r_iic_slave.h @@ -76,10 +76,6 @@ typedef struct st_iic_slave_instance_ctrl volatile bool start_interrupt_enabled; // Tracks whether the start interrupt is enabled volatile bool transaction_completed; // Tracks whether previous transaction restarted -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(i2c_slave_callback_args_t *); i2c_slave_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_iwdt.h b/ra/fsp/inc/instances/r_iwdt.h index a3bda3154..f97174f80 100644 --- a/ra/fsp/inc/instances/r_iwdt.h +++ b/ra/fsp/inc/instances/r_iwdt.h @@ -51,9 +51,6 @@ typedef struct st_iwdt_instance_ctrl void const * p_context; ///< Placeholder for user data. Passed to the user callback in wdt_callback_args_t. R_IWDT_Type * p_reg; ///< Pointer to register base address. -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS). -#endif void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT NMI ISR occurs. wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. } iwdt_instance_ctrl_t; diff --git a/ra/fsp/inc/instances/r_lvd.h b/ra/fsp/inc/instances/r_lvd.h index c9d8edcde..fd3cf0e22 100644 --- a/ra/fsp/inc/instances/r_lvd.h +++ b/ra/fsp/inc/instances/r_lvd.h @@ -52,9 +52,6 @@ typedef struct st_lvd_instance_ctrl uint32_t open; lvd_cfg_t const * p_cfg; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(lvd_callback_args_t *); // Pointer to callback that is called when lvd_current_state_t changes. lvd_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. diff --git a/ra/fsp/inc/instances/r_poeg.h b/ra/fsp/inc/instances/r_poeg.h index 46b1b6915..3c740631a 100644 --- a/ra/fsp/inc/instances/r_poeg.h +++ b/ra/fsp/inc/instances/r_poeg.h @@ -52,9 +52,6 @@ typedef struct st_poeg_instance_ctrl const poeg_cfg_t * p_cfg; // Pointer to initial configurations R_GPT_POEG0_Type * p_reg; // Base register for this channel -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(poeg_callback_args_t *); // Pointer to callback poeg_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/inc/instances/r_qspi.h b/ra/fsp/inc/instances/r_qspi.h index 7b5240b25..33be85995 100644 --- a/ra/fsp/inc/instances/r_qspi.h +++ b/ra/fsp/inc/instances/r_qspi.h @@ -73,39 +73,38 @@ typedef enum e_qspi_qssl_min_high_level /* QSPCLK divider. */ typedef enum e_qspi_qspclk_div { - QSPI_QSPCLK_DIV_2, ///< QSPCLK = PCLK / 2 - QSPI_QSPCLK_DIV_3, ///< QSPCLK = PCLK / 3 - QSPI_QSPCLK_DIV_4, ///< QSPCLK = PCLK / 4 - QSPI_QSPCLK_DIV_5, ///< QSPCLK = PCLK / 5 - QSPI_QSPCLK_DIV_6, ///< QSPCLK = PCLK / 6 - QSPI_QSPCLK_DIV_7, ///< QSPCLK = PCLK / 7 - QSPI_QSPCLK_DIV_8, ///< QSPCLK = PCLK / 8 - QSPI_QSPCLK_DIV_9, ///< QSPCLK = PCLK / 9 - QSPI_QSPCLK_DIV_10, ///< QSPCLK = PCLK / 10 - QSPI_QSPCLK_DIV_11, ///< QSPCLK = PCLK / 11 - QSPI_QSPCLK_DIV_12, ///< QSPCLK = PCLK / 12 - QSPI_QSPCLK_DIV_13, ///< QSPCLK = PCLK / 13 - QSPI_QSPCLK_DIV_14, ///< QSPCLK = PCLK / 14 - QSPI_QSPCLK_DIV_15, ///< QSPCLK = PCLK / 15 - QSPI_QSPCLK_DIV_16, ///< QSPCLK = PCLK / 16 - QSPI_QSPCLK_DIV_17, ///< QSPCLK = PCLK / 17 - QSPI_QSPCLK_DIV_18, ///< QSPCLK = PCLK / 18 - QSPI_QSPCLK_DIV_19, ///< QSPCLK = PCLK / 19 - QSPI_QSPCLK_DIV_20, ///< QSPCLK = PCLK / 20 - QSPI_QSPCLK_DIV_22, ///< QSPCLK = PCLK / 22 - QSPI_QSPCLK_DIV_24, ///< QSPCLK = PCLK / 24 - QSPI_QSPCLK_DIV_26, ///< QSPCLK = PCLK / 26 - QSPI_QSPCLK_DIV_28, ///< QSPCLK = PCLK / 28 - QSPI_QSPCLK_DIV_30, ///< QSPCLK = PCLK / 30 - QSPI_QSPCLK_DIV_32, ///< QSPCLK = PCLK / 32 - QSPI_QSPCLK_DIV_34, ///< QSPCLK = PCLK / 34 - QSPI_QSPCLK_DIV_36, ///< QSPCLK = PCLK / 36 - QSPI_QSPCLK_DIV_38, ///< QSPCLK = PCLK / 38 - QSPI_QSPCLK_DIV_40, ///< QSPCLK = PCLK / 40 - QSPI_QSPCLK_DIV_42, ///< QSPCLK = PCLK / 42 - QSPI_QSPCLK_DIV_44, ///< QSPCLK = PCLK / 44 - QSPI_QSPCLK_DIV_46, ///< QSPCLK = PCLK / 46 - QSPI_QSPCLK_DIV_48, ///< QSPCLK = PCLK / 48 + QSPI_QSPCLK_DIV_2 = 0x0, ///< QSPCLK = PCLK / 2 + QSPI_QSPCLK_DIV_3 = 0x1, ///< QSPCLK = PCLK / 3 + QSPI_QSPCLK_DIV_4 = 0x2, ///< QSPCLK = PCLK / 4 + QSPI_QSPCLK_DIV_5 = 0x3, ///< QSPCLK = PCLK / 5 + QSPI_QSPCLK_DIV_6 = 0x4, ///< QSPCLK = PCLK / 6 + QSPI_QSPCLK_DIV_7 = 0x5, ///< QSPCLK = PCLK / 7 + QSPI_QSPCLK_DIV_8 = 0x6, ///< QSPCLK = PCLK / 8 + QSPI_QSPCLK_DIV_9 = 0x7, ///< QSPCLK = PCLK / 9 + QSPI_QSPCLK_DIV_10 = 0x8, ///< QSPCLK = PCLK / 10 + QSPI_QSPCLK_DIV_11 = 0x9, ///< QSPCLK = PCLK / 11 + QSPI_QSPCLK_DIV_12 = 0xA, ///< QSPCLK = PCLK / 12 + QSPI_QSPCLK_DIV_13 = 0xB, ///< QSPCLK = PCLK / 13 + QSPI_QSPCLK_DIV_14 = 0xC, ///< QSPCLK = PCLK / 14 + QSPI_QSPCLK_DIV_15 = 0xD, ///< QSPCLK = PCLK / 15 + QSPI_QSPCLK_DIV_16 = 0xE, ///< QSPCLK = PCLK / 16 + QSPI_QSPCLK_DIV_17 = 0xF, ///< QSPCLK = PCLK / 17 + QSPI_QSPCLK_DIV_18 = 0x10, ///< QSPCLK = PCLK / 18 + QSPI_QSPCLK_DIV_20 = 0x11, ///< QSPCLK = PCLK / 20 + QSPI_QSPCLK_DIV_22 = 0x12, ///< QSPCLK = PCLK / 22 + QSPI_QSPCLK_DIV_24 = 0x13, ///< QSPCLK = PCLK / 24 + QSPI_QSPCLK_DIV_26 = 0x14, ///< QSPCLK = PCLK / 26 + QSPI_QSPCLK_DIV_28 = 0x15, ///< QSPCLK = PCLK / 28 + QSPI_QSPCLK_DIV_30 = 0x16, ///< QSPCLK = PCLK / 30 + QSPI_QSPCLK_DIV_32 = 0x17, ///< QSPCLK = PCLK / 32 + QSPI_QSPCLK_DIV_34 = 0x18, ///< QSPCLK = PCLK / 34 + QSPI_QSPCLK_DIV_36 = 0x19, ///< QSPCLK = PCLK / 36 + QSPI_QSPCLK_DIV_38 = 0x1A, ///< QSPCLK = PCLK / 38 + QSPI_QSPCLK_DIV_40 = 0x1B, ///< QSPCLK = PCLK / 40 + QSPI_QSPCLK_DIV_42 = 0x1C, ///< QSPCLK = PCLK / 42 + QSPI_QSPCLK_DIV_44 = 0x1D, ///< QSPCLK = PCLK / 44 + QSPI_QSPCLK_DIV_46 = 0x1E, ///< QSPCLK = PCLK / 46 + QSPI_QSPCLK_DIV_48 = 0x1F, ///< QSPCLK = PCLK / 48 } qspi_qspclk_div_t; /* Extended configuration. */ diff --git a/ra/fsp/inc/instances/r_rtc.h b/ra/fsp/inc/instances/r_rtc.h index 8e23baad4..53fa2adf2 100644 --- a/ra/fsp/inc/instances/r_rtc.h +++ b/ra/fsp/inc/instances/r_rtc.h @@ -56,9 +56,6 @@ typedef struct st_rtc_ctrl const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations volatile bool carry_isr_triggered; ///< Was the carry isr triggered -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(rtc_callback_args_t *); // Pointer to callback that is called when a rtc_event_t occurs. rtc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. diff --git a/ra/fsp/inc/instances/r_sci_i2c.h b/ra/fsp/inc/instances/r_sci_i2c.h index 039b1d625..e35feb869 100644 --- a/ra/fsp/inc/instances/r_sci_i2c.h +++ b/ra/fsp/inc/instances/r_sci_i2c.h @@ -87,10 +87,6 @@ typedef struct st_sci_i2c_instance_ctrl volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt */ volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt */ -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(i2c_master_callback_args_t *); i2c_master_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_sci_spi.h b/ra/fsp/inc/instances/r_sci_spi.h index 795711285..c746736e6 100644 --- a/ra/fsp/inc/instances/r_sci_spi.h +++ b/ra/fsp/inc/instances/r_sci_spi.h @@ -70,10 +70,6 @@ typedef struct st_sci_spi_instance_ctrl uint32_t rx_count; uint32_t count; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(spi_callback_args_t *); spi_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_sci_uart.h b/ra/fsp/inc/instances/r_sci_uart.h index 7e9bae853..2bb698c0f 100644 --- a/ra/fsp/inc/instances/r_sci_uart.h +++ b/ra/fsp/inc/instances/r_sci_uart.h @@ -93,9 +93,6 @@ typedef struct st_sci_uart_instance_ctrl /* Base register for this channel */ R_SCI0_Type * p_reg; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. diff --git a/ra/fsp/inc/instances/r_spi.h b/ra/fsp/inc/instances/r_spi.h index 8da2cec98..b30c6448a 100644 --- a/ra/fsp/inc/instances/r_spi.h +++ b/ra/fsp/inc/instances/r_spi.h @@ -147,10 +147,6 @@ typedef struct st_spi_instance_ctrl uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(spi_callback_args_t *); spi_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_ssi.h b/ra/fsp/inc/instances/r_ssi.h index 1cfebe7c2..2489c844e 100644 --- a/ra/fsp/inc/instances/r_ssi.h +++ b/ra/fsp/inc/instances/r_ssi.h @@ -90,10 +90,6 @@ typedef struct st_ssi_instance_ctrl uint32_t rx_dest_samples; transfer_size_t fifo_access_size; // Access the FIFO as 1 byte, 2 bytes, or 4 bytes -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif - /* Pointer to callback and optional working memory */ void (* p_callback)(i2s_callback_args_t *); i2s_callback_args_t * p_callback_memory; diff --git a/ra/fsp/inc/instances/r_wdt.h b/ra/fsp/inc/instances/r_wdt.h index a7da66b35..ff82f2aa2 100644 --- a/ra/fsp/inc/instances/r_wdt.h +++ b/ra/fsp/inc/instances/r_wdt.h @@ -51,9 +51,6 @@ typedef struct st_wdt_instance_ctrl // called. void const * p_context; // Placeholder for user data. Passed to the user callback in // wdt_callback_args_t. -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS). -#endif void (* p_callback)(wdt_callback_args_t * p_args); // Callback provided when a WDT NMI ISR occurs. wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. } wdt_instance_ctrl_t; diff --git a/ra/fsp/inc/instances/rm_littlefs_flash.h b/ra/fsp/inc/instances/rm_littlefs_flash.h index beed2cafe..3839c39cd 100644 --- a/ra/fsp/inc/instances/rm_littlefs_flash.h +++ b/ra/fsp/inc/instances/rm_littlefs_flash.h @@ -27,6 +27,11 @@ #include "rm_littlefs_api.h" #include "r_flash_api.h" #include "lfs.h" +#if LFS_THREAD_SAFE + #include "FreeRTOS.h" + #include "semphr.h" + +#endif /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ FSP_HEADER @@ -56,6 +61,10 @@ typedef struct st_rm_littlefs_flash_instance_ctrl { uint32_t open; rm_littlefs_cfg_t const * p_cfg; +#if LFS_THREAD_SAFE + SemaphoreHandle_t xSemaphore; + StaticSemaphore_t xMutexBuffer; +#endif } rm_littlefs_flash_instance_ctrl_t; /********************************************************************************************************************** @@ -88,6 +97,10 @@ int rm_littlefs_flash_write(const struct lfs_config * c, int rm_littlefs_flash_erase(const struct lfs_config * c, lfs_block_t block); +int rm_littlefs_flash_lock(const struct lfs_config * c); + +int rm_littlefs_flash_unlock(const struct lfs_config * c); + int rm_littlefs_flash_sync(const struct lfs_config * c); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/instances/rm_vee_flash.h b/ra/fsp/inc/instances/rm_vee_flash.h index 48b19ab1d..9c04345b3 100644 --- a/ra/fsp/inc/instances/rm_vee_flash.h +++ b/ra/fsp/inc/instances/rm_vee_flash.h @@ -115,9 +115,6 @@ typedef struct st_rm_vee_flash_instance_ctrl flash_instance_t const * p_flash; uint32_t segment_size; -#if BSP_TZ_SECURE_BUILD - bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) -#endif void (* p_callback)(rm_vee_callback_args_t *); // Pointer to callback rm_vee_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory void const * p_context; // Pointer to context to be passed into callback function diff --git a/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a b/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a index 286bdd791..c4d861948 100644 Binary files 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a/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a b/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a index e432c6750..8b4a976ea 100644 Binary files a/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a and b/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a differ diff --git a/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a index 006b6642d..0c3c37cc3 100644 Binary files a/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a and b/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a differ diff --git a/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a index b238752f2..6621ddeb3 100644 Binary files a/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a and b/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a differ diff --git a/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a index f809f69fb..fdedcaa11 100644 Binary files a/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a and b/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a differ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h index 68983b5cb..2c37d6b71 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -17638,7 +17638,36 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED47[24]; + __IM uint32_t RESERVED47[8]; + + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[15]; union { @@ -17661,8 +17690,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED48; - __IM uint32_t RESERVED49[3]; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51[3]; union { @@ -17674,7 +17703,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED50; + __IM uint8_t RESERVED52; union { @@ -17689,8 +17718,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[7]; + __IM uint8_t RESERVED53; + __IM uint32_t RESERVED54[7]; union { @@ -17729,7 +17758,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED53; + __IM uint8_t RESERVED55; union { @@ -17743,7 +17772,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED54; + __IM uint8_t RESERVED56; union { @@ -17755,7 +17784,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED55; + __IM uint8_t RESERVED57; union { @@ -17890,9 +17919,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED56; - __IM uint16_t RESERVED57; - __IM uint32_t RESERVED58[15]; + __IM uint8_t RESERVED58; + __IM uint16_t RESERVED59; + __IM uint32_t RESERVED60[15]; union { @@ -28772,6 +28801,22 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure /* ======================================================== VBTCR1 ========================================================= */ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ /* ======================================================== SOSCCR ========================================================= */ #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd index 1d2bd186d..98e589681 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd @@ -71726,6 +71726,11 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang 0x01 registers + + 0x00000440 + 0x002 + registers + 0x00000480 0x002 @@ -75924,6 +75929,171 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang + + DCDCCTL + DCDC/LDO Control Register + 0x440 + 8 + read-write + 0xC0 + 0xFF + + + PD + DCDC VREF Generate Disable bit + 7 + 7 + read-write + + + 0 + DCDC VREF BIAS output enable + #0 + + + 1 + DCDC VREF BIAS output disable + #1 + + + + + FST + DCDC Fast Startup + 6 + 6 + read-write + + + 0 + The DCDC VREF BIAS is in low power mode + #0 + + + 1 + The DCDC VREF BIAS is in High-speed mode + #1 + + + + + LCBOOST + LDO LCBOOST Mode Control bit + 5 + 5 + read-write + + + 0 + LDO power mode is other than LCBOOST + #0 + + + 1 + LDO power mode is in LCBOOST + #1 + + + + + STOPZA + DCDC IO Buffer Power Control bit + 4 + 4 + read-write + + + 0 + DCDC IO buffer power down + #0 + + + 1 + DCDC IO buffer power up + #1 + + + + + OCPEN + DCDC OCP Function Enable bit + 1 + 1 + read-write + + + 0 + DCDC OCP (Over Current Protection) Function disable + #0 + + + 1 + DCDC OCP (Over Current Protection) Function enable + #1 + + + + + DCDCON + LDO/DCDC on/off Control bit + 0 + 0 + read-write + + + 0 + LDO is on and DCDC is off + #0 + + + 1 + LDO is off and DCDC is on + #1 + + + + + + + VCCSEL + Voltage Level Selection Control Register + 0x441 + 8 + read-write + 0x00 + 0xFF + + + VCCSEL + DCDC Working Voltage Level Selection + 0 + 1 + read-write + + + 00 + 2.7V <= VCC < 3.6V + #00 + + + 01 + 3.6V <= VCC < 4.5V + #01 + + + 10 + 4.5V <= VCC <= 5.5V + #10 + + + 11 + 2.4V <= VCC < 2.7V + #11 + + + + + SOSCCR Sub-Clock Oscillator Control Register diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c index 2a10e92eb..2a3b83f18 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -31,6 +31,11 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ +#if BSP_TZ_SECURE_BUILD + #define BSP_TZ_STACK_SEAL_SIZE (8U) +#else + #define BSP_TZ_STACK_SEAL_SIZE (0U) +#endif /*********************************************************************************************************************** * Typedef definitions @@ -80,8 +85,8 @@ void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) BSP_PLACE_IN_SECTION( - BSP_SECTION_STACK); +static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); /* Heap */ #if (BSP_CFG_HEAP_BYTES > 0) diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index 60815a7c8..ae94d35c5 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -57,6 +57,8 @@ #define BSP_PRV_STACK_TOP ((uint32_t) &__StackTop) #endif +#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -148,8 +150,21 @@ void SystemInit (void) SCB->CPACR = (uint32_t) CP_MASK; #endif -/* Set the Secure/Non-Secure VTOR to the vector table address based on the build. */ -#if FSP_PRIV_TZ_USE_SECURE_REGS +#if BSP_TZ_SECURE_BUILD + + /* Seal the main stack for secure projects. Reference: + * https://developer.arm.com/documentation/100720/0300 + * https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */ + uint32_t * p_main_stack = (uint32_t *) __Vectors[0]; + p_main_stack[BSP_CFG_STACK_MAIN_BYTES / sizeof(uint32_t)] = BSP_TZ_STACK_SEAL_VALUE; +#endif + +#if !BSP_TZ_NONSECURE_BUILD + + /* VTOR is in undefined state out of RESET: + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en. + * Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure + * projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */ SCB->VTOR = (uint32_t) &__Vectors; #endif @@ -295,6 +310,8 @@ void SystemInit (void) #endif #endif +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Ensure that the PMSAR registers are reset (Soft reset does not reset PMSAR). */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); @@ -302,8 +319,8 @@ void SystemInit (void) { R_PMISC->PMSAR[i].PMSAR = UINT16_MAX; } - R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif #if BSP_TZ_SECURE_BUILD diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index c532c2e3d..b924c1283 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -100,6 +100,17 @@ #endif #endif +/* Choose the value to write to FLLCR2 (if applicable). */ +#if BSP_PRV_HOCO_USE_FLL + #if 0U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x1E9U) + #elif 1U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x226U) + #elif 2U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x263U) + #endif +#endif + /* Calculate the value to write to SCKDIVCR. */ #define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 7U) << 24U) #if BSP_FEATURE_CGC_HAS_PCLKD @@ -362,6 +373,20 @@ static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode) **********************************************************************************************************************/ void bsp_prv_operating_mode_set (uint8_t operating_mode) { + #if BSP_PRV_POWER_USE_DCDC + static bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; + + /* Disable DCDC if transitioning to an incompatible mode. */ + if ((operating_mode > BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk)) + { + /* LDO boost must be used if entering subclock speed mode (see RA2L1 User's Manual (R01UH0853EJ0100) Section + * 10.5.1 (5) Switching from High-speed/Middle-speed mode in DCDC power mode to Subosc-speed mode or Software + * Standby mode). */ + power_mode = R_BSP_PowerModeSet((BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) ? + BSP_POWER_MODE_LDO_BOOST : BSP_POWER_MODE_LDO); + } + #endif + if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) { /* Wait for transition to complete. */ @@ -388,6 +413,16 @@ void bsp_prv_operating_mode_set (uint8_t operating_mode) bsp_prv_operating_mode_opccr_set(operating_mode); } + + #if BSP_PRV_POWER_USE_DCDC + + /* Enable DCDC if it was previously enabled. */ + if ((operating_mode <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (power_mode < BSP_POWER_MODE_LDO)) + { + R_BSP_PowerModeSet(power_mode); + power_mode = BSP_POWER_MODE_LDO; + } + #endif } #endif @@ -749,9 +784,9 @@ void bsp_clock_init (void) /* Configure the subclock drive if the subclock is not already running. */ R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); R_SYSTEM->SOSCCR = 0U; - #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) - /* If the subclock is the system clock source, wait for it to stabilize. */ + /* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */ R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS); #endif } @@ -807,6 +842,14 @@ void bsp_clock_init (void) #endif #endif + /* The FLL function can only be used when the subclock is running. */ +#if BSP_PRV_HOCO_USE_FLL + + /* If FLL is to be used configure FLLCR1 and FLLCR2 before starting HOCO. */ + R_SYSTEM->FLLCR2 = BSP_PRV_FLL_FLLCR2; + R_SYSTEM->FLLCR1 = 1U; +#endif + /* If the PLL is the desired source clock, ensure the source clock is running and stable and the power mode * allows PLL operation. */ #if BSP_PRV_PLL_SUPPORTED @@ -838,6 +881,11 @@ void bsp_clock_init (void) /* Verify PLL source is stable before starting PLL. */ #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #if BSP_PRV_HOCO_USE_FLL + + /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif /* Wait for HOCO to stabilize. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); @@ -853,6 +901,12 @@ void bsp_clock_init (void) #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE R_SYSTEM->HOCOCR = 0U; + #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE) + + /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + /* Wait for HOCO to stabilize. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); #elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE @@ -920,6 +974,13 @@ void bsp_clock_init (void) #endif #endif +#if defined(BSP_PRV_POWER_USE_DCDC) && (BSP_PRV_POWER_USE_DCDC == BSP_PRV_POWER_DCDC_STARTUP) && \ + (BSP_PRV_STARTUP_OPERATING_MODE <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) + + /* Start DCDC as part of BSP startup when configured (BSP_CFG_DCDC_ENABLE == 2). */ + R_BSP_PowerModeSet(BSP_CFG_DCDC_VOLTAGE_RANGE); +#endif + /* Configure BCLK if it exists on the MCU. */ #ifdef BSP_CFG_BCLK_OUTPUT #if BSP_CFG_BCLK_OUTPUT > 0U @@ -952,20 +1013,31 @@ void bsp_clock_init (void) #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED - /* Start PLL source clock. */ - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + /* Start PLL2 source clock. */ + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE) && \ + (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_CLOCK_SOURCE) R_SYSTEM->HOCOCR = 0U; - #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE + + #if BSP_PRV_HOCO_USE_FLL + + /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE && \ + (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC != BSP_CFG_PLL_SOURCE) && \ + (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC != BSP_CFG_CLOCK_SOURCE) R_SYSTEM->MOSCCR = 0U; FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); #endif /* BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE */ R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; - /* Start the PLL. */ + /* Start PLL2. */ R_SYSTEM->PLL2CR = 0U; - /* Wait for the PLL to stabilize. */ + /* Wait for PLL2 to stabilize. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 1U); #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index ca4764ebe..04b86941f 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -244,6 +244,17 @@ FSP_HEADER BSP_PRV_SCKDIVCR_PCLKA_MASK) | \ BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK) +/* FLL is only used when enabled, present and the subclock is populated. */ +#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_PRV_HOCO_USE_FLL (1) + #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US + #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) + #endif +#else + #define BSP_PRV_HOCO_USE_FLL (0) + #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) +#endif + /* Operating power control modes. */ #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c index 7f0e72ff1..910061e4e 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_security.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -23,7 +23,7 @@ **********************************************************************************************************************/ #include "bsp_api.h" -#if BSP_TZ_SECURE_BUILD +#if BSP_FEATURE_TZ_HAS_TRUSTZONE /*********************************************************************************************************************** * Macro definitions @@ -54,7 +54,7 @@ typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void); typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); #endif - #if defined(__IAR_SYSTEMS_ICC__) + #if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD #pragma section=".tz_flash_nsc_start" #pragma section=".tz_flash_ns_start" #pragma section=".tz_ram_nsc_start" @@ -102,23 +102,35 @@ extern const uint32_t Image$$__tz_OSPI_DEVICE_0_N$$Base; extern const uint32_t Image$$__tz_OSPI_DEVICE_0_S$$Base; extern const uint32_t Image$$__tz_OSPI_DEVICE_1_N$$Base; extern const uint32_t Image$$__tz_OSPI_DEVICE_1_S$$Base; - - #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base - #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base - #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base - #define __tz_RAM_N Image$$__tz_RAM_N$$Base - #define __tz_RAM_C Image$$__tz_RAM_C$$Base - #define __tz_RAM_S Image$$__tz_RAM_S$$Base - #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base - #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base - #define __tz_QSPI_FLASH_N Image$$__tz_QSPI_FLASH_N$$Base - #define __tz_QSPI_FLASH_S Image$$__tz_QSPI_FLASH_S$$Base - #define __tz_SDRAM_N Image$$__tz_SDRAM_N$$Base - #define __tz_SDRAM_S Image$$__tz_SDRAM_S$$Base - #define __tz_OSPI_DEVICE_0_N Image$$__tz_OSPI_DEVICE_0_N$$Base - #define __tz_OSPI_DEVICE_0_S Image$$__tz_OSPI_DEVICE_0_S$$Base - #define __tz_OSPI_DEVICE_1_N Image$$__tz_OSPI_DEVICE_1_N$$Base - #define __tz_OSPI_DEVICE_1_S Image$$__tz_OSPI_DEVICE_1_S$$Base +extern const uint32_t Image$$__tz_OPTION_SETTING_N$$Base; +extern const uint32_t Image$$__tz_OPTION_SETTING_S$$Base; +extern const uint32_t Image$$__tz_OPTION_SETTING_S_N$$Base; +extern const uint32_t Image$$__tz_OPTION_SETTING_S_S$$Base; +extern const uint32_t Image$$__tz_ID_CODE_N$$Base; +extern const uint32_t Image$$__tz_ID_CODE_S$$Base; + + #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base + #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base + #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base + #define __tz_RAM_N Image$$__tz_RAM_N$$Base + #define __tz_RAM_C Image$$__tz_RAM_C$$Base + #define __tz_RAM_S Image$$__tz_RAM_S$$Base + #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base + #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base + #define __tz_QSPI_FLASH_N Image$$__tz_QSPI_FLASH_N$$Base + #define __tz_QSPI_FLASH_S Image$$__tz_QSPI_FLASH_S$$Base + #define __tz_SDRAM_N Image$$__tz_SDRAM_N$$Base + #define __tz_SDRAM_S Image$$__tz_SDRAM_S$$Base + #define __tz_OSPI_DEVICE_0_N Image$$__tz_OSPI_DEVICE_0_N$$Base + #define __tz_OSPI_DEVICE_0_S Image$$__tz_OSPI_DEVICE_0_S$$Base + #define __tz_OSPI_DEVICE_1_N Image$$__tz_OSPI_DEVICE_1_N$$Base + #define __tz_OSPI_DEVICE_1_S Image$$__tz_OSPI_DEVICE_1_S$$Base + #define __tz_OPTION_SETTING_N Image$$__tz_OPTION_SETTING_N$$Base + #define __tz_OPTION_SETTING_S Image$$__tz_OPTION_SETTING_S$$Base + #define __tz_OPTION_SETTING_S_N Image$$__tz_OPTION_SETTING_S_N$$Base + #define __tz_OPTION_SETTING_S_S Image$$__tz_OPTION_SETTING_S_S$$Base + #define __tz_ID_CODE_N Image$$__tz_ID_CODE_N$$Base + #define __tz_ID_CODE_S Image$$__tz_ID_CODE_S$$Base /* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the * start addresses of Secure, Non-secure and Non-secure Callable regions. */ @@ -130,19 +142,33 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = &_ BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ram = &__tz_RAM_S; BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = &__tz_DATA_FLASH_N; BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_data_flash = &__tz_DATA_FLASH_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_qspi_flash = &__tz_QSPI_FLASH_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_qspi_flash = &__tz_QSPI_FLASH_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_sdram = &__tz_SDRAM_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_sdram = &__tz_SDRAM_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_0 = &__tz_OSPI_DEVICE_0_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_0 = &__tz_OSPI_DEVICE_0_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_1 = &__tz_OSPI_DEVICE_1_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_1 = &__tz_OSPI_DEVICE_1_S; + + #if BSP_TZ_SECURE_BUILD + +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_qspi_flash = &__tz_QSPI_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_qspi_flash = &__tz_QSPI_FLASH_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_sdram = &__tz_SDRAM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_sdram = &__tz_SDRAM_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_0 = &__tz_OSPI_DEVICE_0_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_0 = &__tz_OSPI_DEVICE_0_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_1 = &__tz_OSPI_DEVICE_1_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_1 = &__tz_OSPI_DEVICE_1_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_option_setting = &__tz_OPTION_SETTING_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_option_setting = &__tz_OPTION_SETTING_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_option_setting_s = &__tz_OPTION_SETTING_S_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_option_setting_s = &__tz_OPTION_SETTING_S_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_id_code = &__tz_ID_CODE_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code = &__tz_ID_CODE_S; + + #endif + #elif defined(__GNUC__) extern const uint32_t __tz_FLASH_N; BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; #endif + #if BSP_TZ_SECURE_BUILD + /*******************************************************************************************************************//** * @addtogroup BSP_MCU * @{ @@ -192,7 +218,7 @@ void R_BSP_SecurityInit (void) /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the * SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */ - #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ @@ -202,9 +228,9 @@ void R_BSP_SecurityInit (void) ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif + #endif - #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) /* Configure whether the FPU can be accessed in the non-secure project. */ @@ -217,7 +243,7 @@ void R_BSP_SecurityInit (void) ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); - #endif + #endif /* Disable PRCR for SARs. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); @@ -257,7 +283,7 @@ void R_BSP_SecurityInit (void) R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ - #if BSP_TZ_CFG_ICUSARC != UINT32_MAX + #if BSP_TZ_CFG_ICUSARC != UINT32_MAX R_BSP_MODULE_START(FSP_IP_DMAC, 0); /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST @@ -266,9 +292,9 @@ void R_BSP_SecurityInit (void) /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ R_DMA->DMAST = 1U; - #endif + #endif - #if BSP_TZ_CFG_DTC_USED + #if BSP_TZ_CFG_DTC_USED R_BSP_MODULE_START(FSP_IP_DTC, 0); /* If the DTC is used by the secure program, disable nonsecure write access to DTCST @@ -277,7 +303,7 @@ void R_BSP_SecurityInit (void) /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ R_DTC->DTCST = 1U; - #endif + #endif /* Initialize security attribution registers for Pins. */ R_BSP_PinCfgSecurityInit(); @@ -299,40 +325,5 @@ BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void) { } -#else - - #if defined(__ARMCC_VERSION) && BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* These symbols are required to allocate non-secure memory in flat projects on MCUs that support TrustZone. */ - -extern const uint32_t Image$$__tz_FLASH_N$$Base; -extern const uint32_t Image$$__tz_FLASH_C$$Base; -extern const uint32_t Image$$__tz_FLASH_S$$Base; -extern const uint32_t Image$$__tz_RAM_N$$Base; -extern const uint32_t Image$$__tz_RAM_C$$Base; -extern const uint32_t Image$$__tz_RAM_S$$Base; -extern const uint32_t Image$$__tz_DATA_FLASH_N$$Base; -extern const uint32_t Image$$__tz_DATA_FLASH_S$$Base; - - #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base - #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base - #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base - #define __tz_RAM_N Image$$__tz_RAM_N$$Base - #define __tz_RAM_C Image$$__tz_RAM_C$$Base - #define __tz_RAM_S Image$$__tz_RAM_S$$Base - #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base - #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base - -/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the - * start addresses of Secure, Non-secure and Non-secure Callable regions. */ -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = &__tz_RAM_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = &__tz_RAM_C; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ram = &__tz_RAM_S; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = &__tz_DATA_FLASH_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_data_flash = &__tz_DATA_FLASH_S; #endif - #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index a596b7994..53a41946e 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -100,6 +100,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. @@ -119,6 +120,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) #define BSP_FEATURE_CGC_HAS_PCLKA (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h new file mode 100644 index 000000000..c33f235a0 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h @@ -0,0 +1,218 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2L1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra2l1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x1), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x2), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x3), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x4), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x5), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x6), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x7), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x8), // External pin interrupt 7 + ELC_EVENT_DTC_COMPLETE = (0x9), // DTC last transfer + ELC_EVENT_DTC_END = (0xA), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0xB), // Canceling from Snooze mode + ELC_EVENT_FCU_FRDYI = (0xC), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0xD), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0xE), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0xF), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x10), // Snooze entry + ELC_EVENT_AGT0_INT = (0x11), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x12), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x13), // Compare match B + ELC_EVENT_AGT1_INT = (0x14), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x15), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x16), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x17), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x18), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x19), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x1A), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x1B), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x1C), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x1D), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x1E), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x1F), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x20), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x21), // Compare mismatch + ELC_EVENT_ACMPLP0_INT = (0x23), // Analog Comparator Channel 0 interrupt + ELC_EVENT_ACMPLP1_INT = (0x24), // Analog Comparator Channel 1 interrupt= + ELC_EVENT_IIC0_RXI = (0x27), // Receive data full + ELC_EVENT_IIC0_TXI = (0x28), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x29), // Transmit end + ELC_EVENT_IIC0_ERI = (0x2A), // Transfer error + ELC_EVENT_IIC0_WUI = (0x2B), // Slave address match + ELC_EVENT_IIC1_RXI = (0x2C), // Receive data full + ELC_EVENT_IIC1_TXI = (0x2D), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x2E), // Transmit end + ELC_EVENT_IIC1_ERI = (0x2F), // Transfer error + ELC_EVENT_CTSU_WRITE = (0x30), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x31), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x32), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x33), // Key interrupt + ELC_EVENT_DOC_INT = (0x34), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x35), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x36), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x37), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x38), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x39), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x3A), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x3B), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x3C), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x3D), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x3E), // Port 2 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x3F), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x40), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x41), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x42), // Port Output disable interrupt B + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x46), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x47), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x48), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x49), // Compare match D + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x4A), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x4B), // Underflow + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x4C), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x4D), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x4E), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x4F), // Compare match D + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x50), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x51), // Underflow + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x52), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x53), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x54), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x55), // Compare match D + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x56), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x57), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x58), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x59), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x5A), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x5B), // Compare match D + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x5C), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x5D), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x5E), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x5F), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x60), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x61), // Compare match D + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x62), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x63), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x64), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x65), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x66), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x67), // Compare match D + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x68), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x69), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x6A), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x6B), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x6C), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x6D), // Compare match D + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x6E), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x6F), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x70), // UVW edge event + ELC_EVENT_SCI0_RXI = (0x71), // Receive data full + ELC_EVENT_SCI0_TXI = (0x72), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x73), // Transmit end + ELC_EVENT_SCI0_ERI = (0x74), // Receive error + ELC_EVENT_SCI0_AM = (0x75), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x76), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x77), // Received data full + ELC_EVENT_SCI1_TXI = (0x78), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x79), // Transmit end + ELC_EVENT_SCI1_ERI = (0x7A), // Receive error + ELC_EVENT_SCI1_AM = (0x7B), // Address match event + ELC_EVENT_SCI9_RXI = (0x7C), // Received data full + ELC_EVENT_SCI9_TXI = (0x7D), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x7E), // Transmit end + ELC_EVENT_SCI9_ERI = (0x7F), // Receive error + ELC_EVENT_SCI9_AM = (0x80), // Address match event + ELC_EVENT_SPI0_RXI = (0x81), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x82), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x83), // Idle + ELC_EVENT_SPI0_ERI = (0x84), // Error + ELC_EVENT_SPI0_TEI = (0x85), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x86), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x87), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x88), // Idle + ELC_EVENT_SPI1_ERI = (0x89), // Error + ELC_EVENT_SPI1_TEI = (0x8A), // Transmission complete event + ELC_EVENT_AES_WRREQ = (0x8B), + ELC_EVENT_AES_RDREQ = (0x8C), + ELC_EVENT_TRNG_RDREQ = (0x8D), + ELC_EVENT_SCI2_RXI = (0x8E), // Receive data full + ELC_EVENT_SCI2_TXI = (0x8F), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x90), // Transmit end + ELC_EVENT_SCI2_ERI = (0x91), // Receive error + ELC_EVENT_SCI2_AM = (0x92), // Address match event + ELC_EVENT_SCI3_RXI = (0x93), // Receive data full + ELC_EVENT_SCI3_TXI = (0x94), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x95), // Transmit end + ELC_EVENT_SCI3_ERI = (0x96), // Receive error + ELC_EVENT_SCI3_AM = (0x97), // Address match event + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x98), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x99), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x9A), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x9B), // Compare match D + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x9C), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x9D), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x9E), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x9F), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0xA0), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0xA1), // Compare match D + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0xA2), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0xA3), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0xA4), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0xA5), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0xA6), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0xA7), // Compare match D + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0xA8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0xA9), // Underflow +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA2L1) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h new file mode 100644 index 000000000..da0751794 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -0,0 +1,285 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (9999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#else + #define CGC_MAINCLOCK_DRIVE (0x01U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKD) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3300) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F7FFF) // 0 to 14, 16 (ADCTDR) 17 to 20 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (1) + +#define BSP_FEATURE_BSP_FLASH_CACHE (0) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (1U) +#define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01001C00U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (1U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) +#define BSP_FEATURE_CGC_HAS_FCLK (0U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_FLL (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (0U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (0U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (0U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) // This MCU does have Low Speed Mode, up to 2 MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (24000000U) // This MCU does have Middle Speed Mode, up to 24 MHz +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (0U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (4U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (4U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (2) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU + +#define BSP_FEATURE_DWT_CYCCNT (0U) + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004D30FU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_ICLK) // RA2L1 Flash uses ICLK +#define BSP_FEATURE_FLASH_LP_VERSION (4) +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FF) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (2) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) // Feature not available on this MCU + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x20FU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0) // Feature not available on this MCU + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h new file mode 100644 index 000000000..9993efda7 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h @@ -0,0 +1,207 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ICU_H +#define BSP_ICU_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2L1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events to be used with the IELSR register to link interrupt events to the NVIC + * @note This list is device specific. + * */ +typedef enum e_icu_event_ra2l1 +{ + ICU_EVENT_ACMPLP0_INT = (0x09), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ACMPLP1_INT = (0x07), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ADC0_COMPARE_MATCH = (0x08), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ADC0_COMPARE_MISMATCH = (0x06), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ADC0_SCAN_END = (0x07), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ADC0_SCAN_END_B = (0x05), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ADC0_WINDOW_A = (0x05), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ADC0_WINDOW_B = (0x05), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_AES_RDREQ = (0x12), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_AES_WRREQ = (0x15), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_AGT0_COMPARE_A = (0x16), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_AGT0_COMPARE_B = (0x13), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_AGT0_INT = (0x11), // group3 (IELSR3/11/19/27) + ICU_EVENT_AGT1_COMPARE_A = (0x03), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_AGT1_COMPARE_B = (0x03), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_AGT1_INT = (0x05), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_CAC_FREQUENCY_ERROR = (0x0B), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_CAC_MEASUREMENT_END = (0x08), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_CAC_OVERFLOW = (0x08), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_CAN0_ERROR = (0x0C), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_CAN0_FIFO_RX = (0x0C), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_CAN0_FIFO_TX = (0x09), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_CAN0_MAILBOX_RX = (0x09), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_CAN0_MAILBOX_TX = (0x0D), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_CTSU_END = (0x07), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_CTSU_READ = (0x07), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_CTSU_WRITE = (0x09), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_DOC_INT = (0x0A), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_DTC_COMPLETE = (0x02), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0A), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0A), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_FCU_FRDYI = (0x02), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0E), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0D), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_GPT0_COMPARE_C = (0x0C), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT0_COMPARE_D = (0x0C), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_GPT0_COUNTER_OVERFLOW = (0x0F), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0E), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_GPT1_CAPTURE_COMPARE_A = (0x19), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT1_CAPTURE_COMPARE_B = (0x16), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT1_COMPARE_C = (0x14), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT1_COMPARE_D = (0x12), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT1_COUNTER_OVERFLOW = (0x18), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT1_COUNTER_UNDERFLOW = (0x15), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT2_CAPTURE_COMPARE_A = (0x10), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0F), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_GPT2_COMPARE_C = (0x0D), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT2_COMPARE_D = (0x0D), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_GPT2_COUNTER_OVERFLOW = (0x0E), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0E), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_GPT3_CAPTURE_COMPARE_A = (0x19), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT3_CAPTURE_COMPARE_B = (0x16), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT3_COMPARE_C = (0x15), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT3_COMPARE_D = (0x12), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT3_COUNTER_OVERFLOW = (0x1A), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT3_COUNTER_UNDERFLOW = (0x17), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT4_CAPTURE_COMPARE_A = (0x1B), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT4_CAPTURE_COMPARE_B = (0x18), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT4_COMPARE_C = (0x15), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT4_COMPARE_D = (0x13), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT4_COUNTER_OVERFLOW = (0x16), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT4_COUNTER_UNDERFLOW = (0x13), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT5_CAPTURE_COMPARE_A = (0x1A), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT5_CAPTURE_COMPARE_B = (0x17), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT5_COMPARE_C = (0x17), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT5_COMPARE_D = (0x14), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT5_COUNTER_OVERFLOW = (0x16), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT5_COUNTER_UNDERFLOW = (0x14), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT6_CAPTURE_COMPARE_A = (0x1C), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT6_CAPTURE_COMPARE_B = (0x19), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT6_COMPARE_C = (0x17), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT6_COMPARE_D = (0x15), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT6_COUNTER_OVERFLOW = (0x18), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT6_COUNTER_UNDERFLOW = (0x15), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT7_CAPTURE_COMPARE_A = (0x1B), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT7_CAPTURE_COMPARE_B = (0x18), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT7_COMPARE_C = (0x19), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT7_COMPARE_D = (0x16), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT7_COUNTER_OVERFLOW = (0x18), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT7_COUNTER_UNDERFLOW = (0x16), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT8_CAPTURE_COMPARE_A = (0x1D), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT8_CAPTURE_COMPARE_B = (0x1A), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT8_COMPARE_C = (0x19), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT8_COMPARE_D = (0x17), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT8_COUNTER_OVERFLOW = (0x1A), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT8_COUNTER_UNDERFLOW = (0x17), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT9_CAPTURE_COMPARE_A = (0x1C), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT9_CAPTURE_COMPARE_B = (0x19), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT9_COMPARE_C = (0x1B), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT9_COMPARE_D = (0x18), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT9_COUNTER_OVERFLOW = (0x1A), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT9_COUNTER_UNDERFLOW = (0x18), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT_UVWEDGE = (0x11), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ0 = (0x01), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ1 = (0x01), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ICU_IRQ2 = (0x01), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ICU_IRQ3 = (0x01), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_ICU_IRQ4 = (0x16), // group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ5 = (0x13), // group5 (IELSR5/13/21/29) + ICU_EVENT_ICU_IRQ6 = (0x13), // group6 (IELSR6/14/22/30) + ICU_EVENT_ICU_IRQ7 = (0x11), // group7 (IELSR7/15/23/31) + ICU_EVENT_ICU_SNOOZE_CANCEL = (0x03), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IIC0_ERI = (0x06), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_IIC0_RXI = (0x0A), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IIC0_TEI = (0x06), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_IIC0_TXI = (0x08), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_IIC0_WUI = (0x0B), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IIC1_ERI = (0x14), // group5 (IELSR5/13/21/29) + ICU_EVENT_IIC1_RXI = (0x17), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_IIC1_TEI = (0x17), // group4 (IELSR4/12/20/28) + ICU_EVENT_IIC1_TXI = (0x14), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_IOPORT_EVENT_1 = (0x15), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_IOPORT_EVENT_2 = (0x13), // group2 (IELSR2/10/18/26) + ICU_EVENT_IWDT_UNDERFLOW = (0x03), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_KEY_INT = (0x18), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_LPM_SNOOZE_REQUEST = (0x02), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_LVD_LVD1 = (0x04), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_LVD_LVD2 = (0x02), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_MOSC_STOP = (0x14), // group6 (IELSR6/14/22/30) + ICU_EVENT_POEG0_EVENT = (0x0B), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_POEG1_EVENT = (0x0B), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_RTC_ALARM = (0x04), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_RTC_CARRY = (0x04), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_RTC_PERIOD = (0x04), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SCI0_AM = (0x13), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SCI0_ERI = (0x0F), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_SCI0_RXI = (0x12), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SCI0_TEI = (0x0F), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SCI0_TXI = (0x10), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_SCI1_AM = (0x1A), // group5 (IELSR5/13/21/29) + ICU_EVENT_SCI1_ERI = (0x19), // group3 (IELSR3/11/19/27) + ICU_EVENT_SCI1_RXI = (0x1E), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_SCI1_TEI = (0x1B), // group2 (IELSR2/10/18/26) + ICU_EVENT_SCI1_TXI = (0x1B), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_SCI2_AM = (0x1C), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_SCI2_ERI = (0x19), // group7 (IELSR7/15/23/31) + ICU_EVENT_SCI2_RXI = (0x1D), // group4 (IELSR4/12/20/28) + ICU_EVENT_SCI2_TEI = (0x1C), // group6 (IELSR6/14/22/30) + ICU_EVENT_SCI2_TXI = (0x1B), // group5 (IELSR5/13/21/29) + ICU_EVENT_SCI3_AM = (0x1D), // group6 (IELSR6/14/22/30) + ICU_EVENT_SCI3_ERI = (0x1A), // group3 (IELSR3/11/19/27) + ICU_EVENT_SCI3_RXI = (0x1F), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_SCI3_TEI = (0x1C), // group2 (IELSR2/10/18/26) + ICU_EVENT_SCI3_TXI = (0x1D), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_SCI9_AM = (0x1B), // group3 (IELSR3/11/19/27) + ICU_EVENT_SCI9_ERI = (0x1A), // group7 (IELSR7/15/23/31) + ICU_EVENT_SCI9_RXI = (0x1E), // group4 (IELSR4/12/20/28) + ICU_EVENT_SCI9_TEI = (0x1E), // group6 (IELSR6/14/22/30) + ICU_EVENT_SCI9_TXI = (0x1C), // group5 (IELSR5/13/21/29) + ICU_EVENT_SPI0_ERI = (0x10), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_SPI0_IDLE = (0x10), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SPI0_RXI = (0x14), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SPI0_TEI = (0x11), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SPI0_TXI = (0x11), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_SPI1_ERI = (0x1B), // group7 (IELSR7/15/23/31) + ICU_EVENT_SPI1_IDLE = (0x1D), // group2 (IELSR2/10/18/26) + ICU_EVENT_SPI1_RXI = (0x1F), // group4 (IELSR4/12/20/28) + ICU_EVENT_SPI1_TEI = (0x1F), // group6 (IELSR6/14/22/30) + ICU_EVENT_SPI1_TXI = (0x1D), // group5 (IELSR5/13/21/29) + ICU_EVENT_TRNG_RDREQ = (0x12), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_WDT_UNDERFLOW = (0x06), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) +} icu_event_t; + +/** @} (end addtogroup BSP_MCU_RA2L1) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h new file mode 100644 index 000000000..15abdca1b --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA2L1 RA2L1 + * @includedoc config_bsp_ra2l1_fsp.html + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_icu.h" +#include "bsp_feature.h" +#include "bsp_power.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef icu_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end defgroup BSP_MCU_RA2L1) */ diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c new file mode 100644 index 000000000..9e2fba8a7 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c @@ -0,0 +1,170 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#include "bsp_api.h" + +#if BSP_PRV_POWER_USE_DCDC + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_PRV_LDO_STABILIZATION_TIME_US (60U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Switch from DCDC to LDO. Requires LPM register protection and interrupts to be disabled. + * + * This function follows the procedure given in the RA2L1 User's Manual (R01UH0853EJ0100) Section 10.5.1 (4) "Switching + * from High-speed/Middle-speed mode (DCDC power mode) to High-speed/Middle-speed mode (LDO power mode)" + **********************************************************************************************************************/ +static inline void bsp_power_dcdc_disable (bsp_power_mode_t mode) +{ + /* Save all module stop bits, then stop all peripherals. */ + uint32_t mstpcrb = R_MSTP->MSTPCRB; + R_MSTP->MSTPCRB = UINT32_MAX; + uint32_t mstpcrc = R_MSTP->MSTPCRC; + R_MSTP->MSTPCRC = UINT32_MAX; + uint32_t mstpcrd = R_MSTP->MSTPCRD; + R_MSTP->MSTPCRD = UINT32_MAX; + + /* Switch to LDO. */ + R_SYSTEM->DCDCCTL = (uint8_t) mode; + + /* Wait for LDO to stabilize. */ + R_BSP_SoftwareDelay(BSP_PRV_LDO_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Restore all module stop bits. */ + R_MSTP->MSTPCRB = mstpcrb; + R_MSTP->MSTPCRC = mstpcrc; + R_MSTP->MSTPCRD = mstpcrd; +} + +/*********************************************************************************************************************** + * Switch from LDO to DCDC. Requires LPM register protection and interrupts to be disabled. + * + * This function follows the procedure given in the RA2L1 User's Manual (R01UH0853EJ0100) Section 10.5.1 (3) "Switching + * from the High-Speed/Middle-Speed mode (LDO power mode) to the High-speed/Middle speed mode (DCDC power mode)" + **********************************************************************************************************************/ +static inline void bsp_power_dcdc_enable () +{ + /* Enable DCDC IO buffer. */ + uint8_t dcdcctl = R_SYSTEM->DCDCCTL | R_SYSTEM_DCDCCTL_STOPZA_Msk; + R_SYSTEM->DCDCCTL = dcdcctl; + + /* Turn on DCDC Vref. */ + R_SYSTEM->DCDCCTL = dcdcctl & (uint8_t) (~R_SYSTEM_DCDCCTL_PD_Msk); + + /* Wait for Vref to stabilize. */ + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MICROSECONDS); + + /* Switch DCDC Vref to low-power mode. */ + R_SYSTEM->DCDCCTL = 0x10; + + /* Wait for Vref to stabilize. */ + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MICROSECONDS); + + /* Turn off LDO and turn on DCDC. */ + R_SYSTEM->DCDCCTL = 0x11; + + /* Wait for DCDC to stabilize. */ + R_BSP_SoftwareDelay(2, BSP_DELAY_UNITS_MICROSECONDS); + + /* Enable DCDC overcurrent protection. */ + R_SYSTEM->DCDCCTL = 0x13; +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2L1 + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Select either the LDO or DCDC regulator and/or update the MCU supply voltage range. Returns the previously selected + * mode. + * + * @note DCDC mode has the following limitations: + * - Supply voltage must be 2.4V or greater + * - Low- and Subosc-speed modes are not available + * - Software Standby is not available + * Ensure these limitations are respected before entering DCDC mode. If supply voltage may drop below 2.4V during + * operation, configure a LVD channel to interrupt or reset the MCU near this threshold to switch back to the LDO. + * + * @note Switching to DCDC mode temporarily disables all interrupts and blocks for 22 microseconds; switching to LDO + * from DCDC temporarily disables all peripherals and interrupts and blocks for 60 microseconds. + * + * @note If the supply voltage falls outside the range originally specified when starting the DCDC regulator, call this + * function again with the updated supply voltage. + * + * @return The previously selected power mode. + **********************************************************************************************************************/ +bsp_power_mode_t R_BSP_PowerModeSet (bsp_power_mode_t mode) +{ + /* Get current mode to return to caller. */ + bsp_power_mode_t previous_mode = R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk ? + (bsp_power_mode_t) R_SYSTEM->VCCSEL : BSP_POWER_MODE_LDO; + + /* Enable writing to Low Power Mode registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Set VCCSEL if a DCDC mode is selected. */ + bool dcdc_mode = mode < BSP_POWER_MODE_LDO; + if (dcdc_mode) + { + /* Set supply voltage range. */ + R_SYSTEM->VCCSEL = (uint8_t) mode; + } + + /* Only change mode if the specified mode is not already set. */ + if (dcdc_mode != (previous_mode < BSP_POWER_MODE_LDO)) + { + /* Enter critical section to prevent any peripheral or power mode changes while transitioning. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (mode >= BSP_POWER_MODE_LDO) + { + bsp_power_dcdc_disable(mode); + } + else + { + bsp_power_dcdc_enable(); + } + + FSP_CRITICAL_SECTION_EXIT; + } + + /* Disable writing to Low Power Mode registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + + return previous_mode; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU_RA2L1) + **********************************************************************************************************************/ + +#endif /* BSP_PRV_POWER_USE_DCDC */ diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h new file mode 100644 index 000000000..8114a1a0a --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_POWER_H +#define BSP_POWER_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2L1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_HAS_DCDC_REGULATOR + #define BSP_PRV_POWER_USE_DCDC (BSP_CFG_DCDC_ENABLE) +#else + #define BSP_PRV_POWER_USE_DCDC (0) +#endif + +#define BSP_PRV_POWER_DCDC_DISABLE (0) +#define BSP_PRV_POWER_DCDC_MANUAL (1) +#define BSP_PRV_POWER_DCDC_STARTUP (2) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Voltage regulator mode */ +typedef enum e_bsp_power_mode_t +{ + BSP_POWER_MODE_DCDC_2V4_TO_2V7 = 3, ///< DCDC mode; 2.4V to 2.7V supply + BSP_POWER_MODE_DCDC_2V7_TO_3V6 = 0, ///< DCDC mode; 2.7V to 3.6V supply + BSP_POWER_MODE_DCDC_3V6_TO_4V5 = 1, ///< DCDC mode; 3.6V to 4.5V supply + BSP_POWER_MODE_DCDC_4V5_TO_5V5 = 2, ///< DCDC mode; 4.5V to 5.5V supply + + BSP_POWER_MODE_LDO = 0x90, ///< LDO mode + BSP_POWER_MODE_LDO_BOOST = 0xB0 // Alternate DCDCCTL value for entering subclock and low-power modes + // (see RA2L1 User's Manual (R01UH0853EJ0100) Section 10.5.1 (5)) +} bsp_power_mode_t; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +bsp_power_mode_t R_BSP_PowerModeSet(bsp_power_mode_t mode); + +/*******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU_RA2L1) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index 515a526e1..04c87f1a2 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -100,6 +100,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. @@ -119,6 +120,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h new file mode 100644 index 000000000..4b2f7551c --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h @@ -0,0 +1,283 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/******************************************************************************************************************* + * @addtogroup BSP_MCU_RA4M3 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra4m3 +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC transfer end 0 + ELC_EVENT_DMAC1_INT = (0x021), // DMAC transfer end 1 + ELC_EVENT_DMAC2_INT = (0x022), // DMAC transfer end 2 + ELC_EVENT_DMAC3_INT = (0x023), // DMAC transfer end 3 + ELC_EVENT_DMAC4_INT = (0x024), // DMAC transfer end 4 + ELC_EVENT_DMAC5_INT = (0x025), // DMAC transfer end 5 + ELC_EVENT_DMAC6_INT = (0x026), // DMAC transfer end 6 + ELC_EVENT_DMAC7_INT = (0x027), // DMAC transfer end 7 + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x02B), // DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Slave address match + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x0A1), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x0A2), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x0A3), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x0A4), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x0A5), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x0A6), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x0A7), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x0A8), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x0A9), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x0AA), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable interrupt B + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable interrupt C + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable interrupt D + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // A/D scan end interrupt + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x186), // Received data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Received data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Received data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Received data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Received data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA4M3) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h new file mode 100644 index 000000000..7783f9cea --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -0,0 +1,290 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (19999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x01U) +#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x02U) +#else + #define CGC_MAINCLOCK_DRIVE (0x03U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) +#define BSP_FEATURE_BSP_HAS_SP_MON (0U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4M3 there are specific registers for configuring the USB clock. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA4M3 there is another PLL that can be used as a clock source for USB. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA4M3 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M3 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFFU) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) +#define BSP_FEATURE_SCI_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x219U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 0 (2^0) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (1U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h new file mode 100644 index 000000000..f73daa07e --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA4M3 RA4M3 + * @includedoc config_bsp_ra4m3_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA4M3) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index 349b391cb..af79cdb94 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -100,6 +100,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. @@ -119,6 +120,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index 6bc828dba..c0835c774 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -104,6 +104,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. @@ -123,6 +124,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index b33995526..ea81fd55e 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -104,6 +104,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. @@ -123,6 +124,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index 372f8d19e..b0ecb37da 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -104,6 +104,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. @@ -123,6 +124,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index 0a75e15fc..d85b22efb 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -85,6 +85,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. @@ -103,6 +104,7 @@ #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index ee5a6428c..d849801f1 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -103,6 +103,7 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. @@ -118,10 +119,11 @@ #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) -#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) #define BSP_FEATURE_CGC_HAS_PCLKA (1U) diff --git a/ra/fsp/src/r_adc/r_adc.c b/ra/fsp/src/r_adc/r_adc.c index 479bc1c7d..cd444c118 100644 --- a/ra/fsp/src/r_adc/r_adc.c +++ b/ra/fsp/src/r_adc/r_adc.c @@ -239,13 +239,7 @@ fsp_err_t R_ADC_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) #endif /* Save configurations. */ - p_instance_ctrl->p_cfg = p_cfg; - -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; -#endif + p_instance_ctrl->p_cfg = p_cfg; p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; @@ -320,6 +314,7 @@ fsp_err_t R_ADC_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_channel_cfg) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_ADC_CallbackSet (adc_ctrl_t * const p_api_ctrl, void ( * p_callback)(adc_callback_args_t *), @@ -338,11 +333,24 @@ fsp_err_t R_ADC_CallbackSet (adc_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if ADC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + adc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif + + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(adc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -688,10 +696,13 @@ fsp_err_t R_ADC_Close (adc_ctrl_t * p_ctrl) /* Stop the ADC. */ p_instance_ctrl->p_reg->ADCSR = 0U; +#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG + /* Disable sample and hold before entering module stop state to reduce power consumption (reference section 47.6.8 * "Available Functions and Register Settings of AN000 to AN002, AN007, AN100 to AN102, and AN107" in the RA6M3 * manual R01UH0886EJ0100. */ p_instance_ctrl->p_reg->ADSHCR = 0U; +#endif #if BSP_FEATURE_ADC_HAS_VREFAMPCNT @@ -1277,7 +1288,7 @@ static void r_adc_sensor_sample_state_calculation (uint32_t * const p_sample_sta uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_ADC_CLOCK_SOURCE); /* Calculate sample states required for the current ADC conversion clock (reference section 47.2.14 "A/D Sampling - * State Register n (ADSSTRn) (n = 00 to 07, L, T, O) in the RA6M3 manual R01UH0886EJ0100. + * State Register n (ADSSTRn) (n = 00 to 07, L, T, O)" in the RA6M3 manual R01UH0886EJ0100. * * sample_states = required_sample_time / adclk_period * = required_sample_time (nsec) * adclk_frequency (kHz) / 1000000 (usec / sec) + 1 @@ -1399,11 +1410,14 @@ static void r_adc_scan_cfg (adc_instance_ctrl_t * const p_instance_ctrl, adc_cha r_adc_sensor_cfg(p_instance_ctrl, p_channel_cfg); } +#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG + /* Configure sample and hold. */ uint32_t adshcr = p_channel_cfg->sample_hold_states; adshcr |= (p_channel_cfg->sample_hold_mask & ADC_MASK_SAMPLE_HOLD_BYPASS_CHANNELS) << ADC_MASK_SAMPLE_HOLD_BYPASS_SHIFT; p_instance_ctrl->p_reg->ADSHCR = (uint16_t) adshcr; +#endif /* Set group A priority action (not interrupt priority!) * This will also start the Group B scans if configured for ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN. @@ -1501,7 +1515,7 @@ static void r_adc_scan_end_common_isr (adc_event_t event) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_instance_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_instance_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c index ffdf2870c..7f2c6e932 100644 --- a/ra/fsp/src/r_agt/r_agt.c +++ b/ra/fsp/src/r_agt/r_agt.c @@ -164,8 +164,11 @@ fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c /* Power on the AGT channel. */ R_BSP_MODULE_START(FSP_IP_AGT, p_cfg->channel); - /* Forcibly stop timer and clear flags. */ - p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS; + /* Clear AGTCR. This stops the timer if it is running and clears the flags. */ + p_instance_ctrl->p_reg->AGTCR = 0U; + + /* The timer is stopped in sync with the count clock, or in sync with PCLK in event and external count modes. */ + FSP_HARDWARE_REGISTER_WAIT(0U, p_instance_ctrl->p_reg->AGTCR_b.TCSTF); /* Clear AGTMR2 before AGTMR1 is set. Reference Note 3 in section 25.2.6 "AGT Mode Register 2 (AGTMR2)" * of the RA6M3 manual R01UH0886EJ0100. */ @@ -183,12 +186,6 @@ fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c } /* Set callback and context pointers */ - -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; -#endif p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; @@ -516,7 +513,7 @@ fsp_err_t R_AGT_CallbackSet (timer_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if AGT_CFG_PARAM_CHECKING_ENABLE @@ -524,19 +521,17 @@ fsp_err_t R_AGT_CallbackSet (timer_ctrl_t * const p_api_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - #if BSP_TZ_SECURE_BUILD - - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = - (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -992,7 +987,7 @@ void agt_int_isr (void) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_instance_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_instance_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_cac/r_cac.c b/ra/fsp/src/r_cac/r_cac.c index 5b3a12238..6f1e403c4 100644 --- a/ra/fsp/src/r_cac/r_cac.c +++ b/ra/fsp/src/r_cac/r_cac.c @@ -165,9 +165,6 @@ fsp_err_t R_CAC_Open (cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg) p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_instance_ctrl->callback_is_secure = true; -#endif /* Configure the CAC per the configuration. */ r_cac_hw_configure(p_instance_ctrl); @@ -281,7 +278,7 @@ fsp_err_t R_CAC_CallbackSet (cac_ctrl_t * const p_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_instance_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if CAC_CFG_PARAM_CHECKING_ENABLE @@ -289,13 +286,15 @@ fsp_err_t R_CAC_CallbackSet (cac_ctrl_t * const p_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ cac_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_instance_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), - FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif -#endif /* Store callback and context */ - p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(cac_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif p_instance_ctrl->p_context = p_context; p_instance_ctrl->p_callback_memory = p_callback_memory; @@ -477,7 +476,7 @@ static void r_cac_isr_handler (cac_event_t event, uint32_t clear_mask) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_instance_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_instance_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_can/r_can.c b/ra/fsp/src/r_can/r_can.c index 06d791cff..d1743aac9 100644 --- a/ra/fsp/src/r_can/r_can.c +++ b/ra/fsp/src/r_can/r_can.c @@ -283,10 +283,6 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c /* Initialize the control block */ p_ctrl->p_cfg = p_cfg; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif - /* Set callback and context pointers, if configured */ p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; @@ -620,7 +616,7 @@ fsp_err_t R_CAN_CallbackSet (can_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if CAN_CFG_PARAM_CHECKING_ENABLE @@ -628,12 +624,17 @@ fsp_err_t R_CAN_CallbackSet (can_ctrl_t * const p_api_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ can_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(can_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -698,7 +699,7 @@ static void r_can_call_callback (can_instance_ctrl_t * p_ctrl, can_callback_args #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args_memory); diff --git a/ra/fsp/src/r_cgc/r_cgc.c b/ra/fsp/src/r_cgc/r_cgc.c index e10a1af3d..6e7236eab 100644 --- a/ra/fsp/src/r_cgc/r_cgc.c +++ b/ra/fsp/src/r_cgc/r_cgc.c @@ -283,10 +283,6 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) FSP_ERROR_RETURN(CGC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); #endif -#if BSP_TZ_SECURE_BUILD - p_instance_ctrl->callback_is_secure = true; -#endif - /* Store the control structure in a private global variable so the oscillation stop detection function can be * called from the NMI callback. */ gp_cgc_ctrl = p_instance_ctrl; @@ -339,6 +335,7 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) * the input frequency is less than 12.5 MHz. * @retval FSP_ERR_NOT_STABILIZED PLL clock source is not stable. * @retval FSP_ERR_PLL_SRC_INACTIVE PLL clock source is not running. + * @retval FSP_ERR_INVALID_STATE The subclock must be running before activating HOCO with FLL. **********************************************************************************************************************/ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg) { @@ -373,6 +370,24 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c /* HOCO must be running in low voltage mode. */ FSP_ASSERT(CGC_CLOCK_CHANGE_STOP != p_clock_cfg->hoco_state); #endif + #if BSP_PRV_HOCO_USE_FLL + + /* Determine if HOCO will be started. */ + #if BSP_PRV_PLL2_SUPPORTED + uint8_t start_hoco = (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock)) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll2_cfg.source_clock)); + #else + uint8_t start_hoco = (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock)); + #endif + + /* Subclock must be running to use FLL. */ + FSP_ERROR_RETURN(!(start_hoco && R_SYSTEM->SOSCCR), FSP_ERR_INVALID_STATE); + #endif #endif #if BSP_PRV_PLL_SUPPORTED options[CGC_CLOCK_PLL] = p_clock_cfg->pll_state; @@ -463,6 +478,14 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c /* Prerequisite to starting clocks or changing the system clock. */ r_cgc_pre_change(CGC_PRV_CHANGE_LPM_CGC); +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) + { + /* If FLL is to be used set FLLCR1 before starting HOCO. */ + R_SYSTEM->FLLCR1 = 1U; + } +#endif + #if BSP_PRV_PLL_SUPPORTED if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) { @@ -473,6 +496,16 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c { /* Need to start PLL source clock and let it stabilize before starting PLL. */ r_cgc_clock_change(p_clock_cfg->pll_cfg.source_clock, CGC_CLOCK_CHANGE_START); + + #if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock) + { + /* If FLL is enabled and HOCO is turned on an additional stabilization wait is required before + * checking the flag and starting the PLL. */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(p_clock_cfg->pll_cfg.source_clock), FSP_SUCCESS); } } @@ -487,6 +520,16 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c { /* Need to start PLL source clock and let it stabilize before starting PLL. */ r_cgc_clock_change(p_clock_cfg->pll2_cfg.source_clock, CGC_CLOCK_CHANGE_START); + + #if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == p_clock_cfg->pll2_cfg.source_clock) + { + /* If FLL is enabled and HOCO is turned on an additional stabilization wait is required before + * checking the flag and starting PLL2. */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(p_clock_cfg->pll2_cfg.source_clock), FSP_SUCCESS); } } @@ -517,6 +560,14 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c } } +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_CHANGE_STOP == p_clock_cfg->hoco_state) + { + /* If HOCO is disabled then disable FLL as well. */ + R_SYSTEM->FLLCR1 = 0U; + } +#endif + /* Verify the requested clock is stable if it has a stabilization flag. */ FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(requested_system_clock), FSP_SUCCESS); @@ -561,7 +612,7 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c } /* Reduce the operating speed mode to the optimal setting for these clock configurations and restore the cache to - * it's previous state. */ + * its previous state. */ r_cgc_post_change(CGC_PRV_CHANGE_LPM_CGC); return FSP_SUCCESS; @@ -585,6 +636,7 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c * @retval FSP_ERR_CLOCK_ACTIVE PLL configuration cannot be changed while PLL is running. * @retval FSP_ERR_OSC_STOP_DET_ENABLED PLL multiplier must be less than 20 if oscillation stop detect is enabled and * the input frequency is less than 12.5 MHz. + * @retval FSP_ERR_INVALID_STATE The subclock must be running before activating HOCO with FLL. **********************************************************************************************************************/ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const * const p_pll_cfg) { @@ -619,6 +671,9 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } #endif + #if BSP_PRV_HOCO_USE_FLL + FSP_ERROR_RETURN(!((CGC_CLOCK_HOCO == clock_source) && R_SYSTEM->SOSCCR), FSP_ERR_INVALID_STATE); + #endif #else FSP_PARAMETER_NOT_USED(p_instance_ctrl); #endif @@ -662,6 +717,14 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, #endif #endif +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == clock_source) + { + /* If FLL is to be used set FLLCR1 before starting HOCO. */ + R_SYSTEM->FLLCR1 = 1U; + } +#endif + /* Start the clock. */ r_cgc_clock_change(clock_source, CGC_CLOCK_CHANGE_START); @@ -730,6 +793,16 @@ fsp_err_t R_CGC_ClockStop (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source) /* Stop the clock. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); r_cgc_clock_change(clock_source, CGC_CLOCK_CHANGE_STOP); + +#if BSP_PRV_HOCO_USE_FLL + + /* FLL must be disabled after stopping HOCO. */ + if (CGC_CLOCK_HOCO == clock_source) + { + R_SYSTEM->FLLCR1 = 0U; + } +#endif + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); #if !BSP_CFG_USE_LOW_VOLTAGE_MODE @@ -1089,6 +1162,7 @@ fsp_err_t R_CGC_OscStopStatusClear (cgc_ctrl_t * const p_ctrl) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_CGC_CallbackSet (cgc_ctrl_t * const p_api_ctrl, void ( * p_callback)(cgc_callback_args_t *), @@ -1112,20 +1186,20 @@ fsp_err_t R_CGC_CallbackSet (cgc_ctrl_t * const p_api_ctrl, FSP_ASSERT(NULL != p_callback); #if BSP_TZ_SECURE_BUILD - if (!callback_is_secure) - { - FSP_ASSERT(NULL != p_callback_memory); - } + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + cgc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif #if BSP_TZ_SECURE_BUILD - - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = callback_is_secure; + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(cgc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1883,7 +1957,7 @@ static void r_cgc_nmi_internal_callback (bsp_grp_irq_t irq) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (gp_cgc_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(gp_cgc_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ gp_cgc_ctrl->p_callback(&args); diff --git a/ra/fsp/src/r_ctsu/r_ctsu.c b/ra/fsp/src/r_ctsu/r_ctsu.c index 961783c60..cb7e85dfb 100644 --- a/ra/fsp/src/r_ctsu/r_ctsu.c +++ b/ra/fsp/src/r_ctsu/r_ctsu.c @@ -104,7 +104,6 @@ #endif #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - #define CTSU_REG_ADCTDR (*(uint16_t *) 0x4005C040) // ADCTDR address #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) #define CTSU_CALIB_REF ((6144000 * 10) / CTSU_CFG_VCC_MV) // 1.5V Reference value (4096 * 1500 * 10) #else @@ -427,7 +426,8 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf if (CTSU_MODE_CURRENT_SCAN == p_cfg->md) { /* Current scan does not run multiple frequency */ - p_instance_ctrl->p_ctsuwr[element_id].ctsuso = (uint32_t) (element_cfgs->snum << 10); + p_instance_ctrl->p_ctsuwr[element_id].ctsuso = + (uint32_t) ((element_cfgs->sdpa << 24) | (element_cfgs->snum << 10) | element_cfgs->so); } else { @@ -629,11 +629,6 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf p_instance_ctrl->wr_index = 0; p_instance_ctrl->state = CTSU_STATE_IDLE; -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; -#endif p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; @@ -934,6 +929,7 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_CTSU_CallbackSet (ctsu_ctrl_t * const p_api_ctrl, void ( * p_callback)(ctsu_callback_args_t *), @@ -948,15 +944,28 @@ fsp_err_t R_CTSU_CallbackSet (ctsu_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(CTSU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ - #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CTSU_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ctsu_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ctsu_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1399,10 +1408,11 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & CTSU_SNUM_MAX; - corr_data[i] = (uint16_t) ((uint32_t) (corr_data[i] * (CTSU_SNUM_RECOMMEND + 1)) / (snum + 1)); + corr_data[i] = (uint16_t) (((uint32_t) corr_data[i] * (CTSU_SNUM_RECOMMEND + 1)) / (snum + 1)); /* Calculate CTSUSO equivalent difference between current value and target value */ - diff = (int32_t) (corr_data[i] - target_val) / (CTSU_CORRECTION_OFFSET_UNIT >> p_instance_ctrl->range); + diff = (int32_t) ((int32_t) corr_data[i] - (int32_t) target_val) / + (CTSU_CORRECTION_OFFSET_UNIT >> p_instance_ctrl->range); ctsuso = (int32_t) (p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso & CTSU_TUNING_MAX); ctsuso += diff; @@ -1463,9 +1473,9 @@ void ctsu_moving_average (uint16_t * p_average, uint16_t new_data, uint16_t aver { uint32_t work; - work = (uint32_t) (*p_average * ((average_num) - 1)); /* Average * (num - 1) */ - work += new_data; /* Add Now data */ - *p_average = (uint16_t) (work / average_num); /* Average calculation */ + work = (uint32_t) ((uint32_t) *p_average * (uint32_t) (average_num - 1)); /* Average * (num - 1) */ + work += new_data; /* Add Now data */ + *p_average = (uint16_t) (work / average_num); /* Average calculation */ } /*********************************************************************************************************************** @@ -1719,7 +1729,7 @@ void ctsu_end_isr (void) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_instance_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_instance_ctrl->p_callback(p_args); @@ -1814,7 +1824,8 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) /* Step2-a : Measure the current input to the ICO by passing current through the internal resistance */ /* in each range. The theoretical value of the current is 12.5uA. */ - R_CTSU->CTSUCHAC0 = 1; + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; R_CTSU->CTSUCALIB_b.TSOC = 1; for (i = 0; i < CTSU_RANGE_NUM; i++) { @@ -1845,6 +1856,7 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) } /* Step3 : Measure by inputting each constant current from internal DAC to ICO. */ + R_CTSU->CTSUCRB_b.SSCNT = 0; R_CTSU->CTSUCALIB_b.CCOCLK = 0; R_CTSU->CTSUCALIB_b.CCOCALIB = 1; @@ -1871,16 +1883,17 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) for (i = 0; i < CTSU_RANGE_NUM; i++) { g_ctsu_correction_info.error_rate[i] = - (uint16_t) ((g_ctsu_correction_info.base_value[i] * error_registance[i]) / + (uint16_t) (((uint32_t) g_ctsu_correction_info.base_value[i] * (uint32_t) error_registance[i]) / g_ctsu_correction_info.dac_value[9]); for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) { g_ctsu_correction_info.real_value[j] = - (uint16_t) ((g_ctsu_correction_info.dac_value[j] * g_ctsu_correction_info.error_rate[i]) >> + (uint16_t) (((uint32_t) g_ctsu_correction_info.dac_value[j] * + (uint32_t) g_ctsu_correction_info.error_rate[i]) >> CTSU_SHIFT_AMOUNT); g_ctsu_correction_info.coefficient[i][j] = - (uint16_t) (((CTSU_CORRECTION_STD_UNIT * (j + 1)) << CTSU_SHIFT_AMOUNT) / + (uint16_t) ((uint32_t) ((CTSU_CORRECTION_STD_UNIT * (j + 1)) << CTSU_SHIFT_AMOUNT) / g_ctsu_correction_info.real_value[j]); } } @@ -1888,7 +1901,7 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) for (i = 0; i < CTSU_RANGE_NUM - 1; i++) { g_ctsu_correction_info.range_ratio[i] = - (uint16_t) ((g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA] << CTSU_SHIFT_AMOUNT) / + (uint16_t) (((uint32_t) g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA] << CTSU_SHIFT_AMOUNT) / g_ctsu_correction_info.error_rate[i]); } g_ctsu_correction_info.status = CTSU_CORRECTION_COMPLETE; @@ -2166,30 +2179,30 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl) ***********************************************************************************************************************/ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) { - adc_status_t status; - uint16_t i; - uint16_t adctdr_ave; - uint32_t adctdr_sum; - int16_t diff; - int16_t dir = 0; - uint16_t comp = 0; + adc_status_t status; + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + uint16_t i; + uint16_t adctdr_result; + uint16_t adctdr_ave; + uint32_t adctdr_sum; + int16_t diff; + int16_t dir = 0; + uint16_t comp = 0; adctdr_sum = 0; for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) { - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStart( - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl); + p_adc->p_api->scanStart(p_adc->p_ctrl); /* Wait for conversion to complete. */ status.state = ADC_STATE_SCAN_IN_PROGRESS; while (ADC_STATE_SCAN_IN_PROGRESS == status.state) { - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStatusGet( - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl, - &status); + p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); } - adctdr_sum += (uint32_t) (CTSU_REG_ADCTDR); + p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); + adctdr_sum += adctdr_result; } g_ctsu_correction_info.tscap_voltage = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); @@ -2223,23 +2236,21 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) adctdr_sum = 0; for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) { - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStart( - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl); + p_adc->p_api->scanStart(p_adc->p_ctrl); /* Wait for conversion to complete. */ status.state = ADC_STATE_SCAN_IN_PROGRESS; while (ADC_STATE_SCAN_IN_PROGRESS == status.state) { - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStatusGet( - p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl, - &status); + p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); } - adctdr_sum += (uint32_t) (CTSU_REG_ADCTDR); + p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); + adctdr_sum += adctdr_result; } adctdr_ave = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); - diff = (int16_t) (adctdr_ave - CTSU_CALIB_REF); + diff = (int16_t) ((adctdr_ave - CTSU_CALIB_REF) / 10); /* The change unit of the voltage by the RTRIM register is about 4mV (4096 * 4) = 16.384 */ if (diff > CTSU_CALIB_THRESHOLD) @@ -2283,11 +2294,15 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) ***********************************************************************************************************************/ void ctsu_correction_offset_adjust (uint16_t * p_adj_data, uint16_t raw_data, int32_t offset_error) { + int32_t diff; + + diff = (int32_t) ((int32_t) raw_data - offset_error); + if (offset_error > 0) { - if (0 > (int32_t) (raw_data - offset_error)) + if (0 < diff) { - *p_adj_data = (uint16_t) (raw_data - offset_error); + *p_adj_data = diff; } else { @@ -2296,13 +2311,13 @@ void ctsu_correction_offset_adjust (uint16_t * p_adj_data, uint16_t raw_data, in } else { - if (CTSU_COUNT_MAX < (int32_t) (raw_data - offset_error)) + if (CTSU_COUNT_MAX < diff) { *p_adj_data = CTSU_COUNT_MAX; } else { - *p_adj_data = (uint16_t) (raw_data - offset_error); + *p_adj_data = diff; } } } @@ -2389,7 +2404,7 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c /* Since the correction coefficient table is created with the recommended measurement time, */ /* If the measurement time is different, adjust the value level. */ - cmp_data = (int32_t) ((raw_data * (CTSU_SNUM_RECOMMEND + 1)) / (p_calc->snum + 1)); + cmp_data = (int32_t) (((int32_t) raw_data * (CTSU_SNUM_RECOMMEND + 1)) / (p_calc->snum + 1)); /* y = y0 + (y1 - y0) * (x - x0) / (x1 - x0); [y=coefficient, x=value] */ if (CTSU_MODE_MUTUAL_CFC_SCAN != p_calc->md) @@ -2430,7 +2445,7 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c #endif /* Get output count data */ - answer = (uint32_t) ((raw_data * coefficient) >> CTSU_SHIFT_AMOUNT); + answer = (uint32_t) (((uint32_t) raw_data * (uint32_t) coefficient) >> CTSU_SHIFT_AMOUNT); /* Value Overflow Check */ if (CTSU_COUNT_MAX < answer) @@ -2561,11 +2576,18 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) /* Correction offset current by TSCAP voltage error */ - multi.offset_error[i] = - (int32_t) ((g_ctsu_correction_info.tscap_voltage << CTSU_SHIFT_AMOUNT) / CTSU_CALIB_REF); - multi.offset_error[i] = - (int32_t) (((multi.offset[i] * (uint32_t) multi.offset_error[i]) >> CTSU_SHIFT_AMOUNT) - - multi.offset[i]); + if (0 == g_ctsu_correction_info.tscap_voltage) + { + multi.offset_error[i] = 0; + } + else + { + multi.offset_error[i] = + (int32_t) (((uint32_t) g_ctsu_correction_info.tscap_voltage << CTSU_SHIFT_AMOUNT) / CTSU_CALIB_REF); + multi.offset_error[i] = + (int32_t) (((multi.offset[i] * (uint32_t) multi.offset_error[i]) >> CTSU_SHIFT_AMOUNT) - + multi.offset[i]); + } multi.offset[i] = (multi.offset[i] + (uint32_t) multi.offset_error[i]); #endif #endif @@ -2744,11 +2766,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) void ctsu_correction_multi (ctsu_correction_multi_t * p_multi, uint16_t * p_pri, uint16_t * p_snd) { uint32_t i; - uint16_t pri_calc[CTSU_CFG_NUM_SUMULTI]; - uint16_t snd_calc[CTSU_CFG_NUM_SUMULTI]; - uint16_t sumulti[CTSU_CFG_NUM_SUMULTI]; - uint32_t add_pri; - uint32_t add_snd; + int32_t pri_calc[CTSU_CFG_NUM_SUMULTI]; + int32_t snd_calc[CTSU_CFG_NUM_SUMULTI]; + int32_t sumulti[CTSU_CFG_NUM_SUMULTI]; + int32_t pri_total; + int32_t snd_total; + int32_t add_pri; + int32_t add_snd; #if CTSU_CFG_NUM_SUMULTI >= 3 int32_t diff[CTSU_CFG_NUM_SUMULTI]; #endif @@ -2764,8 +2788,8 @@ void ctsu_correction_multi (ctsu_correction_multi_t * p_multi, uint16_t * p_pri, pri_calc[0] = p_multi->pri[0]; for (i = 1; i < CTSU_CFG_NUM_SUMULTI; i++) { - pri_calc[i] = - (uint16_t) ((((p_multi->pri[i] + p_multi->offset[i]) * sumulti[0]) / sumulti[i]) - p_multi->offset[0]); + pri_total = (int32_t) (p_multi->pri[i] + p_multi->offset[i]); + pri_calc[i] = (int32_t) (((pri_total * sumulti[0]) / sumulti[i]) - (int32_t) p_multi->offset[0]); } if (NULL == p_snd) @@ -2780,8 +2804,8 @@ void ctsu_correction_multi (ctsu_correction_multi_t * p_multi, uint16_t * p_pri, snd_calc[0] = p_multi->snd[0]; for (i = 1; i < CTSU_CFG_NUM_SUMULTI; i++) { - snd_calc[i] = - (uint16_t) ((((p_multi->snd[i] + p_multi->offset[i]) * sumulti[0]) / sumulti[i]) - p_multi->offset[0]); + snd_total = (int32_t) (p_multi->snd[i] + p_multi->offset[i]); + snd_calc[i] = (int32_t) (((snd_total * sumulti[0]) / sumulti[i]) - (int32_t) p_multi->offset[0]); } } @@ -2789,22 +2813,22 @@ void ctsu_correction_multi (ctsu_correction_multi_t * p_multi, uint16_t * p_pri, { for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { - p_pri[i] = pri_calc[i]; + p_pri[i] = (uint16_t) pri_calc[i]; if (NULL != p_snd) { - p_snd[i] = snd_calc[i]; + p_snd[i] = (uint16_t) snd_calc[i]; } } } else { #if CTSU_CFG_NUM_SUMULTI == 1 - add_pri = (uint32_t) (pri_calc[0]); - add_snd = (uint32_t) (snd_calc[0]); + add_pri = pri_calc[0]; + add_snd = snd_calc[0]; #endif #if CTSU_CFG_NUM_SUMULTI == 2 - add_pri = (uint32_t) (pri_calc[0] + pri_calc[1]); - add_snd = (uint32_t) (snd_calc[0] + snd_calc[1]); + add_pri = pri_calc[0] + pri_calc[1]; + add_snd = snd_calc[0] + snd_calc[1]; #endif #if CTSU_CFG_NUM_SUMULTI >= 3 diff[0] = (snd_calc[1] - pri_calc[1]) - (snd_calc[0] - pri_calc[0]); @@ -2824,20 +2848,20 @@ void ctsu_correction_multi (ctsu_correction_multi_t * p_multi, uint16_t * p_pri, /* Compare with the combination with the other frequency difference (including margin). */ if ((diff[0] < (diff[1] * 2)) && (diff[0] < ((diff[2] * 3) / 2))) { - add_pri = (uint32_t) (pri_calc[0] + pri_calc[1]); - add_snd = (uint32_t) (snd_calc[0] + snd_calc[1]); + add_pri = pri_calc[0] + pri_calc[1]; + add_snd = snd_calc[0] + snd_calc[1]; } else { if (diff[1] < diff[2]) { - add_pri = (uint32_t) (pri_calc[0] + pri_calc[2]); - add_snd = (uint32_t) (snd_calc[0] + snd_calc[2]); + add_pri = pri_calc[0] + pri_calc[2]; + add_snd = snd_calc[0] + snd_calc[2]; } else { - add_pri = (uint32_t) (pri_calc[1] + pri_calc[2]); - add_snd = (uint32_t) (snd_calc[1] + snd_calc[2]); + add_pri = pri_calc[1] + pri_calc[2]; + add_snd = snd_calc[1] + snd_calc[2]; } } #endif @@ -2934,6 +2958,7 @@ void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.base_value[index], 1); /* Step2 : Measure by inputting each constant current from internal DAC to CFC-ICO. */ + R_CTSU->CTSUCRB_b.SSCNT = 0; R_CTSU->CTSUCRA_b.LOAD = 1; R_CTSU->CTSUCALIB_b.CCOCLK = 0; R_CTSU->CTSUCALIB_b.CFCMODE = 1; diff --git a/ra/fsp/src/r_doc/r_doc.c b/ra/fsp/src/r_doc/r_doc.c index f4855d4ea..7148631f7 100644 --- a/ra/fsp/src/r_doc/r_doc.c +++ b/ra/fsp/src/r_doc/r_doc.c @@ -113,12 +113,7 @@ fsp_err_t R_DOC_Open (doc_ctrl_t * const p_api_ctrl, doc_cfg_t const * const p_c #endif /* save pointers for later use */ - p_ctrl->p_cfg = p_cfg; -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_ctrl->callback_is_secure = true; -#endif + p_ctrl->p_cfg = p_cfg; p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; @@ -261,6 +256,7 @@ fsp_err_t R_DOC_VersionGet (fsp_version_t * const p_version) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_DOC_CallbackSet (doc_ctrl_t * const p_api_ctrl, void ( * p_callback)(doc_callback_args_t *), @@ -279,13 +275,26 @@ fsp_err_t R_DOC_CallbackSet (doc_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if DOC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + doc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(doc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -337,7 +346,7 @@ void doc_int_isr (void) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_flash_hp/r_flash_hp.c b/ra/fsp/src/r_flash_hp/r_flash_hp.c index c673dd2c9..6420c4111 100644 --- a/ra/fsp/src/r_flash_hp/r_flash_hp.c +++ b/ra/fsp/src/r_flash_hp/r_flash_hp.c @@ -397,12 +397,6 @@ fsp_err_t R_FLASH_HP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - - /* If a callback is not supplied this will get set during callbackSet */ - p_ctrl->callback_is_secure = true; -#endif - /* Enable FCU interrupts. */ R_FACI_HP->FRDYIE = 1U; R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl); @@ -1077,7 +1071,7 @@ fsp_err_t R_FLASH_HP_CallbackSet (flash_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE @@ -1085,12 +1079,17 @@ fsp_err_t R_FLASH_HP_CallbackSet (flash_ctrl_t * const p_api_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ flash_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(flash_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -2423,7 +2422,7 @@ static void r_flash_hp_call_callback (flash_hp_instance_ctrl_t * p_ctrl, flash_e #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_gpt/r_gpt.c b/ra/fsp/src/r_gpt/r_gpt.c index 604bcb25e..57760f21e 100644 --- a/ra/fsp/src/r_gpt/r_gpt.c +++ b/ra/fsp/src/r_gpt/r_gpt.c @@ -759,7 +759,7 @@ fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if GPT_CFG_PARAM_CHECKING_ENABLE @@ -767,12 +767,17 @@ fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const p_api_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -903,10 +908,6 @@ static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_ uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0)); p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address; -#if BSP_TZ_SECURE_BUILD - p_instance_ctrl->callback_is_secure = true; -#endif - /* Set callback and context pointers, if configured */ p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; @@ -1312,7 +1313,7 @@ static void r_gpt_call_callback (gpt_instance_ctrl_t * p_ctrl, timer_event_t eve #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_icu/r_icu.c b/ra/fsp/src/r_icu/r_icu.c index 4a3e3f2c7..6b264a4dd 100644 --- a/ra/fsp/src/r_icu/r_icu.c +++ b/ra/fsp/src/r_icu/r_icu.c @@ -131,8 +131,7 @@ fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, externa #if BSP_TZ_SECURE_BUILD /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_ctrl->p_callback_memory = NULL; - p_ctrl->callback_is_secure = true; + p_ctrl->p_callback_memory = NULL; #endif /* Initialize control block. */ @@ -228,6 +227,7 @@ fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, void ( * p_callback)( @@ -252,20 +252,22 @@ fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, FSP_ASSERT(NULL != p_callback); #if BSP_TZ_SECURE_BUILD - if (!callback_is_secure) - { - FSP_ASSERT(NULL != p_callback_memory); - } + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif #if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = callback_is_secure; - p_ctrl->p_callback_memory = p_callback_memory; -#endif - + p_ctrl->p_callback_memory = p_callback_memory; + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback); +#else p_ctrl->p_callback = p_callback; - p_ctrl->p_context = p_context; +#endif + p_ctrl->p_context = p_context; return FSP_SUCCESS; } @@ -348,9 +350,8 @@ void r_icu_isr (void) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - external_irq_callback_args_t args; - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ args.channel = p_ctrl->channel; diff --git a/ra/fsp/src/r_iic_master/r_iic_master.c b/ra/fsp/src/r_iic_master/r_iic_master.c index 9fbead2e3..4b5424260 100644 --- a/ra/fsp/src/r_iic_master/r_iic_master.c +++ b/ra/fsp/src/r_iic_master/r_iic_master.c @@ -263,9 +263,6 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); @@ -430,6 +427,7 @@ fsp_err_t R_IIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, void ( * p_callback)(i2c_master_callback_args_t *), @@ -444,21 +442,28 @@ fsp_err_t R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctr FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE - if (!p_ctrl->callback_is_secure) - { - FSP_ASSERT(p_callback_memory); - } + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif - p_ctrl->p_callback = p_callback; + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -664,7 +669,7 @@ static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_ma #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_iic_slave/r_iic_slave.c b/ra/fsp/src/r_iic_slave/r_iic_slave.c index 593edb9db..aeaa1ebbb 100644 --- a/ra/fsp/src/r_iic_slave/r_iic_slave.c +++ b/ra/fsp/src/r_iic_slave/r_iic_slave.c @@ -225,9 +225,6 @@ fsp_err_t R_IIC_SLAVE_Open (i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); @@ -311,6 +308,7 @@ fsp_err_t R_IIC_SLAVE_Write (i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * cons * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t * const p_api_ctrl, void ( * p_callback)(i2c_slave_callback_args_t *), @@ -325,21 +323,28 @@ fsp_err_t R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(IIC_SLAVE_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE - if (!p_ctrl->callback_is_secure) - { - FSP_ASSERT(p_callback_memory); - } + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_slave_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif - p_ctrl->p_callback = p_callback; + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_slave_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -736,7 +741,7 @@ static void r_iic_slave_call_callback (iic_slave_instance_ctrl_t * p_ctrl, #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_iwdt/r_iwdt.c b/ra/fsp/src/r_iwdt/r_iwdt.c index b5d36cf97..d32a38f86 100644 --- a/ra/fsp/src/r_iwdt/r_iwdt.c +++ b/ra/fsp/src/r_iwdt/r_iwdt.c @@ -393,6 +393,7 @@ fsp_err_t R_IWDT_TimeoutGet (wdt_ctrl_t * const p_api_ctrl, wdt_timeout_values_t * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_IWDT_CallbackSet (wdt_ctrl_t * const p_ctrl, void ( * p_callback)(wdt_callback_args_t *), @@ -410,12 +411,26 @@ fsp_err_t R_IWDT_CallbackSet (wdt_ctrl_t * const p_ctrl, /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_instance_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IWDT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + wdt_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif #endif - p_instance_ctrl->p_callback = p_callback; + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(wdt_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif p_instance_ctrl->p_context = p_context; p_instance_ctrl->p_callback_memory = p_callback_memory; @@ -478,7 +493,7 @@ static void iwdt_nmi_internal_callback (bsp_grp_irq_t irq) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (gp_iwdt_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(gp_iwdt_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ gp_iwdt_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_jpeg/r_jpeg.c b/ra/fsp/src/r_jpeg/r_jpeg.c index d9ce6aa72..4de4ed76b 100644 --- a/ra/fsp/src/r_jpeg/r_jpeg.c +++ b/ra/fsp/src/r_jpeg/r_jpeg.c @@ -825,7 +825,7 @@ fsp_err_t R_JPEG_ModeSet (jpeg_ctrl_t * const p_api_ctrl, jpeg_mode_t mode) /*******************************************************************************************************************//** * Cancel an outstanding JPEG codec operation and close the device. * - * @retval FSP_SUCCESS The input data buffer is closed. + * @retval FSP_SUCCESS The JPEG unit is stopped and the driver is closed. * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. * @retval FSP_ERR_NOT_OPEN JPEG not opened. **********************************************************************************************************************/ diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index 6157fa145..136b1b4e4 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -277,7 +277,7 @@ fsp_err_t R_LPM_IoKeepClear (lpm_ctrl_t * const p_api_ctrl) /*******************************************************************************************************************//** * Close the LPM Instance * - * @retval FSP_SUCCESS LPM mode closed + * @retval FSP_SUCCESS LPM driver closed * @retval FSP_ERR_NOT_OPEN LPM instance is not open * @retval FSP_ERR_ASSERTION Null Pointer **********************************************************************************************************************/ @@ -559,6 +559,7 @@ fsp_err_t r_lpm_check_clocks (uint32_t clock_source) * * @retval FSP_SUCCESS Successfully entered and woke from low power mode. * @retval FSP_ERR_INVALID_MODE One of the following: + * - FLL function is enabled when requesting Software Standby. * - HOCO was not system clock when using snooze mode with SCI0/RXD0. * - HOCO was not stable when using snooze mode with SCI0/RXD0. * - MOCO was running when using snooze mode with SCI0/RXD0. @@ -580,11 +581,20 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) uint32_t stopped_modules = 0; #endif #endif +#if BSP_PRV_POWER_USE_DCDC + bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; +#endif if (1U == R_SYSTEM->SBYCR_b.SSBY) { /* Execute pre-wfi standby tasks */ +#if BSP_PRV_HOCO_USE_FLL + + /* If FLL is available it must not be active when entering Software Standby. */ + FSP_ERROR_RETURN(0U == R_SYSTEM->FLLCR1, FSP_ERR_INVALID_MODE); +#endif + /* Get system clock */ uint32_t clock_source = R_SYSTEM->SCKSCR; @@ -689,6 +699,15 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); } #endif +#endif +#if BSP_PRV_POWER_USE_DCDC + + /* DCDC cannot be used in Software Standby, so switch back to LDO if needed (see RA2L1 User's Manual + * (R01UH0853EJ0100) Section 40.3 Usage Notes). */ + if (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk) + { + power_mode = R_BSP_PowerModeSet(BSP_POWER_MODE_LDO_BOOST); + } #endif } @@ -719,9 +738,11 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) * See Section 11.8.2 "Canceling Snooze Mode" in the RA6M3 manual R01UM0004EU0110 */ R_SYSTEM->SNZCR_b.SNZE = 0; -#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY || (BSP_PRV_POWER_USE_DCDC) if (1U == R_SYSTEM->SBYCR_b.SSBY) { + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ r_lpm_wait_for_operating_mode_flags(); @@ -729,16 +750,24 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) R_SYSTEM->OPCCR = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; R_SYSTEM->OSTDCR_b.OSTDE = 0x1U & saved_ostdcr_ostde; - #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (saved_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); - #endif + #endif /* Disable writing to CGC and Low Power Mode registers. */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); - #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED + #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED bsp_prv_power_change_mstp_clear(stopped_modules); + #endif + #endif + #if BSP_PRV_POWER_USE_DCDC + if (power_mode < BSP_POWER_MODE_LDO) + { + /* Switch back to DCDC if it was enabled before. */ + R_BSP_PowerModeSet(power_mode); + } #endif } diff --git a/ra/fsp/src/r_lvd/r_lvd.c b/ra/fsp/src/r_lvd/r_lvd.c index a4711b36b..58fb17355 100644 --- a/ra/fsp/src/r_lvd/r_lvd.c +++ b/ra/fsp/src/r_lvd/r_lvd.c @@ -183,13 +183,7 @@ fsp_err_t R_LVD_Open (lvd_ctrl_t * const p_api_ctrl, lvd_cfg_t const * const p_c #endif /* Store the user configuration. */ - p_ctrl->p_cfg = p_cfg; - -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_ctrl->callback_is_secure = true; -#endif + p_ctrl->p_cfg = p_cfg; p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; @@ -283,6 +277,7 @@ fsp_err_t R_LVD_StatusClear (lvd_ctrl_t * const p_api_ctrl) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_LVD_CallbackSet (lvd_ctrl_t * const p_api_ctrl, void ( * p_callback)(lvd_callback_args_t *), @@ -297,15 +292,28 @@ fsp_err_t R_LVD_CallbackSet (lvd_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(LVD_OPENED == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ - #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if LVD_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + lvd_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(lvd_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -700,7 +708,7 @@ static void lvd_common_isr_handler (lvd_instance_ctrl_t * p_ctrl) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_poeg/r_poeg.c b/ra/fsp/src/r_poeg/r_poeg.c index 516e33b85..af9acd743 100644 --- a/ra/fsp/src/r_poeg/r_poeg.c +++ b/ra/fsp/src/r_poeg/r_poeg.c @@ -147,9 +147,6 @@ fsp_err_t R_POEG_Open (poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cf p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_instance_ctrl->callback_is_secure = true; -#endif /* Make sure the module is marked open before enabling the interrupt since the interrupt could fire immediately. */ p_instance_ctrl->open = POEG_OPEN; @@ -261,7 +258,7 @@ fsp_err_t R_POEG_CallbackSet (poeg_ctrl_t * const p_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_instance_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if POEG_CFG_PARAM_CHECKING_ENABLE @@ -269,13 +266,17 @@ fsp_err_t R_POEG_CallbackSet (poeg_ctrl_t * const p_ctrl, /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ poeg_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_instance_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), - FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - p_instance_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(poeg_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif p_instance_ctrl->p_context = p_context; p_instance_ctrl->p_callback_memory = p_callback_memory; @@ -370,7 +371,7 @@ void poeg_event_isr (void) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_instance_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_instance_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c index 23c3850aa..3a32eb988 100644 --- a/ra/fsp/src/r_rtc/r_rtc.c +++ b/ra/fsp/src/r_rtc/r_rtc.c @@ -214,11 +214,6 @@ fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) /* Save the configuration */ p_instance_ctrl->p_cfg = p_cfg; -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; -#endif p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; @@ -725,6 +720,7 @@ fsp_err_t R_RTC_VersionGet (fsp_version_t * p_version) * @retval FSP_ERR_ASSERTION Pointer to RTC control block is NULL or the RTC is not configured to use the * internal clock. * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_RTC_CallbackSet (rtc_ctrl_t * const p_ctrl, void ( * p_callback)(rtc_callback_args_t *), @@ -743,11 +739,26 @@ fsp_err_t R_RTC_CallbackSet (rtc_ctrl_t * const p_ctrl, #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_instance_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if RTC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + rtc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(rtc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; #endif - p_instance_ctrl->p_callback = p_callback; p_instance_ctrl->p_context = p_context; p_instance_ctrl->p_callback_memory = p_callback_memory; @@ -923,7 +934,7 @@ static void r_rtc_call_callback (rtc_instance_ctrl_t * p_ctrl, rtc_event_t event #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c index 60e54cff7..b0155f062 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c @@ -24,24 +24,28 @@ typedef enum e_sce_aes_key_size { SCE_AES_KEY_SIZE_128 = 0, + SCE_AES_KEY_SIZE_192, SCE_AES_KEY_SIZE_256 } sce_aes_key_size_t; fsp_err_t (* init[])(const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) = { [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptInitSub, + [SCE_AES_KEY_SIZE_192] = HW_SCE_Aes192EncryptDecryptInitSub, [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptInitSub, }; void (* update[])(const uint32_t * InData_Text, uint32_t * OutData_Text, const uint32_t MAX_CNT) = { [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptUpdateSub, + [SCE_AES_KEY_SIZE_192] = HW_SCE_Aes192EncryptDecryptUpdateSub, [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptUpdateSub, }; fsp_err_t (* final[])(void) = { [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptFinalSub, + [SCE_AES_KEY_SIZE_192] = HW_SCE_Aes192EncryptDecryptFinalSub, [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptFinalSub, }; @@ -131,6 +135,58 @@ fsp_err_t HW_SCE_AES_128EcbDecrypt (const uint32_t * InData_KeyIndex, OutData_Text); } +fsp_err_t HW_SCE_AES_192EcbEncryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_192, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_192EcbDecryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_192, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_192EcbEncrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_192, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_192EcbDecrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_192, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + fsp_err_t HW_SCE_AES_256EcbEncryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, const uint32_t num_words, const uint32_t * InData_Text, @@ -193,6 +249,16 @@ fsp_err_t HW_SCE_AES_128CreateEncryptedKey (uint32_t * OutData_KeyIndex) return FSP_SUCCESS; } +fsp_err_t HW_SCE_AES_192CreateEncryptedKey (uint32_t * OutData_KeyIndex) +{ + if (FSP_SUCCESS != HW_SCE_GenerateAes192RandomKeyIndexSub(OutData_KeyIndex)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + fsp_err_t HW_SCE_AES_256CreateEncryptedKey (uint32_t * OutData_KeyIndex) { if (FSP_SUCCESS != HW_SCE_GenerateAes256RandomKeyIndexSub(OutData_KeyIndex)) diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c index 3f37a966b..9c86274f6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c @@ -93,12 +93,12 @@ fsp_err_t HW_SCE_ECC_256GenerateSign (const uint32_t * InData_DomainParam, sce_oem_cmd_t key_command; /* NIST curve */ - if (0U == *InData_DomainParam) + if (SCE_ECC_CURVE_TYPE_NIST == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P256_PRIVATE; } /* Brainpool Curve */ - else if (1U == *InData_DomainParam) + else if (SCE_ECC_CURVE_TYPE_BRAINPOOL == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P256R1_PRIVATE; } @@ -117,7 +117,7 @@ fsp_err_t HW_SCE_ECC_256GenerateSign (const uint32_t * InData_DomainParam, wrapped_private_key); if (FSP_SUCCESS == err) { - err = HW_SCE_EcdsaSigunatureGenerateSub(InData_DomainParam, + err = HW_SCE_EcdsaSignatureGenerateSub(InData_DomainParam, InData_G, wrapped_private_key, InData_MsgDgst, @@ -140,7 +140,7 @@ fsp_err_t HW_SCE_ECC_256HrkGenerateSign (const uint32_t * InData_DomainParam, uint32_t * OutData_S) { uint32_t signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U)] = {0}; - fsp_err_t err = HW_SCE_EcdsaSigunatureGenerateSub(InData_DomainParam, + fsp_err_t err = HW_SCE_EcdsaSignatureGenerateSub(InData_DomainParam, InData_G, InData_KeyIndex, InData_MsgDgst, @@ -165,12 +165,12 @@ fsp_err_t HW_SCE_ECC_384GenerateSign (const uint32_t * InData_DomainParam, uint32_t wrapped_private_key[17U]; sce_oem_cmd_t key_command; /* NIST curve */ - if (0U == *InData_DomainParam) + if (SCE_ECC_CURVE_TYPE_NIST == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P384_PRIVATE; } /* Brainpool Curve */ - else if (1U == *InData_DomainParam) + else if (SCE_ECC_CURVE_TYPE_BRAINPOOL == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P384R1_PRIVATE; } @@ -189,7 +189,7 @@ fsp_err_t HW_SCE_ECC_384GenerateSign (const uint32_t * InData_DomainParam, if (FSP_SUCCESS == err) { err = - HW_SCE_EcdsaP384SigunatureGenerateSub(InData_DomainParam, wrapped_private_key, InData_MsgDgst, signature); + HW_SCE_EcdsaP384SignatureGenerateSub(InData_DomainParam, wrapped_private_key, InData_MsgDgst, signature); } if (FSP_SUCCESS == err) { @@ -208,7 +208,7 @@ fsp_err_t HW_SCE_ECC_384HrkGenerateSign (const uint32_t * InData_DomainParam, uint32_t * OutData_S) { uint32_t signature[HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U] = {0}; - fsp_err_t err = HW_SCE_EcdsaP384SigunatureGenerateSub(InData_DomainParam, InData_KeyIndex, InData_MsgDgst, signature); + fsp_err_t err = HW_SCE_EcdsaP384SignatureGenerateSub(InData_DomainParam, InData_KeyIndex, InData_MsgDgst, signature); if (FSP_SUCCESS == err) { memcpy(OutData_R, signature, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); @@ -231,12 +231,12 @@ fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_DomainParam, memcpy(&signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], InData_S, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); sce_oem_cmd_t key_command; /* NIST curve */ - if (0U == *InData_DomainParam) + if (SCE_ECC_CURVE_TYPE_NIST == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P256_PUBLIC; } /* Brainpool Curve */ - else if (1U == *InData_DomainParam) + else if (SCE_ECC_CURVE_TYPE_BRAINPOOL == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P256R1_PUBLIC; } @@ -255,7 +255,7 @@ fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_DomainParam, if (FSP_SUCCESS == err) { /* InData_DomainParam = curve type; InData_G = command */ - err = HW_SCE_EcdsaSigunatureVerificationSub(InData_DomainParam, InData_G, formatted_public_key, InData_MsgDgst, + err = HW_SCE_EcdsaSignatureVerificationSub(InData_DomainParam, InData_G, formatted_public_key, InData_MsgDgst, signature); } return err; @@ -275,12 +275,12 @@ fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_DomainParam, sce_oem_cmd_t key_command; /* NIST curve */ - if (0U == *InData_DomainParam) + if (SCE_ECC_CURVE_TYPE_NIST == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P384_PUBLIC; } /* Brainpool Curve */ - else if (1U == *InData_DomainParam) + else if (SCE_ECC_CURVE_TYPE_BRAINPOOL == *InData_DomainParam) { key_command = SCE_OEM_CMD_ECC_P384R1_PUBLIC; } @@ -298,7 +298,7 @@ fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_DomainParam, formatted_public_key); if (FSP_SUCCESS == err) { - err = HW_SCE_EcdsaP384SigunatureVerificationSub(InData_DomainParam, formatted_public_key, InData_MsgDgst, signature); + err = HW_SCE_EcdsaP384SignatureVerificationSub(InData_DomainParam, formatted_public_key, InData_MsgDgst, signature); } return err; diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c index 862bb493d..65f019282 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c @@ -124,10 +124,9 @@ fsp_err_t HW_SCE_McuSpecificInit (void) if (FSP_SUCCESS == iret) { - iret = HW_SCE_SelfCheck2Sub(); - /* Change SCE to little endian mode */ SCE->REG_1D4H = 0x0000ffff; + if (FSP_SUCCESS == iret) { iret = HW_SCE_HUK_Load_LCS(); @@ -135,6 +134,12 @@ fsp_err_t HW_SCE_McuSpecificInit (void) if (FSP_SUCCESS == iret) { iret = HW_SCE_FwIntegrityCheck(); + + /* This check is moved from before the endian setting for the updated fastboot procedures */ + iret = HW_SCE_SelfCheck2Sub(); + + /* This check is only needed if RSA 3K or 4K are bing used. */ + iret = HW_SCE_SelfCheck3Sub(); } } } diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c index d11b95dfa..87d6d5017 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c index a9dc906b2..c86c27521 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c index e1fbd0a88..4ddd9389c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c index 3fe52818b..0f484a8e6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c index 7e8a40314..79ba6fa7e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c index defeadce4..a99696133 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c index 9b8fb004a..e5274e671 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c index 4c7d37735..1e6fecfc3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c index bf8e69012..010bd1ef6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c index 16d2f435f..f87d8eabe 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c index 04c7c4401..14a93a752 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c index 882e4850e..5be712224 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c index 7afa3da9a..ff89b886d 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c index 0460a9f27..847bc7039 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c index 3fbc1c4d2..6e1d5a64f 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c index 6672fd601..69d16475d 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c index bcb573eb0..2971c283e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c index 43f3cb9ca..6453c32ff 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c index 6b355eebf..170203912 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c index 164342466..66bea49f2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c index 5f098fb3e..8b869f10f 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c index 6f2d9a5f1..0c8ce979e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c index ff3863091..288f408e5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c index 55d6be917..261a6404b 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c index 4ea2a87ec..be1f750a9 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c index b45d6cb5e..96f0759ad 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c index ef42caca4..b9f1336c1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c index 2f650bdc0..f6f86d097 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c index 7748ee081..6178f1135 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c index f43962b0a..0166a15bb 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c index f98149efd..5b75553a2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c index f63b6122b..86f318eb5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c index 3ecf76770..c15e668ad 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c index b918e939f..81dca6851 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c index e7f7eccf1..66516d1ff 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c index 17edf1a06..fa9a11601 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c index 7e76d7c72..1548eb1ce 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c index daed00e47..ce3dfecde 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c index c6b7ee2e6..a545eb8e0 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c index dbeeedecf..4e3f27a9e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func205.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func205.c new file mode 100644 index 000000000..9c5e016ac --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func205.c @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func205(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000u; + SCE->REG_1CH = 0x002d0000u; + SCE->REG_B0H = 0x00000001u; + SCE->REG_A4H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func205.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c index 2aeaf2be2..a69445ebe 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func207.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func207.c new file mode 100644 index 000000000..907c3ee5e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func207.c @@ -0,0 +1,82 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func207(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000u; + SCE->REG_104H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000u; + SCE->REG_1CH = 0x002d0000u; + SCE->REG_B0H = 0x00000001u; + SCE->REG_A4H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func207.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c index 32f931b2f..10da2c0d7 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c index 241ef399d..01718660a 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c index a3bc06bad..01a233937 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c index 45d3a8634..6eb9ff5ee 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c index 22d8615f5..f0bb8c4de 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c index 171bf0964..7fed7e79b 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c index 2ca462575..d0d4398fd 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c index 3734454db..48ebfb438 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c index 250fb6aea..5b15178a8 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c index 40c477e21..46dd345c9 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c index c3f1b966c..57602cef4 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c index c6653cf11..ba5748807 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c index a32908109..e847e8c39 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c index 8a23a6b8b..2442a13a6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c index 80eba1cf0..465793eb2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c index df5accfe2..8282e8784 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c index 8b5e32cc7..e871c49ef 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c index 7e4e739f2..61bd69428 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c index b211f54fc..6a39b9e1b 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c index 0c8967151..8afe480b8 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c index abfb14544..c7373b77c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c index b8140d134..cff45c47d 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c index c904dd279..bc0faf70b 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c index 785e7b51a..a906c50bd 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c index f3d439a45..14a0a07b3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c index 141b8547a..7eb3c8fa3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00000201u; + SCE->REG_84H = 0x00000202u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x00093b8cu; @@ -76,7 +77,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x01c7ba56u; + SCE->REG_100H = change_endian_long(0x01c7ba56u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x00070804u; /* WAIT_LOOP */ @@ -84,7 +85,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; + SCE->REG_100H = change_endian_long(0x00000000u); SCE->REG_ECH = 0x3000a820u; SCE->REG_ECH = 0x00000003u; SCE->REG_ECH = 0x00010020u; @@ -113,7 +114,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) SCE->REG_ECH = 0x000000b7u; for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) { - HW_SCE_p_func100(change_endian_long(0x600eb3f3u), change_endian_long(0x5be54db5u), change_endian_long(0xd957da80u), change_endian_long(0xb7be0bbdu)); + HW_SCE_p_func100(0x6c71e264u, 0x905d3c7cu, 0x2a4c435eu, 0xbdb4777bu); SCE->REG_ECH = 0x00007c01u; SCE->REG_1CH = 0x00600000u; SCE->REG_1D0H = 0x00000000u; @@ -125,7 +126,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) /* waiting */ } SCE->REG_64H = 0x0020901cu; - HW_SCE_p_func101(change_endian_long(0x1cb8f160u), change_endian_long(0x44a42eb9u), change_endian_long(0xb9d9de91u), change_endian_long(0xf7e69233u)); + HW_SCE_p_func101(0x4ed68504u, 0x34692cfcu, 0xa224db89u, 0x08268dfbu); } else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) { @@ -135,7 +136,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) /* waiting */ } SCE->REG_64H = 0x0020901eu; - HW_SCE_p_func101(change_endian_long(0x59fb7336u), change_endian_long(0x9c8f2482u), change_endian_long(0xc090f97fu), change_endian_long(0x0dba80dfu)); + HW_SCE_p_func101(0x7de6d907u, 0x8a506eeau, 0x951e9155u, 0x15bb7447u); } else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) { @@ -145,7 +146,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) /* waiting */ } SCE->REG_64H = 0x0020901du; - HW_SCE_p_func101(change_endian_long(0xed4e6151u), change_endian_long(0xc771e206u), change_endian_long(0x81266996u), change_endian_long(0x2bbee94du)); + HW_SCE_p_func101(0x6f12da0du, 0xb83a404au, 0x1332d5efu, 0x94827cceu); } SCE->REG_C4H = 0x41001e5eu; SCE->REG_00H = 0x80002401u; @@ -185,7 +186,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) SCE->REG_ECH = 0x34202808u; SCE->REG_ECH = 0x10005066u; SCE->REG_ECH = 0x00003485u; - HW_SCE_p_func101(change_endian_long(0x48b1bfc2u), change_endian_long(0x2f0d98c0u), change_endian_long(0xff07792fu), change_endian_long(0x166d190cu)); + HW_SCE_p_func101(0xca3b3ea4u, 0x71236437u, 0x3e0d1f89u, 0x58d2df4bu); } SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000B50u; @@ -227,12 +228,12 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) SCE->REG_ECH = 0x00000000u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(change_endian_long(0xaddf6f7bu), change_endian_long(0xae6de2f8u), change_endian_long(0xf97e7cdau), change_endian_long(0x68b0a447u)); + HW_SCE_p_func100(0x25d4d69bu, 0x231245f9u, 0x52a77bdau, 0xba7e5bc8u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(change_endian_long(0x2c21e21cu), change_endian_long(0x8f10bb7au), change_endian_long(0x7714e304u), change_endian_long(0x3807136cu)); + HW_SCE_p_func102(0x7d948770u, 0x3e084379u, 0xc51558cau, 0x81647cd1u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -243,6 +244,11 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) } else { + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000001f0u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x2e24c972u; + SCE->REG_ECH = 0x00003ffeu; /* WAIT_LOOP */ while (0u != SCE->REG_64H_b.B11) { @@ -256,7 +262,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; + SCE->REG_100H = change_endian_long(0x00000000u); SCE->REG_E0H = 0x80040000u; SCE->REG_00H = 0x00008213u; /* WAIT_LOOP */ @@ -287,7 +293,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) /* waiting */ } SCE->REG_1CH = 0x00001800u; - HW_SCE_p_func100(change_endian_long(0xcfbe1fc5u), change_endian_long(0xae3c0b75u), change_endian_long(0xfa1b775cu), change_endian_long(0xfccd985au)); + HW_SCE_p_func100(0x8d0bfb78u, 0xe6d5ba61u, 0xf547a492u, 0x401bf606u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x000b0804u; /* WAIT_LOOP */ @@ -295,7 +301,7 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; + SCE->REG_100H = change_endian_long(0x00000000u); SCE->REG_104H = 0x00000352u; SCE->REG_C4H = 0x00070805u; /* WAIT_LOOP */ @@ -303,11 +309,11 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; - SCE->REG_100H = 0x00000000u; - SCE->REG_100H = 0x00000000u; - SCE->REG_100H = 0x00000001u; - HW_SCE_p_func100(change_endian_long(0xd69c553bu), change_endian_long(0x72e04337u), change_endian_long(0xcf6834e5u), change_endian_long(0x29b2da04u)); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000001u); + HW_SCE_p_func100(0xbffc56f3u, 0x242ee8afu, 0xd6f5a7f5u, 0xdc95f65eu); SCE->REG_D0H = 0x00000100u; SCE->REG_C4H = 0x0100b7f7u; SCE->REG_E0H = 0x81080000u; @@ -334,9 +340,9 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) /* waiting */ } SCE->REG_1CH = 0x00001800u; - HW_SCE_p_func100(change_endian_long(0x1c99323fu), change_endian_long(0x6c63dba1u), change_endian_long(0x38229203u), change_endian_long(0x22d91767u)); + HW_SCE_p_func100(0x48de5befu, 0x8b1403c2u, 0x1e08e8feu, 0xa1a7a87cu); HW_SCE_p_func103(); - HW_SCE_p_func100(change_endian_long(0x80b45ab9u), change_endian_long(0x4d97ab5fu), change_endian_long(0x3ef09550u), change_endian_long(0xa94d5b6eu)); + HW_SCE_p_func100(0x3cb5779eu, 0xbab174adu, 0xf71b0f88u, 0xbe7d89cdu); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x010d0c04u; /* WAIT_LOOP */ @@ -344,10 +350,10 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; - HW_SCE_p_func100(change_endian_long(0xe6c8760fu), change_endian_long(0x099c6fc6u), change_endian_long(0x1406eda2u), change_endian_long(0x580bd39cu)); + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x95ad7aabu, 0x2279e4ddu, 0x55fb6a92u, 0x431d725eu); HW_SCE_p_func103(); - HW_SCE_p_func100(change_endian_long(0xff2b1e8au), change_endian_long(0x3e6453b3u), change_endian_long(0xe33170b8u), change_endian_long(0xe2d6af49u)); + HW_SCE_p_func100(0x70782e85u, 0x7706b601u, 0x736af867u, 0x38a12bdfu); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -355,19 +361,19 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) { /* waiting */ } - SCE->REG_100H = 0x00000000u; + SCE->REG_100H = change_endian_long(0x00000000u); SCE->REG_04H = 0x00000212u; /* WAIT_LOOP */ while (1u != SCE->REG_04H_b.B30) { /* waiting */ } - S_RAM[16] = change_endian_long(SCE->REG_100H); - S_RAM[17] = change_endian_long(SCE->REG_100H); - S_RAM[18] = change_endian_long(SCE->REG_100H); - S_RAM[19] = change_endian_long(SCE->REG_100H); - SCE->REG_13CH = 0x00000221u; - HW_SCE_p_func102(change_endian_long(0xf3939357u), change_endian_long(0x04e0f3c0u), change_endian_long(0x2c7db127u), change_endian_long(0x9914e276u)); + S_RAM[20] = change_endian_long(SCE->REG_100H); + S_RAM[21] = change_endian_long(SCE->REG_100H); + S_RAM[22] = change_endian_long(SCE->REG_100H); + S_RAM[23] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000202u; + HW_SCE_p_func102(0x75fe6fe1u, 0x9ab95ef0u, 0xec59c801u, 0x84cb693au); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -379,5 +385,5 @@ fsp_err_t HW_SCE_SelfCheck2Sub(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p02.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p02_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c index edf432f31..54c3d02f0 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,9 +68,9 @@ fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00000701u; + SCE->REG_84H = 0x00000702u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0xf7efeb7eu, 0x5bdda299u, 0xe42a1e4fu, 0x767dea6au); + HW_SCE_p_func100(0x95582d71u, 0x39635633u, 0x15288f50u, 0x17f47b88u); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -103,7 +104,7 @@ fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) /* waiting */ } SCE->REG_100H = change_endian_long(0x00000007u); - HW_SCE_p_func101(0x513bef76u, 0xa59e0bb3u, 0xcdfad875u, 0x8d637e2eu); + HW_SCE_p_func101(0x41eb044fu, 0xd0879d0fu, 0x836bd0a6u, 0xdd94cd7au); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000005u; @@ -197,5 +198,5 @@ fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p07.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p07_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c index c1fd1d731..108b253b1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,9 +68,9 @@ fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00000801u; + SCE->REG_84H = 0x00000802u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0xabd3565cu, 0x38ca4728u, 0x0c8efe13u, 0x081a2236u); + HW_SCE_p_func100(0x486a111du, 0x29f6d6dau, 0xce91597du, 0xc63a80a5u); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -103,7 +104,7 @@ fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) /* waiting */ } SCE->REG_100H = change_endian_long(0x00000008u); - HW_SCE_p_func101(0x10a39676u, 0xc3d8a8a9u, 0xfbeb969eu, 0x182d783du); + HW_SCE_p_func101(0x9d1d30efu, 0x04e6289bu, 0x0e7f730cu, 0x678b980cu); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000007u; @@ -223,5 +224,5 @@ fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p08.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p08_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p15.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p15.c new file mode 100644 index 000000000..cbbbcf564 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p15.c @@ -0,0 +1,235 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00001502u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x8a3f7abfu, 0x7a0fe242u, 0x2449afa3u, 0xb83f77f7u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000015u); + HW_SCE_p_func101(0x22bac565u, 0x0cf2f0ecu, 0xe2e27d12u, 0xc9ed944cu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000015u); + HW_SCE_p_func101(0x43a602beu, 0xa4429645u, 0xfc3db196u, 0xd7ddd670u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x594fe665u, 0x313bef0du, 0xbab591bcu, 0x02e355f5u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0x0b19c726u, 0x20c53570u, 0x6e8e367fu, 0x0ed1140eu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x78784c0bu, 0x3dea15d3u, 0x5a6e702au, 0x1e3b4f1au); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xbe7d9f88u, 0x8bf3700fu, 0x4e302cbdu, 0xc15dac08u); + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02e487b7u; + SCE->REG_E0H = 0x81060000u; + SCE->REG_00H = 0x0000281bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000200bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000002u); + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func102(0x51a7e640u, 0x3745d3b6u, 0x46baf5d7u, 0x6b52b63au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p15_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p16.c new file mode 100644 index 000000000..7d52f40b1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p16.c @@ -0,0 +1,228 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00001602u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x23abec22u, 0x8cf54808u, 0xc13237e2u, 0x9a50f88eu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000016u); + HW_SCE_p_func101(0xe3d75acdu, 0x11fa95d0u, 0x508ff661u, 0xcd3dfd25u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000016u); + HW_SCE_p_func101(0x0a880954u, 0x2767556eu, 0x46025dcau, 0x03f28176u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x78fddeb7u, 0xcd696f78u, 0x248a93b6u, 0xdb183ccau); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0xc3dfa0c4u, 0xe272767cu, 0x89df66a4u, 0x60ea4544u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x5ed79631u, 0x284935b8u, 0xc863a7c0u, 0x60086c93u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x18ecfd57u, 0xcfc37c4du, 0x13576bd2u, 0x9a282ac0u); + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02e487b7u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00002823u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000002u); + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func102(0x047a9547u, 0xe7880d65u, 0xc7a1f12bu, 0xe56f2361u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p16_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p17.c new file mode 100644 index 000000000..35f9717f3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p17.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00001702u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x737bb4a5u, 0xbff6a348u, 0xaeb16686u, 0xe2d29c1au); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000017u); + HW_SCE_p_func101(0x4815a41cu, 0x00916820u, 0xbe01c103u, 0x1dec006au); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000009u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000017u); + HW_SCE_p_func101(0xd842bfd1u, 0xd2970d65u, 0xbc2702f7u, 0x02db49feu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xf7d92364u, 0x5552bf8au, 0x97e251cdu, 0xecbc6a8cu); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0x9393aedfu, 0x0a40b1f7u, 0x05756c3au, 0x1b56ba0cu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80100000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xac85b8abu, 0xee4cd758u, 0xa30bc79du, 0x400754d0u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x72864ca0u, 0xa02a9463u, 0x51458194u, 0x25480ca7u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xca854ddfu, 0x013d0d2bu, 0xbae6953fu, 0x203b2168u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x98a0b10bu, 0xbc9e675fu, 0xc7c22bccu, 0xc608476eu); + SCE->REG_D0H = 0x40000300u; + SCE->REG_C4H = 0x02e487b7u; + SCE->REG_E0H = 0x81100000u; + SCE->REG_00H = 0x00002843u; + SCE->REG_04H = 0x00000242u; + for(iLoop=1; iLoop<17; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_p_func100(0x6d2f16f6u, 0xa21672b3u, 0x54a9986cu, 0xb2894ec7u); + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000004u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + HW_SCE_p_func102(0xe907d5eeu, 0x06fc1a87u, 0x4695e21du, 0x9b334c1du); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p17_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c index d683ecfc1..3e50dcc1f 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,9 +68,9 @@ fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00002001u; + SCE->REG_84H = 0x00002002u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0x39474ca5u, 0x2734ab38u, 0xac8a3b6eu, 0xd618ffa1u); + HW_SCE_p_func100(0xcc566a95u, 0xd54b495bu, 0x13b7c5d5u, 0xf9a0c228u); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -79,7 +80,7 @@ fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) /* waiting */ } SCE->REG_100H = change_endian_long(0x00000000u); - HW_SCE_p_func100(0x78680554u, 0x7e6bcbf3u, 0x28e0c2d1u, 0x77ed0e82u); + HW_SCE_p_func100(0xf90a114au, 0x4d146fe5u, 0x5da04d77u, 0xef4683f4u); SCE->REG_04H = 0x00000213u; /* WAIT_LOOP */ while (1u != SCE->REG_04H_b.B30) @@ -90,7 +91,7 @@ fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) OutData_Text[1] = SCE->REG_100H; OutData_Text[2] = SCE->REG_100H; OutData_Text[3] = SCE->REG_100H; - HW_SCE_p_func102(0xabc3a4dbu, 0x2a94f5aeu, 0xd92f7679u, 0x10c3f31bu); + HW_SCE_p_func102(0x5cf23bfeu, 0x974c37aeu, 0xb6dfffc7u, 0xb05e02eeu); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -101,5 +102,5 @@ fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p20.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p20_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c index 4c464249c..0191e5a65 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c index 8edcbe80e..2251d88b1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -69,8 +70,18 @@ fsp_err_t HW_SCE_FwIntegrityCheck(void) } SCE->REG_84H = 0x00002601u; SCE->REG_108H = 0x00000000u; + SCE->REG_84H = 0x00010002u; + SCE->REG_13CH = 0x00000F01u; + SCE->REG_84H = 0x00010003u; + SCE->REG_13CH = 0x00000F01u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000001f0u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003ffeu; + SCE->REG_84H = 0x00010001u; SCE->REG_13CH = 0x00000202u; - HW_SCE_p_func102(0xe8e880e8u, 0xe878ca41u, 0x69b6222du, 0x05286da4u); + HW_SCE_p_func102(0x5e152cc3u, 0x70c33839u, 0x6c11afcdu, 0x3a544458u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -81,5 +92,5 @@ fsp_err_t HW_SCE_FwIntegrityCheck(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p26.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p26_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c index 90a2fa316..dbb413c8e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -81,5 +82,5 @@ void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CN } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29a.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29a_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c index 12594caeb..b3d51c135 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -228,5 +229,5 @@ fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InDat } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29f.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29f_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c index 97f7765df..21ff60daf 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00002901u; + SCE->REG_84H = 0x00002902u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -75,10 +76,10 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010000u; /* WAIT_LOOP */ @@ -91,7 +92,7 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD SCE->REG_ECH = 0x00000001u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x14acce85u, 0xe0e82b06u, 0x325e8e2bu, 0x080c3070u); + HW_SCE_p_func100(0xaf5f3545u, 0x1ae9eac6u, 0x97916425u, 0xda489c67u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -107,7 +108,7 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD SCE->REG_ECH = 0x38000c00u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0x6632700eu, 0x54bb2b0au, 0x0628c928u, 0x67a53130u); + HW_SCE_p_func100(0x47510073u, 0x644e4901u, 0x2941a0fbu, 0x133e01c2u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -120,7 +121,7 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000029u); - HW_SCE_p_func101(0x1d5278e5u, 0xa5f75927u, 0xbe17b68bu, 0xe94b042du); + HW_SCE_p_func101(0x3e47319cu, 0xd7bff6aau, 0xf4e0b9ebu, 0x1dea1c02u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000005u; @@ -137,11 +138,11 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000029u); - HW_SCE_p_func101(0x5de8814fu, 0x0934c569u, 0x807e2b3du, 0x9714458eu); + HW_SCE_p_func101(0x9aa21d07u, 0x688a82edu, 0x1189b8d7u, 0xe29f2684u); HW_SCE_p_func068(); SCE->REG_ECH = 0x0000b4e0u; - SCE->REG_ECH = 0x2a46c04bu; - HW_SCE_p_func101(0xc33a264eu, 0x5c158979u, 0xd4fbbf71u, 0xd47008abu); + SCE->REG_ECH = 0x0146c04bu; + HW_SCE_p_func101(0xe420a06fu, 0x2d5c4d73u, 0x07a4a937u, 0x9a0afc88u); } SCE->REG_104H = 0x00000058u; SCE->REG_E0H = 0x800103a0u; @@ -281,7 +282,7 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000029u); - HW_SCE_p_func101(0x068dd838u, 0xf01d1660u, 0x2496a07du, 0x5528979bu); + HW_SCE_p_func101(0x2adc7d02u, 0x788211e1u, 0x24bdf442u, 0xdf007432u); HW_SCE_p_func059(); HW_SCE_p_func100(0x85c33db3u, 0xfaf76717u, 0x874d3287u, 0x50161587u); SCE->REG_104H = 0x00000362u; @@ -397,5 +398,5 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InD } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29i_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29i_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c index 4b72cf1d3..78e93db63 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -84,5 +85,5 @@ void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29t.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29t_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c index fc4621970..7969638d1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -119,5 +120,5 @@ void HW_SCE_Aes128GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_T } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29u.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29u_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c index 1e2e4a30d..492c8b217 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,11 +68,11 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00002b01u; + SCE->REG_84H = 0x00002b02u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0x8c22ebc6u, 0xbac7b812u, 0x923c6843u, 0xf8ce1439u); + HW_SCE_p_func100(0x29802336u, 0xd159a0b7u, 0xe311d54cu, 0x36dce5c5u); HW_SCE_p_func103(); - HW_SCE_p_func100(0x94583792u, 0x24e30c80u, 0x32f50786u, 0x671c03ecu); + HW_SCE_p_func100(0xb8dc77d4u, 0x3247864du, 0xc9a3aaf3u, 0x419c0ae7u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01080c84u; /* WAIT_LOOP */ @@ -164,7 +165,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou } SCE->REG_1CH = 0x00001800u; SCE->REG_28H = 0x009f0001u; - HW_SCE_p_func100(0x7e5acf8bu, 0xd2737edau, 0x4eae0493u, 0x1a30791cu); + HW_SCE_p_func100(0x7c3be8a4u, 0x10077703u, 0x98320738u, 0x5903bfb6u); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -194,7 +195,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1CH = 0x00001800u; for(iLoop = 0; iLoop < 24; iLoop = iLoop + 4) { - HW_SCE_p_func100(0x07a1fbc9u, 0xe02e1b04u, 0xfe51796bu, 0x3e56e547u); + HW_SCE_p_func100(0x10e16e07u, 0x8fb49ab6u, 0xf23e1fdfu, 0x970de29au); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -211,9 +212,9 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou /* waiting */ } SCE->REG_1CH = 0x00001800u; - HW_SCE_p_func101(0xd2b54d13u, 0xf1bac9dbu, 0x985665fcu, 0x4686ee7du); + HW_SCE_p_func101(0xfc43caa7u, 0xb55af2a9u, 0x6c16fba1u, 0x313b167cu); } - HW_SCE_p_func100(0x07a1fbc9u, 0xe02e1b04u, 0xfe51796bu, 0x3e56e547u); + HW_SCE_p_func100(0x10e16e07u, 0x8fb49ab6u, 0xf23e1fdfu, 0x970de29au); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -292,17 +293,17 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou /* waiting */ } SCE->REG_1CH = 0x00210000u; - HW_SCE_p_func100(0xf2a4147au, 0x0eab872fu, 0x3dd27a2bu, 0x1960df16u); + HW_SCE_p_func100(0x90ae1e92u, 0x8bca1ce6u, 0x377f1b58u, 0x7427eca8u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0x2b6e9024u, 0x64c4b8b0u, 0xb11bfcd4u, 0xf8f01459u); + HW_SCE_p_func101(0x5cba8941u, 0x18800bcfu, 0x699933a2u, 0xc0a9c83du); continue; } else { - HW_SCE_p_func101(0xbce884a9u, 0xb4300625u, 0xeb8ed2e5u, 0x145cbbdau); + HW_SCE_p_func101(0x755f15bcu, 0xfaa7c752u, 0x8cdee2ccu, 0x7c5d5e22u); } SCE->REG_ECH = 0x38008a20u; SCE->REG_ECH = 0x00000001u; @@ -379,7 +380,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0x6e42246au, 0x0051e8dcu, 0x3afb2da8u, 0xfc5b0241u); + HW_SCE_p_func101(0xe281d2f1u, 0x0c9fbf53u, 0xf7faeb43u, 0xc9102828u); continue; } else @@ -456,7 +457,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0xa0c54035u, 0xdbc1038cu, 0x6dffe9ffu, 0x22939bb3u); + HW_SCE_p_func101(0xebf0bae4u, 0x21cca239u, 0xd872659au, 0xfcdcf0fcu); continue; } SCE->REG_24H = 0x000011c0u; @@ -540,7 +541,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0xa64df750u, 0x1eacebc9u, 0xa9607bc6u, 0xea154560u); + HW_SCE_p_func101(0x5436329au, 0x9632d27fu, 0x10281c9eu, 0xc0df0d5fu); } else { @@ -632,7 +633,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0x0c4d57c7u, 0x3f5c6c0fu, 0x0a22b208u, 0xc6301377u); + HW_SCE_p_func101(0xbe8e9962u, 0x0bda5eb5u, 0x5c30c9c9u, 0x33a96ae3u); continue; } SCE->REG_24H = 0x000098d0u; @@ -1196,7 +1197,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0x144c6c66u, 0x8a422809u, 0xaca7266eu, 0xcd70f9f0u); + HW_SCE_p_func101(0x72ead49bu, 0x3189737du, 0x9848fc7du, 0x2304bad9u); break; } else @@ -1213,12 +1214,12 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou { /* waiting */ } - HW_SCE_p_func101(0x817dcc5du, 0x7630144fu, 0x631df7e6u, 0xd908d8c8u); + HW_SCE_p_func101(0x4165eaaau, 0xde546422u, 0x77a875aau, 0x47feb412u); } } else { - HW_SCE_p_func101(0xdbba2aa6u, 0xbe5543d3u, 0xd39ab5a0u, 0x758fd189u); + HW_SCE_p_func101(0x424beb5fu, 0x7e7bd614u, 0xc3225a20u, 0xaa7eb3c8u); } } } @@ -1226,12 +1227,12 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou SCE->REG_ECH = 0x00000002u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x43009d9cu, 0xb0aaa3a1u, 0x29a32de2u, 0x777a8077u); + HW_SCE_p_func100(0x797c9f8cu, 0xf9c42989u, 0xc34235dcu, 0xabd7d990u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0xdcc9ddc5u, 0x77d8925bu, 0xe4eec2cfu, 0x8a66a099u); + HW_SCE_p_func102(0x9557ba67u, 0x07316373u, 0x90ae53f1u, 0x62dc9458u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -1240,7 +1241,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou } return FSP_ERR_CRYPTO_SCE_FAIL; } - HW_SCE_p_func100(0xc897604bu, 0x7ea24896u, 0x6b2b64f0u, 0x4757ffa2u); + HW_SCE_p_func100(0xac0314bdu, 0x515c4e7eu, 0xb9f37c2bu, 0xa620448du); SCE->REG_ECH = 0x0000b5c0u; SCE->REG_ECH = 0x00010001u; SCE->REG_24H = 0x000019c0u; @@ -1297,7 +1298,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou S_HEAP[iLoop + 2] = SCE->REG_100H; S_HEAP[iLoop + 3] = SCE->REG_100H; } - HW_SCE_p_func100(0xf04437edu, 0xd2f2aa45u, 0x8905e13bu, 0x87f50a93u); + HW_SCE_p_func100(0xd43ec52du, 0x5fb382ecu, 0xa9cc436cu, 0x4d6b8853u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x00000c84u; /* WAIT_LOOP */ @@ -1376,12 +1377,12 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou /* waiting */ } SCE->REG_1CH = 0x00210000u; - HW_SCE_p_func100(0x02a10e8bu, 0x345b9ec9u, 0x69707df5u, 0xf1d88be4u); + HW_SCE_p_func100(0xa7c960d8u, 0xb1109e97u, 0x6b23ed89u, 0x19ad0c6du); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func101(0x9493fa8fu, 0xc27e5124u, 0x25f9ca01u, 0x5acd770du); + HW_SCE_p_func101(0x1f9661cdu, 0x28746ae5u, 0x8cd2741du, 0x6ddec20bu); break; } else @@ -1404,7 +1405,7 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou { /* waiting */ } - HW_SCE_p_func101(0x0c4f97b0u, 0x9a3e48e8u, 0x89031f6bu, 0x5b814724u); + HW_SCE_p_func101(0x3f844510u, 0xe045fee9u, 0x9ccc4a88u, 0x014d4648u); } } SCE->REG_24H = 0x000094d0u; @@ -2297,5 +2298,5 @@ fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Ou } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p2b_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p2b_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c index fbf460a87..e0b3aba5f 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -81,5 +82,5 @@ void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CN } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32a.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32a_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c index dfabe2dd2..dae142eee 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -297,5 +298,5 @@ fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InDat } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32f.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32f_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c index 5b16e3114..e3110aa9e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00003201u; + SCE->REG_84H = 0x00003202u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -75,10 +76,10 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010000u; /* WAIT_LOOP */ @@ -94,7 +95,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD SCE->REG_ECH = 0x00000002u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0x717c7867u, 0x54b3db59u, 0xf733f6adu, 0x08933694u); + HW_SCE_p_func100(0x3e15d278u, 0x29418229u, 0x20cbf19fu, 0xd78e8134u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -110,7 +111,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD SCE->REG_ECH = 0x38000c00u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0xb32b9023u, 0x24f2ee1au, 0x9b53c05au, 0x9a3965beu); + HW_SCE_p_func100(0x87a0b2ddu, 0x026adc03u, 0x93a8dfeau, 0xf5ae5b87u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -123,7 +124,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000032u); - HW_SCE_p_func101(0x5ac26175u, 0x3e3950b9u, 0x3a17208du, 0xacd9c2fcu); + HW_SCE_p_func101(0x08eafffau, 0x3c3455aeu, 0x69a6c0f4u, 0xb54f8ea7u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000005u; @@ -140,7 +141,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000032u); - HW_SCE_p_func101(0x3136f03du, 0x13cefeacu, 0x38471846u, 0xb5290306u); + HW_SCE_p_func101(0x7259cb1bu, 0x9f84c893u, 0xa6879bddu, 0x63d60a09u); HW_SCE_p_func068(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0146c04bu; @@ -230,7 +231,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD SCE->REG_ECH = 0x00000001u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0x34d06864u, 0xfcdeb896u, 0x6bf199cau, 0x8dd419d7u); + HW_SCE_p_func100(0x3f3e1153u, 0xcf793552u, 0xe4d7efe6u, 0x14c50f80u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -292,7 +293,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000032u); - HW_SCE_p_func101(0xfdbb289cu, 0xb29b7e31u, 0x8abf765cu, 0x1f97cc5eu); + HW_SCE_p_func101(0x047ee2ccu, 0x6bd55018u, 0x422b9459u, 0x9faaf0aeu); HW_SCE_p_func059(); SCE->REG_104H = 0x00000362u; SCE->REG_D0H = 0x40000000u; @@ -374,7 +375,7 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD /* waiting */ } SCE->REG_100H = change_endian_long(0x00000005u); - HW_SCE_p_func101(0x9b614c1au, 0xbb50c8ccu, 0xaed5668du, 0x7f6205dau); + HW_SCE_p_func101(0xb5c6f42fu, 0x7a27fa8cu, 0xa5ddd6adu, 0x57736414u); HW_SCE_p_func068(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0195f71du; @@ -512,5 +513,5 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32i_r2.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32i_r3.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c index 774787274..21e169905 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -84,5 +85,5 @@ void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32t.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32t_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c index e675059bb..f592de159 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -119,5 +120,5 @@ void HW_SCE_Aes128GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_T } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32u.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32u_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c index 4726e3859..1daee1408 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c index fa240ecd4..45fd771ed 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c index ffb1c05c5..f889d9c7a 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c index 8d1531a24..4d1ad07a2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c index 0a5cb67c1..b88397d50 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c index 5d5e1631e..aafed45dd 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c index 3e3e0609d..42e87f082 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c index ff463a376..82461cba5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c index 310b113da..f059376f2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c index ef9b1836f..be7f20a5e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c index 534b6bc32..9959c462b 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -69,16 +70,6 @@ fsp_err_t HW_SCE_LoadHukSub(uint32_t *InData_LC) } SCE->REG_84H = 0x00004001u; SCE->REG_108H = 0x00000000u; - SCE->REG_C4H = 0x200e1a0du; - /* WAIT_LOOP */ - while (1u != SCE->REG_104H_b.B31) - { - /* waiting */ - } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; HW_SCE_p_func048(InData_LC); SCE->REG_ECH = 0x0000b420u; SCE->REG_ECH = 0x00000009u; @@ -89,54 +80,54 @@ fsp_err_t HW_SCE_LoadHukSub(uint32_t *InData_LC) if (InData_LC[0] == 0x00000000) { SCE->REG_1CH = 0x00b80000u; - HW_SCE_p_func101(0xe83b7e4eu, 0xdb097f27u, 0xb31d59d5u, 0x0daab77bu); + HW_SCE_p_func101(0x8df65220u, 0x66b86af0u, 0x024552f0u, 0x698bb6acu); } else if (InData_LC[0] == 0x00000001) { SCE->REG_1CH = 0x00b00000u; - HW_SCE_p_func101(0x78659d26u, 0x860f5f45u, 0x80267e4eu, 0x1f70b510u); + HW_SCE_p_func101(0x75474f29u, 0xcf9f73aau, 0xa8987b45u, 0x01019f0cu); } else if (InData_LC[0] == 0x00000002) { SCE->REG_1CH = 0x00b10000u; - HW_SCE_p_func101(0x2751871bu, 0xe89c2f48u, 0xf573d4cfu, 0x115ecb07u); + HW_SCE_p_func101(0x37fe7e13u, 0xdba1bf8du, 0xad1e7c16u, 0xf4949bbau); } else if (InData_LC[0] == 0x00000003) { SCE->REG_1CH = 0x00b20000u; - HW_SCE_p_func101(0xbba17e71u, 0xbc808154u, 0x1e078979u, 0x86405b9au); + HW_SCE_p_func101(0xcaf7e415u, 0x4128fb42u, 0xdb48afe2u, 0x99074a75u); } else if (InData_LC[0] == 0x00000004) { SCE->REG_1CH = 0x00b30000u; - HW_SCE_p_func101(0x4f20b598u, 0xd0dabac4u, 0xc7ad0190u, 0x75198e1cu); + HW_SCE_p_func101(0x57f8f4a6u, 0x94787521u, 0x31fcee4fu, 0x864d46bdu); } else if (InData_LC[0] == 0x00000005) { SCE->REG_1CH = 0x00b40000u; - HW_SCE_p_func101(0xf19a5f31u, 0x21feee6au, 0xce2fb686u, 0x6804e1f8u); + HW_SCE_p_func101(0xb16bd6fdu, 0xc927d654u, 0xfc8bef50u, 0x3d3513a4u); } else if (InData_LC[0] == 0x00000006) { SCE->REG_1CH = 0x00b50000u; - HW_SCE_p_func101(0x0524bae4u, 0xa2bdb569u, 0x3882d45bu, 0x0c17e0a9u); + HW_SCE_p_func101(0x086e5c12u, 0x2708cae7u, 0x24c60329u, 0xd6a1f0ceu); } else if (InData_LC[0] == 0x00000007) { SCE->REG_1CH = 0x00b60000u; - HW_SCE_p_func101(0xa9029f34u, 0x03b9f72cu, 0x0c3dea38u, 0x2168dc2bu); + HW_SCE_p_func101(0x64586489u, 0xe5ec3887u, 0xaf796043u, 0xf870aad7u); } else if (InData_LC[0] == 0x00000008) { SCE->REG_1CH = 0x00b70000u; - HW_SCE_p_func101(0x370593d5u, 0xa06496acu, 0x346be3f9u, 0x4ab24229u); + HW_SCE_p_func101(0xdd18b7c6u, 0x61da8f10u, 0x2dddd787u, 0x0986d7deu); } else { SCE->REG_ECH = 0x38000c00u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func101(0x4ef037fcu, 0x717efbf1u, 0x95329c71u, 0x33958d8du); + HW_SCE_p_func101(0x855d7c4au, 0x63f263fau, 0x172ed129u, 0x7c8fa20fu); } HW_SCE_p_func100(0xc49e2b89u, 0x3ccaecb7u, 0xa622a807u, 0x78f51bbeu); SCE->REG_1CH = 0x00400000u; @@ -352,5 +343,5 @@ else if (InData_LC[0] == 0x00000008) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p40_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p40_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44f.c new file mode 100644 index 000000000..3c0bd673b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44f.c @@ -0,0 +1,290 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xf12ceb80u, 0xd9c1ad15u, 0xf0601e59u, 0xebbb0fa5u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xda00fcb8u, 0xa57aaf1bu, 0x95160be9u, 0x895676beu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + if ((InData_Cmd[0] == 0x00000000) || (InData_Cmd[0] == 0x00000002)) + { + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00408a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func101(0x12a5767bu, 0x9b238f34u, 0x03fc5a80u, 0xe1114431u); + } + else + { + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00508a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func101(0x105cc13cu, 0xe11d8e1eu, 0x624ffeabu, 0xb00e22f8u); + } + SCE->REG_A4H = 0x00040c05u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + if ((InData_Cmd[0] == 0x00000000) || (InData_Cmd[0] == 0x00000001)) + { + HW_SCE_p_func100(0xab3f8b13u, 0x24985a75u, 0x9d898c5eu, 0x5378c4b9u); + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e95u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_p_func102(0xd572dcd4u, 0xdc606567u, 0x854156cau, 0x4c0d8e84u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010040u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x3420a840u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b460u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x34202862u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x2d0117a5u, 0x824ffaadu, 0xdc4caf16u, 0x2cc10babu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xd84af4b1u, 0x556cb646u, 0xbc9c491bu, 0x55808f8du); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e95u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e2u; + SCE->REG_ECH = 0x000568e7u; + SCE->REG_ECH = 0x00026ce7u; + SCE->REG_ECH = 0x00003827u; + SCE->REG_ECH = 0x0000b4c0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x00003402u; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x000028c0u; + SCE->REG_ECH = 0x00008cc0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x00004406u; + SCE->REG_ECH = 0x00007421u; + SCE->REG_ECH = 0x00007821u; + SCE->REG_ECH = 0x00003c27u; + SCE->REG_ECH = 0x000034c2u; + SCE->REG_ECH = 0x0000a4c0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x000568c6u; + SCE->REG_ECH = 0x000034e6u; + SCE->REG_ECH = 0x00026ce7u; + SCE->REG_ECH = 0x00000821u; + for (iLoop = 0; iLoop < 4; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3420a8e0u; + SCE->REG_ECH = 0x0000000du; + SCE->REG_ECH = 0x10003c27u; + SCE->REG_ECH = 0x1000a4e0u; + SCE->REG_ECH = 0x00000004u; + } + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00900c05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + HW_SCE_p_func100(0x5213259fu, 0xa67e25cdu, 0x3200d319u, 0x0cf582a1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x3e4ea75bu, 0x922e715bu, 0x60bb4b70u, 0x7cddda01u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0xa03574e2u, 0xb7c3a1c9u, 0x6c50faf9u, 0x2a69090cu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p44f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44i.c new file mode 100644 index 000000000..269007e0a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44i.c @@ -0,0 +1,192 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004401u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044u); + HW_SCE_p_func101(0xed65bc73u, 0x6a5357d7u, 0x25560ad3u, 0xd86b72bdu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044u); + HW_SCE_p_func101(0xd0478eddu, 0x872c4fe9u, 0x386eaf75u, 0x05893f0eu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x8a54b357u, 0x98550891u, 0x69fe01e2u, 0x4af1d4c9u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xf88a2aeeu, 0xf10d2f2cu, 0xf9a5b838u, 0xa6e9c999u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa211f1d0u, 0xb5eeecbdu, 0xc44ad209u, 0x84285284u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0f02d0e8u, 0x5e2fa0dbu, 0xd2e9123cu, 0x2aaa80ebu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p44i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44u.c new file mode 100644 index 000000000..7fdef1318 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p44u.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e16u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func101(0x8b06047cu, 0x92d9cc20u, 0xcec17685u, 0xe38a2596u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p44u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c index 56c2ffff4..6849f6305 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -111,5 +112,5 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47f.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47f_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c index f24dcf907..30db2bcd6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -69,7 +70,7 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00004701u; + SCE->REG_84H = 0x00004702u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -77,10 +78,10 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_E0H = 0x80010000u; SCE->REG_104H = 0x00000068u; /* WAIT_LOOP */ @@ -99,7 +100,7 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, SCE->REG_ECH = 0x00000005u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0xb52dabe4u, 0x204b14aau, 0xc2240b7du, 0x23a73aa2u); + HW_SCE_p_func100(0x858a1019u, 0xc34f62cdu, 0xea57d0acu, 0x0aee4802u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -120,7 +121,7 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, /* waiting */ } SCE->REG_100H = change_endian_long(0x00000047u); - HW_SCE_p_func101(0xd4e33cfeu, 0xd2687192u, 0x90dacf91u, 0x23025eabu); + HW_SCE_p_func101(0x0d35081bu, 0xbfc89a44u, 0x4b817b82u, 0x1e3a9efau); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000005u; @@ -244,7 +245,7 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, /* waiting */ } SCE->REG_100H = change_endian_long(0x00000047u); - HW_SCE_p_func101(0x777d2dd1u, 0x6efca390u, 0x2da7d617u, 0x6914cb47u); + HW_SCE_p_func101(0x771f6fe9u, 0x155336bcu, 0xa502adc2u, 0x151b8494u); HW_SCE_p_func059(); HW_SCE_p_func100(0x1d35c958u, 0x8ab99b81u, 0x1fab250au, 0xeeb14dabu); SCE->REG_104H = 0x00000362u; @@ -367,5 +368,5 @@ fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47i.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47i_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c index 7e4169b59..3609aa0d2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -171,5 +172,5 @@ void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_ } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47u.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47u_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c index d35655703..f7170c7f5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -111,5 +112,5 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50f.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50f_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c index 761d6f823..508723c19 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -69,7 +70,7 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00005001u; + SCE->REG_84H = 0x00005002u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -77,10 +78,10 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_E0H = 0x80010000u; SCE->REG_104H = 0x00000068u; /* WAIT_LOOP */ @@ -99,7 +100,7 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, SCE->REG_ECH = 0x00000005u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0x0e21cf93u, 0x39ff2075u, 0x975fe4d6u, 0xe5002de5u); + HW_SCE_p_func100(0xa75beb2du, 0x0b0dc6e8u, 0x742eeb18u, 0xde0c5645u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -120,7 +121,7 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, /* waiting */ } SCE->REG_100H = change_endian_long(0x00000050u); - HW_SCE_p_func101(0x63a10ee4u, 0x1c9962a7u, 0xc5c75ca8u, 0xa459db17u); + HW_SCE_p_func101(0xf2c83e65u, 0x7f80c6a7u, 0xaea2052au, 0x050e7614u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000007u; @@ -262,7 +263,7 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, /* waiting */ } SCE->REG_100H = change_endian_long(0x00000050u); - HW_SCE_p_func101(0x328609eau, 0xd57d7798u, 0xfb710b61u, 0xc3f90299u); + HW_SCE_p_func101(0xbe7770c1u, 0x76a8f8b8u, 0x83aabf34u, 0x8aaf31f8u); HW_SCE_p_func059(); HW_SCE_p_func100(0xfc41514eu, 0x17da911bu, 0xd1be8b6au, 0xb76ef6c2u); SCE->REG_104H = 0x00000762u; @@ -403,5 +404,5 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50i.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50i_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c index 32260fa6d..756a93041 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -176,5 +177,5 @@ void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_ } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50u.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50u_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c index 4fc1512b4..b8359d1d1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c index b6f66de27..c1e07c00e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, con { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00005701u; + SCE->REG_84H = 0x00005702u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x800100e0u; @@ -85,7 +86,7 @@ fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, con /* waiting */ } SCE->REG_100H = change_endian_long(0x00000057u); - HW_SCE_p_func101(0x1d6969f5u, 0x0401b04bu, 0x453404b5u, 0x19622c0cu); + HW_SCE_p_func101(0x0bf55ad3u, 0x2adb1b69u, 0x1d9b9787u, 0x023888abu); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0000000du; @@ -383,5 +384,5 @@ fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, con } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p57.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p57_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c index b3125580b..eccbdf910 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00006e01u; + SCE->REG_84H = 0x00006e02u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x800103e0u; @@ -80,7 +81,7 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa SCE->REG_ECH = 0x38000fffu; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0x785685e4u, 0x1eb8d70du, 0xe603298au, 0xf0890493u); + HW_SCE_p_func100(0x65d6015fu, 0xcef163cdu, 0xd36f3dbau, 0x9ff542e9u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -107,12 +108,12 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa SCE->REG_ECH = 0x00000010u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x1fc2eb2au, 0xb7a01ddau, 0xe60b956au, 0x2cd96153u); + HW_SCE_p_func100(0x98244c8cu, 0x79b8693eu, 0x27d09331u, 0x54bd7297u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0x158158fau, 0xac8c3ed0u, 0xa6fff060u, 0x701fd272u); + HW_SCE_p_func102(0x619b2415u, 0x1a64fb8fu, 0x72abf3c5u, 0xb1a9f8d3u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -133,7 +134,7 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa /* waiting */ } SCE->REG_100H = change_endian_long(0x0000006eu); - HW_SCE_p_func101(0x4e05f96fu, 0x9b1167c2u, 0x75157ed6u, 0x55f37badu); + HW_SCE_p_func101(0xa7637c51u, 0x0fdd3f7fu, 0x3ef7d917u, 0x86dcab7au); HW_SCE_p_func058(InData_SessionKey,OFS_ADR); SCE->REG_104H = 0x00000058u; SCE->REG_E0H = 0x80010380u; @@ -193,12 +194,12 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa SCE->REG_ECH = 0x00000024u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x3ddcbafau, 0x68190098u, 0x71aaccc8u, 0x13400e2fu); + HW_SCE_p_func100(0x7aef0fcbu, 0x9258934au, 0x8b4dbf1fu, 0xf15611dcu); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0x32392174u, 0x42e93794u, 0xfb704f82u, 0x2fa0736cu); + HW_SCE_p_func102(0x638045bau, 0xdc6175a9u, 0x99105401u, 0x7086cb16u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -218,7 +219,7 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa /* waiting */ } SCE->REG_100H = change_endian_long(0x0000006eu); - HW_SCE_p_func101(0xf791c673u, 0xdde49f4cu, 0xe3b14380u, 0x967940b2u); + HW_SCE_p_func101(0x083ef1a1u, 0x630e194cu, 0x4b5f490eu, 0x96a54f99u); HW_SCE_p_func065_r1(InData_InstData,OutData_KeyIndex); HW_SCE_p_func100(0x1cf9ac81u, 0x590924eau, 0xd4425eb1u, 0xd5db5292u); SCE->REG_E0H = 0x81010000u; @@ -242,5 +243,5 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p6e_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p6e_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c index 7b81799e7..45f39d43c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c index dc3a74f93..c28f551a2 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -309,5 +310,5 @@ fsp_err_t HW_SCE_Sha256HmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_MAC, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76f.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76f_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c index 87fcaa060..bec7b0d3c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00007601u; + SCE->REG_84H = 0x00007602u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -75,10 +76,10 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_7CH = 0x00000011u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010000u; @@ -91,7 +92,7 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke SCE->REG_ECH = 0x38000c00u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00260000u; - HW_SCE_p_func100(0xf359ed55u, 0xeaf5291fu, 0x95c1799fu, 0x61437f67u); + HW_SCE_p_func100(0xa5d155a0u, 0x90320ae4u, 0x73fb4254u, 0xd884af26u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) @@ -112,7 +113,7 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke /* waiting */ } SCE->REG_100H = change_endian_long(0x00000076u); - HW_SCE_p_func101(0x950afab4u, 0xf29174adu, 0x4756ab39u, 0x919653d1u); + HW_SCE_p_func101(0x4d5ff0d1u, 0x1216c70eu, 0xa3f4925cu, 0xb6a59070u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0000001bu; @@ -243,7 +244,7 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke /* waiting */ } SCE->REG_100H = change_endian_long(0x00000076u); - HW_SCE_p_func101(0xc893c247u, 0x8ee29456u, 0xf2c5efc8u, 0x848d8db3u); + HW_SCE_p_func101(0x3a2e97efu, 0x1f14d6e0u, 0x37d57d03u, 0xee2e9e0fu); HW_SCE_p_func059(); SCE->REG_104H = 0x00000762u; SCE->REG_D0H = 0x40000100u; @@ -335,5 +336,5 @@ fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_Ke } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76i.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76i_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c index 72cf5ecfc..f8dc1022e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -68,5 +69,5 @@ void HW_SCE_Sha256HmacUpdateSub(uint32_t *InData_PaddedMsg, uint32_t MAX_CNT) } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76u.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76u_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c index f3cbc8773..48675e6fa 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t *InData_KeyInde { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00007901u; + SCE->REG_84H = 0x00007903u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x800100e0u; @@ -85,7 +86,7 @@ fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t *InData_KeyInde /* waiting */ } SCE->REG_100H = change_endian_long(0x00000079u); - HW_SCE_p_func101(0x0fd665fbu, 0x35663e4cu, 0x472c9c29u, 0x480cabf3u); + HW_SCE_p_func101(0x9930b009u, 0x81e95a8cu, 0xe8edfc49u, 0xa9c2f412u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0000000eu; @@ -827,5 +828,5 @@ fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t *InData_KeyInde } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p79_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p79_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c index 34168a577..26b8bc470 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyInde { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00007b01u; + SCE->REG_84H = 0x00007b03u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x800100e0u; @@ -85,7 +86,7 @@ fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyInde /* waiting */ } SCE->REG_100H = change_endian_long(0x0000007bu); - HW_SCE_p_func101(0xc0289cc8u, 0x0da9ca5au, 0x10386cecu, 0xb3028594u); + HW_SCE_p_func101(0xb075d3d7u, 0xf61f2d39u, 0xc46c26acu, 0x8db6a4f9u); HW_SCE_p_func043(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x00000010u; @@ -783,5 +784,5 @@ fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyInde } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p7b_r1.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p7b_r2.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83a.c new file mode 100644 index 000000000..5c96f2c54 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83a.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0x8165a682u, 0x057c2c61u, 0x22687c65u, 0xf6c82157u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p83a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83f.c new file mode 100644 index 000000000..4df9f5b06 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83f.c @@ -0,0 +1,233 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x1c5fd38au, 0xbb281f4cu, 0x06f32c33u, 0x3f0d1a13u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf84b38c2u, 0x5d3f0695u, 0x73fdba7fu, 0xecbf89e3u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x7670c563u, 0xd967071eu, 0xb87a350bu, 0x2870cc29u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000030u; + SCE->REG_A4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x59efb123u, 0xbb4edc63u, 0x1d3268cau, 0x56c5122au); + SCE->REG_A4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00004813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xcc3ebaa1u, 0xc7fa9dc1u, 0xf9869924u, 0x8d88b03bu); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x3ad1e64fu, 0x298378e7u, 0xef5241a8u, 0x09ccb269u); + SCE->REG_B0H = 0x40000030u; + SCE->REG_A4H = 0x000087b5u; + SCE->REG_00H = 0x00001513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_p_func102(0x5e51140au, 0x46ecc5d4u, 0x6fd45c30u, 0x99793214u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p83f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83i.c new file mode 100644 index 000000000..0fdef0d7a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83i.c @@ -0,0 +1,241 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008301u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000083u); + HW_SCE_p_func101(0x84ac02c5u, 0x8dd0a073u, 0x6dc9b82fu, 0x03d41e37u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000083u); + HW_SCE_p_func101(0x2c8ad926u, 0x3de8b014u, 0x034a1235u, 0xa559cac1u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x18660b22u, 0xc964460cu, 0x67195656u, 0x108283bbu); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x9e08e9ddu, 0x0668ff5du, 0x3e762a11u, 0x9dbfad92u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xc5a33008u, 0xbc8de0f9u, 0xd2585b7fu, 0x28c85160u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5ce71104u, 0x38d31448u, 0xe322ccd5u, 0x19656ec0u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00008a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005113u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p83i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83t.c new file mode 100644 index 000000000..fbdbac34d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83t.c @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p83t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83u.c new file mode 100644 index 000000000..0d4479f3f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p83u.c @@ -0,0 +1,124 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x3eb1fa6au, 0x3624eb6eu, 0x0d9b82f1u, 0x276dabe6u); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000030u; + SCE->REG_A4H = 0x000087b6u; + SCE->REG_C4H = 0x00000886u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xee297a68u, 0x4d9b7c56u, 0x83350b73u, 0x53e523b8u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p83u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85a.c new file mode 100644 index 000000000..6521a1b0e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85a.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0x0ac93771u, 0xd7ac029cu, 0x363c07d8u, 0x8d4f8f6au); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p85a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85f.c new file mode 100644 index 000000000..a3d11e459 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85f.c @@ -0,0 +1,302 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x7e77cbbau, 0x173242d0u, 0x905c6012u, 0x92a08d85u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xa78e5625u, 0x1c356b17u, 0x3622d00au, 0xc1826f48u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x96608198u, 0xfb81f3afu, 0x9d675d2cu, 0x0d909e69u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00000885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_D0H = 0x40000030u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00007113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x8815b4d1u, 0x270bd3bdu, 0x2e31e5a5u, 0x6453b313u); + SCE->REG_C4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000213u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xcaa030b7u, 0x85d7cce6u, 0xabf927c9u, 0x00d6ab94u); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000030u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00002513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000362u; + SCE->REG_C4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00000000u; + HW_SCE_p_func100(0xbcf86870u, 0xbfb89ad4u, 0xba4c0d39u, 0x2d73a273u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xbec06d50u, 0xd0d0f3ecu, 0xd61c911du, 0x14d3fa2cu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0xaece36fcu, 0x1401eb3eu, 0xd2b724d6u, 0x943cd55eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p85f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85i.c new file mode 100644 index 000000000..8c355d813 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85i.c @@ -0,0 +1,250 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008501u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000085u); + HW_SCE_p_func101(0xe07e8f74u, 0x2a826c66u, 0x0d03786cu, 0xa14cb824u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000085u); + HW_SCE_p_func101(0x27b8cd9du, 0x5b4d5484u, 0x025b0739u, 0xad75a550u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008223u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x7f580f58u, 0xd0e49a86u, 0x549e4e93u, 0xbb5def4fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x92430e5fu, 0xeaf95742u, 0xc3ff848eu, 0x2e1c9922u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xe82d34e4u, 0xe8e1e9fau, 0x91fa95b0u, 0x87580ed5u); + SCE->REG_E0H = 0x81080000u; + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x82937cb4u, 0x55eb782bu, 0x198879e5u, 0xbd5e3457u); + SCE->REG_C4H = 0x00090805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000010u; + SCE->REG_C4H = 0x00008a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005213u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p85i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85t.c new file mode 100644 index 000000000..912455f72 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85t.c @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p85t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85u.c new file mode 100644 index 000000000..adfdff276 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p85u.c @@ -0,0 +1,124 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x46fd637bu, 0xd98c869du, 0x50416c0cu, 0x633d0584u); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000886u; + SCE->REG_D0H = 0x40000030u; + SCE->REG_C4H = 0x000087b6u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xaf1be1bdu, 0xd3e8155bu, 0x5b06a223u, 0x92d71ac0u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p85u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89f.c new file mode 100644 index 000000000..1c23f07ea --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89f.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x529eb8a4u, 0xbbfb9486u, 0x90411712u, 0x130be43au); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x726aa5e0u, 0x8652e5c5u, 0x4ffc2ee5u, 0x58c35758u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x87a0e5f5u, 0x753db70au, 0xefe63a11u, 0x8fa5a3cau); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xda5abb50u, 0x88397877u, 0x6adbab94u, 0xe5827a23u); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x594c14e1u, 0x7a8d4bb0u, 0x87a899a8u, 0x66ac7516u); + } + HW_SCE_p_func100(0x0a6d6c60u, 0xb3b40ae8u, 0x7498d060u, 0xdc8f87a2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x8621b7b4u, 0xdf4bde26u, 0x51a0438bu, 0xba4e4693u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xf9c42484u, 0x22f278bcu, 0x3e90cfbau, 0xdfc2f6c5u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p89f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89i.c new file mode 100644 index 000000000..151d4e0a8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89i.c @@ -0,0 +1,257 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008901u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000089u); + HW_SCE_p_func101(0xd2d17f17u, 0x9ed64bfbu, 0xebed71f8u, 0xd0f1de28u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000089u); + HW_SCE_p_func101(0x3a350608u, 0xf1283fdeu, 0xb7c2416eu, 0x378561d5u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x112550f9u, 0x2ef76aeau, 0x48f9d518u, 0xe2095dc6u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x7106f61eu, 0x705629cfu, 0x82ae645fu, 0xc89bfb94u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xca5b4afcu, 0xbae7dfd1u, 0x9e7fd8b3u, 0x09358784u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xc78ea399u, 0xa678759fu, 0x300215feu, 0xf2ce9a45u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_E0H = 0x80010000u; + SCE->REG_104H = 0x00000068u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x3000a800u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00010020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000080u; + HW_SCE_p_func100(0xe11f3cd4u, 0x4287c0d2u, 0xe2b6bf61u, 0x6afc0ad0u); + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x2c0be082u, 0x51950bd2u, 0x5501e81du, 0x37634e53u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xf7c9cd50u, 0xc14979ebu, 0xe09af696u, 0x823702e1u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0xb5faa29fu, 0xb8d5f49fu, 0xbc20a648u, 0x49f17503u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x3a1757deu, 0x5d8bf593u, 0xa8dd7442u, 0x5d4eae78u); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x85c9c52eu, 0x99021743u, 0xeb05d66fu, 0x9be91a40u); + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p89i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89u.c new file mode 100644 index 000000000..42d69df28 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p89u.c @@ -0,0 +1,181 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0xf2720436u, 0x566f8ebfu, 0x8600badfu, 0x8b943ad3u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00008a86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x1726c41eu, 0xdc246ce5u, 0x66981e2bu, 0x3d2adcdcu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x0000ca86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0xc605e562u, 0xaea80e58u, 0xf22f88fau, 0x30d5a7c1u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00008e96u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x8af836f5u, 0x6e503bd4u, 0xb28a1123u, 0x81021aafu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x0000c9a6u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x4b9602acu, 0xc9a8ee92u, 0x9dc351f8u, 0x5e9a52d7u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x000087b6u; + SCE->REG_04H = 0x0000c100u; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x229f460cu, 0xfcdaec64u, 0xd2d073dbu, 0xf5b19467u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x61db0a12u, 0x60c99b33u, 0xea6949b8u, 0x2be8ef9bu); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xfa0454c5u, 0x974a12ccu, 0x2a23dddbu, 0xe2ef57bdu); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x96e87ddcu, 0x869f5434u, 0xf6eec13fu, 0x408a88e2u); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x9332c1e8u, 0xf702f588u, 0xca87649cu, 0xafc9c1feu); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p89u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p92.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p92.c new file mode 100644 index 000000000..69cc1166a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p92.c @@ -0,0 +1,441 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_SelfCheck3Sub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009203u; + SCE->REG_108H = 0x00000000u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000001f0u; + SCE->REG_ECH = 0x00003bfeu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x2e24c972u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x7252ffb3u, 0xa4f2970fu, 0xccf82b60u, 0xfaf63abcu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00093b8cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01c7ba56u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00070804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_ECH = 0x3000a820u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x00010020u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x00000080u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00002008u; + SCE->REG_ECH = 0x00000863u; + SCE->REG_ECH = 0x00000884u; + SCE->REG_ECH = 0x000008a5u; + SCE->REG_ECH = 0x0000b4c0u; + SCE->REG_ECH = 0x00000013u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000348u; + SCE->REG_ECH = 0x0000b500u; + SCE->REG_ECH = 0x000000b7u; + for(jLoop = 0; jLoop < 1; jLoop = jLoop + 1) + { + HW_SCE_p_func100(0x79c46a3cu, 0x0ae625b1u, 0x2ec940fdu, 0xfd6753fbu); + SCE->REG_ECH = 0x00007c01u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901cu; + HW_SCE_p_func101(0x584ce62cu, 0x7c8ea760u, 0x07dd1294u, 0x228e5267u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901eu; + HW_SCE_p_func101(0x7c885349u, 0x7333bee5u, 0x63655723u, 0x31e16865u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901du; + HW_SCE_p_func101(0x796ca859u, 0x963097eau, 0x416c1f4du, 0x6acf9612u); + } + SCE->REG_C4H = 0x41001e5eu; + SCE->REG_00H = 0x80002401u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001200u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B30) + { + /* waiting */ + } + SCE->REG_00H = 0x00000001u; + SCE->REG_C4H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0010B008u; + SCE->REG_ECH = 0x00000800u; + SCE->REG_E0H = 0x80900000u; + SCE->REG_00H = 0x00008443u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000038a0u; + SCE->REG_ECH = 0x00003405u; + SCE->REG_ECH = 0x00002804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x34202808u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00003485u; + HW_SCE_p_func101(0xa8ec0974u, 0x20eb43a5u, 0x794d25d7u, 0x4bdd0550u); + } + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000005Au; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000002u; + for(iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00002440u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_ECH = 0x00002485u; + } + SCE->REG_ECH = 0x00002c20u; + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000033u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x0000003cu; + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x0000003eu; + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x38008860u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x61e61c3du, 0x30283a89u, 0x5909828eu, 0xa7699c6eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4e350eeeu, 0xd9878500u, 0xcc805ef3u, 0x77d220feu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000001cu; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000cc4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x41001eddu; + SCE->REG_00H = 0x00002413u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000000u; + SCE->REG_E0H = 0x80040080u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x99af7425u, 0x2113d46au, 0xff58fb18u, 0x24edfe4bu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x000b0804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000352u; + SCE->REG_C4H = 0x00070805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000001u); + HW_SCE_p_func100(0x094f8766u, 0x911c9512u, 0xfb3f4bbdu, 0x460e53e2u); + SCE->REG_D0H = 0x00000100u; + SCE->REG_C4H = 0x0100b7f7u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00002823u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000b0805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00070805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x0b1343bfu, 0xfa20139bu, 0xb28498c2u, 0x9a061f91u); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x27268344u, 0xed4d73cbu, 0x2e42dad1u, 0x2e6e640bu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x010d0c04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0xb3878676u, 0x7e57894eu, 0xd6748786u, 0x77254975u); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xa50fc7c5u, 0x110c56e9u, 0xad65e984u, 0x00e91a6cu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[24] = change_endian_long(SCE->REG_100H); + S_RAM[25] = change_endian_long(SCE->REG_100H); + S_RAM[26] = change_endian_long(SCE->REG_100H); + S_RAM[27] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000202u; + HW_SCE_p_func102(0x079c4c8cu, 0x962acb2eu, 0x9a5c0aebu, 0x6ec75008u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + else + { + HW_SCE_p_func100(0x6b276b23u, 0x11089165u, 0x87325daau, 0x63f67f53u); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x9eb0ec5fu, 0xd6b216c4u, 0xe5b5cb54u, 0x17139ef3u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x010d0c04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x19d71d04u, 0xf4910acdu, 0x09b90550u, 0x57b49033u); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x0f03b51cu, 0x5b024757u, 0x31ea3b4du, 0xf4eb1056u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[24] = change_endian_long(SCE->REG_100H); + S_RAM[25] = change_endian_long(SCE->REG_100H); + S_RAM[26] = change_endian_long(SCE->REG_100H); + S_RAM[27] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000202u; + HW_SCE_p_func102(0x974ace4au, 0xbf7d7d22u, 0xfbcbcfc6u, 0xdd8d0fe8u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p92_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95f.c new file mode 100644 index 000000000..fdf1835f9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95f.c @@ -0,0 +1,209 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xea930652u, 0xe5416dadu, 0xa11f4404u, 0xb9a96648u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x9ae58a76u, 0x65cd4da8u, 0xacf9799au, 0xb7b42675u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xbad40f14u, 0xc78b89b3u, 0xa252d30eu, 0xc9208cc0u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00e007b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0xc5998f3cu, 0xb91e9ce7u, 0xbe18dd1eu, 0x884e95abu); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xc2626e38u, 0xa2c70c0bu, 0x1c976a44u, 0x318ad104u); + } + else + { + HW_SCE_p_func101(0x8363490fu, 0xa5ebde9fu, 0xa7731d1au, 0xcf7c133du); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x74630d5au, 0x082e62b4u, 0x4a9a6dcau, 0x537abf4cu); + SCE->REG_A4H = 0x000009c5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + HW_SCE_p_func102(0x200ea14fu, 0xcf7da4e6u, 0x9348db26u, 0x979da628u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p95f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95i.c new file mode 100644 index 000000000..7aa00f667 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95i.c @@ -0,0 +1,233 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009501u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000095u); + HW_SCE_p_func101(0x51f67bd8u, 0xfcc657cfu, 0xd622dc74u, 0x87656ee9u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000095u); + HW_SCE_p_func101(0x32c7872bu, 0xd179c137u, 0x9d8f0906u, 0x3daf47e1u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x29ccfd70u, 0x5f7a7f3fu, 0x1309d3e3u, 0xb3c106beu); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xeb9a65d8u, 0x0864bd61u, 0xebd7245fu, 0xe36bbfb6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x27f80a9au, 0xd8cc95b7u, 0xa66b7060u, 0x911ba3eeu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00e00806u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0xf7d476c3u, 0x47f11b22u, 0x6c3d5f84u, 0x98513dedu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xe982680fu, 0x86aaab93u, 0xef168f78u, 0xf6a2b392u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p95i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95u.c new file mode 100644 index 000000000..a02e60b08 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p95u.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x79ec7ce6u, 0x192c8e50u, 0xa482edbcu, 0x84fdaa03u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00e007b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xd7e08a8bu, 0xc155debfu, 0x3ced38f0u, 0x606d0df4u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p95u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98f.c new file mode 100644 index 000000000..159bde0db --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98f.c @@ -0,0 +1,302 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x756b282cu, 0x61eb6ac1u, 0x0547ad54u, 0x815d9795u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4d7e857eu, 0x5942cc85u, 0x11512bd8u, 0x9082677fu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x4b30af9cu, 0x00e6d366u, 0x3f556c28u, 0x6921cbe7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x244b3723u, 0x6289e7c3u, 0x70bcef3eu, 0xadab16b8u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x57ba30d3u, 0xb4a20ffbu, 0x524455f6u, 0x51864c0bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x000007b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0xff6bcd24u, 0xccea5981u, 0x25a23be6u, 0x30ea4398u); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_A4H = 0x00000e55u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x83b4fb12u, 0xd4bd83dfu, 0xb02262a6u, 0x3b226c3fu); + } + else + { + HW_SCE_p_func101(0x6d97421au, 0x5f0f11c6u, 0xa6a28818u, 0x7eec6ce3u); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000cc4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_A4H = 0x010007b5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000a540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000821u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00000000u; + HW_SCE_p_func100(0x2ec91e0cu, 0x029318e5u, 0x3e6a1b6fu, 0xec4debb6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x938a13abu, 0x03a235feu, 0xfcc53764u, 0xa819ed6fu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x37ca3bdbu, 0x3a9bf024u, 0x635e7718u, 0x23aaa7e0u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p98f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98i.c new file mode 100644 index 000000000..bca3564d1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98i.c @@ -0,0 +1,233 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009801u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000098u); + HW_SCE_p_func101(0x0da2937au, 0x0b7f353du, 0xe7e89a7fu, 0x6785e6dcu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000098u); + HW_SCE_p_func101(0x0464c2edu, 0x5a52563bu, 0xb6ea28feu, 0x288c6d08u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x5ee543bbu, 0xbe019c49u, 0x44a68e5fu, 0xf3593618u); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x618cd000u, 0x2d1ecb45u, 0xc62f6223u, 0xb2e272c2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5ed1ca11u, 0xd2a31758u, 0xc846afeau, 0x165569fdu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00f00806u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0x8ad0847au, 0x4eabc1dbu, 0x0739c466u, 0xec2cacc5u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf8f9baf4u, 0x859a37e3u, 0x8c01f8b2u, 0x016958e8u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p98i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98u.c new file mode 100644 index 000000000..4213c3cc1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p98u.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x637820ffu, 0xe3c3138eu, 0x44d0311du, 0x74408fdfu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00f007b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xdcd6eefdu, 0xdac4a136u, 0xe93fb895u, 0x6de334e9u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p98u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c index 7f0c17346..37c99701e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00009a01u; + SCE->REG_84H = 0x00009a02u; SCE->REG_108H = 0x00000000u; SCE->REG_28H = 0x00870001u; SCE->REG_104H = 0x00000068u; @@ -134,12 +135,12 @@ fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, SCE->REG_ECH = 0x00000003u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x9f58c96cu, 0x24afabb1u, 0xd7924d6du, 0xffcb5f05u); + HW_SCE_p_func100(0x3965c2d2u, 0x82748bcdu, 0xc40cd983u, 0x4cfda6a2u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0xe52fe7beu, 0x50ce0297u, 0xd96d5fb9u, 0x734916fbu); + HW_SCE_p_func102(0x57ec98c4u, 0x37655b01u, 0xbd5955d6u, 0x4b280573u); SCE->REG_1B8H = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -166,7 +167,7 @@ fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, /* waiting */ } SCE->REG_100H = change_endian_long(0x0000009au); - HW_SCE_p_func101(0x6026ca65u, 0x5c1ca45du, 0x10ae9afcu, 0x9e7b87b4u); + HW_SCE_p_func101(0x3aa30067u, 0x566ddb9au, 0x5cee2e76u, 0x4083c512u); HW_SCE_p_func043(); HW_SCE_p_func074_r1(); SCE->REG_ECH = 0x000034feu; @@ -678,5 +679,5 @@ fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9a_r3.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9a_r4.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c index f59270e1d..d2fbf34b8 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x00009b01u; + SCE->REG_84H = 0x00009b02u; SCE->REG_108H = 0x00000000u; SCE->REG_28H = 0x008b0001u; SCE->REG_104H = 0x00000068u; @@ -94,7 +95,7 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, /* waiting */ } SCE->REG_100H = change_endian_long(0x0000009bu); - HW_SCE_p_func101(0x05ccca86u, 0xc9809ae4u, 0x1b82b071u, 0xab553c28u); + HW_SCE_p_func101(0x729ab639u, 0xfe0a0d1du, 0x1e7fbae5u, 0x6d0e18e6u); HW_SCE_p_func043(); HW_SCE_p_func076(); SCE->REG_ECH = 0x000034feu; @@ -610,5 +611,5 @@ fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9b_r2.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9b_r3.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1f.c new file mode 100644 index 000000000..deb67a06e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1f.c @@ -0,0 +1,211 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x547a3ccfu, 0xf5355e5du, 0x3e91bfacu, 0xc4257c3fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xefc12503u, 0xc06f4847u, 0x69b50c3bu, 0x3b230642u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0f7b7772u, 0xd8485cb0u, 0x3f64a0e8u, 0x464e9d9eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00e087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x8af9e419u, 0x65bedac8u, 0xe10579a8u, 0x533cb403u); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xab3b29f0u, 0xfd1b71eau, 0x48e3e211u, 0x33b0e4ebu); + } + else + { + HW_SCE_p_func101(0x87094cd1u, 0x89f8b1bdu, 0x47902d77u, 0xf78739d8u); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x0e35a83au, 0x8480598au, 0xeaa9c94fu, 0x9506d643u); + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x000089c5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + HW_SCE_p_func102(0x5ba6336fu, 0x0e80895du, 0x03a65f8du, 0xf84805bau); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa1f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1i.c new file mode 100644 index 000000000..c850db8d7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1i.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000a101u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a1u); + HW_SCE_p_func101(0x7284ec1au, 0xaa15c187u, 0x16838c12u, 0xa7399e51u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a1u); + HW_SCE_p_func101(0x518b8ce9u, 0x8dbf76c4u, 0x51cce413u, 0xb6ee3bb5u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x05255eafu, 0xbb8ee12cu, 0x0b5c438au, 0x03694643u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x0e42e528u, 0x697d2e85u, 0xb3709985u, 0xe75d31c8u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x6752277au, 0xc69f620fu, 0x46219ec6u, 0xb6e408b1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0257d3afu, 0x13038f5au, 0x02a7c01bu, 0xd61eac1au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00058e56u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0xb9e8fcf6u, 0xb4ea8932u, 0x1b72f566u, 0xff824869u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xb45659f9u, 0xbb4e896du, 0x566c184du, 0xb6d59c0eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa1i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1u.c new file mode 100644 index 000000000..b081c824c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa1u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x318af8c0u, 0x4a2b38cfu, 0xb3007d47u, 0x2a78a297u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00e087b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xa5388defu, 0x953aea8au, 0x05ec439bu, 0xb60fd897u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa1u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4f.c new file mode 100644 index 000000000..3ee392d72 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4f.c @@ -0,0 +1,305 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x1947bce2u, 0xb6dd8cefu, 0x72f49a52u, 0xaf05502eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7c1b7ea3u, 0xf18dfaa8u, 0xe8780c1fu, 0x9959f912u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xb2cb41d9u, 0x8f1c5bc0u, 0x95ce1a2au, 0x5b1f71d8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x6ea3e4f6u, 0xd9b8445fu, 0xa3c85ad4u, 0x274f912au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x4d69888du, 0x907ce4c9u, 0xec2167c2u, 0xb4887c76u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0xe0008a61u, 0xaf3a2505u, 0x1b72c8feu, 0x4cda0270u); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e55u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xb2c1c419u, 0x2daab86du, 0xb3644f3eu, 0x7dcb2c5bu); + } + else + { + HW_SCE_p_func101(0x18194dc3u, 0x55159f50u, 0x743daa12u, 0x7361ff72u); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000cc4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x010087b5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000a540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000821u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00000000u; + HW_SCE_p_func100(0x26a02e05u, 0x2e0d7c97u, 0x5a42f7e8u, 0xc9307893u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x439cff70u, 0x32634fd1u, 0x3f0a3267u, 0xe61861f1u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xa19bacb9u, 0x31b73ae7u, 0x93a90fb2u, 0x617899fcu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa4f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4i.c new file mode 100644 index 000000000..3510856b6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4i.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000a401u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a4u); + HW_SCE_p_func101(0x9987f3cbu, 0x6589cf9fu, 0xa9068193u, 0x4868b895u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a4u); + HW_SCE_p_func101(0xbe7f1890u, 0x1b07cb65u, 0x5ae28a45u, 0xed92be4eu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x9bdde299u, 0xd7bb9828u, 0xd054a005u, 0x5c075b38u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x5d7fd712u, 0xc15088b0u, 0x5150fc22u, 0xb8cbcffbu); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x8765069fu, 0xd90a7f65u, 0x31f5aae0u, 0x31931d14u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x21ecde34u, 0x7d279b27u, 0x6576116du, 0x2654af5eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e56u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0x56ff7118u, 0xaf0e4a64u, 0xcb88969fu, 0xbe33c357u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x78d151e3u, 0x897f0e42u, 0xf2e9a3e7u, 0x3b140c4fu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa4i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4u.c new file mode 100644 index 000000000..13b239e3e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa4u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xdea86ac4u, 0x80614a90u, 0x583fc2b0u, 0xf48ed5ebu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00f087b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x6fb47568u, 0x0401ee23u, 0x9c86f289u, 0x92194a0cu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa4u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7f.c new file mode 100644 index 000000000..d290ad553 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7f.c @@ -0,0 +1,211 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x0955f5c4u, 0x6f589e4au, 0x094a9029u, 0x51c3c8deu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x447006aau, 0x2106c9d2u, 0x2b2f4193u, 0xb7fe3f1du); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x533194d8u, 0xc6c53b53u, 0xce9b76a1u, 0xc7285458u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00e087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x265ce6e0u, 0x8fbee97eu, 0x2194fe55u, 0xe97fec01u); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0x9696e04du, 0x2bafad47u, 0xb0deacf3u, 0x3f0c7e1bu); + } + else + { + HW_SCE_p_func101(0x0e71a7c9u, 0x7b823e4au, 0x8f0b3487u, 0x68378caau); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0xe876698cu, 0xca041bb6u, 0x98be0d1du, 0x3ecc49c9u); + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x000089c5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + HW_SCE_p_func102(0x50393f64u, 0x8200d2a3u, 0x7d51364au, 0x5d7bbba9u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa7f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7i.c new file mode 100644 index 000000000..63063da03 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7i.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000a701u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a7u); + HW_SCE_p_func101(0x98b7c339u, 0xccbb44a8u, 0xd55098f5u, 0x0d6b75e8u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a7u); + HW_SCE_p_func101(0x69ae2359u, 0xc1253b04u, 0xf91fff11u, 0xe3f154b7u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xa36f9c4du, 0x37e9c677u, 0x8ec01528u, 0xea48bd9fu); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xde214992u, 0xf942e85fu, 0xafa19138u, 0x2cd51c14u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xaf3cf47fu, 0xcaa9f87fu, 0xbc272f9du, 0xc956bf1au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xfcd0cc8eu, 0x1ac446d7u, 0x062aa28eu, 0xac7f72a3u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00058e56u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0xbb3e71a7u, 0x5b7e113fu, 0x566bd588u, 0x28c333d9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4a7126bbu, 0x08691572u, 0x01bf8522u, 0xe3d418e5u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa7i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7u.c new file mode 100644 index 000000000..83502ca54 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pa7u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xa03a0215u, 0x0c1d5d69u, 0x63f0669cu, 0x70db5adfu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00e087b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xa92e0439u, 0x5ece18ecu, 0x8fe70c59u, 0x6340ff94u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pa7u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0f.c new file mode 100644 index 000000000..1326f7087 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0f.c @@ -0,0 +1,305 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x26af63b6u, 0x2380b8a2u, 0x3ffdd73au, 0xaf08b6b2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xad4a5577u, 0x08513a85u, 0x388e49aau, 0xfb01c2bcu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xd349ede2u, 0x7d4e9a7du, 0x50e8a223u, 0xd5a45cc8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x87a74f51u, 0x93aa34a0u, 0xf2c0e489u, 0xa4242a17u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x908dafbcu, 0x7a190575u, 0x2722df91u, 0x458e37a2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x0000a400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x0e939bd4u, 0x998bc030u, 0x6fa068efu, 0x9c49870eu); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00008e55u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x534d33e4u, 0xd1bebc7du, 0xc0d24399u, 0x4fa6ba70u); + } + else + { + HW_SCE_p_func101(0x60cb1579u, 0xdfb576c0u, 0xbf5276b8u, 0xcfeb2d6eu); + } + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000cc4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x010087b5u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000a540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000821u; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00000000u; + HW_SCE_p_func100(0x6c425cecu, 0x192adbe0u, 0xc5a9f23fu, 0x9ca8d5bfu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5cd83331u, 0xf341d027u, 0xa9a7f36du, 0x80224432u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x2147e2dbu, 0xd5bad0c8u, 0xc4e93291u, 0x1ce9be56u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb0f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0i.c new file mode 100644 index 000000000..d497727e6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0i.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b001u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b0u); + HW_SCE_p_func101(0xbdd17f39u, 0x08088efeu, 0x35974f03u, 0x7e5b170cu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b0u); + HW_SCE_p_func101(0x42001f4cu, 0xd3136d01u, 0x69ac7c8bu, 0xc56dd6b8u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xb415d07fu, 0x65b938e5u, 0xbcbe29a7u, 0xb22a1080u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xc53a1e0fu, 0x2de3033du, 0xf96b4fd1u, 0x9b9529f2u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x6d67554cu, 0xaf4b35f3u, 0x9e34693bu, 0x6a7e461bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x8be5abacu, 0x4d261e29u, 0x2edada3eu, 0x7140c6e9u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00008e56u; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + HW_SCE_p_func100(0xd160a2aeu, 0x155a728eu, 0x8e7b2421u, 0xfd62a0e3u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xfca9b293u, 0xe2bd4011u, 0x35a81beau, 0x56d06150u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb0i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0u.c new file mode 100644 index 000000000..e62ceb22b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb0u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes192CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x3d853e89u, 0x7aafb046u, 0x695230c8u, 0x2639c87eu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_A4H = 0x00f087b6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x8b222a75u, 0x87614b65u, 0x078b5347u, 0x1427584eu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb0u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3f.c new file mode 100644 index 000000000..5d1c0c4d6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3f.c @@ -0,0 +1,379 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_ECH = 0x000037c0u; + SCE->REG_ECH = 0x00076bdeu; + SCE->REG_ECH = 0x00026fdeu; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x2000abc0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xad40f525u, 0x552fe1a0u, 0x010897f9u, 0xe0e389ddu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0009f09au, 0x9d3e2b34u, 0x6ae01d0cu, 0x4bf49bf1u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xfe5dca73u, 0x08cc0978u, 0x98b6f585u, 0xa843022au); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_p_func100(0xe0102f0cu, 0xf120e54cu, 0x11b41821u, 0xbd53d74du); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008da6u; + SCE->REG_04H = 0x0000c100u; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func100(0xe172eb4au, 0x2d4b73feu, 0x7554ebaau, 0xf0d03c8bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xdbe6b8d7u, 0x70b75292u, 0x08bff4a7u, 0x0321e806u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xf7feb80bu, 0xf012f7edu, 0x61b6bcbcu, 0x544a1c4au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008da5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x80840006u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80840007u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003500u; + SCE->REG_ECH = 0x00036908u; + SCE->REG_ECH = 0x00008d00u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x000024e8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00003847u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00008c60u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_ECH = 0x00004403u; + SCE->REG_ECH = 0x00007484u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00001484u; + SCE->REG_ECH = 0x00000c44u; + SCE->REG_ECH = 0x00001041u; + SCE->REG_ECH = 0x00003c47u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x38008fe0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000a7e0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00002bdfu; + SCE->REG_ECH = 0x00056bdeu; + SCE->REG_ECH = 0x0000353eu; + HW_SCE_p_func100(0x43b55f31u, 0x800162aau, 0xe080c202u, 0xf8240dc2u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x000024e5u; + SCE->REG_ECH = 0x00003ba6u; + SCE->REG_ECH = 0x00003fa7u; + SCE->REG_ECH = 0x000033c0u; + HW_SCE_p_func101(0xb7a81182u, 0xf79854d8u, 0xe46b3c43u, 0x4ed0ac4fu); + } + SCE->REG_ECH = 0x38000fdeu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0x94909a24u, 0xce4d9e60u, 0x76135666u, 0xb5af3e2bu); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008da5u; + SCE->REG_E0H = 0x81840007u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00003c26u; + SCE->REG_ECH = 0x00000bffu; + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x00003fe6u; + SCE->REG_ECH = 0x00003120u; + HW_SCE_p_func101(0xd0f5eec8u, 0xacc05fcdu, 0x76ac3301u, 0x03700592u); + } + HW_SCE_p_func100(0x1a1a0d1cu, 0xf347e5e8u, 0x5e9966d6u, 0xbc3fca09u); + SCE->REG_ECH = 0x38000d29u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x81840006u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_p_func101(0x26c1c523u, 0x69d64c70u, 0x201c76dcu, 0x42b3d6bdu); + } + HW_SCE_p_func102(0xc6c80c94u, 0x4115ede4u, 0x3cd02c22u, 0x212a144au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb3f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3i.c new file mode 100644 index 000000000..99a66ba59 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3i.c @@ -0,0 +1,195 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b301u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b3u); + HW_SCE_p_func101(0xa3847694u, 0xba217b7du, 0x761fc8f0u, 0x1fe1218cu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b3u); + HW_SCE_p_func101(0x1814288bu, 0x6b57786cu, 0x6f589fcbu, 0xc4affa6bu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x5c7e3adau, 0x2e7118f6u, 0x80e1963bu, 0xd32bc1a7u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa2848470u, 0xe9fa7aebu, 0x5e4cac5eu, 0x78b70946u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x84e62500u, 0x9a34e5e7u, 0x7bee933cu, 0xe449a4a0u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x94484a86u, 0x6ac09497u, 0xacca3456u, 0x2007aa2cu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00041a05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb3i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3u.c new file mode 100644 index 000000000..f07155982 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb3u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xa4bb076du, 0x0493889bu, 0x2b873600u, 0x5c4453d2u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008da6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x0c801001u, 0x701d60a4u, 0xeabcd548u, 0xb097d101u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb3u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6f.c new file mode 100644 index 000000000..c55670b4a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6f.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_ECH = 0x000037c0u; + SCE->REG_ECH = 0x00076bdeu; + SCE->REG_ECH = 0x00026fdeu; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x2000abc0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xca624a8du, 0xdadff4e7u, 0x2a86a494u, 0xbafc5094u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xd37a0b7cu, 0xc42aa712u, 0x183f3f79u, 0x3b712616u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1565838du, 0xc2d03568u, 0x6ad73cfbu, 0x860aef7fu); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_p_func100(0xf539e42bu, 0x46f05f8du, 0xfaaa2b74u, 0xf2bd30b3u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x0000cda6u; + SCE->REG_04H = 0x0000c100u; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func100(0xbbc12c23u, 0x0cfb3332u, 0x1ac38658u, 0x5528d3dcu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xb0f2e41au, 0x8539baf3u, 0x13fe00e9u, 0x40a8cdbeu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x8b26e6abu, 0x4d0c31c0u, 0xf8a616f6u, 0x2c8001f6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0x6b7ed0d5u, 0xf35452ddu, 0xa81e9a1au, 0xd5e7e882u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040140u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x0000cd24u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x0000cda5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x80840006u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80840007u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003500u; + SCE->REG_ECH = 0x00036908u; + SCE->REG_ECH = 0x00008d00u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x000024e8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00003847u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00008c60u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_ECH = 0x00004403u; + SCE->REG_ECH = 0x00007484u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00001484u; + SCE->REG_ECH = 0x00000c44u; + SCE->REG_ECH = 0x00001041u; + SCE->REG_ECH = 0x00003c47u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x38008fe0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000a7e0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00002bdfu; + SCE->REG_ECH = 0x00056bdeu; + SCE->REG_ECH = 0x0000353eu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x000024e5u; + SCE->REG_ECH = 0x00003ba6u; + SCE->REG_ECH = 0x00003fa7u; + SCE->REG_ECH = 0x000033c0u; + HW_SCE_p_func101(0xcddc449bu, 0x4e86b813u, 0x9f7d8b1fu, 0xa333ba6fu); + } + HW_SCE_p_func100(0x630cb437u, 0xe87d589du, 0x42e79c01u, 0xc3d8d05eu); + SCE->REG_ECH = 0x38000fdeu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x0000cda5u; + SCE->REG_E0H = 0x81840007u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00003c26u; + SCE->REG_ECH = 0x00000bffu; + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x00003fe6u; + SCE->REG_ECH = 0x00003120u; + HW_SCE_p_func101(0x3ffc373fu, 0x6967e754u, 0xec3ec0dbu, 0x2f0c1b7eu); + } + HW_SCE_p_func100(0x9f55dc28u, 0xe577c2f2u, 0x87e6055au, 0xa66aecd0u); + SCE->REG_ECH = 0x38000d29u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x81840006u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_p_func101(0x5c4e6f65u, 0x36ef7d88u, 0x846364a9u, 0xfe581a43u); + } + HW_SCE_p_func102(0x642757a2u, 0x712ec770u, 0x3bde479bu, 0x19e636fau); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb6f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6i.c new file mode 100644 index 000000000..5bb137b64 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6i.c @@ -0,0 +1,195 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b601u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b6u); + HW_SCE_p_func101(0x4c614de9u, 0x5e8ab367u, 0x8f0ec989u, 0xabac3714u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b6u); + HW_SCE_p_func101(0x922537c5u, 0xa9a9461fu, 0xd4343eaau, 0x3ed82bd8u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x59700e14u, 0x47fa423cu, 0x7408c9eau, 0x8ea9b7b6u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x5d49c1ceu, 0x2dc53336u, 0xb3bd49a8u, 0xc5aab113u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x1467aa39u, 0x6d7b3825u, 0x22152c4bu, 0x021db04eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x3ae42f8du, 0x0275f942u, 0x97e65683u, 0x20dbf82au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00041a05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb6i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6u.c new file mode 100644 index 000000000..3819f13a5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb6u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x1f5b9b2au, 0xdc4bb111u, 0xcc7658c6u, 0xe2a8e6e4u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x0000cda6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x0bad6ff4u, 0x21a29b22u, 0xb39b0111u, 0x27bbba8cu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb6u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9f.c new file mode 100644 index 000000000..c0f6e02d9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9f.c @@ -0,0 +1,379 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_ECH = 0x000037c0u; + SCE->REG_ECH = 0x00076bdeu; + SCE->REG_ECH = 0x00026fdeu; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x2000abc0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xe915e6d7u, 0x1d65d1c4u, 0x8ff5b85bu, 0xa4526103u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xe3234672u, 0x27bcdd00u, 0xcdf184b4u, 0xc0195e81u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xd572f89fu, 0x8c16b8adu, 0xc63fc14eu, 0x5b2dafdcu); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_p_func100(0xe22fe9a3u, 0x19b8ff1du, 0x41e0e0ccu, 0x7f45f38au); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x00008da6u; + SCE->REG_04H = 0x0000c100u; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func100(0xbb591048u, 0x64c28870u, 0x5398d50du, 0x5e3ab165u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x3f5592d3u, 0x4bcce341u, 0x90e9f640u, 0x3be1cb9au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x1eec6f52u, 0x5e74c52au, 0x1b2d8528u, 0x000c9a2du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x00008da5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x80840006u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80840007u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003500u; + SCE->REG_ECH = 0x00036908u; + SCE->REG_ECH = 0x00008d00u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x000024e8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00003847u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00008c60u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_ECH = 0x00004403u; + SCE->REG_ECH = 0x00007484u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00001484u; + SCE->REG_ECH = 0x00000c44u; + SCE->REG_ECH = 0x00001041u; + SCE->REG_ECH = 0x00003c47u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x38008fe0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000a7e0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00002bdfu; + SCE->REG_ECH = 0x00056bdeu; + SCE->REG_ECH = 0x0000353eu; + HW_SCE_p_func100(0x4c3b7f8eu, 0x431841b4u, 0xcf3c2a19u, 0x475aee98u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x000024e5u; + SCE->REG_ECH = 0x00003ba6u; + SCE->REG_ECH = 0x00003fa7u; + SCE->REG_ECH = 0x000033c0u; + HW_SCE_p_func101(0x951a9435u, 0xe4953a42u, 0x053c0042u, 0x3e4cfe4au); + } + SCE->REG_ECH = 0x38000fdeu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + HW_SCE_p_func100(0xc7c98e4du, 0x464f55cau, 0x7a20898fu, 0xe1485eb3u); + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x00008da5u; + SCE->REG_E0H = 0x81840007u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00003c26u; + SCE->REG_ECH = 0x00000bffu; + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x00003fe6u; + SCE->REG_ECH = 0x00003120u; + HW_SCE_p_func101(0x88630b84u, 0x09e52004u, 0xa0f8a19fu, 0x3e97a8a7u); + } + SCE->REG_ECH = 0x38000d29u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0xb7ce9444u, 0x95bb5d55u, 0xa6254961u, 0x786d3859u); + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x81840006u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_p_func101(0x31dbc936u, 0xd6f4103cu, 0xb55ba7e0u, 0x9f882e30u); + } + HW_SCE_p_func102(0x1af1cb45u, 0xcbab59ffu, 0x4010b50eu, 0x0ad6f321u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb9f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9i.c new file mode 100644 index 000000000..d3a24fcdb --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9i.c @@ -0,0 +1,235 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b901u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b9u); + HW_SCE_p_func101(0xe8aebccau, 0x08905231u, 0xd1629beau, 0xd2afa2c7u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000009u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000b9u); + HW_SCE_p_func101(0xd3078522u, 0x8c545c34u, 0x21c26adfu, 0xc34e8d5bu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x6db1b7a5u, 0x42f16527u, 0x6822dfd3u, 0x9fb93cfau); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x88f6f429u, 0x2b207c89u, 0xabb5649au, 0xbdb82cbau); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x1d1fce8fu, 0xb058c6bfu, 0xe14da850u, 0xc9294f88u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x00f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_A4H = 0x000a0805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x440234afu, 0x93d1de5fu, 0x1a0d0914u, 0xa38cc8c1u); + SCE->REG_A4H = 0x000b0805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa7478611u, 0x403128d9u, 0x156b540eu, 0x45be9252u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xbcd15933u, 0x9fd141b7u, 0xe83eed90u, 0xd38ae4eeu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x0004aa05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb9i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9u.c new file mode 100644 index 000000000..47afddca5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pb9u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xeb84927au, 0xbaa13227u, 0x5e221552u, 0x159aad71u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x00008da6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xc3c2f4a8u, 0xdc58441du, 0x76aeb7e0u, 0x93572d27u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pb9u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2f.c new file mode 100644 index 000000000..ed93d774c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2f.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_ECH = 0x000037c0u; + SCE->REG_ECH = 0x00076bdeu; + SCE->REG_ECH = 0x00026fdeu; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x2000abc0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xfae4674du, 0xd71a8d44u, 0xfda7fc43u, 0xe2f0a49bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xadffe2f2u, 0x15ef16c2u, 0x7cccbab5u, 0x4476dc7cu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x18ed9061u, 0x9f68c4f2u, 0x0ca876ceu, 0xbab18046u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_p_func100(0x15720916u, 0x4928aec9u, 0x9aec1c5cu, 0x2a99bea9u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x0000cda6u; + SCE->REG_04H = 0x0000c100u; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func100(0xdfe9ad83u, 0x17fc5993u, 0x5e9d63e7u, 0x6c1c43fbu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7c1fd1a2u, 0x724ba216u, 0x1618d36cu, 0xb919c74bu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xf699d6ecu, 0xc3789eafu, 0xc2619429u, 0x11f98a28u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0x7e1f6a4cu, 0x5944e041u, 0x8718c3e6u, 0x5a5db474u); + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040140u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x0000cd24u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x0000cda5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x80840006u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80840007u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003500u; + SCE->REG_ECH = 0x00036908u; + SCE->REG_ECH = 0x00008d00u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x000024e8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00003847u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00008c60u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_ECH = 0x00004403u; + SCE->REG_ECH = 0x00007484u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00001484u; + SCE->REG_ECH = 0x00000c44u; + SCE->REG_ECH = 0x00001041u; + SCE->REG_ECH = 0x00003c47u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x0000007fu; + SCE->REG_ECH = 0x38008fe0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000a7e0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00002bdfu; + SCE->REG_ECH = 0x00056bdeu; + SCE->REG_ECH = 0x0000353eu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x000024e5u; + SCE->REG_ECH = 0x00003ba6u; + SCE->REG_ECH = 0x00003fa7u; + SCE->REG_ECH = 0x000033c0u; + HW_SCE_p_func101(0x779c56b5u, 0x4650dd64u, 0xe8ad07e3u, 0xae4a4ddcu); + } + HW_SCE_p_func100(0x80546670u, 0x081ae0e5u, 0x9a758775u, 0x3da1afa6u); + SCE->REG_ECH = 0x38000fdeu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x0000cda5u; + SCE->REG_E0H = 0x81840007u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x000024c8u; + SCE->REG_ECH = 0x00003826u; + SCE->REG_ECH = 0x00000c24u; + SCE->REG_ECH = 0x00003c26u; + SCE->REG_ECH = 0x00000bffu; + for (jLoop = 0; jLoop < S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000024c5u; + SCE->REG_ECH = 0x00003fe6u; + SCE->REG_ECH = 0x00003120u; + HW_SCE_p_func101(0x29a06074u, 0xbdcbb2c4u, 0x5219eb7eu, 0x6e6e6eefu); + } + HW_SCE_p_func100(0x23f0dc1eu, 0x8497a1d5u, 0x8b5eaf23u, 0x8e25429eu); + SCE->REG_ECH = 0x38000d29u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_E0H = 0x81840006u; + SCE->REG_04H = 0x00000613u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_p_func101(0xffd6f98au, 0xeb205568u, 0xb0b90841u, 0x1a612f24u); + } + HW_SCE_p_func102(0xce7b9474u, 0x78b1de12u, 0xb22a31c4u, 0xc86ac379u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pc2f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2i.c new file mode 100644 index 000000000..198aaf2df --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2i.c @@ -0,0 +1,235 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000c201u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000c2u); + HW_SCE_p_func101(0x64f3220du, 0x22e30a77u, 0x226d2950u, 0x99636fa0u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000009u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000c2u); + HW_SCE_p_func101(0x92b4071bu, 0x488ba86cu, 0xb12db5c7u, 0x22f81140u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x83e016f1u, 0xc8145747u, 0xdf402c37u, 0x475507c9u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x650e1e8fu, 0x0eeeefc1u, 0xc66d9626u, 0xc92ddf65u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xc7d82035u, 0x5c97b869u, 0x164f07dcu, 0xe289816fu); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x00f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_A4H = 0x000a0805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x78ea820eu, 0xa4d34913u, 0xa9b13f98u, 0x8c104d27u); + SCE->REG_A4H = 0x000b0805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xe00ff40eu, 0x4ce66660u, 0x29f91899u, 0x2e7d40bcu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5c87614cu, 0x072c8029u, 0xe1f5444fu, 0x6022c195u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x0004aa05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pc2i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2u.c new file mode 100644 index 000000000..2cddb1faa --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pc2u.c @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xac021f62u, 0xfdca2f62u, 0x5fef28a4u, 0x1a305201u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x0000cda6u; + SCE->REG_04H = 0x0000c100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x3463be16u, 0xe4a9e5d5u, 0x49deaa65u, 0xcf163906u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pc2u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c index 95c0c992a..deac57bff 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Improved pefromance for secure boot. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x0000e201u; + SCE->REG_84H = 0x0000e202u; SCE->REG_108H = 0x00000000u; SCE->REG_C4H = 0x200e1a0du; /* WAIT_LOOP */ @@ -75,10 +76,10 @@ fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t { /* waiting */ } - SCE->REG_100H = S_RAM[16+0 + 0]; - SCE->REG_100H = S_RAM[16+0 + 1]; - SCE->REG_100H = S_RAM[16+0 + 2]; - SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; SCE->REG_104H = 0x00000368u; SCE->REG_E0H = 0x80040000u; /* WAIT_LOOP */ @@ -124,12 +125,12 @@ fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t SCE->REG_ECH = 0x00000007u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0xd244310fu, 0x547e382fu, 0xb318a02du, 0x464efc11u); + HW_SCE_p_func100(0x48be1967u, 0x16593d09u, 0xd82736a4u, 0x036ab5f6u); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0x2b469163u, 0xf6f625a5u, 0xdc4f65eau, 0xba0c2c3bu); + HW_SCE_p_func102(0xbb364183u, 0x653b285eu, 0x0be0eea8u, 0x2aa3f295u); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -174,7 +175,7 @@ fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t /* waiting */ } SCE->REG_100H = change_endian_long(0x000000e2u); - HW_SCE_p_func101(0xad6085ccu, 0x12c5aee4u, 0x062f76d2u, 0x4b1b7c5cu); + HW_SCE_p_func101(0xe6a71effu, 0x4e0998a4u, 0x2cc3e9bdu, 0xa7c2735au); HW_SCE_p_func059(); SCE->REG_ECH = 0x0000b4e0u; SCE->REG_ECH = 0x0154569cu; @@ -635,5 +636,5 @@ fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pe2.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pe2_r1.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c index 73c7983cf..8fabd5d7c 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -47,7 +48,7 @@ Exported global variables (to be accessed by other files) Private global variables and functions ***********************************************************************************************************************/ -fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) { uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; uint32_t dummy = 0u; @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x0000f001u; + SCE->REG_84H = 0x0000f002u; SCE->REG_108H = 0x00000000u; SCE->REG_28H = 0x00870001u; SCE->REG_104H = 0x00000068u; @@ -127,12 +128,12 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co SCE->REG_ECH = 0x00000003u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0xf5d8c06eu, 0xc83bb08au, 0xae510efbu, 0x36a7af08u); + HW_SCE_p_func100(0x80b99bc2u, 0x9ee4a418u, 0x49ce3627u, 0x4351adfau); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0x8f775961u, 0x0b5a28aau, 0x87943f60u, 0x0f2c8f26u); + HW_SCE_p_func102(0x563d1fa8u, 0x5a5d6fb3u, 0x1459421cu, 0xe53d7473u); SCE->REG_1B8H = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -143,7 +144,7 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co } else { - HW_SCE_p_func100(0x405aceaau, 0x2e5e12d4u, 0x11fcc9ccu, 0xf58f11d1u); + HW_SCE_p_func100(0x451200efu, 0xc8d401b7u, 0x2fa241a7u, 0xb8a7f10cu); SCE->REG_28H = 0x00870001u; SCE->REG_ECH = 0x30003340u; SCE->REG_ECH = 0x00050020u; @@ -174,9 +175,9 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co } S_RAM[0] = change_endian_long(SCE->REG_100H); OFS_ADR = S_RAM[0]; - HW_SCE_p_func100(0x45761474u, 0x57cc450bu, 0x5ceb52e5u, 0x6b5c37e2u); + HW_SCE_p_func100(0xf071916eu, 0xbb83fee2u, 0xd34567d9u, 0x5f50077eu); HW_SCE_p_func070_r2(OFS_ADR); - HW_SCE_p_func100(0x00613584u, 0x5c3272c3u, 0x996ad0bdu, 0x304f803du); + HW_SCE_p_func100(0x470710d8u, 0x2d41069cu, 0xa5095108u, 0xfec111dbu); SCE->REG_34H = 0x00000003u; SCE->REG_24H = 0x800068d0u; /* WAIT_LOOP */ @@ -216,7 +217,7 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co /* waiting */ } HW_SCE_p_func103(); - HW_SCE_p_func100(0x6805778au, 0x816c6846u, 0x3b6d78aeu, 0x3bcdbe72u); + HW_SCE_p_func100(0x704a81dfu, 0xd750501au, 0xfdc7daaau, 0x30ad6bdfu); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -273,7 +274,7 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co { /* waiting */ } - HW_SCE_p_func100(0xebac350fu, 0x45ec962fu, 0x32c6f830u, 0xe58ac3c3u); + HW_SCE_p_func100(0xef5f6f61u, 0x8b7b541du, 0x60a83d4cu, 0xe6fcc2f3u); HW_SCE_p_func071_r2(OFS_ADR); SCE->REG_34H = 0x00000802u; SCE->REG_24H = 0x800088d0u; @@ -428,7 +429,7 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co SCE->REG_ECH = 0x000000f0u; SCE->REG_ECH = 0x0000373cu; SCE->REG_ECH = 0x00000b9cu; - HW_SCE_p_func100(0xf3ab3173u, 0x27de0948u, 0x5353a013u, 0x2e638bd8u); + HW_SCE_p_func100(0x1d4ac2e4u, 0x51589b8eu, 0x542a868au, 0x975cf1b6u); SCE->REG_E0H = 0x81010380u; SCE->REG_04H = 0x00000607u; /* WAIT_LOOP */ @@ -439,13 +440,13 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co S_RAM[0] = change_endian_long(SCE->REG_100H); for(iLoop=0;iLoop<256;iLoop=iLoop+1) { - HW_SCE_p_func101(0x3c677163u, 0xea4d3d2eu, 0xafceb4b7u, 0xe2e493feu); + HW_SCE_p_func101(0x78e307d7u, 0x63d014e3u, 0x594119d3u, 0xc6df9701u); HW_SCE_p_func300(); if (S_RAM[0] == 0x00000001) { break; } - HW_SCE_p_func101(0xa7c1a7c6u, 0x18421ea5u, 0x850f9fdbu, 0xfaf97de6u); + HW_SCE_p_func101(0x6db06aceu, 0xebbad615u, 0x7726e7c9u, 0x4983ea35u); } SCE->REG_24H = 0x00001dc0u; /* WAIT_LOOP */ @@ -1594,5 +1595,5 @@ fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, co } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf0_r4.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf0_r5.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c index 5ebc50ca4..6f8ddead1 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -47,7 +48,7 @@ Exported global variables (to be accessed by other files) Private global variables and functions ***********************************************************************************************************************/ -fsp_err_t HW_SCE_EcdsaSigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) { uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; uint32_t dummy = 0u; diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c index 9668b3da8..f44e2658a 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,7 +68,7 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x0000f401u; + SCE->REG_84H = 0x0000f402u; SCE->REG_108H = 0x00000000u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010340u; @@ -103,12 +104,12 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, SCE->REG_ECH = 0x00000002u; SCE->REG_E0H = 0x00000080u; SCE->REG_1CH = 0x00A60000u; - HW_SCE_p_func100(0x61eee86cu, 0xcb13e52eu, 0x0959472eu, 0x7f912219u); + HW_SCE_p_func100(0x559bf95fu, 0xebb795a1u, 0x6dc7cb91u, 0x6ee821fbu); SCE->REG_1CH = 0x00400000u; SCE->REG_1D0H = 0x00000000u; if (1u == (SCE->REG_1CH_b.B22)) { - HW_SCE_p_func102(0x874384e1u, 0x11b1983eu, 0x04bc55c7u, 0x166a1ad8u); + HW_SCE_p_func102(0x7fbe7fe1u, 0xa5906d5eu, 0x43e09b67u, 0x4d4cf4ffu); SCE->REG_1BCH = 0x00000040u; /* WAIT_LOOP */ while (0u != SCE->REG_18H_b.B12) @@ -119,7 +120,7 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } else { - HW_SCE_p_func100(0xcee8c68fu, 0xd879df00u, 0x95b02707u, 0x7b8cb6deu); + HW_SCE_p_func100(0xb7d91f1du, 0x1603c2b5u, 0x01b8091du, 0x6410772cu); SCE->REG_28H = 0x00870001u; SCE->REG_ECH = 0x30003340u; SCE->REG_ECH = 0x00050020u; @@ -150,9 +151,9 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } S_RAM[0] = change_endian_long(SCE->REG_100H); OFS_ADR = S_RAM[0]; - HW_SCE_p_func100(0x46096261u, 0x56f41cd7u, 0x90a6aef4u, 0x6a809daau); + HW_SCE_p_func100(0x93efae5eu, 0xdfb854afu, 0xeaead505u, 0xf922d3fbu); HW_SCE_p_func070_r2(OFS_ADR); - HW_SCE_p_func100(0xb2df82d6u, 0xd8db101eu, 0x46294cb8u, 0xeff1925au); + HW_SCE_p_func100(0xac5929b8u, 0x9009251bu, 0x3d6d1fdfu, 0x1da02173u); SCE->REG_34H = 0x00000400u; SCE->REG_24H = 0x8000c0d0u; /* WAIT_LOOP */ @@ -162,7 +163,7 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } SCE->REG_28H = 0x00890001u; HW_SCE_p_func103(); - HW_SCE_p_func100(0x53bc48e0u, 0xf409e715u, 0x3c15c334u, 0x23cadbe8u); + HW_SCE_p_func100(0x88a8f9acu, 0x709537c5u, 0xef19b46au, 0xd7f9fa8fu); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -180,7 +181,7 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } SCE->REG_1CH = 0x00001800u; HW_SCE_p_func103(); - HW_SCE_p_func100(0x02dd0676u, 0x9678ebe1u, 0x10c7b8d2u, 0x520bc80fu); + HW_SCE_p_func100(0xb4ea2121u, 0x3fec0e34u, 0xde041e9du, 0xb8f5bb73u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -197,7 +198,7 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } SCE->REG_1CH = 0x00001800u; HW_SCE_p_func103(); - HW_SCE_p_func100(0xe1e50ca9u, 0x5e876405u, 0xe9d604d9u, 0xb03217d0u); + HW_SCE_p_func100(0x780a5964u, 0x6e5c9e99u, 0x8c0a5040u, 0x002f258au); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -226,17 +227,17 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) { SCE->REG_28H = 0x00890001u; - HW_SCE_p_func101(0x27e9ba0cu, 0xc682106bu, 0x0e239312u, 0x450aa767u); + HW_SCE_p_func101(0x9f1db89du, 0x0f5aa67bu, 0x2b151cd8u, 0x3dc562ecu); } else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) { SCE->REG_28H = 0x00880001u; - HW_SCE_p_func101(0x8f7dfdc3u, 0x6faa8ac8u, 0x1c6cf5fcu, 0x09387fffu); + HW_SCE_p_func101(0xca3f7eeeu, 0x09a4472au, 0x2e218f86u, 0x908b33dau); } else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) { SCE->REG_28H = 0x00870001u; - HW_SCE_p_func101(0x19521efau, 0x2f282005u, 0x0ae78c0du, 0x94ed7e6bu); + HW_SCE_p_func101(0x9c093ae5u, 0x1ed6255au, 0x8f67f24au, 0xeb53eefbu); } SCE->REG_24H = 0x000019c0u; /* WAIT_LOOP */ @@ -846,5 +847,5 @@ fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf4_r3.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf4_r4.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c index d8c8dfa38..27c5c9cd6 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -47,7 +48,7 @@ Exported global variables (to be accessed by other files) Private global variables and functions ***********************************************************************************************************************/ -fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) { uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; uint32_t dummy = 0u; @@ -67,9 +68,9 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x0000f501u; + SCE->REG_84H = 0x0000f502u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0xa7f12ee1u, 0x27da227du, 0x9461ff19u, 0x6881bdbdu); + HW_SCE_p_func100(0x312c0105u, 0xe39ac18fu, 0x3efce70du, 0x82ee3947u); SCE->REG_28H = 0x008b0001u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010340u; @@ -96,9 +97,9 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType } S_RAM[0] = change_endian_long(SCE->REG_100H); OFS_ADR = S_RAM[0]; - HW_SCE_p_func100(0xf46088a1u, 0xf9dbfbbbu, 0xb25ee1f4u, 0x85dd652du); + HW_SCE_p_func100(0x254f5bceu, 0xd0e0ae32u, 0x5e264fe5u, 0xe6343b1bu); HW_SCE_p_func027_r2(OFS_ADR); - HW_SCE_p_func100(0xd55c4eb5u, 0x7f198c94u, 0x721f4f41u, 0x1814ae3du); + HW_SCE_p_func100(0x5b67e65cu, 0x89b76efbu, 0x195f48f7u, 0x3a5ca1cfu); SCE->REG_24H = 0x000084d0u; /* WAIT_LOOP */ while (0u != SCE->REG_24H_b.B21) @@ -131,7 +132,7 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType /* waiting */ } HW_SCE_p_func103(); - HW_SCE_p_func100(0xa166c3d1u, 0x63f3e146u, 0x3407e331u, 0x077ac6f2u); + HW_SCE_p_func100(0x4d397cd5u, 0xbd352a05u, 0x2cc33cbau, 0xd1dd9e81u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -164,7 +165,7 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType /* waiting */ } SCE->REG_1CH = 0x00001800u; - HW_SCE_p_func100(0xbb59feb0u, 0x4dfb2a9bu, 0x836cc811u, 0x64f2af03u); + HW_SCE_p_func100(0xd3087966u, 0xf666cb88u, 0x5f0fa4acu, 0xa25c4eceu); HW_SCE_p_func103(); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; @@ -205,7 +206,7 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType { /* waiting */ } - HW_SCE_p_func100(0x41d0bf49u, 0xaa66c69au, 0xf4980677u, 0xfd0c6fa7u); + HW_SCE_p_func100(0x03845026u, 0xbbcf7d47u, 0xedb094b2u, 0x90542a64u); HW_SCE_p_func028_r2(OFS_ADR); SCE->REG_34H = 0x00000802u; SCE->REG_24H = 0x800088d0u; @@ -359,7 +360,7 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType SCE->REG_ECH = 0x0000b7a0u; SCE->REG_ECH = 0x000000f5u; SCE->REG_ECH = 0x00000b9cu; - HW_SCE_p_func100(0xfc034238u, 0xa16bf6e9u, 0xd5414d16u, 0x07a0874eu); + HW_SCE_p_func100(0x61153670u, 0xfb15e115u, 0xdfc162fdu, 0xc428f26au); SCE->REG_E0H = 0x81010380u; SCE->REG_04H = 0x00000607u; /* WAIT_LOOP */ @@ -370,13 +371,13 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType S_RAM[0] = change_endian_long(SCE->REG_100H); for(iLoop=0;iLoop<384;iLoop=iLoop+1) { - HW_SCE_p_func101(0x756940cau, 0x38631cc2u, 0x3a832969u, 0x9de523a9u); + HW_SCE_p_func101(0x60de8cceu, 0x0a5d67fau, 0xd6c84176u, 0xc734a08bu); HW_SCE_p_func300(); if (S_RAM[0] == 0x00000001) { break; } - HW_SCE_p_func101(0xc2cd7dc5u, 0x4cea4522u, 0xfd87c0a8u, 0x03011e3au); + HW_SCE_p_func101(0x8c1694a4u, 0xf381dd63u, 0x9a202387u, 0x1768b8d1u); } SCE->REG_24H = 0x00001dc0u; /* WAIT_LOOP */ @@ -1539,5 +1540,5 @@ fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf5_r4.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf5_r5.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c index de7075541..d1d8fb9b3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -47,7 +48,7 @@ Exported global variables (to be accessed by other files) Private global variables and functions ***********************************************************************************************************************/ -fsp_err_t HW_SCE_EcdsaP384SigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) { uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; uint32_t dummy = 0u; diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c index 576019ec2..408877283 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** @@ -67,9 +68,9 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy { return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; } - SCE->REG_84H = 0x0000f901u; + SCE->REG_84H = 0x0000f902u; SCE->REG_108H = 0x00000000u; - HW_SCE_p_func100(0x71955c20u, 0x3ac12303u, 0x15fa1bdau, 0xb60a3db0u); + HW_SCE_p_func100(0xba8ae618u, 0x5d822127u, 0xa6afe272u, 0x6caf7220u); SCE->REG_28H = 0x008b0001u; SCE->REG_104H = 0x00000068u; SCE->REG_E0H = 0x80010340u; @@ -96,12 +97,12 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy } S_RAM[0] = change_endian_long(SCE->REG_100H); OFS_ADR = S_RAM[0]; - HW_SCE_p_func100(0x4f0f541eu, 0x1a44960eu, 0x563abdb1u, 0xe3baac79u); + HW_SCE_p_func100(0x0b6231a1u, 0x4082f030u, 0x48c52f06u, 0x5326581du); HW_SCE_p_func027_r2(OFS_ADR); - HW_SCE_p_func100(0xc801a728u, 0x47ab14b5u, 0xf9ee4545u, 0xd37aac4fu); + HW_SCE_p_func100(0x0b7f37d0u, 0xd0a2a81eu, 0x474b3adfu, 0x9178501bu); SCE->REG_28H = 0x008d0001u; HW_SCE_p_func103(); - HW_SCE_p_func100(0x6d82e07fu, 0x8dad4d87u, 0xa9117322u, 0x58cdcce9u); + HW_SCE_p_func100(0x41340726u, 0x77095143u, 0x72576630u, 0x93c93c46u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -119,7 +120,7 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy } SCE->REG_1CH = 0x00001800u; HW_SCE_p_func103(); - HW_SCE_p_func100(0x60a4b8bau, 0x3aa18769u, 0xfaf0117du, 0x2d608defu); + HW_SCE_p_func100(0xe7d4d41fu, 0x6983ba59u, 0x15f1cca4u, 0xf5ee9a3eu); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -136,7 +137,7 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy } SCE->REG_1CH = 0x00001800u; HW_SCE_p_func103(); - HW_SCE_p_func100(0x11cdcd6cu, 0xa3872140u, 0x68e4fa6au, 0xe51f5637u); + HW_SCE_p_func100(0xb89c36f1u, 0xebc180b7u, 0xd992e7d8u, 0x4a0de3e7u); SCE->REG_104H = 0x00000052u; SCE->REG_C4H = 0x01000c84u; /* WAIT_LOOP */ @@ -233,7 +234,7 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy { /* waiting */ } - HW_SCE_p_func100(0x60c968fcu, 0x219d0e28u, 0x9436dee9u, 0xcc67ad17u); + HW_SCE_p_func100(0x3d1a8336u, 0x622e0f62u, 0xb1697e91u, 0xa005292fu); SCE->REG_24H = 0x000084d0u; /* WAIT_LOOP */ while (0u != SCE->REG_24H_b.B21) @@ -285,7 +286,7 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy /* waiting */ } HW_SCE_p_func028_r2(OFS_ADR); - HW_SCE_p_func100(0xdfa41c30u, 0xd99f4cfdu, 0xf7a85de6u, 0xa99c9005u); + HW_SCE_p_func100(0x64d66971u, 0x64ca9b9eu, 0x5940c872u, 0x204325b7u); SCE->REG_34H = 0x00000802u; SCE->REG_24H = 0x800088d0u; /* WAIT_LOOP */ @@ -329,13 +330,13 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy S_RAM[0] = change_endian_long(SCE->REG_100H); for(iLoop=0;iLoop<384;iLoop=iLoop+1) { - HW_SCE_p_func101(0xfbcc0d7fu, 0x36080ac4u, 0xcf7b143cu, 0x6ff21498u); + HW_SCE_p_func101(0xdbe796a4u, 0x6b1d9355u, 0xf4fd2662u, 0xd98cb7d6u); HW_SCE_p_func300(); if (S_RAM[0] == 0x00000001) { break; } - HW_SCE_p_func101(0xa45737d5u, 0xb1b23b5au, 0x2de55314u, 0x1d084e61u); + HW_SCE_p_func101(0xc0de3a65u, 0xfe27f27fu, 0x4d239102u, 0xb50f0d0au); } SCE->REG_24H = 0x00001dc0u; /* WAIT_LOOP */ @@ -802,5 +803,5 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveTy } /*********************************************************************************************************************** -End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf9_r3.prc +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf9_r4.prc ***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c index 0dc98aaa5..a1b7e141a 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c @@ -17,8 +17,9 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 05.10.2020 1.00 First Release. + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c index e803ba6a1..0340383e0 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c @@ -17,13 +17,14 @@ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. *********************************************************************************************************************/ /********************************************************************************************************************** - * File Name : s_flash.c - * Version : 1.09 + * File Name : s_flash2.c + * Version : 1.01 * Description : Key information file. *********************************************************************************************************************/ /********************************************************************************************************************** * History : DD.MM.YYYY Version Description - * : 31.03.2020 1.09 First Release + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. *********************************************************************************************************************/ /********************************************************************************************************************** @@ -752,7 +753,7 @@ uint32_t const S_FLASH2[] = 0x360a7d17, 0xa0c3d95a, 0xb712ee6d, 0x988346a3, 0x72c97b16, 0xb577609d, 0x50fc6d92, 0xe76c3ed0, 0x0292cc2a, 0x90ca06cd, 0x5471810e, 0xe7720dc8, -#endif /* defined __LIT */ +#endif /* defined __ARMEB__ */ }; /********************************************************************************************************************** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h index fd7ce6311..e2e916cf3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h @@ -88,6 +88,19 @@ fsp_err_t HW_SCE_Aes128CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uin fsp_err_t HW_SCE_Aes128CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes192EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes192EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes192EcbDecryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes192EcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EcbDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes192CbcEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes192CbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CbcEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes192CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes192CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + fsp_err_t HW_SCE_Aes256EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_Aes256EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); @@ -101,6 +114,40 @@ fsp_err_t HW_SCE_Aes256CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uin fsp_err_t HW_SCE_Aes256CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CtrEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes128CtrEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CtrEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CtrDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes128CtrDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CtrDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes192CtrEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes192CtrEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CtrEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes192CtrDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes192CtrDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CtrDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes256CtrEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes256CtrEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CtrEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256CtrDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_ICOUNTER); +fsp_err_t HW_SCE_Aes256CtrDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CtrDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes128XtsEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128XtsEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsEncryptFinalPrivate(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128XtsDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128XtsDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsDecryptFinalPrivate(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256XtsEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsEncryptFinalPrivate(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256XtsDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsDecryptFinalPrivate(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Aes128GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); fsp_err_t HW_SCE_Aes128GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); @@ -111,6 +158,18 @@ fsp_err_t HW_SCE_Aes128GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32 fsp_err_t HW_SCE_Aes128GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); fsp_err_t HW_SCE_Aes128GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes192GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes192GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes192GcmDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes192GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Aes256GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); fsp_err_t HW_SCE_Aes256GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); @@ -121,8 +180,11 @@ fsp_err_t HW_SCE_Aes256GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32 fsp_err_t HW_SCE_Aes256GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); fsp_err_t HW_SCE_Aes256GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); + void HW_SCE_Aes128GcmEncryptUpdateTransitionPrivate(void); void HW_SCE_Aes128GcmDecryptUpdateTransitionPrivate(void); +void HW_SCE_Aes192GcmEncryptUpdateTransitionPrivate(void); +void HW_SCE_Aes192GcmDecryptUpdateTransitionPrivate(void); void HW_SCE_Aes256GcmEncryptUpdateTransitionPrivate(void); void HW_SCE_Aes256GcmDecryptUpdateTransitionPrivate(void); @@ -136,6 +198,18 @@ fsp_err_t HW_SCE_Aes128CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint fsp_err_t HW_SCE_Aes128CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes192CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmEncryptFinalPrivate(uint32_t *InData_TextLen, uint32_t *InData_Text, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes192CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Aes256CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len); fsp_err_t HW_SCE_Aes256CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); @@ -155,6 +229,7 @@ fsp_err_t HW_SCE_Aes128CmacVerifyInitPrivate(sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_Aes128CmacVerifyUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CmacVerifyFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen); + fsp_err_t HW_SCE_Aes256CmacGenerateInitPrivate(sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_Aes256CmacGenerateUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, @@ -261,6 +336,7 @@ fsp_err_t HW_SCE_KeyUnwrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Te void HW_SCE_SoftwareResetSub(void); fsp_err_t HW_SCE_SelfCheck1Sub(void); fsp_err_t HW_SCE_SelfCheck2Sub(void); +fsp_err_t HW_SCE_SelfCheck3Sub(void); fsp_err_t HW_SCE_LoadHukSub(uint32_t *InData_LC); fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndexSub(uint32_t *InData_LC, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); @@ -269,9 +345,12 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InDa fsp_err_t HW_SCE_GenerateAes128KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes192KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateAes256KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub(uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateTdesKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); @@ -323,6 +402,7 @@ fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndexSub(uint32_t *InData_LC, uint32_t uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); fsp_err_t HW_SCE_UpdateAes128KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateAes192KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_UpdateAes256KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_UpdateTdesKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, @@ -362,12 +442,31 @@ fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, uint32_t MAX_CNT); + fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); void HW_SCE_Aes128GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, @@ -376,12 +475,16 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InD void HW_SCE_Aes128GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); -void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void); -void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void); -void HW_SCE_Aes256GcmDecryptUpdateTransitionSub(void); -void HW_SCE_Aes256GcmEncryptUpdateTransitionSub(void); -void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); -void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes192GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes192GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); void HW_SCE_Aes256GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, @@ -390,6 +493,17 @@ fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *In void HW_SCE_Aes256GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); + +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes192GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); void HW_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); void HW_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); @@ -403,6 +517,18 @@ fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *In void HW_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes192CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes192CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); + fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len); void HW_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); @@ -418,6 +544,10 @@ fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex); void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes192CmacInitSub(uint32_t *InData_KeyIndex); +void HW_SCE_Aes192CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen, uint32_t *OutData_DataT); fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex); void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, @@ -485,13 +615,13 @@ fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyInde fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, uint32_t *OutData_Text); -fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); -fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); -fsp_err_t HW_SCE_EcdsaSigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); -fsp_err_t HW_SCE_EcdsaP384SigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); fsp_err_t HW_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, @@ -556,7 +686,9 @@ void HW_SCE_p_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4 void HW_SCE_p_func103(void); void HW_SCE_p_func200(void); void HW_SCE_p_func202(void); +void HW_SCE_p_func205(void); void HW_SCE_p_func206(void); +void HW_SCE_p_func207(void); void HW_SCE_p_func300(void); void HW_SCE_p_func301(void); void HW_SCE_p_func302(void); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h index d64611b31..4f1672448 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h @@ -73,16 +73,24 @@ /* For AES operation. */ #define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_AES192_KEY_INDEX_WORD_SIZE (16U) #define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) #define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES192_KEY_WORD_SIZE (8U) #define HW_SCE_AES256_KEY_WORD_SIZE (8U) #define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES192_KEY_BYTE_SIZE (32U) #define HW_SCE_AES256_KEY_BYTE_SIZE (32U) #define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_BLOCK_BIT_SIZE (128U) #define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE (16U) #define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) #define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) +#define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) /* For TDES operation. */ #define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) @@ -294,6 +302,7 @@ typedef enum SCE_FW_CB_REQ_PRG_WT_LAST_BLK, SCE_FW_CB_REQ_GET_UPDATE_PRG_CHKSUM, SCE_FW_CB_REQ_STORE_MAC, + } SCE_FW_CB_REQ_TYPE; /* key index type */ @@ -301,6 +310,7 @@ typedef enum { SCE_KEY_INDEX_TYPE_INVALID = 0U, SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES192, SCE_KEY_INDEX_TYPE_AES256, SCE_KEY_INDEX_TYPE_TDES, SCE_KEY_INDEX_TYPE_HMAC_SHA1, @@ -314,6 +324,7 @@ typedef enum SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, @@ -328,11 +339,19 @@ typedef enum SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, - SCE_KEY_INDEX_TYPE_ECC_ESCP256K1_PUBLIC, - SCE_KEY_INDEX_TYPE_ECC_ESCP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_XTS, + SCE_KEY_INDEX_TYPE_AES256_XTS, SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_KEY_WRAP_FOR_DLMS_COSEM, } SCE_KEY_INDEX_TYPE; // added for RA6M4 start @@ -407,7 +426,7 @@ typedef sce_byte_data_t sce_ecdsa_byte_data_t; typedef struct sce_aes_key_index { uint32_t type; - /* AES128, AES256, AES128 for TLS, AES256 for TLS are supported */ + /* AES128, AES192, AES256, AES128 for TLS, AES256 for TLS are supported */ uint32_t value[HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE]; } sce_aes_key_index_t; @@ -625,10 +644,12 @@ typedef struct sce_update_key_ring typedef struct sce_aes_handle { uint32_t id; - sce_aes_key_index_t key_index; + sce_aes_key_index_t key_index; uint32_t current_input_data_size; uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; uint8_t current_ivec[HW_SCE_AES_CBC_IV_BYTE_SIZE]; + uint8_t current_icounter[HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE]; uint8_t flag_call_init; } sce_aes_handle_t; @@ -742,6 +763,8 @@ fsp_err_t HW_SCE_Open(lifecycle_t lifecycle, sce_tls_ca_certification_public_key sce_update_key_ring_t *key_index_2); fsp_err_t HW_SCE_Close(void); void HW_SCE_SoftwareReset(void); +fsp_err_t HW_SCE_SelfCheck2(void); +fsp_err_t HW_SCE_SelfCheck3(void); // added for RA6M4 start fsp_err_t HW_SCE_FwIntegrityCheck(void); @@ -751,6 +774,8 @@ fsp_err_t HW_SCE_UpdateOemKeyIndex(lifecycle_t lifecycle, sce_oem_cmd_t key_type fsp_err_t HW_SCE_GenerateAes128KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes192KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateAes256KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateTdesKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, @@ -796,7 +821,10 @@ fsp_err_t HW_SCE_GenerateSha256HmacKeyIndex(uint8_t *encrypted_provisioning_key, fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndex(sce_tls_p256_ecc_key_index_t *tls_p256_ecc_key_index, uint8_t *ephemeral_ecdh_public_key); fsp_err_t HW_SCE_GenerateAes128RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndex(sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateAes256RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndex(sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndex(sce_rsa1024_key_pair_index_t *key_pair_index); fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndex(sce_rsa2048_key_pair_index_t *key_pair_index); fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndex(sce_rsa3072_key_pair_index_t *key_pair_index); @@ -812,7 +840,10 @@ fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(lifecycle_t lifecycle, uint8_t *e uint32_t HW_SCE_GetVersion(void); fsp_err_t HW_SCE_GenerateAes128PlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes192PlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateAes256PlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes128XtsPlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256XtsPlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_GenerateRsa2048PublicPlainKeyIndex(uint8_t *plain_key, sce_rsa2048_public_key_index_t *key_index); fsp_err_t HW_SCE_GenerateRsa2048PrivatePlainKeyIndex(uint8_t *plain_key, sce_rsa2048_private_key_index_t *key_index); fsp_err_t HW_SCE_GenerateRsa3072PublicPlainKeyIndex(uint8_t *plain_key, sce_rsa3072_public_key_index_t *key_index); @@ -827,11 +858,19 @@ fsp_err_t HW_SCE_GenerateEccP256PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc fsp_err_t HW_SCE_GenerateEccP384PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); fsp_err_t HW_SCE_GenerateSha256HmacPlainKeyIndex(uint8_t *plain_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256r1PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256r1PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); + fsp_err_t HW_SCE_GenerateEccSecp256k1PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); fsp_err_t HW_SCE_GenerateEccSecp256k1PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); fsp_err_t HW_SCE_UpdateAes128KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes192KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_UpdateAes256KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes128XtsKeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes256XtsKeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_UpdateTdesKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_tdes_key_index_t *key_index); fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_rsa1024_public_key_index_t *key_index); @@ -898,6 +937,23 @@ fsp_err_t HW_SCE_Aes128CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *ciphe uint32_t cipher_length); fsp_err_t HW_SCE_Aes128CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes192EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes192EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192EcbEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes192EcbDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes192CbcEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes192CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + fsp_err_t HW_SCE_Aes256EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); fsp_err_t HW_SCE_Aes256EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, uint32_t plain_length); @@ -915,6 +971,54 @@ fsp_err_t HW_SCE_Aes256CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *ciphe uint32_t cipher_length); fsp_err_t HW_SCE_Aes256CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes128CtrEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes128CtrEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CtrEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes128CtrDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes192CtrEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes192CtrEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CtrEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes192CtrDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes256CtrEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes256CtrEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CtrEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *icounter); +fsp_err_t HW_SCE_Aes256CtrDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes128XtsEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128XtsEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsEncryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128XtsDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256XtsEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256XtsDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t text_bitlen); + fsp_err_t HW_SCE_Aes128GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, uint32_t ivec_len); fsp_err_t HW_SCE_Aes128GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, @@ -927,6 +1031,20 @@ fsp_err_t HW_SCE_Aes128GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *ciphe uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); fsp_err_t HW_SCE_Aes128GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, uint8_t *atag, uint32_t atag_len); + +fsp_err_t HW_SCE_Aes192GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmEncryptFinal(sce_gcm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_data_len, + uint8_t *atag); +fsp_err_t HW_SCE_Aes192GcmDecryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, + uint8_t *atag, uint32_t atag_len); + fsp_err_t HW_SCE_Aes256GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, uint32_t ivec_len); fsp_err_t HW_SCE_Aes256GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, @@ -952,6 +1070,20 @@ fsp_err_t HW_SCE_Aes128CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *ciphe uint32_t cipher_length); fsp_err_t HW_SCE_Aes128CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_Aes192CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CcmEncryptFinal(sce_ccm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes192CcmDecryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, + uint8_t *mac, uint32_t mac_length); + fsp_err_t HW_SCE_Aes256CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); fsp_err_t HW_SCE_Aes256CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, diff --git a/ra/fsp/src/r_sce/hw_sce_aes_private.h b/ra/fsp/src/r_sce/hw_sce_aes_private.h index 0ee552df6..d4e1236d3 100644 --- a/ra/fsp/src/r_sce/hw_sce_aes_private.h +++ b/ra/fsp/src/r_sce/hw_sce_aes_private.h @@ -33,7 +33,7 @@ #define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 32) -#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (416) +#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (448) /* Added 32 bits here to differentiate 192 wrapped key from 256 wrapped key in the psa_crypto stack. */ #define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 32) @@ -104,6 +104,16 @@ extern fsp_err_t HW_SCE_AES_128XtsDecrypt(const uint32_t * InData_Key, uint32_t * OutData_Text, uint32_t * OutData_IV); +extern fsp_err_t HW_SCE_AES_192EcbEncrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192EcbDecrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + extern fsp_err_t HW_SCE_AES_256EcbEncrypt(const uint32_t * InData_Key, const uint32_t num_words, const uint32_t * InData_Text, @@ -161,6 +171,18 @@ extern fsp_err_t HW_SCE_AES_128EcbDecryptUsingEncryptedKey(const uint32_t * InDa const uint32_t * InData_Text, uint32_t * OutData_Text); +extern fsp_err_t HW_SCE_AES_192CreateEncryptedKey(uint32_t * OutData_KeyIndex); + +extern fsp_err_t HW_SCE_AES_192EcbEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192EcbDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + extern fsp_err_t HW_SCE_AES_256CreateEncryptedKey(uint32_t * OutData_KeyIndex); extern fsp_err_t HW_SCE_AES_256EcbEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, diff --git a/ra/fsp/src/r_sce/hw_sce_private.h b/ra/fsp/src/r_sce/hw_sce_private.h index 9d8cf4946..ce0525c96 100644 --- a/ra/fsp/src/r_sce/hw_sce_private.h +++ b/ra/fsp/src/r_sce/hw_sce_private.h @@ -39,6 +39,9 @@ /********************************************************************************************************************** * Macro definitions ***********************************************************************************************************************/ +#define SCE_ECC_CURVE_TYPE_NIST (0x00000000U) +#define SCE_ECC_CURVE_TYPE_BRAINPOOL (0x01000000U) +#define SCE_ECC_CURVE_TYPE_KOBLITZ (0x02000000U) /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c index 65ba5731a..67cd91865 100644 --- a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c +++ b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c @@ -248,9 +248,6 @@ fsp_err_t R_SCI_I2C_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif #if SCI_I2C_CFG_DTC_ENABLE @@ -420,6 +417,7 @@ fsp_err_t R_SCI_I2C_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_SCI_I2C_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, void ( * p_callback)(i2c_master_callback_args_t *), @@ -434,21 +432,28 @@ fsp_err_t R_SCI_I2C_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); #if SCI_I2C_CFG_PARAM_CHECKING_ENABLE - if (!p_ctrl->callback_is_secure) - { - FSP_ASSERT(p_callback_memory); - } + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif - p_ctrl->p_callback = p_callback; + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -643,7 +648,7 @@ void sci_i2c_notify (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_sci_spi/r_sci_spi.c b/ra/fsp/src/r_sci_spi/r_sci_spi.c index 2a43f5357..93c715998 100644 --- a/ra/fsp/src/r_sci_spi/r_sci_spi.c +++ b/ra/fsp/src/r_sci_spi/r_sci_spi.c @@ -152,9 +152,6 @@ fsp_err_t R_SCI_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif #if SCI_SPI_DTC_SUPPORT_ENABLE == 1 @@ -346,6 +343,7 @@ fsp_err_t R_SCI_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_SCI_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, void ( * p_callback)(spi_callback_args_t *), @@ -360,14 +358,28 @@ fsp_err_t R_SCI_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -880,7 +892,7 @@ static void r_sci_spi_call_callback (sci_spi_instance_ctrl_t * p_ctrl, spi_event #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_sci_uart/r_sci_uart.c b/ra/fsp/src/r_sci_uart/r_sci_uart.c index d92825b8b..f8fb685ed 100644 --- a/ra/fsp/src/r_sci_uart/r_sci_uart.c +++ b/ra/fsp/src/r_sci_uart/r_sci_uart.c @@ -344,11 +344,6 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co p_ctrl->p_cfg = p_cfg; -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_ctrl->callback_is_secure = true; -#endif p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; @@ -689,6 +684,7 @@ fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, void ( * p_callback)(uart_callback_args_t *), @@ -703,15 +699,28 @@ fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ - #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_UART_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1502,7 +1511,7 @@ static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_ctrl, uint32_ #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_spi/r_spi.c b/ra/fsp/src/r_spi/r_spi.c index 31b792f88..b0539667e 100644 --- a/ra/fsp/src/r_spi/r_spi.c +++ b/ra/fsp/src/r_spi/r_spi.c @@ -238,9 +238,6 @@ fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif p_ctrl->p_regs = SPI_REG(p_ctrl->p_cfg->channel); @@ -330,6 +327,7 @@ fsp_err_t R_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, void ( * p_callback)(spi_callback_args_t *), @@ -344,14 +342,28 @@ fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SPI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; #endif - p_ctrl->p_callback = p_callback; p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1024,7 +1036,7 @@ static void r_spi_call_callback (spi_instance_ctrl_t * p_ctrl, spi_event_t event #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_ssi/r_ssi.c b/ra/fsp/src/r_ssi/r_ssi.c index 422e8e552..777006905 100644 --- a/ra/fsp/src/r_ssi/r_ssi.c +++ b/ra/fsp/src/r_ssi/r_ssi.c @@ -307,11 +307,6 @@ fsp_err_t R_SSI_Open (i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg) * procedure)" of the RA6M3 manual R01UH0886EJ0100. This function follows this procedure except for enabling * interrupts and enabling communication, which are done before communication begins. */ -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; -#endif p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; @@ -656,6 +651,7 @@ fsp_err_t R_SSI_VersionGet (fsp_version_t * const p_version) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_SSI_CallbackSet (i2s_ctrl_t * const p_api_ctrl, void ( * p_callback)(i2s_callback_args_t *), @@ -670,17 +666,28 @@ fsp_err_t R_SSI_CallbackSet (i2s_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(SSI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - /* Store callback and context */ - #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SSI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2s_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2s_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1175,7 +1182,7 @@ static void r_ssi_call_callback (ssi_instance_ctrl_t * p_ctrl, i2s_event_t event #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args); diff --git a/ra/fsp/src/r_usb_basic/r_usb_basic.c b/ra/fsp/src/r_usb_basic/r_usb_basic.c index cd1fd1560..465bd7e83 100644 --- a/ra/fsp/src/r_usb_basic/r_usb_basic.c +++ b/ra/fsp/src/r_usb_basic/r_usb_basic.c @@ -46,10 +46,6 @@ #include "../r_usb_hmsc/src/inc/r_usb_hmsc_driver.h" #endif /* defined(USB_CFG_HMSC_USE) */ -#if defined(USB_CFG_HVND_USE) - #include "r_usb_vendor.h" -#endif /* defined(USB_CFG_HVND_USE) */ - #if defined(USB_CFG_PHID_USE) #include "r_usb_phid_api.h" #endif /* defined(USB_CFG_PHID_USE) */ @@ -568,11 +564,13 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c { if (USB_MODE_HOST == p_cfg->usb_mode) { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << p_ctrl->type); /* Set USB Open device class */ if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) { g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_HCDCC); /* Set USB Open device class */ } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } else { @@ -592,6 +590,10 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c #if defined(USB_CFG_PMSC_USE) g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << USB_CLASS_INTERNAL_PMSC); #endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_PVND_USE) + g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << USB_CLASS_INTERNAL_PVND); +#endif /* defined(USB_CFG_PVND_USE) */ } } @@ -619,15 +621,8 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - usb_info_t info; - uint8_t ip; - uint8_t dev_addr; - usb_instance_ctrl_t ctrl; - usb_utr_t utr; - uint8_t class_code = USB_IFCLS_CDC; - - info.class_type = 0; - info.speed = 0; + usb_utr_t utr; + uint8_t class_code = USB_IFCLS_CDC; #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ #if USB_CFG_PARAM_CHECKING_ENABLE @@ -692,21 +687,7 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) usb_hstd_driver_release(&utr, class_code); - /* WAIT_LOOP */ - for (ip = 0; ip < USB_NUM_USBIP; ip++) - { - for (dev_addr = 1; dev_addr < (USB_MAXDEVADDR + 1); dev_addr++) - { - ctrl.module_number = ip; - ctrl.device_address = dev_addr; - ctrl.type = p_ctrl->type; - R_USB_InfoGet(&ctrl, &info, ctrl.device_address); - if ((USB_NULL != info.speed) && (ctrl.type == info.class_type)) - { - usb_hstd_clr_pipe_table(ip, dev_addr); - } - } - } + usb_hstd_clr_pipe_table(utr.ip, USB_ADDRESS1); #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } else @@ -1656,6 +1637,10 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 p_ctrl->pipe = pipe_number; + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = USB_ADDRESS1; + #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ERROR_RETURN((((USB_PIPE0 != p_ctrl->pipe)) || (USB_MAXPIPE_NUM < p_ctrl->pipe)), FSP_ERR_USB_PARAMETER) @@ -1663,41 +1648,57 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 FSP_ERROR_RETURN((((uint32_t) p_buf & 0x03) == 0), FSP_ERR_USB_PARAMETER) /* Argument Checking */ - FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number) && - (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number])), - FSP_ERR_USB_PARAMETER) + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ - ret_code = R_USB_InfoGet(p_ctrl, &info); + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) { /* PIPE Transfer set */ if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) { - #if defined(USB_CFG_HVND_USE) - #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - #if (BSP_CFG_RTOS == 2) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS == 2) p_tran_data = (usb_utr_t *) &tran_data; - #else /* (BSP_CFG_RTOS == 2) */ - p_tran_data = (usb_utr_t *) &g_usb_hdata[p_ctrl->module][p_ctrl->pipe]; - #endif /* (BSP_CFG_RTOS == 2) */ - - p_tran_data->ip = p_ctrl->module; - p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_tran_data->ip); - p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ - p_tran_data->p_tranadr = buf; /* Data address */ - p_tran_data->tranlen = size; /* Data Size */ - p_tran_data->p_setup = 0; - p_tran_data->complete = usb_hvnd_read_complete; /* Callback function */ - p_tran_data->segment = USB_TRAN_END; - *(uint32_t *) p_tran_data->p_usr_data = p_ctrl->device_address; - p_tran_data->read_req_len = size; /* Data Size */ - - err = usb_hstd_transfer_start(p_tran_data); /* USB Transfer Start */ + #else /* (BSP_CFG_RTOS == 2) */ + p_tran_data = (usb_utr_t *) &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; + #endif /* (BSP_CFG_RTOS == 2) */ + + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_tran_data->ip); + p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ + p_tran_data->p_tranadr = p_buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->p_setup = 0; + p_tran_data->complete = usb_hvnd_read_complete; /* Callback function */ + p_tran_data->segment = USB_TRAN_END; + p_tran_data->read_req_len = size; /* Data Size */ + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + + err = usb_hstd_transfer_start(p_tran_data); /* USB Transfer Start */ if (USB_OK == err) { ret_code = FSP_SUCCESS; @@ -1709,26 +1710,46 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 else { } - #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ - #endif /* #if defined(USB_CFG_HVND_USE) */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } else { - #if defined(USB_CFG_PVND_USE) - #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - #if (BSP_CFG_RTOS == 2) + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS == 2) p_tran_data = (usb_utr_t *) &tran_data; - #else /* (BSP_CFG_RTOS == 2) */ + #else /* (BSP_CFG_RTOS == 2) */ p_tran_data = (usb_utr_t *) &g_usb_pdata[p_ctrl->pipe]; - #endif /* (BSP_CFG_RTOS == 2) */ + #endif /* (BSP_CFG_RTOS == 2) */ p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ - p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->p_tranadr = p_buf; /* Data address */ p_tran_data->tranlen = size; /* Data Size */ p_tran_data->complete = (usb_cb_t) &usb_pvnd_read_complete; /* Callback function */ p_tran_data->read_req_len = size; /* Data Size */ - err = usb_pstd_transfer_start(p_tran_data); /* USB Transfer Start */ + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + + err = usb_pstd_transfer_start(p_tran_data); /* USB Transfer Start */ if (USB_OK == err) { ret_code = FSP_SUCCESS; @@ -1740,8 +1761,7 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 else { } - #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ - #endif /* defined(USB_CFG_PVND_USE) */ + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ } } return ret_code; @@ -1804,33 +1824,60 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - FSP_ASSERT((USB_NULL != p_buf) && (USB_NULL == size)) - #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + FSP_ASSERT(!((USB_NULL == p_buf) && (0 != size))) + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = USB_ADDRESS1; + #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } - FSP_ERROR_RETURN(USB_NULL == (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ - ret_code = R_USB_InfoGet(p_ctrl, &info); + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) { /* PIPE Transfer set */ if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - #if defined(USB_CFG_HVND_USE) - #if (BSP_CFG_RTOS == 2) + #if (BSP_CFG_RTOS == 2) p_tran_data = (usb_utr_t *) &tran_data; - #else /* (BSP_CFG_RTOS == 2) */ + #else /* (BSP_CFG_RTOS == 2) */ p_tran_data = (usb_utr_t *) &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; - #endif /* (BSP_CFG_RTOS == 2) */ + #endif /* (BSP_CFG_RTOS == 2) */ p_tran_data->ip = p_ctrl->module_number; p_tran_data->ipp = usb_hstd_get_usb_ip_adr((uint8_t) p_ctrl->module_number); p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ - p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->p_tranadr = p_buf; /* Data address */ p_tran_data->tranlen = size; /* Data Size */ p_tran_data->complete = usb_hvnd_write_complete; /* Callback function */ p_tran_data->segment = USB_TRAN_END; + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + err = usb_hstd_transfer_start(p_tran_data); if (USB_OK == err) { @@ -1843,24 +1890,44 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 else { } - #endif /* defined(USB_CFG_HVND_USE) */ #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } else { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) - #if defined(USB_CFG_PVND_USE) - #if (BSP_CFG_RTOS == 2) + #if (BSP_CFG_RTOS == 2) p_tran_data = (usb_utr_t *) &tran_data; - #else /* (BSP_CFG_RTOS == 2) */ + #else /* (BSP_CFG_RTOS == 2) */ p_tran_data = (usb_utr_t *) &g_usb_pdata[p_ctrl->pipe]; - #endif /* (BSP_CFG_RTOS == 2) */ + #endif /* (BSP_CFG_RTOS == 2) */ p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ - p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->p_tranadr = p_buf; /* Data address */ p_tran_data->tranlen = size; /* Data Size */ p_tran_data->complete = usb_pvnd_write_complete; /* Callback function */ + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + err = usb_pstd_transfer_start(p_tran_data); if (USB_OK == err) @@ -1874,7 +1941,6 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 else { } - #endif /* defined(USB_CFG_PVND_USE) */ #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ } } @@ -1906,18 +1972,19 @@ fsp_err_t R_USB_PipeStop (usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number) usb_er_t err = FSP_ERR_USB_FAILED; fsp_err_t ret_code = FSP_ERR_USB_FAILED; usb_info_t info; + usb_utr_t utr; #if USB_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_api_ctrl) #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - usb_utr_t utr; utr.ip = p_ctrl->module_number; if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) { - utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + p_ctrl->device_address = USB_ADDRESS1; } #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ p_ctrl->pipe = pipe_number; @@ -1934,7 +2001,7 @@ fsp_err_t R_USB_PipeStop (usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number) FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ - err = R_USB_InfoGet(p_ctrl, &info); + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); FSP_ERROR_RETURN(USB_STATUS_CONFIGURED == info.device_status, FSP_ERR_USB_FAILED) if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) @@ -2094,7 +2161,8 @@ fsp_err_t R_USB_PipeInfoGet (usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) - utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + p_ctrl->device_address = USB_ADDRESS1; #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c index 39e9654e1..6c7f4af2d 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c @@ -172,7 +172,7 @@ void (* g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) = USB_NULL, USB_NULL, /* USB_PHID (2) */ #endif - /* PVNDR */ + /* PVND */ USB_NULL, USB_NULL, /* USB_PVND (3) */ /* HCDC, HCDCC */ @@ -191,19 +191,19 @@ void (* g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) = USB_NULL, USB_NULL, /* USB_HHID (6) */ #endif - /* HVNDR */ -#if defined(USB_CFG_HVNDR_USE) - usb_hvndr_read_complete, usb_hnvdr_write_complete, /* USB_HVND (7) */ + /* HVND */ +#if defined(USB_CFG_HVND_USE) + usb_hvnd_read_complete, usb_hvnd_write_complete, /* USB_HVND (7) */ #else - USB_NULL, USB_NULL, /* USB_HVND (7) */ + USB_NULL, USB_NULL, /* USB_HVND (7) */ #endif /* HMSC */ - USB_NULL, USB_NULL, /* USB_HMSC (8) */ + USB_NULL, USB_NULL, /* USB_HMSC (8) */ /* PMSC */ - USB_NULL, USB_NULL, /* USB_PMSC (9) */ -}; /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */ + USB_NULL, USB_NULL, /* USB_PMSC (9) */ +}; /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */ #if defined(USB_CFG_PCDC_USE) diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c index 169ae2739..0daed7f2a 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c @@ -89,10 +89,17 @@ static uint16_t usb_shstd_clr_stall_request[USB_NUM_USBIP][5]; static usb_utr_t usb_shstd_clr_stall_ctrl[USB_NUM_USBIP]; #if defined(USB_CFG_HVND_USE) -static void usb_hvnd_configured(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); -static void usb_hvnd_detach(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); -static void usb_hvnd_enumeration(usb_clsinfo_t * mess, uint16_t ** table); -static void usb_hvnd_pipe_info(uint8_t * table, uint16_t speed, uint16_t length); +static usb_er_t usb_hvnd_set_pipe_registration(usb_utr_t * ptr, uint16_t dev_addr); +static void usb_hvnd_configured(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); +static void usb_hvnd_detach(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); +static void usb_hvnd_enumeration(usb_clsinfo_t * mess, uint16_t ** table); +static void usb_hvnd_pipe_info(usb_utr_t * p_utr, uint8_t * table, uint16_t speed, uint16_t length); +static uint8_t usb_hvnd_get_pipe_no(usb_utr_t * p_utr, uint8_t type, uint8_t dir); +static uint8_t usb_hvnd_make_pipe_reg_info(usb_utr_t * p_utr, + uint16_t address, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work); #endif /* defined(USB_CFG_HVND_USE) */ @@ -297,7 +304,7 @@ usb_er_t usb_hstd_transfer_start_req (usb_utr_t * ptr) } *p_tran_data = *ptr; - if (0 != ptr->p_setup) + if ((0 != ptr->p_setup) && (USB_PIPE0 == pipenum)) { p_tran_data->setup_data[0] = ptr->p_setup[0]; p_tran_data->setup_data[1] = ptr->p_setup[1]; @@ -2492,7 +2499,8 @@ usb_er_t usb_hvnd_set_pipe_registration (usb_utr_t * ptr, uint16_t dev_addr) if (USB_TRUE == g_usb_pipe_table[ptr->ip][pipe_no].use_flag) { /* Check USB Device address */ - if ((dev_addr << USB_DEVADDRBIT) == (g_usb_pipe_table[ptr->ip][pipe_no].pipe_maxp & USB_DEVSEL)) + if ((uint16_t) (dev_addr << USB_DEVADDRBIT) == + (uint16_t) (g_usb_pipe_table[ptr->ip][pipe_no].pipe_maxp & USB_DEVSEL)) { usb_hstd_set_pipe_reg(ptr, pipe_no); err = USB_OK; @@ -2523,17 +2531,19 @@ usb_er_t usb_hvnd_set_pipe_registration (usb_utr_t * ptr, uint16_t dev_addr) ******************************************************************************/ void usb_hvnd_configured (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) { + (void) data2; + usb_instance_ctrl_t ctrl; - ctrl.module = ptr->ip; /* Module number setting */ - ctrl.address = dev_addr; + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.device_address = (uint8_t) dev_addr; if (0 != dev_addr) { /* Registration */ usb_hvnd_set_pipe_registration(ptr, dev_addr); /* Host CDC Pipe registration */ } - usb_set_event(USB_STS_CONFIGURED, &ctrl); + usb_set_event(USB_STATUS_CONFIGURED, &ctrl); } /****************************************************************************** @@ -2550,13 +2560,15 @@ void usb_hvnd_configured (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) ******************************************************************************/ void usb_hvnd_detach (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) { + (void) data2; + usb_instance_ctrl_t ctrl; usb_hstd_clr_pipe_table(ptr->ip, dev_addr); - ctrl.module = ptr->ip; /* Module number setting */ - ctrl.address = dev_addr; - usb_set_event(USB_STS_DETACH, &ctrl); + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.device_address = (uint8_t) dev_addr; + usb_set_event(USB_STATUS_DETACH, &ctrl); } /****************************************************************************** @@ -2571,21 +2583,21 @@ void usb_hvnd_detach (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) ******************************************************************************/ void usb_hvnd_enumeration (usb_clsinfo_t * mess, uint16_t ** table) { - uint8_t * pdesc; - uint16_t total_len; + uint8_t * p_desc; + uint16_t desc_len; uint16_t speed; *table[3] = USB_OK; /* Pipe Information table set */ - speed = *table[6]; - pdesc = (uint8_t *) g_usb_hstd_config_descriptor[mess->ip]; + speed = *table[6]; + p_desc = (uint8_t *) g_usb_hstd_config_descriptor[mess->ip]; - total_len = ((uint16_t) *(pdesc + 3)) << 8; - total_len |= (uint16_t) *(pdesc + 2); + desc_len = (uint16_t) (((uint16_t) *(p_desc + 3)) << 8); + desc_len = (uint16_t) (desc_len + *(p_desc + 2)); /* Pipe Information table set */ - usb_hvnd_pipe_info(pdesc, speed, total_len); + usb_hvnd_pipe_info(mess, p_desc, speed, desc_len); #if (BSP_CFG_RTOS == 0) usb_hstd_return_enu_mgr(mess, USB_OK); /* Return to MGR */ @@ -2599,12 +2611,13 @@ void usb_hvnd_enumeration (usb_clsinfo_t * mess, uint16_t ** table) /****************************************************************************** * Function Name : usb_hvnd_pipe_info * Description : Host pipe information check. Set EP table. - * Arguments : uint8_t *table : Descriptor start address. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint8_t *table : Descriptor start address. * : uint16_t speed : Device connected speed * : uint16_t length : Configuration Descriptor Length * Return value : none ******************************************************************************/ -void usb_hvnd_pipe_info (uint8_t * table, uint16_t speed, uint16_t length) +static void usb_hvnd_pipe_info (usb_utr_t * p_utr, uint8_t * table, uint16_t speed, uint16_t length) { uint16_t ofdsc; uint16_t pipe_no; @@ -2619,22 +2632,18 @@ void usb_hvnd_pipe_info (uint8_t * table, uint16_t speed, uint16_t length) /* Search within Interface */ if (USB_DT_ENDPOINT == table[ofdsc + 1]) { - pipe_no = usb_hstd_make_pipe_reg_info(USB_IP0, 1, USB_HVND, speed, &table[ofdsc], &ep_tbl); + pipe_no = (uint16_t) (usb_hvnd_make_pipe_reg_info(p_utr, USB_ADDRESS1, speed, &table[ofdsc], &ep_tbl)); if (USB_NULL == pipe_no) { return; } else { - usb_hstd_set_pipe_info(USB_IP0, pipe_no, &ep_tbl); + usb_hstd_set_pipe_info(p_utr->ip, pipe_no, &ep_tbl); } - - ofdsc += table[ofdsc]; - } - else - { - ofdsc += table[ofdsc]; } + + ofdsc = (uint16_t) (ofdsc + table[ofdsc]); } } @@ -2651,15 +2660,18 @@ void usb_hvnd_pipe_info (uint8_t * table, uint16_t speed, uint16_t length) ******************************************************************************/ void usb_hvnd_read_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) { + (void) data1; + (void) data2; + usb_instance_ctrl_t ctrl; - ctrl.module = ptr->ip; /* Module number setting */ - ctrl.pipe = ptr->keyword; /* Pipe number setting */ - ctrl.type = USB_HVND; /* Vendor class */ + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.pipe = (uint8_t) ptr->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_INTERNAL_HVND; /* Vendor class */ - ctrl.size = ptr->read_req_len - ptr->tranlen; - ctrl.address = usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12; - #if #if (BSP_CFG_RTOS == 2) + ctrl.data_size = ptr->read_req_len - ptr->tranlen; + ctrl.device_address = (uint8_t) (usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12); + #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) ptr->cur_task_hdl; #endif /* #if (BSP_CFG_RTOS == 2) */ @@ -2667,31 +2679,31 @@ void usb_hvnd_read_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) { case USB_DATA_OK: { - ctrl.status = USB_SUCCESS; + ctrl.status = FSP_SUCCESS; break; } case USB_DATA_SHT: { - ctrl.status = USB_ERR_SHORT; + ctrl.status = FSP_ERR_USB_SIZE_SHORT; break; } case USB_DATA_OVR: { - ctrl.status = USB_ERR_OVER; + ctrl.status = FSP_ERR_USB_SIZE_OVER; break; } case USB_DATA_ERR: default: { - ctrl.status = USB_ERR_NG; + ctrl.status = FSP_ERR_USB_FAILED; break; } } - usb_set_event(USB_STS_READ_COMPLETE, &ctrl); /* Set Event() */ + usb_set_event(USB_STATUS_READ_COMPLETE, &ctrl); /* Set Event() */ } /****************************************************************************** @@ -2707,26 +2719,29 @@ void usb_hvnd_read_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) ******************************************************************************/ void usb_hvnd_write_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) { + (void) data1; + (void) data2; + usb_instance_ctrl_t ctrl; - ctrl.module = ptr->ip; /* Module number setting */ - ctrl.pipe = ptr->keyword; /* Pipe number setting */ - ctrl.type = USB_HVND; /* Vendor class */ - ctrl.address = usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12; - #if #if (BSP_CFG_RTOS == 2) + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.pipe = (uint8_t) ptr->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_INTERNAL_HVND; /* Vendor class */ + ctrl.device_address = (uint8_t) (usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12); + #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) ptr->cur_task_hdl; #endif /* #if (BSP_CFG_RTOS == 2) */ if (USB_DATA_NONE == ptr->status) { - ctrl.status = USB_SUCCESS; + ctrl.status = FSP_SUCCESS; } else { - ctrl.status = USB_ERR_NG; + ctrl.status = FSP_ERR_USB_FAILED; } - usb_set_event(USB_STS_WRITE_COMPLETE, &ctrl); /* Set Event() */ + usb_set_event(USB_STATUS_WRITE_COMPLETE, &ctrl); /* Set Event() */ } /****************************************************************************** @@ -2782,6 +2797,224 @@ void usb_hvnd_registration (usb_utr_t * ptr) /****************************************************************************** * End of function usb_hvnd_registration ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_make_pipe_reg_info + * Description : Make value for USB PIPE registers set value. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint16_t address : USB Device address + * : usb_class_t usb_class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint16_t speed : USB speed + * : uint8_t *descriptor : Address for End Point Descriptor + * : usb_pipe_table_reg_t *pipe_table_work : Address for Store PIPE reg set value. + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +static uint8_t usb_hvnd_make_pipe_reg_info (usb_utr_t * p_utr, + uint16_t address, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work) +{ + uint8_t pipe_no; + uint16_t pipe_cfg; + uint16_t pipe_maxp; + uint16_t pipe_peri = USB_NULL; + #if defined(BSP_MCU_GROUP_RA6M3) + uint16_t pipe_buf; + #endif /* defined(BSP_MCU_GROUP_RA6M3) */ + + /* Check Endpoint descriptor */ + if (USB_DT_ENDPOINT != descriptor[USB_DEV_B_DESCRIPTOR_TYPE]) + { + return USB_NULL; /* Error */ + } + + /* set pipe configuration value */ + switch ((uint16_t) (descriptor[USB_EP_B_ATTRIBUTES] & USB_EP_TRNSMASK)) + { + /* Bulk Endpoint */ + case USB_EP_BULK: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_H_IN); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_BULK, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_DIR_H_OUT); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_BULK, USB_PIPE_DIR_OUT); + } + + #if defined(BSP_MCU_GROUP_RA6M3) + if (USB_IP1 == p_utr->ip) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined(BSP_MCU_GROUP_RA6M3) */ + break; + } + + /* Interrupt Endpoint */ + case USB_EP_INT: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_IN); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_INT, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_OUT); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_INT, USB_PIPE_DIR_OUT); + } + + /* Get value for Interval Error Detection Interval */ + pipe_peri = usb_hstd_get_pipe_peri_value(speed, descriptor[USB_EP_B_INTERVAL]); + + break; + } + + default: + { + return USB_NULL; /* Error */ + break; + } + } + + /* Check Pipe no. */ + if (USB_NULL != pipe_no) + { + /* Endpoint number set */ + pipe_cfg = (uint16_t) (pipe_cfg | (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_NUMMASK)); + + /* set max packet size */ + pipe_maxp = (uint16_t) ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_L] | (address << USB_DEVADDRBIT)); + pipe_maxp = (uint16_t) (pipe_maxp | ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_H] << 8)); + + /* Store PIPE reg set value. */ + pipe_table_work->pipe_cfg = pipe_cfg; + pipe_table_work->pipe_maxp = pipe_maxp; + pipe_table_work->pipe_peri = pipe_peri; + #if defined(BSP_MCU_GROUP_RA6M3) + if (USB_IP1 == p_utr->ip) + { + /* PIPEBUF is USBA module only */ + pipe_buf = usb_hstd_get_pipe_buf_value(pipe_no); + pipe_table_work->pipe_buf = pipe_buf; + } + #endif /* #if defined(BSP_MCU_GROUP_RA6M3) */ + } + + return pipe_no; +} + +/****************************************************************************** + * End of function usb_hvnd_make_pipe_reg_info + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_pipe_no + * Description : Get PIPE No. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint16_t address : USB Device address + * : uint16_t class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint8_t type : Transfer Type.(USB_EP_BULK/USB_EP_INT) + * : uint8_t dir : (USB_PIPE_DIR_IN/USB_PIPE_DIR_OUT) + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +static uint8_t usb_hvnd_get_pipe_no (usb_utr_t * p_utr, uint8_t type, uint8_t dir) +{ + #if (USB_CFG_DMA == USB_CFG_DISABLE) + (void) dir; + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + uint8_t pipe_no = USB_NULL; + uint8_t pipe; + + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if ((USB_PIPE1 == pipe) || (USB_PIPE2 == pipe)) + { + if ((USB_PIPE_DIR_IN == dir) && (0 != p_utr->p_transfer_rx)) + { + /* For IN transfer */ + + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = pipe; /* Set Free pipe */ + break; + } + } + else if ((USB_PIPE_DIR_IN != dir) && (0 != p_utr->p_transfer_tx)) + { + /* For OUT Transfer */ + + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = pipe; /* Set Free pipe */ + break; + } + } + else + { + /* Nothing */ + } + } + else + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = pipe; /* Set Free pipe */ + break; + } + } + + #else + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check Free pipe */ + pipe_no = pipe; /* Set Free pipe */ + break; + } + #endif + } + } + + if (USB_EP_INT == type) + { + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check Free pipe */ + pipe_no = pipe; /* Set Free pipe */ + break; + } + } + } + + return pipe_no; +} + +/****************************************************************************** + * End of function usb_hvnd_get_pipe_no + ******************************************************************************/ #endif /* defined(USB_CFG_HVND_USE) */ #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c index 6ad6bd431..c7226277c 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c @@ -563,6 +563,7 @@ uint16_t usb_hstd_write_data (usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode) uint16_t buffer; uint16_t mxps; uint16_t end_flag; + uint16_t read_pid; if (USB_MAX_PIPE_NO < pipe) { @@ -630,6 +631,9 @@ uint16_t usb_hstd_write_data (usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode) count = size; } + read_pid = usb_cstd_get_pid(ptr, pipe); + usb_cstd_set_nak(ptr, pipe); + gp_usb_hstd_data_ptr[ptr->ip][pipe] = usb_hstd_write_fifo(ptr, count, pipemode, gp_usb_hstd_data_ptr[ptr->ip][pipe]); @@ -653,6 +657,14 @@ uint16_t usb_hstd_write_data (usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode) g_usb_hstd_data_cnt[ptr->ip][pipe] -= count; } + hw_usb_clear_status_bemp(ptr, pipe); + + /* USB_PID_BUF ? */ + if (USB_PID_BUF == (USB_PID & read_pid)) + { + usb_cstd_set_buf(ptr, pipe); + } + /* End or Err or Continue */ return end_flag; } @@ -1062,9 +1074,17 @@ void usb_hstd_brdy_pipe_process (usb_utr_t * ptr, uint16_t bitsts) g_usb_cstd_dma_size[ip][dma_ch] = buffer & USB_DTLN; if (set_dma_block_cnt > trans_dma_block_cnt) { - g_usb_cstd_dma_size[ip][dma_ch] = - (uint16_t) ((uint16_t) (g_usb_cstd_dma_size[ip][dma_ch]) + - (uint16_t) ((set_dma_block_cnt - (trans_dma_block_cnt + 1)) * maxps)); + if (0 != g_usb_cstd_dma_size[ip][dma_ch]) + { + g_usb_cstd_dma_size[ip][dma_ch] = + (uint16_t) ((uint16_t) (g_usb_cstd_dma_size[ip][dma_ch]) + + (uint16_t) ((set_dma_block_cnt - (trans_dma_block_cnt + 1)) * maxps)); + } + else + { + g_usb_cstd_dma_size[ip][dma_ch] = + (uint16_t) ((set_dma_block_cnt - (trans_dma_block_cnt)) * maxps); + } } /* Check data count */ @@ -1473,7 +1493,7 @@ uint8_t usb_hstd_get_pipe_no (uint16_t ip_no, uint16_t address, uint16_t usb_cla if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) { /* Check Free pipe */ - pipe_no = pipe; /* Set Free pipe */ + pipe_no = (uint8_t) pipe; /* Set Free pipe */ break; } } @@ -1488,7 +1508,7 @@ uint8_t usb_hstd_get_pipe_no (uint16_t ip_no, uint16_t address, uint16_t usb_cla if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) { /* Check Free pipe */ - pipe_no = pipe; /* Set Free pipe */ + pipe_no = (uint8_t) pipe; /* Set Free pipe */ break; } } @@ -1790,6 +1810,43 @@ uint16_t usb_hstd_get_pipe_buf_value (uint16_t pipe_no) break; } #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HVND_USE) + case USB_PIPE1: + { + pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(8u)); + break; + } + + case USB_PIPE2: + { + pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(24u)); + break; + } + + case USB_PIPE3: + { + pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(40u)); + break; + } + + case USB_PIPE4: + { + pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(56u)); + break; + } + + case USB_PIPE5: + { + pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(72u)); + break; + } + #endif /* defined(USB_CFG_HVND_USE) */ + default: + { + /* Error */ + break; + } } return pipe_buf; diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c index 3a097d0f0..e8a3aebfe 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c @@ -1381,10 +1381,10 @@ usb_er_t usb_pstd_transfer_end (usb_utr_t * p_utr, uint16_t pipe) #if (BSP_CFG_RTOS == 0) usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_STOP, p_utr); #else /* BSP_CFG_RTOS == 0 */ - (void) *p_utr; utr.msghead = (usb_mh_t) USB_NULL; utr.msginfo = USB_MSG_PCD_TRANSEND1; utr.keyword = pipe; + utr.ip = p_utr->ip; /* Send message */ err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) &utr); @@ -1907,12 +1907,15 @@ void usb_peri_interface (usb_utr_t * ptr, uint16_t data1, uint16_t data2) ******************************************************************************/ void usb_pvnd_read_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) { + (void) data1; + (void) data2; + usb_instance_ctrl_t ctrl; /* Set Receive data length */ - ctrl.size = mess->read_req_len - mess->tranlen; - ctrl.pipe = mess->keyword; /* Pipe number setting */ - ctrl.type = USB_PVND; /* Device class setting */ + ctrl.data_size = mess->read_req_len - mess->tranlen; + ctrl.pipe = (uint8_t) mess->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_INTERNAL_PVND; /* Device class setting */ #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) mess->cur_task_hdl; #endif /* (BSP_CFG_RTOS == 2) */ @@ -1920,32 +1923,32 @@ void usb_pvnd_read_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) { case USB_DATA_OK: { - ctrl.status = USB_SUCCESS; + ctrl.status = FSP_SUCCESS; break; } case USB_DATA_SHT: { - ctrl.status = USB_ERR_SHORT; + ctrl.status = FSP_ERR_USB_SIZE_SHORT; break; } case USB_DATA_OVR: { - ctrl.status = USB_ERR_OVER; + ctrl.status = FSP_ERR_USB_SIZE_OVER; break; } case USB_DATA_ERR: default: { - ctrl.status = USB_ERR_NG; + ctrl.status = FSP_ERR_USB_FAILED; break; } } ctrl.module_number = mess->ip; - usb_set_event(USB_STS_READ_COMPLETE, &ctrl); + usb_set_event(USB_STATUS_READ_COMPLETE, &ctrl); } /* End of function usb_pvnd_read_complete() */ /****************************************************************************** @@ -1956,24 +1959,27 @@ void usb_pvnd_read_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) ******************************************************************************/ void usb_pvnd_write_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) { + (void) data1; + (void) data2; + usb_instance_ctrl_t ctrl; - ctrl.pipe = mess->keyword; /* Pipe number setting */ - ctrl.type = USB_PVND; /* CDC Control class */ + ctrl.pipe = (uint8_t) mess->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_INTERNAL_PVND; /* CDC Control class */ if (USB_DATA_NONE == mess->status) { - ctrl.status = USB_SUCCESS; + ctrl.status = FSP_SUCCESS; } else { - ctrl.status = USB_ERR_NG; + ctrl.status = FSP_ERR_USB_FAILED; } ctrl.module_number = mess->ip; #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) mess->cur_task_hdl; #endif /* (BSP_CFG_RTOS == 2) */ - usb_set_event(USB_STS_WRITE_COMPLETE, &ctrl); + usb_set_event(USB_STATUS_WRITE_COMPLETE, &ctrl); } /* End of function usb_pvnd_write_complete() */ #endif /* defined(USB_CFG_PVND_USE) */ diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c index 330e9e135..df9ef17fe 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c @@ -310,6 +310,7 @@ uint16_t usb_pstd_write_data (uint16_t pipe, uint16_t pipemode, usb_utr_t * p_ut uint16_t buffer; uint16_t mxps; uint16_t end_flag; + uint16_t read_pid; if (USB_MAX_PIPE_NO < pipe) { @@ -376,6 +377,9 @@ uint16_t usb_pstd_write_data (uint16_t pipe, uint16_t pipemode, usb_utr_t * p_ut count = size; } + read_pid = usb_cstd_get_pid(p_utr, pipe); + usb_cstd_set_nak(p_utr, pipe); + gp_usb_pstd_data[pipe] = usb_pstd_write_fifo(count, pipemode, gp_usb_pstd_data[pipe], p_utr); /* Check data count to remain */ @@ -400,6 +404,14 @@ uint16_t usb_pstd_write_data (uint16_t pipe, uint16_t pipemode, usb_utr_t * p_ut g_usb_pstd_data_cnt[pipe] -= count; } + hw_usb_clear_status_bemp(p_utr, pipe); + + /* USB_PID_BUF ? */ + if (USB_PID_BUF == (USB_PID & read_pid)) + { + usb_cstd_set_buf(p_utr, pipe); + } + /* End or Err or Continue */ return end_flag; } @@ -834,10 +846,17 @@ void usb_pstd_brdy_pipe_process (usb_utr_t * p_utr, uint16_t bitsts) g_usb_cstd_dma_size[p_utr->ip][dma_ch] = (uint32_t) (buffer & USB_DTLN); if (set_dma_block_cnt > trans_dma_block_cnt) { - g_usb_cstd_dma_size[p_utr->ip][dma_ch] = - g_usb_cstd_dma_size[p_utr->ip][dma_ch] + - (uint32_t) ((set_dma_block_cnt - - (trans_dma_block_cnt + 1)) * maxps); + if (0 != g_usb_cstd_dma_size[p_utr->ip][dma_ch]) + { + g_usb_cstd_dma_size[p_utr->ip][dma_ch] = + g_usb_cstd_dma_size[p_utr->ip][dma_ch] + + (uint32_t) ((set_dma_block_cnt - (trans_dma_block_cnt + 1)) * maxps); + } + else + { + g_usb_cstd_dma_size[p_utr->ip][dma_ch] = + (uint32_t) ((set_dma_block_cnt - (trans_dma_block_cnt)) * maxps); + } } /* Check data count */ @@ -1247,9 +1266,10 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint { if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_BULK_IN].use_flag) { - pipe_no = USB_CFG_PCDC_BULK_IN; /* Set Free pipe */ + pipe_no = USB_CFG_PCDC_BULK_IN; /* Set Free pipe */ } -#if (USB_NULL != USB_CFG_PCDC_BULK_IN2) + + #if (USB_NULL != USB_CFG_PCDC_BULK_IN2) else if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_BULK_IN2].use_flag) { pipe_no = USB_CFG_PCDC_BULK_IN2; /* Set Free pipe */ @@ -1258,15 +1278,16 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint { /* Error */ } -#endif /* (USB_NULL != USB_CFG_PCDC_BULK_IN2) */ + #endif /* (USB_NULL != USB_CFG_PCDC_BULK_IN2) */ } else { if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_BULK_OUT].use_flag) { - pipe_no = USB_CFG_PCDC_BULK_OUT; /* Set Free pipe */ + pipe_no = USB_CFG_PCDC_BULK_OUT; /* Set Free pipe */ } -#if (USB_NULL != USB_CFG_PCDC_BULK_OUT2) + + #if (USB_NULL != USB_CFG_PCDC_BULK_OUT2) else if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_BULK_OUT2].use_flag) { pipe_no = USB_CFG_PCDC_BULK_OUT2; /* Set Free pipe */ @@ -1275,7 +1296,7 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint { /* Error */ } -#endif /* #if (USB_NULL != USB_CFG_PCDC_BULK_OUT2) */ + #endif /* #if (USB_NULL != USB_CFG_PCDC_BULK_OUT2) */ } } } @@ -1288,9 +1309,10 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint { if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_INT_IN].use_flag) { - pipe_no = USB_CFG_PCDC_INT_IN; /* Set Free pipe */ + pipe_no = USB_CFG_PCDC_INT_IN; /* Set Free pipe */ } -#if (USB_NULL != USB_CFG_PCDC_INT_IN2) + + #if (USB_NULL != USB_CFG_PCDC_INT_IN2) else if (USB_FALSE == g_usb_pipe_table[p_utr->ip][USB_CFG_PCDC_INT_IN2].use_flag) { pipe_no = USB_CFG_PCDC_INT_IN2; /* Set Free pipe */ @@ -1299,7 +1321,7 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint { /* Error */ } -#endif /* #if (USB_NULL != USB_CFG_PCDC_INT_IN2) */ + #endif /* #if (USB_NULL != USB_CFG_PCDC_INT_IN2) */ } } } @@ -1348,12 +1370,50 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint /* WAIT_LOOP */ for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) { + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if ((USB_PIPE1 == pipe) || (USB_PIPE2 == pipe)) + { + if ((dir == USB_PIPE_DIR_IN) && (0 != p_utr->p_transfer_tx)) + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = (uint8_t) pipe; /* Set Free pipe */ + break; + } + } + else if ((dir != USB_PIPE_DIR_IN) && (0 != p_utr->p_transfer_rx)) + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = (uint8_t) pipe; /* Set Free pipe */ + break; + } + } + else + { + /* Nothing */ + } + } + else + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + pipe_no = (uint8_t) pipe; /* Set Free pipe */ + break; + } + } + #else + /* Check Free pipe */ if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) { - pipe_no = pipe; /* Set Free pipe */ + pipe_no = (uint8_t) pipe; /* Set Free pipe */ break; } + #endif } } @@ -1366,7 +1426,7 @@ uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint /* Check Free pipe */ if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) { - pipe_no = pipe; /* Set Free pipe */ + pipe_no = (uint8_t) pipe; /* Set Free pipe */ break; } } @@ -1435,7 +1495,7 @@ uint16_t usb_pstd_get_pipe_buf_value (uint16_t pipe_no) } #endif /* defined(USB_CFG_PMSC_USE) */ - #if defined(USB_CFG_PVND_USE) || defined(USB_CFG_HVND_USE) + #if defined(USB_CFG_PVND_USE) case USB_PIPE1: { pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(8U)); @@ -1465,32 +1525,7 @@ uint16_t usb_pstd_get_pipe_buf_value (uint16_t pipe_no) pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(72U)); break; } - #endif /* defined(USB_CFG_PVND_USE) || defined(USB_CFG_HVND_USE) */ - - case USB_PIPE6: - { - pipe_buf = (USB_BUF_SIZE(64U) | USB_BUF_NUMB(4U)); - break; - } - - case USB_PIPE7: - { - pipe_buf = (USB_BUF_SIZE(64U) | USB_BUF_NUMB(5U)); - break; - } - - case USB_PIPE8: - { - pipe_buf = (USB_BUF_SIZE(64U) | USB_BUF_NUMB(6U)); - break; - } - - case USB_PIPE9: - { - pipe_buf = (USB_BUF_SIZE(64U) | USB_BUF_NUMB(7U)); - break; - } - + #endif /* defined(USB_CFG_PVND_USE) */ default: { /* Error */ diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h index 27103663f..e22b57021 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h +++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h @@ -291,9 +291,6 @@ #define USB_TEST_STSelectors (0x0600U) /* Standard test selectors */ #define USB_TEST_RESERVED (0x4000U) /* Reserved */ #define USB_TEST_VSTMODES (0xC000U) /* VendorSpecific test modes */ -#define USB_EP_DIR (0x0080U) /* b7: Endpoint Direction */ -#define USB_EP_DIR_IN (0x0080U) -#define USB_EP_DIR_OUT (0x0000U) /* USB Request Length Register */ #define USB_WLENGTH (0xFFFFU) /* b15-0: wLength */ diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c index df43f4431..f98f2a105 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c @@ -79,19 +79,19 @@ #endif /* USB_CFG_DMA == USB_CFG_ENABLE */ #if USB_CFG_MODE == USB_CFG_HOST - #if defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PVNDR_USE) - #error Can not enable these definitions(USB_CFG_PCDC_USE/USB_CFG_PHID_USE/USB_CFG_PMSC_USE/USB_CFG_PVNDR_USE) \ + #if defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PVND_USE) + #error Can not enable these definitions(USB_CFG_PCDC_USE/USB_CFG_PHID_USE/USB_CFG_PMSC_USE/USB_CFG_PVND_USE) \ when setting USB_MODE_HOST to USB_CFG_MODE in r_usb_basic_cfg.h. - #endif /* defined(USB_CFG_PCDC_USE || USB_CFG_PHID_USE || USB_CFG_PMSC_USE || USB_CFG_PVNDR_USE) */ + #endif /* defined(USB_CFG_PCDC_USE || USB_CFG_PHID_USE || USB_CFG_PMSC_USE || USB_CFG_PVND_USE) */ #endif /* USB_CFG_MODE == USB_MODE_HOST */ #if USB_CFG_MODE == USB_CFG_PERI - #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HVNDR_USE) - #error Can not enable these definitions(USB_CFG_HCDC_USE/USB_CFG_HHID_USE/USB_CFG_HMSC_USE/USB_CFG_HVNDR_USE) \ + #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HVND_USE) + #error Can not enable these definitions(USB_CFG_HCDC_USE/USB_CFG_HHID_USE/USB_CFG_HMSC_USE/USB_CFG_HVND_USE) \ when setting USB_MODE_PERI to USB_CFG_MODE in r_usb_basic_cfg.h. - #endif /* defined(USB_CFG_HCDC_USE || USB_CFG_HHID_USE || USB_CFG_HMSC_USE || USB_CFG_HVNDR_USE) */ + #endif /* defined(USB_CFG_HCDC_USE || USB_CFG_HHID_USE || USB_CFG_HMSC_USE || USB_CFG_HVND_USE) */ #endif /* USB_CFG_MODE == USB_MODE_PERI */ #if !defined(BSP_MCU_GROUP_RA6M3) diff --git a/ra/fsp/src/r_usb_composite/r_usb_pcdc_phid_descriptor.c.template b/ra/fsp/src/r_usb_composite/r_usb_pcdc_phid_descriptor.c.template index 50713b54d..e6702cb14 100644 --- a/ra/fsp/src/r_usb_composite/r_usb_pcdc_phid_descriptor.c.template +++ b/ra/fsp/src/r_usb_composite/r_usb_pcdc_phid_descriptor.c.template @@ -52,6 +52,7 @@ #define ITEM_LEN (76U) #define HID_MXPS (8U) #define NUM_EP (1U) +#define USB_VALUE_22H (0x22U) /* USB Class Definitions for Communications Devices Specification release number in binary-coded decimal. */ @@ -238,7 +239,7 @@ uint8_t g_apl_configuration[USB_PCDC_PHID_CD_LEN + (USB_PCDC_PHID_CD_LEN % 2)] = 0x01, /* 3:HID Ver */ 0x00, /* 4:bCountryCode */ 0x01, /* 5:bNumDescriptors */ - 0x22, /* 6:bDescriptorType */ + USB_VALUE_22H, /* 6:bDescriptorType */ ITEM_LEN, /* 7:wItemLength(L) */ 0x00, /* 8:wItemLength(H) */ diff --git a/ra/fsp/src/r_usb_composite/r_usb_phid_pmsc_descriptor.c.template b/ra/fsp/src/r_usb_composite/r_usb_phid_pmsc_descriptor.c.template index b5c668d14..368e9ef12 100644 --- a/ra/fsp/src/r_usb_composite/r_usb_phid_pmsc_descriptor.c.template +++ b/ra/fsp/src/r_usb_composite/r_usb_phid_pmsc_descriptor.c.template @@ -53,6 +53,8 @@ #define USB_INTERFACE_SUBCLASS (USB_ATAPI) #define USB_VALUE_64 (64) +#define USB_VALUE_100 (100) +#define USB_VALUE_22H (0x22U) /************************************************************ * Device Descriptor * @@ -92,7 +94,7 @@ uint8_t g_apl_configuration[USB_PMSC_PHID_CD_LEN + (USB_PMSC_PHID_CD_LEN % 2)] = 1, /* 5:bConfigurationValue */ 4, /* 6:iConfiguration */ (uint8_t) (USB_CF_RESERVED | USB_CF_SELFP | USB_CF_RWUPON), /* 7:bmAttributes */ - (uint8_t) (100 / 2), /* 8:bMaxPower (2mA unit) */ + (uint8_t) (USB_VALUE_100 / 2), /* 8:bMaxPower (2mA unit) */ /* Mass Storage Class */ @@ -145,7 +147,7 @@ uint8_t g_apl_configuration[USB_PMSC_PHID_CD_LEN + (USB_PMSC_PHID_CD_LEN % 2)] = 0x01, /* 3:HID Ver */ 0x00, /* 4:bCountryCode */ 0x01, /* 5:bNumDescriptors */ - 0x22, /* 6:bDescriptorType */ + USB_VALUE_22H, /* 6:bDescriptorType */ HID_ITEM_LEN, /* 7:wItemLength(L) */ 0x00, /* 8:wItemLength(H) */ diff --git a/ra/fsp/src/r_usb_phid/r_usb_phid_descriptor.c.template b/ra/fsp/src/r_usb_phid/r_usb_phid_descriptor.c.template index 0a9e0aa97..05c97ac47 100644 --- a/ra/fsp/src/r_usb_phid/r_usb_phid_descriptor.c.template +++ b/ra/fsp/src/r_usb_phid/r_usb_phid_descriptor.c.template @@ -28,8 +28,11 @@ #define CD_LEN (34U) /* Descriptor data Mask */ +#define USB_VALUE_32 (32) +#define USB_VALUE_100 (100) #define USB_UCHAR_MAX (0xffU) #define USB_W_TOTAL_LENGTH_MASK (256U) +#define USB_VALUE_22H (0x22U) /************************************************************ * Device Descriptor * @@ -69,7 +72,7 @@ uint8_t g_apl_configuration[CD_LEN + (CD_LEN % 2)] = 1, /* 5:bConfigurationValue */ 4, /* 6:iConfiguration */ (uint8_t) (USB_CF_RESERVED | USB_CF_SELFP | USB_CF_RWUPON), /* 7:bmAttributes */ - (uint8_t) (100 / 2), /* 8:bMaxPower (2mA unit) */ + (uint8_t) (USB_VALUE_100 / 2), /* 8:bMaxPower (2mA unit) */ /* Interface Descriptor */ USB_ID_BLENGTH, /* 0:bLength */ @@ -89,7 +92,7 @@ uint8_t g_apl_configuration[CD_LEN + (CD_LEN % 2)] = 0x01, /* 3:HID Ver */ 0x00, /* 4:bCountryCode */ 0x01, /* 5:bNumDescriptors */ - 0x22, /* 6:bDescriptorType */ + USB_VALUE_22H, /* 6:bDescriptorType */ ITEM_LEN, /* 7:wItemLength(L) */ 0x00, /* 8:wItemLength(H) */ @@ -138,7 +141,7 @@ uint8_t g_apl_string1[] = uint8_t g_apl_string2[] = { - 32, /* 0:bLength */ + USB_VALUE_32, /* 0:bLength */ USB_DT_STRING, /* 1:bDescriptorType */ 'U', 0x00, 'S', 0x00, diff --git a/ra/fsp/src/r_usb_phid/src/r_usb_phid_driver.c b/ra/fsp/src/r_usb_phid/src/r_usb_phid_driver.c index f51f949c0..7cbd306e1 100644 --- a/ra/fsp/src/r_usb_phid/src/r_usb_phid_driver.c +++ b/ra/fsp/src/r_usb_phid/src/r_usb_phid_driver.c @@ -44,6 +44,8 @@ #include "../../r_usb_basic/src/hw/inc/r_usb_reg_access.h" #include "r_usb_phid_api.h" +#ifdef USB_CFG_PHID_USE + /****************************************************************************** * Private global variables and functions ******************************************************************************/ @@ -83,9 +85,9 @@ void usb_phid_write_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) ctrl.status = FSP_ERR_USB_FAILED; } -#if (BSP_CFG_RTOS == 2) + #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) mess->cur_task_hdl; -#endif /* (BSP_CFG_RTOS_USED == 1) */ + #endif /* (BSP_CFG_RTOS_USED == 1) */ usb_set_event(USB_STATUS_WRITE_COMPLETE, &ctrl); } @@ -143,15 +145,16 @@ void usb_phid_read_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) } } -#if (BSP_CFG_RTOS == 2) + #if (BSP_CFG_RTOS == 2) ctrl.p_data = (void *) mess->cur_task_hdl; -#endif /* (BSP_CFG_RTOS_USED == 1) */ + #endif /* (BSP_CFG_RTOS_USED == 1) */ usb_set_event(USB_STATUS_READ_COMPLETE, &ctrl); } /****************************************************************************** * End of function usb_phid_read_complete ******************************************************************************/ +#endif /* USB_CFG_PHID_USE */ /****************************************************************************** * End Of File diff --git a/ra/fsp/src/r_usb_pvnd/r_usb_vendor_descriptor.c.template b/ra/fsp/src/r_usb_pvnd/r_usb_vendor_descriptor.c.template new file mode 100644 index 000000000..1186ae237 --- /dev/null +++ b/ra/fsp/src/r_usb_pvnd/r_usb_vendor_descriptor.c.template @@ -0,0 +1,357 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include "r_usb_basic.h" + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* bcdUSB */ +#define USB_BCDNUM (0x0200U) + +/* Release Number */ +#define USB_RELEASE (0x0200U) + +/* Configuration number */ +#define USB_CONFIGNUM (1U) + +/* vndror ID */ +#define USB_VENDORID (0x0000U) + +/* Product ID */ +#define USB_PRODUCTID (0x00FFU) + +/* DCP max packet size */ +#define USB_DCPMAXP (64U) + +/* Descriptor length */ +#define USB_ID_LEN (9U) /* Interface Descriptor Length */ +#define USB_EPD_LEN (7U) /* Endpoint Descriptor Length */ +#define USB_DD_LEN (18U) /* Device Desciptor Length */ +#define USB_QD_LEN (10U) /* Qualifier Descriptor Length */ +#define USB_CD_LEN (46U) /* Configuration Descriptor Length */ +#define USB_STRING0_LEN (4U) /* String0 Descriptor Length */ +#define USB_STRING1_LEN (16U) /* String1 Descriptor Length (iManufacturer) */ +#define USB_STRING2_LEN (36U) /* String2 Descriptor Length (iProduct) */ +#define USB_STRING3_LEN (30U) /* String3 Descriptor Length (iInterface) */ +#define USB_STRING4_LEN (22U) /* String4 Descriptor Length (iConfiguration) */ +#define USB_STRING5_LEN (18U) /* String5 Descriptor Length (iConfiguration) */ +#define USB_STRING6_LEN (28U) /* String6 Descriptor Length (iSerialNumber) */ +#define NUM_STRING_DESCRIPTOR (7U) /* Number of String Descriptor */ + +#define USB_VALUE_64 (64U) +#define USB_VALUE_100 (100U) +#define USB_VALUE_256 (256U) +#define USB_VALUE_FFH (0xFFU) +#define USB_VENDOR_CODE (USB_VALUE_FFH) +#define USB_NUM_EP (4U) + +#define USB_MXPS_BULK_FULL (64U) +#define USB_MXPS_BULK_HI (512U) +#define USB_MXPS_INT (64U) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +uint8_t g_apl_device[USB_DD_LEN] = +{ + USB_DD_LEN, /* 0:bLength */ + USB_DT_DEVICE, /* 1:bDescriptorType */ + (uint8_t) (USB_BCDNUM & (uint8_t) USB_VALUE_FFH), /* 2:bcdUSB_lo */ + (uint8_t) ((uint8_t) (USB_BCDNUM >> 8) & (uint8_t) USB_VALUE_FFH), /* 3:bcdUSB_hi */ + USB_VENDOR_CODE, /* 4:bDeviceClass */ + USB_VENDOR_CODE, /* 5:bDeviceSubClass */ + USB_VENDOR_CODE, /* 6:bDeviceProtocol */ + (uint8_t) USB_DCPMAXP, /* 7:bMAXPacketSize(for DCP) */ + (uint8_t) (USB_VENDORID & (uint8_t) USB_VALUE_FFH), /* 8:idvndror_lo */ + (uint8_t) ((uint8_t) (USB_VENDORID >> 8) & (uint8_t) USB_VALUE_FFH), /* 9:idvndror_hi */ + (uint8_t) (USB_PRODUCTID & (uint8_t) USB_VALUE_FFH), /* 10:idProduct_lo */ + (uint8_t) ((uint8_t) (USB_PRODUCTID >> 8) & (uint8_t) USB_VALUE_FFH), /* 11:idProduct_hi */ + (uint8_t) (USB_RELEASE & (uint8_t) USB_VALUE_FFH), /* 12:bcdDevice_lo */ + (uint8_t) ((uint8_t) (USB_RELEASE >> 8) & (uint8_t) USB_VALUE_FFH), /* 13:bcdDevice_hi */ + 1, /* 14:iManufacturer */ + 2, /* 15:iProduct */ + 6, /* 16:iSerialNumber */ + USB_CONFIGNUM /* 17:bNumConfigurations */ +}; + +uint8_t g_apl_qualifier[USB_QD_LEN] = +{ + USB_QD_LEN, /* 0:bLength */ + USB_DT_DEVICE_QUALIFIER, /* 1:bDescriptorType */ + (uint8_t) (USB_BCDNUM & (uint8_t) USB_VALUE_FFH), /* 2:bcdUSB_lo */ + (uint8_t) ((uint8_t) (USB_BCDNUM >> 8) & (uint8_t) USB_VALUE_FFH), /* 3:bcdUSB_hi */ + USB_VENDOR_CODE, /* 4:bDeviceClass */ + USB_VENDOR_CODE, /* 5:bDeviceSubClass */ + USB_VENDOR_CODE, /* 6:bDeviceProtocol */ + (uint8_t) USB_DCPMAXP, /* 7:bMAXPacketSize(for DCP) */ + USB_CONFIGNUM, /* 8:bNumConfigurations */ + 0 /* 9:bReserved */ +}; + +uint8_t g_apl_hs_configuration[USB_CD_LEN + (USB_CD_LEN % 2)] = +{ + 9, /* 0:bLength */ + USB_SOFT_CHANGE, /* 1:bDescriptorType */ + (uint8_t) (USB_CD_LEN % USB_VALUE_256), /* 2:wTotalLength(L) */ + (uint8_t) (USB_CD_LEN / USB_VALUE_256), /* 3:wTotalLength(H) */ + 1, /* 4:bNumInterfaces */ + 1, /* 5:bConfigurationValue */ + 5, /* 6:iConfiguration */ + (uint8_t) (USB_CF_RESERVED | USB_CF_SELFP), /* 7:bmAttributes */ + (uint8_t) (USB_VALUE_100 / 2), /* 8:bMaxPower (2mA unit) */ + + /* Interface Descriptor */ + USB_ID_LEN, /* 0:bLength */ + USB_DT_INTERFACE, /* 1:bDescriptor */ + 0, /* 2:bInterfaceNumber */ + 0, /* 3:bAlternateSetting */ + USB_NUM_EP, /* 4:bNumEndpoints */ + USB_VENDOR_CODE, /* 5:bInterfaceClass */ + USB_VENDOR_CODE, /* 6:bInterfaceSubClass */ + USB_VENDOR_CODE, /* 7:bInterfaceProtocol */ + 0, /* 8:iInterface */ + + /* Endpoint Descriptor 0 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_IN | USB_EP1), /* 2:bEndpointAddress */ + USB_EP_BULK, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_BULK_HI % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_BULK_HI / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 0, /* 6:bInterval */ + + /* Endpoint Descriptor 1 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_OUT | USB_EP2), /* 2:bEndpointAddress */ + USB_EP_BULK, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_BULK_HI % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_BULK_HI / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 0, /* 6:bInterval */ + + /* Endpoint Descriptor 5 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_IN | USB_EP6), /* 2:bEndpointAddress */ + USB_EP_INT, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_INT % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_INT / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 1, /* 6:bInterval */ + + /* Endpoint Descriptor 6 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_OUT | USB_EP7), /* 2:bEndpointAddress */ + USB_EP_INT, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_INT % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_INT / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 2, +}; + +uint8_t g_apl_configuration[USB_CD_LEN + (USB_CD_LEN % 2)] = +{ + 9, /* 0:bLength */ + USB_SOFT_CHANGE, /* 1:bDescriptorType */ + (uint8_t) (USB_CD_LEN % USB_VALUE_256), /* 2:wTotalLength(L) */ + (uint8_t) (USB_CD_LEN / USB_VALUE_256), /* 3:wTotalLength(H) */ + 1, /* 4:bNumInterfaces */ + 1, /* 5:bConfigurationValue */ + 4, /* 6:iConfiguration */ + (uint8_t) (USB_CF_RESERVED | USB_CF_SELFP), /* 7:bmAttributes */ + (uint8_t) (USB_VALUE_100 / 2), /* 8:bMaxPower (2mA unit) */ + + /* Interface Descriptor */ + USB_ID_LEN, /* 0:bLength */ + USB_DT_INTERFACE, /* 1:bDescriptor */ + 0, /* 2:bInterfaceNumber */ + 0, /* 3:bAlternateSetting */ + USB_NUM_EP, /* 4:bNumEndpoints */ + USB_VENDOR_CODE, /* 5:bInterfaceClass */ + USB_VENDOR_CODE, /* 6:bInterfaceSubClass */ + USB_VENDOR_CODE, /* 7:bInterfaceProtocol */ + 0, /* 8:iInterface */ + + /* Endpoint Descriptor 0 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_IN | USB_EP1), /* 2:bEndpointAddress */ + USB_EP_BULK, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_BULK_FULL % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_BULK_FULL / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 0, /* 6:bInterval */ + + /* Endpoint Descriptor 1 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_OUT | USB_EP2), /* 2:bEndpointAddress */ + USB_EP_BULK, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_BULK_FULL % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_BULK_FULL / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 0, /* 6:bInterval */ + + /* Endpoint Descriptor 5 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_IN | USB_EP6), /* 2:bEndpointAddress */ + USB_EP_INT, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_INT % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_INT / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 1, /* 6:bInterval */ + + /* Endpoint Descriptor 6 */ + USB_EPD_LEN, /* 0:bLength */ + USB_DT_ENDPOINT, /* 1:bDescriptorType */ + (uint8_t) (USB_EP_OUT | USB_EP7), /* 2:bEndpointAddress */ + USB_EP_INT, /* 3:bmAttribute */ + (uint8_t) (USB_MXPS_INT % USB_VALUE_256), /* 4:wMaxPacketSize_lo */ + (uint8_t) (USB_MXPS_INT / USB_VALUE_256), /* 5:wMaxPacketSize_hi */ + 2, /* 6:bInterval */ +}; + +/* UNICODE 0x0409 English (United States) */ +uint8_t g_apl_string0[USB_STRING0_LEN] = +{ + USB_STRING0_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 0x09, 0x04 /* 2:wLANGID[0] */ +}; + +/* iManufacturer */ +uint8_t g_apl_string1[USB_STRING1_LEN + (USB_STRING1_LEN % 2)] = +{ + USB_STRING1_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 'R', 0x00, + 'E', 0x00, + 'N', 0x00, + 'E', 0x00, + 'S', 0x00, + 'A', 0x00, + 'S', 0x00, +}; + +/* iProduct */ +uint8_t g_apl_string2[USB_STRING2_LEN + (USB_STRING2_LEN % 2)] = +{ + USB_STRING2_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 'U', 0x00, + 'S', 0x00, + 'B', 0x00, + ' ', 0x00, + 'D', 0x00, + 'e', 0x00, + 'm', 0x00, + 'o', 0x00, + 'n', 0x00, + 's', 0x00, + 't', 0x00, + 'r', 0x00, + 'a', 0x00, + 't', 0x00, + 'i', 0x00, + 'o', 0x00, + 'n', 0x00, +}; + +/* iInterface */ +uint8_t g_apl_string3[USB_STRING3_LEN + (USB_STRING3_LEN % 2)] = +{ + USB_STRING3_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 'V', 0x00, + 'e', 0x00, + 'n', 0x00, + 'd', 0x00, + 'o', 0x00, + 'r', 0x00, + + ' ', 0x00, + 'D', 0x00, + 'e', 0x00, + 'v', 0x00, + 'i', 0x00, + 'c', 0x00, + 'e', 0x00, +}; + +/* iConfiguration */ +uint8_t g_apl_string4[USB_STRING4_LEN + (USB_STRING4_LEN % 2)] = +{ + USB_STRING4_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 'F', 0x00, /* 2:wLANGID[0] */ + 'u', 0x00, + 'l', 0x00, + 'l', 0x00, + '-', 0x00, + 'S', 0x00, + 'p', 0x00, + 'e', 0x00, + 'e', 0x00, + 'd', 0x00 +}; + +/* iConfiguration */ +uint8_t g_apl_string5[USB_STRING5_LEN + (USB_STRING5_LEN % 2)] = +{ + USB_STRING5_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + 'H', 0x00, /* 2:wLANGID[0] */ + 'i', 0x00, + '-', 0x00, + 'S', 0x00, + 'p', 0x00, + 'e', 0x00, + 'e', 0x00, + 'd', 0x00 +}; + +/* iSerialNumber */ +uint8_t g_apl_string6[USB_STRING6_LEN + (USB_STRING6_LEN % 2)] = +{ + USB_STRING6_LEN, /* 0:bLength */ + USB_DT_STRING, /* 1:bDescriptorType */ + '0', 0x00, /* 2:wLANGID[0] */ + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '1', 0x00, +}; + +uint8_t * g_apl_string_table[] = +{ + g_apl_string0, + g_apl_string1, + g_apl_string2, + g_apl_string3, + g_apl_string4, + g_apl_string5, + g_apl_string6 +}; + +const usb_descriptor_t g_usb_descriptor = +{ + g_apl_device, /* Pointer to the device descriptor */ + g_apl_configuration, /* Pointer to the configuration descriptor for Full-speed */ + g_apl_hs_configuration, /* Pointer to the configuration descriptor for Hi-speed */ + g_apl_qualifier, /* Pointer to the qualifier descriptor */ + g_apl_string_table, /* Pointer to the string descriptor table */ + NUM_STRING_DESCRIPTOR +}; + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/ra/fsp/src/r_wdt/r_wdt.c b/ra/fsp/src/r_wdt/r_wdt.c index 9d4647f50..daf597beb 100644 --- a/ra/fsp/src/r_wdt/r_wdt.c +++ b/ra/fsp/src/r_wdt/r_wdt.c @@ -488,6 +488,7 @@ fsp_err_t R_WDT_CounterGet (wdt_ctrl_t * const p_ctrl, uint32_t * const p_count) * @retval FSP_SUCCESS Callback updated successfully. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. **********************************************************************************************************************/ fsp_err_t R_WDT_CallbackSet (wdt_ctrl_t * const p_ctrl, void ( * p_callback)(wdt_callback_args_t *), @@ -505,12 +506,26 @@ fsp_err_t R_WDT_CallbackSet (wdt_ctrl_t * const p_ctrl, /* Store callback and context */ #if BSP_TZ_SECURE_BUILD - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - p_instance_ctrl->callback_is_secure = + /* Get security state of p_callback */ + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if WDT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + wdt_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif #endif - p_instance_ctrl->p_callback = p_callback; + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(wdt_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif p_instance_ctrl->p_context = p_context; p_instance_ctrl->p_callback_memory = p_callback_memory; @@ -577,7 +592,7 @@ static void r_wdt_nmi_internal_callback (bsp_grp_irq_t irq) #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (gp_wdt_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(gp_wdt_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ gp_wdt_ctrl->p_callback(p_args); @@ -639,11 +654,6 @@ static void r_wdt_nmi_initialize (wdt_instance_ctrl_t * const p_instance_ctrl, w /* NMI output mode. */ R_BSP_GroupIrqWrite(BSP_GRP_IRQ_WDT_ERROR, r_wdt_nmi_internal_callback); - #if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_instance_ctrl->callback_is_secure = true; - #endif p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; diff --git a/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c b/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c index bb7408717..4dca1770d 100644 --- a/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c +++ b/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c @@ -47,7 +47,6 @@ #include #include "lfs.h" -#include "lfs_util.h" extern lfs_t RM_STDIO_LITTLEFS_CFG_LFS; diff --git a/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c b/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c index 057f3f40d..fc092da38 100644 --- a/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c +++ b/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c @@ -215,23 +215,23 @@ fsp_err_t RM_FREERTOS_PLUS_FAT_DiskInit (rm_freertos_plus_fat_ctrl_t * const FSP_ERROR_RETURN(RM_FREERTOS_PLUS_FAT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); /* Sector size must be a multiple of 512 bytes. */ - FSP_ASSERT(0U == p_disk_cfg->sector_size_bytes % RM_FREERTOS_PLUS_FAT_MIN_SECTOR_SIZE_BYTES); + FSP_ASSERT(0U == p_disk_cfg->device.sector_size_bytes % RM_FREERTOS_PLUS_FAT_MIN_SECTOR_SIZE_BYTES); /* Cache size must be multple of sector size and at least 2 * sector size. */ - FSP_ASSERT(0U == p_disk_cfg->cache_size_bytes % p_disk_cfg->sector_size_bytes); - FSP_ASSERT(p_disk_cfg->cache_size_bytes >= 2 * p_disk_cfg->sector_size_bytes); + FSP_ASSERT(0U == p_disk_cfg->cache_size_bytes % p_disk_cfg->device.sector_size_bytes); + FSP_ASSERT(p_disk_cfg->cache_size_bytes >= 2 * p_disk_cfg->device.sector_size_bytes); #endif /* Initialise the disk structure. memset used to clear unused bitfields. */ memset(p_disk, '\0', sizeof(FF_Disk_t)); - p_disk->ulNumberOfSectors = p_disk_cfg->num_sectors; + p_disk->ulNumberOfSectors = p_disk_cfg->device.sector_count; p_disk->xStatus.bPartitionNumber = p_disk_cfg->partition_number; p_disk->pvTag = p_instance_ctrl; FF_CreationParameters_t xParameters; xParameters.pucCacheMemory = p_disk_cfg->p_cache; xParameters.ulMemorySize = p_disk_cfg->cache_size_bytes; - xParameters.ulSectorSize = (BaseType_t) p_disk_cfg->sector_size_bytes; + xParameters.ulSectorSize = (BaseType_t) p_disk_cfg->device.sector_size_bytes; xParameters.fnWriteBlocks = rm_freertos_plus_fat_write; xParameters.fnReadBlocks = rm_freertos_plus_fat_read; xParameters.pxDisk = p_disk; diff --git a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c index 035028da8..e8e71e5bb 100644 --- a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c +++ b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c @@ -33,14 +33,18 @@ #define RM_LITTLEFS_FLASH_MINIMUM_BLOCK_SIZE (104) +#ifndef RM_LITTLEFS_FLASH_SEMAPHORE_TIMEOUT + #define RM_LITTLEFS_FLASH_SEMAPHORE_TIMEOUT UINT32_MAX +#endif + #ifdef RM_LITTLEFS_FLASH_DATA_START static const uint32_t rm_littlefs_flash_data_start = RM_LITTLEFS_FLASH_DATA_START; #else - #define rm_littlefs_flash_data_start BSP_FEATURE_FLASH_DATA_FLASH_START + #define rm_littlefs_flash_data_start BSP_FEATURE_FLASH_DATA_FLASH_START #endif /** "RLFS" in ASCII, used to determine if channel is open. */ -#define RM_LITTLEFS_FLASH_OPEN (0x524C4653ULL) +#define RM_LITTLEFS_FLASH_OPEN (0x524C4653ULL) const fsp_version_t g_rm_littlefs_flash_version = { @@ -73,6 +77,7 @@ const rm_littlefs_api_t g_rm_littlefs_on_flash = * @retval FSP_ERR_ALREADY_OPEN Module is already open. * @retval FSP_ERR_INVALID_SIZE The provided block size is invalid. * @retval FSP_ERR_INVALID_ARGUMENT Flash BGO mode must be disabled. + * @retval FSP_ERR_INTERNAL Failed to create the semaphore. * * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This * function calls: @@ -110,6 +115,17 @@ fsp_err_t RM_LITTLEFS_FLASH_Open (rm_littlefs_ctrl_t * const p_ctrl, rm_littlefs fsp_err_t err = p_flash->p_api->open(p_flash->p_ctrl, p_flash->p_cfg); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#if LFS_THREAD_SAFE + p_instance_ctrl->xSemaphore = xSemaphoreCreateMutexStatic(&p_instance_ctrl->xMutexBuffer); + + if (NULL == p_instance_ctrl->xSemaphore) + { + p_flash->p_api->close(p_flash->p_ctrl); + + return FSP_ERR_INTERNAL; + } +#endif + /* This module is now open. */ p_instance_ctrl->open = RM_LITTLEFS_FLASH_OPEN; @@ -144,6 +160,10 @@ fsp_err_t RM_LITTLEFS_FLASH_Close (rm_littlefs_ctrl_t * const p_ctrl) p_flash->p_api->close(p_extend->p_flash->p_ctrl); +#if LFS_THREAD_SAFE + vSemaphoreDelete(p_instance_ctrl->xSemaphore); +#endif + return FSP_SUCCESS; } @@ -271,6 +291,62 @@ int rm_littlefs_flash_erase (const struct lfs_config * c, lfs_block_t block) return LFS_ERR_OK; } +/*******************************************************************************************************************//** + * Returns the version of this module. + * + * Implements @ref rm_littlefs_api_t::versionGet(). + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to lock the flash. + **********************************************************************************************************************/ +int rm_littlefs_flash_lock (const struct lfs_config * c) +{ +#if LFS_THREAD_SAFE + rm_littlefs_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_flash_instance_ctrl_t *) c->context; + #if RM_LITTLEFS_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_LITTLEFS_FLASH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + BaseType_t err = xSemaphoreTake(p_instance_ctrl->xSemaphore, RM_LITTLEFS_FLASH_SEMAPHORE_TIMEOUT); + + FSP_ERROR_RETURN(true == err, LFS_ERR_IO); + + return LFS_ERR_OK; +#else + FSP_PARAMETER_NOT_USED(c); + + return LFS_ERR_IO; +#endif +} + +/*******************************************************************************************************************//** + * Returns the version of this module. + * + * Implements @ref rm_littlefs_api_t::versionGet(). + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to unlock the flash. + **********************************************************************************************************************/ +int rm_littlefs_flash_unlock (const struct lfs_config * c) +{ +#if LFS_THREAD_SAFE + rm_littlefs_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_flash_instance_ctrl_t *) c->context; + #if RM_LITTLEFS_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_LITTLEFS_FLASH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + BaseType_t err = xSemaphoreGive(p_instance_ctrl->xSemaphore); + + FSP_ERROR_RETURN(true == err, LFS_ERR_IO); + + return LFS_ERR_OK; +#else + FSP_PARAMETER_NOT_USED(c); + + return LFS_ERR_IO; +#endif +} + /*******************************************************************************************************************//** * Stub function required by LittleFS. All calls immedialy write/erase the lower layer. * @param[in] c Pointer to the LittleFS config block. diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c index 54241efe4..eb7b29570 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c @@ -88,7 +88,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un #if BSP_FEATURE_CRYPTO_HAS_SCE9 /* Create storage to hold the generated OEM key index. Size = Largest key size possible. */ - uint8_t encrypted_aes_key[SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED] = {0}; + uint8_t encrypted_aes_key[SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED] = {0}; #endif switch (keybits) { @@ -123,6 +123,37 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un break; } + case SIZE_AES_192BIT_KEYLEN_BITS: + { + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; + ctx->nr = 12; + if (false == (bool) ctx->vendor_ctx) + { + p_internal_key = encrypted_aes_key; + ret = (int) HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_AES192, + NULL, + NULL, + key, + (uint32_t *) p_internal_key); + ctx->vendor_ctx = (bool *) true; + } + + #else + if (true == (bool) ctx->vendor_ctx) + { + local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; + } + else + { + local_keybits = keybits; + } + ctx->nr = 12; + #endif + break; + } + case SIZE_AES_256BIT_KEYLEN_BITS: { #if BSP_FEATURE_CRYPTO_HAS_SCE9 @@ -165,7 +196,9 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un /* Store the encrypted key into the buffer */ for (uint32_t i = 0; i < (local_keybits >> 5); i++) { - /* buf is large enough to hold AES 256 bit wrapped key */ + /* buf is large enough to hold AES 192 bit wrapped key + * (largest key due to 32 bit padding for differentiating it from 256 wrapped key) + * */ GET_UINT32_LE(ctx->buf[i], p_internal_key, i << 2); } } @@ -229,6 +262,29 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char (uint32_t *) &output[0]); } } + + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + else if (ctx->nr == 12) + { + if (true == (bool) ctx->vendor_ctx) + { + #if (1 == BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED) && \ + ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_AES_FORMAT))) + err = + HW_SCE_AES_192EcbEncryptUsingEncryptedKey(ctx->buf, SIZE_AES_BLOCK_WORDS, (uint32_t *) &input[0], + (uint32_t *) &output[0]); + #else + ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + } + else + { + err = + HW_SCE_AES_192EcbEncrypt(ctx->buf, SIZE_AES_BLOCK_WORDS, (uint32_t *) &input[0], + (uint32_t *) &output[0]); + } + } + #endif else if (ctx->nr == 14) { if (true == (bool) ctx->vendor_ctx) @@ -293,6 +349,29 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char (uint32_t *) &output[0]); } } + + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + if (ctx->nr == 12) + { + if (true == (bool) ctx->vendor_ctx) + { + #if (1 == BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED) && \ + ((PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_AES_FORMAT))) + err = + HW_SCE_AES_192EcbDecryptUsingEncryptedKey(ctx->buf, SIZE_AES_BLOCK_WORDS, (uint32_t *) &input[0], + (uint32_t *) &output[0]); + #else + ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + } + else + { + err = + HW_SCE_AES_192EcbDecrypt(ctx->buf, SIZE_AES_BLOCK_WORDS, (uint32_t *) &input[0], + (uint32_t *) &output[0]); + } + } + #endif else if (ctx->nr == 14) { if (true == (bool) ctx->vendor_ctx) diff --git a/ra/fsp/src/rm_psa_crypto/aes_vendor.c b/ra/fsp/src/rm_psa_crypto/aes_vendor.c index 40f10de6b..3726b5e77 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_vendor.c +++ b/ra/fsp/src/rm_psa_crypto/aes_vendor.c @@ -69,6 +69,13 @@ psa_status_t prepare_raw_data_slot_vendor (psa_key_type_t type, size_t bits, str break; } + case SIZE_AES_192BIT_KEYLEN_BITS: + case SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED: + { + raw->bytes = SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED; + break; + } + case SIZE_AES_256BIT_KEYLEN_BITS: case SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED: { @@ -139,12 +146,22 @@ psa_status_t psa_generate_symmetric_vendor (psa_key_type_t type, size_t bits, ui break; } + #if BSP_FEATURE_CRYPTO_HAS_SCE9 case SIZE_AES_192BIT_KEYLEN_BITS: { - ret = PSA_ERROR_NOT_SUPPORTED; + if (output_size != SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED) + { + ret = PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (!ret) + { + err = HW_SCE_AES_192CreateEncryptedKey((uint32_t *) output); + } + break; } - + #endif case SIZE_AES_256BIT_KEYLEN_BITS: { if (output_size != SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED) @@ -206,7 +223,10 @@ psa_status_t psa_cipher_setup_vendor (psa_cipher_operation_t * operation, /* The mbedcrypto implementation obtains the list of methods based on the keybit size. * Since the wrapped keybit size does not correspond to the raw key size i.e the * AES256 raw bit size is 256 but the wrapped size is 416 bytes, provide the 256 bit value - * to mbedcrypto so that the right methods are invoked. */ + * to mbedcrypto so that the right methods are invoked. + * Since AES192 wrapped size is also 416, there is an addition of 32 dummy bits in the end to make it 448 bits. + * This helps to differentiate between the 256 and 192 wrapped keys. + * */ status = vendor_bitlength_to_raw_bitlength(slot->attr.type, slot->attr.bits, &key_bits); if (status != PSA_SUCCESS) { diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c index 2f4079be4..6a02e7294 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c @@ -190,6 +190,14 @@ static int ecp_group_load_a_only (mbedtls_ecp_group_id gid) { LOAD_GROUP_A_ONLY(secp256r1); + return 1; + } + #endif +#ifdef MBEDTLS_ECP_DP_BP256R1_ENABLED + case MBEDTLS_ECP_DP_BP256R1: + { + LOAD_GROUP_A_ONLY(secp256r1); + return 1; } #endif @@ -198,6 +206,14 @@ static int ecp_group_load_a_only (mbedtls_ecp_group_id gid) { LOAD_GROUP_A_ONLY(secp384r1); + return 1; + } + #endif +#ifdef MBEDTLS_ECP_DP_BP384R1_ENABLED + case MBEDTLS_ECP_DP_BP384R1: + { + LOAD_GROUP_A_ONLY(secp384r1); + return 1; } #endif @@ -323,25 +339,39 @@ int ecp_load_curve_attributes_sce (const mbedtls_ecp_group * grp, uint32_t * p_c { case MBEDTLS_ECP_DP_SECP256R1: { - *p_curve_type = 0x0; + *p_curve_type = SCE_ECC_CURVE_TYPE_NIST; *p_cmd = 0x0; priv_key_command = SCE_OEM_CMD_ECC_P256_PRIVATE; break; } case MBEDTLS_ECP_DP_SECP384R1: { - *p_curve_type = 0x0; + *p_curve_type = SCE_ECC_CURVE_TYPE_NIST; *p_cmd = 0x0; priv_key_command = SCE_OEM_CMD_ECC_P384_PRIVATE; break; } case MBEDTLS_ECP_DP_SECP256K1: { - *p_curve_type = 0x2; + *p_curve_type = SCE_ECC_CURVE_TYPE_KOBLITZ; *p_cmd = 0x0; priv_key_command = SCE_OEM_CMD_ECC_SECP256K1_PRIVATE; break; } + case MBEDTLS_ECP_DP_BP256R1: + { + *p_curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ECC_P256R1_PRIVATE; + break; + } + case MBEDTLS_ECP_DP_BP384R1: + { + *p_curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ECC_P384R1_PRIVATE; + break; + } default: { ret = -1; diff --git a/ra/fsp/src/rm_psa_crypto/inc/aes_vendor.h b/ra/fsp/src/rm_psa_crypto/inc/aes_vendor.h index 6daea706f..0cf5260fc 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/aes_vendor.h +++ b/ra/fsp/src/rm_psa_crypto/inc/aes_vendor.h @@ -28,6 +28,8 @@ extern "C" #define PSA_AES_BITS_VENDOR_RAW(bit_length) \ ((bit_length) == SIZE_AES_128BIT_KEYLEN_BITS ? SIZE_AES_128BIT_KEYLEN_BITS : \ (bit_length) == SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED ? SIZE_AES_128BIT_KEYLEN_BITS : \ + (bit_length) == SIZE_AES_192BIT_KEYLEN_BITS ? SIZE_AES_192BIT_KEYLEN_BITS : \ + (bit_length) == SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED ? SIZE_AES_192BIT_KEYLEN_BITS : \ (bit_length) == SIZE_AES_256BIT_KEYLEN_BITS ? SIZE_AES_256BIT_KEYLEN_BITS : \ (bit_length) == SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED ? SIZE_AES_256BIT_KEYLEN_BITS : \ 0) diff --git a/ra/fsp/src/rm_psa_crypto/vendor.c b/ra/fsp/src/rm_psa_crypto/vendor.c index e13817f17..aacccf7da 100644 --- a/ra/fsp/src/rm_psa_crypto/vendor.c +++ b/ra/fsp/src/rm_psa_crypto/vendor.c @@ -43,8 +43,9 @@ psa_status_t vendor_bitlength_to_raw_bitlength (psa_key_type_t type, size_t vend if (PSA_KEY_TYPE_IS_AES(type)) { /* Check that the bit size is acceptable for the key type - * NOTE: If adding wrapped 192 key support in future note that the size of the wrapped 192 and 256 AES keys - * are the same (416 bits) making this logic unusable */ + * Wrapped 192 key support is differentiated from 256 wrapped key support by increasing its size by 32 bits. + * These 32 bits are prepended and are not used by the crypto primitives (which continue to use 416 bits as the wrapped + * key length for both the keys). */ *raw_bits = PSA_AES_BITS_VENDOR_RAW(vendor_bits); if (0 == *raw_bits) { diff --git a/ra/fsp/src/rm_tfm_port/ra/attest_hal.c b/ra/fsp/src/rm_tfm_port/ra/attest_hal.c index d7a7d1740..3342d36b0 100644 --- a/ra/fsp/src/rm_tfm_port/ra/attest_hal.c +++ b/ra/fsp/src/rm_tfm_port/ra/attest_hal.c @@ -10,19 +10,10 @@ #include "tfm_attest_hal.h" #include "tfm_plat_boot_seed.h" #include "tfm_plat_device_id.h" +#include "tfm_common_config.h" +#include "region_defs.h" -/*! - * \def BOOT_SEED - * - * \brief Fixed value for boot seed used for test. - */ -#define BOOT_SEED 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, \ - 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, \ - 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, \ - 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF - -static const uint8_t boot_seed[BOOT_SEED_SIZE] = {BOOT_SEED}; /* Example verification service URL for initial attestation token */ static const char verification_service_url[] = "www.trustedfirmware.org"; @@ -62,25 +53,23 @@ tfm_attest_hal_get_profile_definition(uint32_t *size) enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf) { - /* FixMe: - This getter function must be ported per target platform. - * - Platform service shall provide an API to further interact this - * getter function to retrieve the boot seed. - */ - uint32_t i; uint8_t *p_dst = buf; - const uint8_t *p_src = boot_seed; + const uint8_t *p_src; - if (size != BOOT_SEED_SIZE) { + if (size != BOOT_TFM_SHARED_SEED_SIZE) + { return TFM_PLAT_ERR_SYSTEM_ERR; } - for (i = size; i > 0; i--) { + p_src = (const uint8_t *)BOOT_TFM_SHARED_SEED_BASE; + + for (i = size; i > 0; i--) + { *p_dst = *p_src; p_src++; p_dst++; } - return TFM_PLAT_ERR_SUCCESS; } diff --git a/ra/fsp/src/rm_tfm_port/ra/boot_hal.c b/ra/fsp/src/rm_tfm_port/ra/boot_hal.c index 73d0850ac..08fdc1ea5 100644 --- a/ra/fsp/src/rm_tfm_port/ra/boot_hal.c +++ b/ra/fsp/src/rm_tfm_port/ra/boot_hal.c @@ -16,6 +16,9 @@ #include "r_flash_api.h" #include "psa/crypto.h" +#if defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) + #include "platform.h" +#endif #if defined(__ARMCC_VERSION) __attribute__((naked)) void boot_clear_bl2_ram_area (void) @@ -77,14 +80,12 @@ __attribute__((naked)) void boot_clear_bl2_ram_area (void) #endif -#ifdef BOOT_DATA_AVAILABLE - /* * The section 'fsp_dtc_vector_table' is reused to store boot data. * This is done to avoid creating a BL2 specific linker script. */ static uint8_t g_tfm_shared_data[BOOT_TFM_SHARED_DATA_SIZE] BSP_PLACE_IN_SECTION(".fsp_dtc_vector_table"); -#endif /* BOOT_DATA_AVAILABLE */ +static uint8_t g_tfm_shared_boot_seed[BOOT_TFM_SHARED_SEED_SIZE] BSP_PLACE_IN_SECTION(".fsp_dtc_vector_table"); #define FAW_START_ADDR (0xFFFC) #define FAW_END_ADDR (0x200000) @@ -94,7 +95,6 @@ extern ARM_DRIVER_FLASH FLASH_DEV_NAME; /* FSP structures required by uart and flash drivers */ extern flash_hp_instance_ctrl_t g_tfm_fsp_flash_ctrl; -extern const flash_cfg_t g_tfm_fsp_flash_cfg; static void flash_FAW_Set (uint32_t start_addr, uint32_t end_addr) { @@ -130,9 +130,8 @@ int32_t boot_platform_init (void) return result; } -#ifdef BOOT_DATA_AVAILABLE memset(g_tfm_shared_data, 0x0, BOOT_TFM_SHARED_DATA_SIZE); -#endif /* BOOT_DATA_AVAILABLE */ + memset(g_tfm_shared_boot_seed, 0x0, BOOT_TFM_SHARED_SEED_SIZE); /* Set the FAW to lock the Secure code and data region */ @@ -141,10 +140,14 @@ int32_t boot_platform_init (void) result = mbedtls_platform_setup(NULL); if (result != 0) { - return result;; + return result; } result = psa_crypto_init(); + if (PSA_SUCCESS == result) + { + result = psa_generate_random(g_tfm_shared_boot_seed, BOOT_TFM_SHARED_SEED_SIZE); + } return result; } diff --git a/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c b/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c index 3c9924103..57d53a1fa 100644 --- a/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c +++ b/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c @@ -20,24 +20,28 @@ #include "platform/include/tfm_attest_hal.h" #include #include "psa/crypto_types.h" +#include "crypto_spe.h" +#include "tfm_plat_defs.h" -/* FIXME: Functions in this file should be implemented by platform vendor. For - * the security of the storage system, it is critical to use a hardware unique - * key. For the security of the attestation, it is critical to use a unique key - * pair and keep the private key is secret. - */ +#define SHA256_LEN_BYTES 32 -#define TFM_KEY_LEN_BYTES 16 +extern const psa_ecc_curve_t initial_attestation_curve_type; +extern const uint8_t initial_attestation_private_key[]; +extern const uint32_t initial_attestation_private_key_size; +const uint8_t tfm_key_derivation_prefix[] = "TFM_DERIVATION_PREFIX"; -static const uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] = +/* HUK to be used for key derivation. */ +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_CRYPTO") +const uint8_t tfm_huk_key[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; -extern const psa_ecc_curve_t initial_attestation_curve_type; -extern const uint8_t initial_attestation_private_key[]; -extern const uint32_t initial_attestation_private_key_size; +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_CRYPTO") +const uint32_t tfm_huk_key_size = sizeof(tfm_huk_key); /** * \brief Copy the key to the destination buffer @@ -69,13 +73,45 @@ enum tfm_plat_err_t tfm_plat_get_huk_derived_key (const uint8_t * label, (void) label_size; (void) context; (void) context_size; + psa_algorithm_t alg = PSA_ALG_SHA_256; + psa_hash_operation_t operation = {0}; + uint8_t hash[SHA256_LEN_BYTES] = {0}; + size_t hash_len = 0; + + /* Maximum derived-key size supported is 256 bits. */ + if (key_size > SHA256_LEN_BYTES) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (PSA_SUCCESS != psa_hash_setup(&operation, alg)) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* This prefix is used here in case the HUK has to be used for some other key derivation other than TFM labels. + * In that case a new prefix can be added without breaking existing code. */ + if (PSA_SUCCESS != psa_hash_update(&operation, tfm_key_derivation_prefix, sizeof(tfm_key_derivation_prefix))) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (PSA_SUCCESS != psa_hash_update(&operation, label, label_size)) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } - if (key_size > TFM_KEY_LEN_BYTES) + if (PSA_SUCCESS != psa_hash_update(&operation, (const uint8_t *) tfm_huk_key, tfm_huk_key_size)) { return TFM_PLAT_ERR_SYSTEM_ERR; } - copy_key(key, sample_tfm_key, key_size); + if (PSA_SUCCESS != psa_hash_finish(&operation, &hash[0], sizeof(hash), &hash_len)) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + copy_key(key, &hash[0], key_size); return TFM_PLAT_ERR_SUCCESS; } @@ -115,4 +151,3 @@ enum tfm_plat_err_t tfm_plat_get_initial_attest_key (uint8_t * key_buf, return TFM_PLAT_ERR_SUCCESS; } - diff --git a/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h b/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h index 2d9715aef..bd904a21e 100644 --- a/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h +++ b/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h @@ -130,8 +130,12 @@ * with TF-M Secure code's MSP stack */ #define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE -#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_SIZE (0x3E0) +#define BOOT_TFM_SHARED_SEED_BASE (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_DATA_SIZE) +#define BOOT_TFM_SHARED_SEED_SIZE (0x20) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_SEED_SIZE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) #endif /* __REGION_DEFS_H__ */ diff --git a/ra/fsp/src/rm_tz_context/tz_context.c b/ra/fsp/src/rm_tz_context/tz_context.c index 3a8595905..f637bd251 100644 --- a/ra/fsp/src/rm_tz_context/tz_context.c +++ b/ra/fsp/src/rm_tz_context/tz_context.c @@ -40,6 +40,10 @@ #define TZ_PROCESS_STACK_SIZE 256U #endif +#define TZ_PROCESS_STACK_SEAL_SIZE 8U + +#define TZ_PROCESS_STACK_SEAL_VALUE 0xFEF5EDA5 + /// MPU is not yet supported #define RM_TZ_CONTEXT_CFG_MPU_ENABLE 0U @@ -50,7 +54,7 @@ typedef struct { } stack_info_t; static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; -static uint32_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/sizeof(uint32_t)] BSP_ALIGN_VARIABLE(8); +static uint32_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][(TZ_PROCESS_STACK_SIZE + TZ_PROCESS_STACK_SEAL_SIZE)/sizeof(uint32_t)] BSP_ALIGN_VARIABLE(8); static uint32_t ProcessStackFreeSlot = UINT32_MAX; /// Initialize secure context memory system @@ -68,6 +72,9 @@ uint32_t TZ_InitContextSystem_S (void) { ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + + /* Seal each process stack. */ + ProcessStackMemory[n][TZ_PROCESS_STACK_SIZE/sizeof(uint32_t)] = TZ_PROCESS_STACK_SEAL_VALUE; } *((uint32_t *)ProcessStackMemory[--n]) = UINT32_MAX; diff --git a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c index a842aa82a..ba7446122 100644 --- a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c +++ b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c @@ -304,10 +304,6 @@ fsp_err_t RM_VEE_FLASH_Open (rm_vee_ctrl_t * const p_api_ctrl, rm_vee_cfg_t cons p_ctrl->ref_hdr.pad = 0; p_ctrl->ref_hdr.valid_code = RM_VEE_FLASH_VALID_CODE; -#if BSP_TZ_SECURE_BUILD - p_ctrl->callback_is_secure = true; -#endif - p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; p_ctrl->p_callback_memory = NULL; @@ -658,20 +654,25 @@ fsp_err_t RM_VEE_FLASH_CallbackSet (rm_vee_ctrl_t * const p_api_ctrl, #if BSP_TZ_SECURE_BUILD /* Get security state of p_callback */ - p_ctrl->callback_is_secure = + bool callback_is_secure = (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); - #if (RM_VEE_FLASH_CFG_PARAM_CHECKING_ENABLE) + #if RM_VEE_FLASH_CFG_PARAM_CHECKING_ENABLE /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ rm_vee_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); #endif #endif /* Store callback and context */ - p_ctrl->p_callback = p_callback; +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(rm_vee_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif p_ctrl->p_context = p_context; p_ctrl->p_callback_memory = p_callback_memory; @@ -1547,7 +1548,7 @@ static void rm_vee_call_callback (rm_vee_flash_instance_ctrl_t * p_ctrl, rm_vee_ #if BSP_TZ_SECURE_BUILD /* p_callback can point to a secure function or a non-secure function. */ - if (p_ctrl->callback_is_secure) + if (!cmse_is_nsfptr(p_ctrl->p_callback)) { /* If p_callback is secure, then the project does not need to change security state. */ p_ctrl->p_callback(p_args_memory);